blob: bf4e0d2709717de9c17b42af40f135b532259176 [file] [log] [blame]
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Top module auto-generated by `reggen`
`include "prim_assert.sv"
module pinmux_reg_top (
input clk_i,
input rst_ni,
input clk_aon_i,
input rst_aon_ni,
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
// To HW
output pinmux_reg_pkg::pinmux_reg2hw_t reg2hw, // Write
input pinmux_reg_pkg::pinmux_hw2reg_t hw2reg, // Read
// Integrity check errors
output logic intg_err_o,
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
import pinmux_reg_pkg::* ;
localparam int AW = 11;
localparam int DW = 32;
localparam int DBW = DW/8; // Byte Width
// register signals
logic reg_we;
logic reg_re;
logic [AW-1:0] reg_addr;
logic [DW-1:0] reg_wdata;
logic [DBW-1:0] reg_be;
logic [DW-1:0] reg_rdata;
logic reg_error;
logic addrmiss, wr_err;
logic [DW-1:0] reg_rdata_next;
logic reg_busy;
tlul_pkg::tl_h2d_t tl_reg_h2d;
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
logic intg_err;
tlul_cmd_intg_chk u_chk (
.tl_i(tl_i),
.err_o(intg_err)
);
// also check for spurious write enables
logic reg_we_err;
logic [413:0] reg_we_check;
prim_reg_we_check #(
.OneHotWidth(414)
) u_prim_reg_we_check (
.clk_i(clk_i),
.rst_ni(rst_ni),
.oh_i (reg_we_check),
.en_i (reg_we && !addrmiss),
.err_o (reg_we_err)
);
logic err_q;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
err_q <= '0;
end else if (intg_err || reg_we_err) begin
err_q <= 1'b1;
end
end
// integrity error output is permanent and should be used for alert generation
// register errors are transactional
assign intg_err_o = err_q | intg_err | reg_we_err;
// outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
tlul_rsp_intg_gen #(
.EnableRspIntgGen(1),
.EnableDataIntgGen(1)
) u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o(tl_o)
);
assign tl_reg_h2d = tl_i;
assign tl_o_pre = tl_reg_d2h;
tlul_adapter_reg #(
.RegAw(AW),
.RegDw(DW),
.EnableDataIntgGen(0)
) u_reg_if (
.clk_i (clk_i),
.rst_ni (rst_ni),
.tl_i (tl_reg_h2d),
.tl_o (tl_reg_d2h),
.en_ifetch_i(prim_mubi_pkg::MuBi4False),
.intg_error_o(),
.we_o (reg_we),
.re_o (reg_re),
.addr_o (reg_addr),
.wdata_o (reg_wdata),
.be_o (reg_be),
.busy_i (reg_busy),
.rdata_i (reg_rdata),
.error_i (reg_error)
);
// cdc oversampling signals
assign reg_rdata = reg_rdata_next ;
assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
// or <reg>_{wd|we|qs} if field == 1 or 0
logic alert_test_we;
logic alert_test_wd;
logic mio_periph_insel_regwen_0_we;
logic mio_periph_insel_regwen_0_qs;
logic mio_periph_insel_regwen_0_wd;
logic mio_periph_insel_regwen_1_we;
logic mio_periph_insel_regwen_1_qs;
logic mio_periph_insel_regwen_1_wd;
logic mio_periph_insel_regwen_2_we;
logic mio_periph_insel_regwen_2_qs;
logic mio_periph_insel_regwen_2_wd;
logic mio_periph_insel_regwen_3_we;
logic mio_periph_insel_regwen_3_qs;
logic mio_periph_insel_regwen_3_wd;
logic mio_periph_insel_regwen_4_we;
logic mio_periph_insel_regwen_4_qs;
logic mio_periph_insel_regwen_4_wd;
logic mio_periph_insel_regwen_5_we;
logic mio_periph_insel_regwen_5_qs;
logic mio_periph_insel_regwen_5_wd;
logic mio_periph_insel_regwen_6_we;
logic mio_periph_insel_regwen_6_qs;
logic mio_periph_insel_regwen_6_wd;
logic mio_periph_insel_regwen_7_we;
logic mio_periph_insel_regwen_7_qs;
logic mio_periph_insel_regwen_7_wd;
logic mio_periph_insel_regwen_8_we;
logic mio_periph_insel_regwen_8_qs;
logic mio_periph_insel_regwen_8_wd;
logic mio_periph_insel_regwen_9_we;
logic mio_periph_insel_regwen_9_qs;
logic mio_periph_insel_regwen_9_wd;
logic mio_periph_insel_regwen_10_we;
logic mio_periph_insel_regwen_10_qs;
logic mio_periph_insel_regwen_10_wd;
logic mio_periph_insel_regwen_11_we;
logic mio_periph_insel_regwen_11_qs;
logic mio_periph_insel_regwen_11_wd;
logic mio_periph_insel_regwen_12_we;
logic mio_periph_insel_regwen_12_qs;
logic mio_periph_insel_regwen_12_wd;
logic mio_periph_insel_regwen_13_we;
logic mio_periph_insel_regwen_13_qs;
logic mio_periph_insel_regwen_13_wd;
logic mio_periph_insel_regwen_14_we;
logic mio_periph_insel_regwen_14_qs;
logic mio_periph_insel_regwen_14_wd;
logic mio_periph_insel_regwen_15_we;
logic mio_periph_insel_regwen_15_qs;
logic mio_periph_insel_regwen_15_wd;
logic mio_periph_insel_regwen_16_we;
logic mio_periph_insel_regwen_16_qs;
logic mio_periph_insel_regwen_16_wd;
logic mio_periph_insel_regwen_17_we;
logic mio_periph_insel_regwen_17_qs;
logic mio_periph_insel_regwen_17_wd;
logic mio_periph_insel_regwen_18_we;
logic mio_periph_insel_regwen_18_qs;
logic mio_periph_insel_regwen_18_wd;
logic mio_periph_insel_regwen_19_we;
logic mio_periph_insel_regwen_19_qs;
logic mio_periph_insel_regwen_19_wd;
logic mio_periph_insel_regwen_20_we;
logic mio_periph_insel_regwen_20_qs;
logic mio_periph_insel_regwen_20_wd;
logic mio_periph_insel_regwen_21_we;
logic mio_periph_insel_regwen_21_qs;
logic mio_periph_insel_regwen_21_wd;
logic mio_periph_insel_regwen_22_we;
logic mio_periph_insel_regwen_22_qs;
logic mio_periph_insel_regwen_22_wd;
logic mio_periph_insel_regwen_23_we;
logic mio_periph_insel_regwen_23_qs;
logic mio_periph_insel_regwen_23_wd;
logic mio_periph_insel_regwen_24_we;
logic mio_periph_insel_regwen_24_qs;
logic mio_periph_insel_regwen_24_wd;
logic mio_periph_insel_regwen_25_we;
logic mio_periph_insel_regwen_25_qs;
logic mio_periph_insel_regwen_25_wd;
logic mio_periph_insel_regwen_26_we;
logic mio_periph_insel_regwen_26_qs;
logic mio_periph_insel_regwen_26_wd;
logic mio_periph_insel_regwen_27_we;
logic mio_periph_insel_regwen_27_qs;
logic mio_periph_insel_regwen_27_wd;
logic mio_periph_insel_regwen_28_we;
logic mio_periph_insel_regwen_28_qs;
logic mio_periph_insel_regwen_28_wd;
logic mio_periph_insel_regwen_29_we;
logic mio_periph_insel_regwen_29_qs;
logic mio_periph_insel_regwen_29_wd;
logic mio_periph_insel_regwen_30_we;
logic mio_periph_insel_regwen_30_qs;
logic mio_periph_insel_regwen_30_wd;
logic mio_periph_insel_regwen_31_we;
logic mio_periph_insel_regwen_31_qs;
logic mio_periph_insel_regwen_31_wd;
logic mio_periph_insel_regwen_32_we;
logic mio_periph_insel_regwen_32_qs;
logic mio_periph_insel_regwen_32_wd;
logic mio_periph_insel_0_we;
logic [5:0] mio_periph_insel_0_qs;
logic [5:0] mio_periph_insel_0_wd;
logic mio_periph_insel_1_we;
logic [5:0] mio_periph_insel_1_qs;
logic [5:0] mio_periph_insel_1_wd;
logic mio_periph_insel_2_we;
logic [5:0] mio_periph_insel_2_qs;
logic [5:0] mio_periph_insel_2_wd;
logic mio_periph_insel_3_we;
logic [5:0] mio_periph_insel_3_qs;
logic [5:0] mio_periph_insel_3_wd;
logic mio_periph_insel_4_we;
logic [5:0] mio_periph_insel_4_qs;
logic [5:0] mio_periph_insel_4_wd;
logic mio_periph_insel_5_we;
logic [5:0] mio_periph_insel_5_qs;
logic [5:0] mio_periph_insel_5_wd;
logic mio_periph_insel_6_we;
logic [5:0] mio_periph_insel_6_qs;
logic [5:0] mio_periph_insel_6_wd;
logic mio_periph_insel_7_we;
logic [5:0] mio_periph_insel_7_qs;
logic [5:0] mio_periph_insel_7_wd;
logic mio_periph_insel_8_we;
logic [5:0] mio_periph_insel_8_qs;
logic [5:0] mio_periph_insel_8_wd;
logic mio_periph_insel_9_we;
logic [5:0] mio_periph_insel_9_qs;
logic [5:0] mio_periph_insel_9_wd;
logic mio_periph_insel_10_we;
logic [5:0] mio_periph_insel_10_qs;
logic [5:0] mio_periph_insel_10_wd;
logic mio_periph_insel_11_we;
logic [5:0] mio_periph_insel_11_qs;
logic [5:0] mio_periph_insel_11_wd;
logic mio_periph_insel_12_we;
logic [5:0] mio_periph_insel_12_qs;
logic [5:0] mio_periph_insel_12_wd;
logic mio_periph_insel_13_we;
logic [5:0] mio_periph_insel_13_qs;
logic [5:0] mio_periph_insel_13_wd;
logic mio_periph_insel_14_we;
logic [5:0] mio_periph_insel_14_qs;
logic [5:0] mio_periph_insel_14_wd;
logic mio_periph_insel_15_we;
logic [5:0] mio_periph_insel_15_qs;
logic [5:0] mio_periph_insel_15_wd;
logic mio_periph_insel_16_we;
logic [5:0] mio_periph_insel_16_qs;
logic [5:0] mio_periph_insel_16_wd;
logic mio_periph_insel_17_we;
logic [5:0] mio_periph_insel_17_qs;
logic [5:0] mio_periph_insel_17_wd;
logic mio_periph_insel_18_we;
logic [5:0] mio_periph_insel_18_qs;
logic [5:0] mio_periph_insel_18_wd;
logic mio_periph_insel_19_we;
logic [5:0] mio_periph_insel_19_qs;
logic [5:0] mio_periph_insel_19_wd;
logic mio_periph_insel_20_we;
logic [5:0] mio_periph_insel_20_qs;
logic [5:0] mio_periph_insel_20_wd;
logic mio_periph_insel_21_we;
logic [5:0] mio_periph_insel_21_qs;
logic [5:0] mio_periph_insel_21_wd;
logic mio_periph_insel_22_we;
logic [5:0] mio_periph_insel_22_qs;
logic [5:0] mio_periph_insel_22_wd;
logic mio_periph_insel_23_we;
logic [5:0] mio_periph_insel_23_qs;
logic [5:0] mio_periph_insel_23_wd;
logic mio_periph_insel_24_we;
logic [5:0] mio_periph_insel_24_qs;
logic [5:0] mio_periph_insel_24_wd;
logic mio_periph_insel_25_we;
logic [5:0] mio_periph_insel_25_qs;
logic [5:0] mio_periph_insel_25_wd;
logic mio_periph_insel_26_we;
logic [5:0] mio_periph_insel_26_qs;
logic [5:0] mio_periph_insel_26_wd;
logic mio_periph_insel_27_we;
logic [5:0] mio_periph_insel_27_qs;
logic [5:0] mio_periph_insel_27_wd;
logic mio_periph_insel_28_we;
logic [5:0] mio_periph_insel_28_qs;
logic [5:0] mio_periph_insel_28_wd;
logic mio_periph_insel_29_we;
logic [5:0] mio_periph_insel_29_qs;
logic [5:0] mio_periph_insel_29_wd;
logic mio_periph_insel_30_we;
logic [5:0] mio_periph_insel_30_qs;
logic [5:0] mio_periph_insel_30_wd;
logic mio_periph_insel_31_we;
logic [5:0] mio_periph_insel_31_qs;
logic [5:0] mio_periph_insel_31_wd;
logic mio_periph_insel_32_we;
logic [5:0] mio_periph_insel_32_qs;
logic [5:0] mio_periph_insel_32_wd;
logic mio_outsel_regwen_0_we;
logic mio_outsel_regwen_0_qs;
logic mio_outsel_regwen_0_wd;
logic mio_outsel_regwen_1_we;
logic mio_outsel_regwen_1_qs;
logic mio_outsel_regwen_1_wd;
logic mio_outsel_regwen_2_we;
logic mio_outsel_regwen_2_qs;
logic mio_outsel_regwen_2_wd;
logic mio_outsel_regwen_3_we;
logic mio_outsel_regwen_3_qs;
logic mio_outsel_regwen_3_wd;
logic mio_outsel_regwen_4_we;
logic mio_outsel_regwen_4_qs;
logic mio_outsel_regwen_4_wd;
logic mio_outsel_regwen_5_we;
logic mio_outsel_regwen_5_qs;
logic mio_outsel_regwen_5_wd;
logic mio_outsel_regwen_6_we;
logic mio_outsel_regwen_6_qs;
logic mio_outsel_regwen_6_wd;
logic mio_outsel_regwen_7_we;
logic mio_outsel_regwen_7_qs;
logic mio_outsel_regwen_7_wd;
logic mio_outsel_regwen_8_we;
logic mio_outsel_regwen_8_qs;
logic mio_outsel_regwen_8_wd;
logic mio_outsel_regwen_9_we;
logic mio_outsel_regwen_9_qs;
logic mio_outsel_regwen_9_wd;
logic mio_outsel_regwen_10_we;
logic mio_outsel_regwen_10_qs;
logic mio_outsel_regwen_10_wd;
logic mio_outsel_regwen_11_we;
logic mio_outsel_regwen_11_qs;
logic mio_outsel_regwen_11_wd;
logic mio_outsel_regwen_12_we;
logic mio_outsel_regwen_12_qs;
logic mio_outsel_regwen_12_wd;
logic mio_outsel_regwen_13_we;
logic mio_outsel_regwen_13_qs;
logic mio_outsel_regwen_13_wd;
logic mio_outsel_regwen_14_we;
logic mio_outsel_regwen_14_qs;
logic mio_outsel_regwen_14_wd;
logic mio_outsel_regwen_15_we;
logic mio_outsel_regwen_15_qs;
logic mio_outsel_regwen_15_wd;
logic mio_outsel_regwen_16_we;
logic mio_outsel_regwen_16_qs;
logic mio_outsel_regwen_16_wd;
logic mio_outsel_regwen_17_we;
logic mio_outsel_regwen_17_qs;
logic mio_outsel_regwen_17_wd;
logic mio_outsel_regwen_18_we;
logic mio_outsel_regwen_18_qs;
logic mio_outsel_regwen_18_wd;
logic mio_outsel_regwen_19_we;
logic mio_outsel_regwen_19_qs;
logic mio_outsel_regwen_19_wd;
logic mio_outsel_regwen_20_we;
logic mio_outsel_regwen_20_qs;
logic mio_outsel_regwen_20_wd;
logic mio_outsel_regwen_21_we;
logic mio_outsel_regwen_21_qs;
logic mio_outsel_regwen_21_wd;
logic mio_outsel_regwen_22_we;
logic mio_outsel_regwen_22_qs;
logic mio_outsel_regwen_22_wd;
logic mio_outsel_regwen_23_we;
logic mio_outsel_regwen_23_qs;
logic mio_outsel_regwen_23_wd;
logic mio_outsel_regwen_24_we;
logic mio_outsel_regwen_24_qs;
logic mio_outsel_regwen_24_wd;
logic mio_outsel_regwen_25_we;
logic mio_outsel_regwen_25_qs;
logic mio_outsel_regwen_25_wd;
logic mio_outsel_regwen_26_we;
logic mio_outsel_regwen_26_qs;
logic mio_outsel_regwen_26_wd;
logic mio_outsel_regwen_27_we;
logic mio_outsel_regwen_27_qs;
logic mio_outsel_regwen_27_wd;
logic mio_outsel_regwen_28_we;
logic mio_outsel_regwen_28_qs;
logic mio_outsel_regwen_28_wd;
logic mio_outsel_regwen_29_we;
logic mio_outsel_regwen_29_qs;
logic mio_outsel_regwen_29_wd;
logic mio_outsel_regwen_30_we;
logic mio_outsel_regwen_30_qs;
logic mio_outsel_regwen_30_wd;
logic mio_outsel_regwen_31_we;
logic mio_outsel_regwen_31_qs;
logic mio_outsel_regwen_31_wd;
logic mio_outsel_0_we;
logic [5:0] mio_outsel_0_qs;
logic [5:0] mio_outsel_0_wd;
logic mio_outsel_1_we;
logic [5:0] mio_outsel_1_qs;
logic [5:0] mio_outsel_1_wd;
logic mio_outsel_2_we;
logic [5:0] mio_outsel_2_qs;
logic [5:0] mio_outsel_2_wd;
logic mio_outsel_3_we;
logic [5:0] mio_outsel_3_qs;
logic [5:0] mio_outsel_3_wd;
logic mio_outsel_4_we;
logic [5:0] mio_outsel_4_qs;
logic [5:0] mio_outsel_4_wd;
logic mio_outsel_5_we;
logic [5:0] mio_outsel_5_qs;
logic [5:0] mio_outsel_5_wd;
logic mio_outsel_6_we;
logic [5:0] mio_outsel_6_qs;
logic [5:0] mio_outsel_6_wd;
logic mio_outsel_7_we;
logic [5:0] mio_outsel_7_qs;
logic [5:0] mio_outsel_7_wd;
logic mio_outsel_8_we;
logic [5:0] mio_outsel_8_qs;
logic [5:0] mio_outsel_8_wd;
logic mio_outsel_9_we;
logic [5:0] mio_outsel_9_qs;
logic [5:0] mio_outsel_9_wd;
logic mio_outsel_10_we;
logic [5:0] mio_outsel_10_qs;
logic [5:0] mio_outsel_10_wd;
logic mio_outsel_11_we;
logic [5:0] mio_outsel_11_qs;
logic [5:0] mio_outsel_11_wd;
logic mio_outsel_12_we;
logic [5:0] mio_outsel_12_qs;
logic [5:0] mio_outsel_12_wd;
logic mio_outsel_13_we;
logic [5:0] mio_outsel_13_qs;
logic [5:0] mio_outsel_13_wd;
logic mio_outsel_14_we;
logic [5:0] mio_outsel_14_qs;
logic [5:0] mio_outsel_14_wd;
logic mio_outsel_15_we;
logic [5:0] mio_outsel_15_qs;
logic [5:0] mio_outsel_15_wd;
logic mio_outsel_16_we;
logic [5:0] mio_outsel_16_qs;
logic [5:0] mio_outsel_16_wd;
logic mio_outsel_17_we;
logic [5:0] mio_outsel_17_qs;
logic [5:0] mio_outsel_17_wd;
logic mio_outsel_18_we;
logic [5:0] mio_outsel_18_qs;
logic [5:0] mio_outsel_18_wd;
logic mio_outsel_19_we;
logic [5:0] mio_outsel_19_qs;
logic [5:0] mio_outsel_19_wd;
logic mio_outsel_20_we;
logic [5:0] mio_outsel_20_qs;
logic [5:0] mio_outsel_20_wd;
logic mio_outsel_21_we;
logic [5:0] mio_outsel_21_qs;
logic [5:0] mio_outsel_21_wd;
logic mio_outsel_22_we;
logic [5:0] mio_outsel_22_qs;
logic [5:0] mio_outsel_22_wd;
logic mio_outsel_23_we;
logic [5:0] mio_outsel_23_qs;
logic [5:0] mio_outsel_23_wd;
logic mio_outsel_24_we;
logic [5:0] mio_outsel_24_qs;
logic [5:0] mio_outsel_24_wd;
logic mio_outsel_25_we;
logic [5:0] mio_outsel_25_qs;
logic [5:0] mio_outsel_25_wd;
logic mio_outsel_26_we;
logic [5:0] mio_outsel_26_qs;
logic [5:0] mio_outsel_26_wd;
logic mio_outsel_27_we;
logic [5:0] mio_outsel_27_qs;
logic [5:0] mio_outsel_27_wd;
logic mio_outsel_28_we;
logic [5:0] mio_outsel_28_qs;
logic [5:0] mio_outsel_28_wd;
logic mio_outsel_29_we;
logic [5:0] mio_outsel_29_qs;
logic [5:0] mio_outsel_29_wd;
logic mio_outsel_30_we;
logic [5:0] mio_outsel_30_qs;
logic [5:0] mio_outsel_30_wd;
logic mio_outsel_31_we;
logic [5:0] mio_outsel_31_qs;
logic [5:0] mio_outsel_31_wd;
logic mio_pad_attr_regwen_0_we;
logic mio_pad_attr_regwen_0_qs;
logic mio_pad_attr_regwen_0_wd;
logic mio_pad_attr_regwen_1_we;
logic mio_pad_attr_regwen_1_qs;
logic mio_pad_attr_regwen_1_wd;
logic mio_pad_attr_regwen_2_we;
logic mio_pad_attr_regwen_2_qs;
logic mio_pad_attr_regwen_2_wd;
logic mio_pad_attr_regwen_3_we;
logic mio_pad_attr_regwen_3_qs;
logic mio_pad_attr_regwen_3_wd;
logic mio_pad_attr_regwen_4_we;
logic mio_pad_attr_regwen_4_qs;
logic mio_pad_attr_regwen_4_wd;
logic mio_pad_attr_regwen_5_we;
logic mio_pad_attr_regwen_5_qs;
logic mio_pad_attr_regwen_5_wd;
logic mio_pad_attr_regwen_6_we;
logic mio_pad_attr_regwen_6_qs;
logic mio_pad_attr_regwen_6_wd;
logic mio_pad_attr_regwen_7_we;
logic mio_pad_attr_regwen_7_qs;
logic mio_pad_attr_regwen_7_wd;
logic mio_pad_attr_regwen_8_we;
logic mio_pad_attr_regwen_8_qs;
logic mio_pad_attr_regwen_8_wd;
logic mio_pad_attr_regwen_9_we;
logic mio_pad_attr_regwen_9_qs;
logic mio_pad_attr_regwen_9_wd;
logic mio_pad_attr_regwen_10_we;
logic mio_pad_attr_regwen_10_qs;
logic mio_pad_attr_regwen_10_wd;
logic mio_pad_attr_regwen_11_we;
logic mio_pad_attr_regwen_11_qs;
logic mio_pad_attr_regwen_11_wd;
logic mio_pad_attr_regwen_12_we;
logic mio_pad_attr_regwen_12_qs;
logic mio_pad_attr_regwen_12_wd;
logic mio_pad_attr_regwen_13_we;
logic mio_pad_attr_regwen_13_qs;
logic mio_pad_attr_regwen_13_wd;
logic mio_pad_attr_regwen_14_we;
logic mio_pad_attr_regwen_14_qs;
logic mio_pad_attr_regwen_14_wd;
logic mio_pad_attr_regwen_15_we;
logic mio_pad_attr_regwen_15_qs;
logic mio_pad_attr_regwen_15_wd;
logic mio_pad_attr_regwen_16_we;
logic mio_pad_attr_regwen_16_qs;
logic mio_pad_attr_regwen_16_wd;
logic mio_pad_attr_regwen_17_we;
logic mio_pad_attr_regwen_17_qs;
logic mio_pad_attr_regwen_17_wd;
logic mio_pad_attr_regwen_18_we;
logic mio_pad_attr_regwen_18_qs;
logic mio_pad_attr_regwen_18_wd;
logic mio_pad_attr_regwen_19_we;
logic mio_pad_attr_regwen_19_qs;
logic mio_pad_attr_regwen_19_wd;
logic mio_pad_attr_regwen_20_we;
logic mio_pad_attr_regwen_20_qs;
logic mio_pad_attr_regwen_20_wd;
logic mio_pad_attr_regwen_21_we;
logic mio_pad_attr_regwen_21_qs;
logic mio_pad_attr_regwen_21_wd;
logic mio_pad_attr_regwen_22_we;
logic mio_pad_attr_regwen_22_qs;
logic mio_pad_attr_regwen_22_wd;
logic mio_pad_attr_regwen_23_we;
logic mio_pad_attr_regwen_23_qs;
logic mio_pad_attr_regwen_23_wd;
logic mio_pad_attr_regwen_24_we;
logic mio_pad_attr_regwen_24_qs;
logic mio_pad_attr_regwen_24_wd;
logic mio_pad_attr_regwen_25_we;
logic mio_pad_attr_regwen_25_qs;
logic mio_pad_attr_regwen_25_wd;
logic mio_pad_attr_regwen_26_we;
logic mio_pad_attr_regwen_26_qs;
logic mio_pad_attr_regwen_26_wd;
logic mio_pad_attr_regwen_27_we;
logic mio_pad_attr_regwen_27_qs;
logic mio_pad_attr_regwen_27_wd;
logic mio_pad_attr_regwen_28_we;
logic mio_pad_attr_regwen_28_qs;
logic mio_pad_attr_regwen_28_wd;
logic mio_pad_attr_regwen_29_we;
logic mio_pad_attr_regwen_29_qs;
logic mio_pad_attr_regwen_29_wd;
logic mio_pad_attr_regwen_30_we;
logic mio_pad_attr_regwen_30_qs;
logic mio_pad_attr_regwen_30_wd;
logic mio_pad_attr_regwen_31_we;
logic mio_pad_attr_regwen_31_qs;
logic mio_pad_attr_regwen_31_wd;
logic mio_pad_attr_0_re;
logic mio_pad_attr_0_we;
logic mio_pad_attr_0_invert_0_qs;
logic mio_pad_attr_0_invert_0_wd;
logic mio_pad_attr_0_virtual_od_en_0_qs;
logic mio_pad_attr_0_virtual_od_en_0_wd;
logic mio_pad_attr_0_pull_en_0_qs;
logic mio_pad_attr_0_pull_en_0_wd;
logic mio_pad_attr_0_pull_select_0_qs;
logic mio_pad_attr_0_pull_select_0_wd;
logic mio_pad_attr_0_keeper_en_0_qs;
logic mio_pad_attr_0_keeper_en_0_wd;
logic mio_pad_attr_0_schmitt_en_0_qs;
logic mio_pad_attr_0_schmitt_en_0_wd;
logic mio_pad_attr_0_od_en_0_qs;
logic mio_pad_attr_0_od_en_0_wd;
logic [1:0] mio_pad_attr_0_slew_rate_0_qs;
logic [1:0] mio_pad_attr_0_slew_rate_0_wd;
logic [3:0] mio_pad_attr_0_drive_strength_0_qs;
logic [3:0] mio_pad_attr_0_drive_strength_0_wd;
logic mio_pad_attr_1_re;
logic mio_pad_attr_1_we;
logic mio_pad_attr_1_invert_1_qs;
logic mio_pad_attr_1_invert_1_wd;
logic mio_pad_attr_1_virtual_od_en_1_qs;
logic mio_pad_attr_1_virtual_od_en_1_wd;
logic mio_pad_attr_1_pull_en_1_qs;
logic mio_pad_attr_1_pull_en_1_wd;
logic mio_pad_attr_1_pull_select_1_qs;
logic mio_pad_attr_1_pull_select_1_wd;
logic mio_pad_attr_1_keeper_en_1_qs;
logic mio_pad_attr_1_keeper_en_1_wd;
logic mio_pad_attr_1_schmitt_en_1_qs;
logic mio_pad_attr_1_schmitt_en_1_wd;
logic mio_pad_attr_1_od_en_1_qs;
logic mio_pad_attr_1_od_en_1_wd;
logic [1:0] mio_pad_attr_1_slew_rate_1_qs;
logic [1:0] mio_pad_attr_1_slew_rate_1_wd;
logic [3:0] mio_pad_attr_1_drive_strength_1_qs;
logic [3:0] mio_pad_attr_1_drive_strength_1_wd;
logic mio_pad_attr_2_re;
logic mio_pad_attr_2_we;
logic mio_pad_attr_2_invert_2_qs;
logic mio_pad_attr_2_invert_2_wd;
logic mio_pad_attr_2_virtual_od_en_2_qs;
logic mio_pad_attr_2_virtual_od_en_2_wd;
logic mio_pad_attr_2_pull_en_2_qs;
logic mio_pad_attr_2_pull_en_2_wd;
logic mio_pad_attr_2_pull_select_2_qs;
logic mio_pad_attr_2_pull_select_2_wd;
logic mio_pad_attr_2_keeper_en_2_qs;
logic mio_pad_attr_2_keeper_en_2_wd;
logic mio_pad_attr_2_schmitt_en_2_qs;
logic mio_pad_attr_2_schmitt_en_2_wd;
logic mio_pad_attr_2_od_en_2_qs;
logic mio_pad_attr_2_od_en_2_wd;
logic [1:0] mio_pad_attr_2_slew_rate_2_qs;
logic [1:0] mio_pad_attr_2_slew_rate_2_wd;
logic [3:0] mio_pad_attr_2_drive_strength_2_qs;
logic [3:0] mio_pad_attr_2_drive_strength_2_wd;
logic mio_pad_attr_3_re;
logic mio_pad_attr_3_we;
logic mio_pad_attr_3_invert_3_qs;
logic mio_pad_attr_3_invert_3_wd;
logic mio_pad_attr_3_virtual_od_en_3_qs;
logic mio_pad_attr_3_virtual_od_en_3_wd;
logic mio_pad_attr_3_pull_en_3_qs;
logic mio_pad_attr_3_pull_en_3_wd;
logic mio_pad_attr_3_pull_select_3_qs;
logic mio_pad_attr_3_pull_select_3_wd;
logic mio_pad_attr_3_keeper_en_3_qs;
logic mio_pad_attr_3_keeper_en_3_wd;
logic mio_pad_attr_3_schmitt_en_3_qs;
logic mio_pad_attr_3_schmitt_en_3_wd;
logic mio_pad_attr_3_od_en_3_qs;
logic mio_pad_attr_3_od_en_3_wd;
logic [1:0] mio_pad_attr_3_slew_rate_3_qs;
logic [1:0] mio_pad_attr_3_slew_rate_3_wd;
logic [3:0] mio_pad_attr_3_drive_strength_3_qs;
logic [3:0] mio_pad_attr_3_drive_strength_3_wd;
logic mio_pad_attr_4_re;
logic mio_pad_attr_4_we;
logic mio_pad_attr_4_invert_4_qs;
logic mio_pad_attr_4_invert_4_wd;
logic mio_pad_attr_4_virtual_od_en_4_qs;
logic mio_pad_attr_4_virtual_od_en_4_wd;
logic mio_pad_attr_4_pull_en_4_qs;
logic mio_pad_attr_4_pull_en_4_wd;
logic mio_pad_attr_4_pull_select_4_qs;
logic mio_pad_attr_4_pull_select_4_wd;
logic mio_pad_attr_4_keeper_en_4_qs;
logic mio_pad_attr_4_keeper_en_4_wd;
logic mio_pad_attr_4_schmitt_en_4_qs;
logic mio_pad_attr_4_schmitt_en_4_wd;
logic mio_pad_attr_4_od_en_4_qs;
logic mio_pad_attr_4_od_en_4_wd;
logic [1:0] mio_pad_attr_4_slew_rate_4_qs;
logic [1:0] mio_pad_attr_4_slew_rate_4_wd;
logic [3:0] mio_pad_attr_4_drive_strength_4_qs;
logic [3:0] mio_pad_attr_4_drive_strength_4_wd;
logic mio_pad_attr_5_re;
logic mio_pad_attr_5_we;
logic mio_pad_attr_5_invert_5_qs;
logic mio_pad_attr_5_invert_5_wd;
logic mio_pad_attr_5_virtual_od_en_5_qs;
logic mio_pad_attr_5_virtual_od_en_5_wd;
logic mio_pad_attr_5_pull_en_5_qs;
logic mio_pad_attr_5_pull_en_5_wd;
logic mio_pad_attr_5_pull_select_5_qs;
logic mio_pad_attr_5_pull_select_5_wd;
logic mio_pad_attr_5_keeper_en_5_qs;
logic mio_pad_attr_5_keeper_en_5_wd;
logic mio_pad_attr_5_schmitt_en_5_qs;
logic mio_pad_attr_5_schmitt_en_5_wd;
logic mio_pad_attr_5_od_en_5_qs;
logic mio_pad_attr_5_od_en_5_wd;
logic [1:0] mio_pad_attr_5_slew_rate_5_qs;
logic [1:0] mio_pad_attr_5_slew_rate_5_wd;
logic [3:0] mio_pad_attr_5_drive_strength_5_qs;
logic [3:0] mio_pad_attr_5_drive_strength_5_wd;
logic mio_pad_attr_6_re;
logic mio_pad_attr_6_we;
logic mio_pad_attr_6_invert_6_qs;
logic mio_pad_attr_6_invert_6_wd;
logic mio_pad_attr_6_virtual_od_en_6_qs;
logic mio_pad_attr_6_virtual_od_en_6_wd;
logic mio_pad_attr_6_pull_en_6_qs;
logic mio_pad_attr_6_pull_en_6_wd;
logic mio_pad_attr_6_pull_select_6_qs;
logic mio_pad_attr_6_pull_select_6_wd;
logic mio_pad_attr_6_keeper_en_6_qs;
logic mio_pad_attr_6_keeper_en_6_wd;
logic mio_pad_attr_6_schmitt_en_6_qs;
logic mio_pad_attr_6_schmitt_en_6_wd;
logic mio_pad_attr_6_od_en_6_qs;
logic mio_pad_attr_6_od_en_6_wd;
logic [1:0] mio_pad_attr_6_slew_rate_6_qs;
logic [1:0] mio_pad_attr_6_slew_rate_6_wd;
logic [3:0] mio_pad_attr_6_drive_strength_6_qs;
logic [3:0] mio_pad_attr_6_drive_strength_6_wd;
logic mio_pad_attr_7_re;
logic mio_pad_attr_7_we;
logic mio_pad_attr_7_invert_7_qs;
logic mio_pad_attr_7_invert_7_wd;
logic mio_pad_attr_7_virtual_od_en_7_qs;
logic mio_pad_attr_7_virtual_od_en_7_wd;
logic mio_pad_attr_7_pull_en_7_qs;
logic mio_pad_attr_7_pull_en_7_wd;
logic mio_pad_attr_7_pull_select_7_qs;
logic mio_pad_attr_7_pull_select_7_wd;
logic mio_pad_attr_7_keeper_en_7_qs;
logic mio_pad_attr_7_keeper_en_7_wd;
logic mio_pad_attr_7_schmitt_en_7_qs;
logic mio_pad_attr_7_schmitt_en_7_wd;
logic mio_pad_attr_7_od_en_7_qs;
logic mio_pad_attr_7_od_en_7_wd;
logic [1:0] mio_pad_attr_7_slew_rate_7_qs;
logic [1:0] mio_pad_attr_7_slew_rate_7_wd;
logic [3:0] mio_pad_attr_7_drive_strength_7_qs;
logic [3:0] mio_pad_attr_7_drive_strength_7_wd;
logic mio_pad_attr_8_re;
logic mio_pad_attr_8_we;
logic mio_pad_attr_8_invert_8_qs;
logic mio_pad_attr_8_invert_8_wd;
logic mio_pad_attr_8_virtual_od_en_8_qs;
logic mio_pad_attr_8_virtual_od_en_8_wd;
logic mio_pad_attr_8_pull_en_8_qs;
logic mio_pad_attr_8_pull_en_8_wd;
logic mio_pad_attr_8_pull_select_8_qs;
logic mio_pad_attr_8_pull_select_8_wd;
logic mio_pad_attr_8_keeper_en_8_qs;
logic mio_pad_attr_8_keeper_en_8_wd;
logic mio_pad_attr_8_schmitt_en_8_qs;
logic mio_pad_attr_8_schmitt_en_8_wd;
logic mio_pad_attr_8_od_en_8_qs;
logic mio_pad_attr_8_od_en_8_wd;
logic [1:0] mio_pad_attr_8_slew_rate_8_qs;
logic [1:0] mio_pad_attr_8_slew_rate_8_wd;
logic [3:0] mio_pad_attr_8_drive_strength_8_qs;
logic [3:0] mio_pad_attr_8_drive_strength_8_wd;
logic mio_pad_attr_9_re;
logic mio_pad_attr_9_we;
logic mio_pad_attr_9_invert_9_qs;
logic mio_pad_attr_9_invert_9_wd;
logic mio_pad_attr_9_virtual_od_en_9_qs;
logic mio_pad_attr_9_virtual_od_en_9_wd;
logic mio_pad_attr_9_pull_en_9_qs;
logic mio_pad_attr_9_pull_en_9_wd;
logic mio_pad_attr_9_pull_select_9_qs;
logic mio_pad_attr_9_pull_select_9_wd;
logic mio_pad_attr_9_keeper_en_9_qs;
logic mio_pad_attr_9_keeper_en_9_wd;
logic mio_pad_attr_9_schmitt_en_9_qs;
logic mio_pad_attr_9_schmitt_en_9_wd;
logic mio_pad_attr_9_od_en_9_qs;
logic mio_pad_attr_9_od_en_9_wd;
logic [1:0] mio_pad_attr_9_slew_rate_9_qs;
logic [1:0] mio_pad_attr_9_slew_rate_9_wd;
logic [3:0] mio_pad_attr_9_drive_strength_9_qs;
logic [3:0] mio_pad_attr_9_drive_strength_9_wd;
logic mio_pad_attr_10_re;
logic mio_pad_attr_10_we;
logic mio_pad_attr_10_invert_10_qs;
logic mio_pad_attr_10_invert_10_wd;
logic mio_pad_attr_10_virtual_od_en_10_qs;
logic mio_pad_attr_10_virtual_od_en_10_wd;
logic mio_pad_attr_10_pull_en_10_qs;
logic mio_pad_attr_10_pull_en_10_wd;
logic mio_pad_attr_10_pull_select_10_qs;
logic mio_pad_attr_10_pull_select_10_wd;
logic mio_pad_attr_10_keeper_en_10_qs;
logic mio_pad_attr_10_keeper_en_10_wd;
logic mio_pad_attr_10_schmitt_en_10_qs;
logic mio_pad_attr_10_schmitt_en_10_wd;
logic mio_pad_attr_10_od_en_10_qs;
logic mio_pad_attr_10_od_en_10_wd;
logic [1:0] mio_pad_attr_10_slew_rate_10_qs;
logic [1:0] mio_pad_attr_10_slew_rate_10_wd;
logic [3:0] mio_pad_attr_10_drive_strength_10_qs;
logic [3:0] mio_pad_attr_10_drive_strength_10_wd;
logic mio_pad_attr_11_re;
logic mio_pad_attr_11_we;
logic mio_pad_attr_11_invert_11_qs;
logic mio_pad_attr_11_invert_11_wd;
logic mio_pad_attr_11_virtual_od_en_11_qs;
logic mio_pad_attr_11_virtual_od_en_11_wd;
logic mio_pad_attr_11_pull_en_11_qs;
logic mio_pad_attr_11_pull_en_11_wd;
logic mio_pad_attr_11_pull_select_11_qs;
logic mio_pad_attr_11_pull_select_11_wd;
logic mio_pad_attr_11_keeper_en_11_qs;
logic mio_pad_attr_11_keeper_en_11_wd;
logic mio_pad_attr_11_schmitt_en_11_qs;
logic mio_pad_attr_11_schmitt_en_11_wd;
logic mio_pad_attr_11_od_en_11_qs;
logic mio_pad_attr_11_od_en_11_wd;
logic [1:0] mio_pad_attr_11_slew_rate_11_qs;
logic [1:0] mio_pad_attr_11_slew_rate_11_wd;
logic [3:0] mio_pad_attr_11_drive_strength_11_qs;
logic [3:0] mio_pad_attr_11_drive_strength_11_wd;
logic mio_pad_attr_12_re;
logic mio_pad_attr_12_we;
logic mio_pad_attr_12_invert_12_qs;
logic mio_pad_attr_12_invert_12_wd;
logic mio_pad_attr_12_virtual_od_en_12_qs;
logic mio_pad_attr_12_virtual_od_en_12_wd;
logic mio_pad_attr_12_pull_en_12_qs;
logic mio_pad_attr_12_pull_en_12_wd;
logic mio_pad_attr_12_pull_select_12_qs;
logic mio_pad_attr_12_pull_select_12_wd;
logic mio_pad_attr_12_keeper_en_12_qs;
logic mio_pad_attr_12_keeper_en_12_wd;
logic mio_pad_attr_12_schmitt_en_12_qs;
logic mio_pad_attr_12_schmitt_en_12_wd;
logic mio_pad_attr_12_od_en_12_qs;
logic mio_pad_attr_12_od_en_12_wd;
logic [1:0] mio_pad_attr_12_slew_rate_12_qs;
logic [1:0] mio_pad_attr_12_slew_rate_12_wd;
logic [3:0] mio_pad_attr_12_drive_strength_12_qs;
logic [3:0] mio_pad_attr_12_drive_strength_12_wd;
logic mio_pad_attr_13_re;
logic mio_pad_attr_13_we;
logic mio_pad_attr_13_invert_13_qs;
logic mio_pad_attr_13_invert_13_wd;
logic mio_pad_attr_13_virtual_od_en_13_qs;
logic mio_pad_attr_13_virtual_od_en_13_wd;
logic mio_pad_attr_13_pull_en_13_qs;
logic mio_pad_attr_13_pull_en_13_wd;
logic mio_pad_attr_13_pull_select_13_qs;
logic mio_pad_attr_13_pull_select_13_wd;
logic mio_pad_attr_13_keeper_en_13_qs;
logic mio_pad_attr_13_keeper_en_13_wd;
logic mio_pad_attr_13_schmitt_en_13_qs;
logic mio_pad_attr_13_schmitt_en_13_wd;
logic mio_pad_attr_13_od_en_13_qs;
logic mio_pad_attr_13_od_en_13_wd;
logic [1:0] mio_pad_attr_13_slew_rate_13_qs;
logic [1:0] mio_pad_attr_13_slew_rate_13_wd;
logic [3:0] mio_pad_attr_13_drive_strength_13_qs;
logic [3:0] mio_pad_attr_13_drive_strength_13_wd;
logic mio_pad_attr_14_re;
logic mio_pad_attr_14_we;
logic mio_pad_attr_14_invert_14_qs;
logic mio_pad_attr_14_invert_14_wd;
logic mio_pad_attr_14_virtual_od_en_14_qs;
logic mio_pad_attr_14_virtual_od_en_14_wd;
logic mio_pad_attr_14_pull_en_14_qs;
logic mio_pad_attr_14_pull_en_14_wd;
logic mio_pad_attr_14_pull_select_14_qs;
logic mio_pad_attr_14_pull_select_14_wd;
logic mio_pad_attr_14_keeper_en_14_qs;
logic mio_pad_attr_14_keeper_en_14_wd;
logic mio_pad_attr_14_schmitt_en_14_qs;
logic mio_pad_attr_14_schmitt_en_14_wd;
logic mio_pad_attr_14_od_en_14_qs;
logic mio_pad_attr_14_od_en_14_wd;
logic [1:0] mio_pad_attr_14_slew_rate_14_qs;
logic [1:0] mio_pad_attr_14_slew_rate_14_wd;
logic [3:0] mio_pad_attr_14_drive_strength_14_qs;
logic [3:0] mio_pad_attr_14_drive_strength_14_wd;
logic mio_pad_attr_15_re;
logic mio_pad_attr_15_we;
logic mio_pad_attr_15_invert_15_qs;
logic mio_pad_attr_15_invert_15_wd;
logic mio_pad_attr_15_virtual_od_en_15_qs;
logic mio_pad_attr_15_virtual_od_en_15_wd;
logic mio_pad_attr_15_pull_en_15_qs;
logic mio_pad_attr_15_pull_en_15_wd;
logic mio_pad_attr_15_pull_select_15_qs;
logic mio_pad_attr_15_pull_select_15_wd;
logic mio_pad_attr_15_keeper_en_15_qs;
logic mio_pad_attr_15_keeper_en_15_wd;
logic mio_pad_attr_15_schmitt_en_15_qs;
logic mio_pad_attr_15_schmitt_en_15_wd;
logic mio_pad_attr_15_od_en_15_qs;
logic mio_pad_attr_15_od_en_15_wd;
logic [1:0] mio_pad_attr_15_slew_rate_15_qs;
logic [1:0] mio_pad_attr_15_slew_rate_15_wd;
logic [3:0] mio_pad_attr_15_drive_strength_15_qs;
logic [3:0] mio_pad_attr_15_drive_strength_15_wd;
logic mio_pad_attr_16_re;
logic mio_pad_attr_16_we;
logic mio_pad_attr_16_invert_16_qs;
logic mio_pad_attr_16_invert_16_wd;
logic mio_pad_attr_16_virtual_od_en_16_qs;
logic mio_pad_attr_16_virtual_od_en_16_wd;
logic mio_pad_attr_16_pull_en_16_qs;
logic mio_pad_attr_16_pull_en_16_wd;
logic mio_pad_attr_16_pull_select_16_qs;
logic mio_pad_attr_16_pull_select_16_wd;
logic mio_pad_attr_16_keeper_en_16_qs;
logic mio_pad_attr_16_keeper_en_16_wd;
logic mio_pad_attr_16_schmitt_en_16_qs;
logic mio_pad_attr_16_schmitt_en_16_wd;
logic mio_pad_attr_16_od_en_16_qs;
logic mio_pad_attr_16_od_en_16_wd;
logic [1:0] mio_pad_attr_16_slew_rate_16_qs;
logic [1:0] mio_pad_attr_16_slew_rate_16_wd;
logic [3:0] mio_pad_attr_16_drive_strength_16_qs;
logic [3:0] mio_pad_attr_16_drive_strength_16_wd;
logic mio_pad_attr_17_re;
logic mio_pad_attr_17_we;
logic mio_pad_attr_17_invert_17_qs;
logic mio_pad_attr_17_invert_17_wd;
logic mio_pad_attr_17_virtual_od_en_17_qs;
logic mio_pad_attr_17_virtual_od_en_17_wd;
logic mio_pad_attr_17_pull_en_17_qs;
logic mio_pad_attr_17_pull_en_17_wd;
logic mio_pad_attr_17_pull_select_17_qs;
logic mio_pad_attr_17_pull_select_17_wd;
logic mio_pad_attr_17_keeper_en_17_qs;
logic mio_pad_attr_17_keeper_en_17_wd;
logic mio_pad_attr_17_schmitt_en_17_qs;
logic mio_pad_attr_17_schmitt_en_17_wd;
logic mio_pad_attr_17_od_en_17_qs;
logic mio_pad_attr_17_od_en_17_wd;
logic [1:0] mio_pad_attr_17_slew_rate_17_qs;
logic [1:0] mio_pad_attr_17_slew_rate_17_wd;
logic [3:0] mio_pad_attr_17_drive_strength_17_qs;
logic [3:0] mio_pad_attr_17_drive_strength_17_wd;
logic mio_pad_attr_18_re;
logic mio_pad_attr_18_we;
logic mio_pad_attr_18_invert_18_qs;
logic mio_pad_attr_18_invert_18_wd;
logic mio_pad_attr_18_virtual_od_en_18_qs;
logic mio_pad_attr_18_virtual_od_en_18_wd;
logic mio_pad_attr_18_pull_en_18_qs;
logic mio_pad_attr_18_pull_en_18_wd;
logic mio_pad_attr_18_pull_select_18_qs;
logic mio_pad_attr_18_pull_select_18_wd;
logic mio_pad_attr_18_keeper_en_18_qs;
logic mio_pad_attr_18_keeper_en_18_wd;
logic mio_pad_attr_18_schmitt_en_18_qs;
logic mio_pad_attr_18_schmitt_en_18_wd;
logic mio_pad_attr_18_od_en_18_qs;
logic mio_pad_attr_18_od_en_18_wd;
logic [1:0] mio_pad_attr_18_slew_rate_18_qs;
logic [1:0] mio_pad_attr_18_slew_rate_18_wd;
logic [3:0] mio_pad_attr_18_drive_strength_18_qs;
logic [3:0] mio_pad_attr_18_drive_strength_18_wd;
logic mio_pad_attr_19_re;
logic mio_pad_attr_19_we;
logic mio_pad_attr_19_invert_19_qs;
logic mio_pad_attr_19_invert_19_wd;
logic mio_pad_attr_19_virtual_od_en_19_qs;
logic mio_pad_attr_19_virtual_od_en_19_wd;
logic mio_pad_attr_19_pull_en_19_qs;
logic mio_pad_attr_19_pull_en_19_wd;
logic mio_pad_attr_19_pull_select_19_qs;
logic mio_pad_attr_19_pull_select_19_wd;
logic mio_pad_attr_19_keeper_en_19_qs;
logic mio_pad_attr_19_keeper_en_19_wd;
logic mio_pad_attr_19_schmitt_en_19_qs;
logic mio_pad_attr_19_schmitt_en_19_wd;
logic mio_pad_attr_19_od_en_19_qs;
logic mio_pad_attr_19_od_en_19_wd;
logic [1:0] mio_pad_attr_19_slew_rate_19_qs;
logic [1:0] mio_pad_attr_19_slew_rate_19_wd;
logic [3:0] mio_pad_attr_19_drive_strength_19_qs;
logic [3:0] mio_pad_attr_19_drive_strength_19_wd;
logic mio_pad_attr_20_re;
logic mio_pad_attr_20_we;
logic mio_pad_attr_20_invert_20_qs;
logic mio_pad_attr_20_invert_20_wd;
logic mio_pad_attr_20_virtual_od_en_20_qs;
logic mio_pad_attr_20_virtual_od_en_20_wd;
logic mio_pad_attr_20_pull_en_20_qs;
logic mio_pad_attr_20_pull_en_20_wd;
logic mio_pad_attr_20_pull_select_20_qs;
logic mio_pad_attr_20_pull_select_20_wd;
logic mio_pad_attr_20_keeper_en_20_qs;
logic mio_pad_attr_20_keeper_en_20_wd;
logic mio_pad_attr_20_schmitt_en_20_qs;
logic mio_pad_attr_20_schmitt_en_20_wd;
logic mio_pad_attr_20_od_en_20_qs;
logic mio_pad_attr_20_od_en_20_wd;
logic [1:0] mio_pad_attr_20_slew_rate_20_qs;
logic [1:0] mio_pad_attr_20_slew_rate_20_wd;
logic [3:0] mio_pad_attr_20_drive_strength_20_qs;
logic [3:0] mio_pad_attr_20_drive_strength_20_wd;
logic mio_pad_attr_21_re;
logic mio_pad_attr_21_we;
logic mio_pad_attr_21_invert_21_qs;
logic mio_pad_attr_21_invert_21_wd;
logic mio_pad_attr_21_virtual_od_en_21_qs;
logic mio_pad_attr_21_virtual_od_en_21_wd;
logic mio_pad_attr_21_pull_en_21_qs;
logic mio_pad_attr_21_pull_en_21_wd;
logic mio_pad_attr_21_pull_select_21_qs;
logic mio_pad_attr_21_pull_select_21_wd;
logic mio_pad_attr_21_keeper_en_21_qs;
logic mio_pad_attr_21_keeper_en_21_wd;
logic mio_pad_attr_21_schmitt_en_21_qs;
logic mio_pad_attr_21_schmitt_en_21_wd;
logic mio_pad_attr_21_od_en_21_qs;
logic mio_pad_attr_21_od_en_21_wd;
logic [1:0] mio_pad_attr_21_slew_rate_21_qs;
logic [1:0] mio_pad_attr_21_slew_rate_21_wd;
logic [3:0] mio_pad_attr_21_drive_strength_21_qs;
logic [3:0] mio_pad_attr_21_drive_strength_21_wd;
logic mio_pad_attr_22_re;
logic mio_pad_attr_22_we;
logic mio_pad_attr_22_invert_22_qs;
logic mio_pad_attr_22_invert_22_wd;
logic mio_pad_attr_22_virtual_od_en_22_qs;
logic mio_pad_attr_22_virtual_od_en_22_wd;
logic mio_pad_attr_22_pull_en_22_qs;
logic mio_pad_attr_22_pull_en_22_wd;
logic mio_pad_attr_22_pull_select_22_qs;
logic mio_pad_attr_22_pull_select_22_wd;
logic mio_pad_attr_22_keeper_en_22_qs;
logic mio_pad_attr_22_keeper_en_22_wd;
logic mio_pad_attr_22_schmitt_en_22_qs;
logic mio_pad_attr_22_schmitt_en_22_wd;
logic mio_pad_attr_22_od_en_22_qs;
logic mio_pad_attr_22_od_en_22_wd;
logic [1:0] mio_pad_attr_22_slew_rate_22_qs;
logic [1:0] mio_pad_attr_22_slew_rate_22_wd;
logic [3:0] mio_pad_attr_22_drive_strength_22_qs;
logic [3:0] mio_pad_attr_22_drive_strength_22_wd;
logic mio_pad_attr_23_re;
logic mio_pad_attr_23_we;
logic mio_pad_attr_23_invert_23_qs;
logic mio_pad_attr_23_invert_23_wd;
logic mio_pad_attr_23_virtual_od_en_23_qs;
logic mio_pad_attr_23_virtual_od_en_23_wd;
logic mio_pad_attr_23_pull_en_23_qs;
logic mio_pad_attr_23_pull_en_23_wd;
logic mio_pad_attr_23_pull_select_23_qs;
logic mio_pad_attr_23_pull_select_23_wd;
logic mio_pad_attr_23_keeper_en_23_qs;
logic mio_pad_attr_23_keeper_en_23_wd;
logic mio_pad_attr_23_schmitt_en_23_qs;
logic mio_pad_attr_23_schmitt_en_23_wd;
logic mio_pad_attr_23_od_en_23_qs;
logic mio_pad_attr_23_od_en_23_wd;
logic [1:0] mio_pad_attr_23_slew_rate_23_qs;
logic [1:0] mio_pad_attr_23_slew_rate_23_wd;
logic [3:0] mio_pad_attr_23_drive_strength_23_qs;
logic [3:0] mio_pad_attr_23_drive_strength_23_wd;
logic mio_pad_attr_24_re;
logic mio_pad_attr_24_we;
logic mio_pad_attr_24_invert_24_qs;
logic mio_pad_attr_24_invert_24_wd;
logic mio_pad_attr_24_virtual_od_en_24_qs;
logic mio_pad_attr_24_virtual_od_en_24_wd;
logic mio_pad_attr_24_pull_en_24_qs;
logic mio_pad_attr_24_pull_en_24_wd;
logic mio_pad_attr_24_pull_select_24_qs;
logic mio_pad_attr_24_pull_select_24_wd;
logic mio_pad_attr_24_keeper_en_24_qs;
logic mio_pad_attr_24_keeper_en_24_wd;
logic mio_pad_attr_24_schmitt_en_24_qs;
logic mio_pad_attr_24_schmitt_en_24_wd;
logic mio_pad_attr_24_od_en_24_qs;
logic mio_pad_attr_24_od_en_24_wd;
logic [1:0] mio_pad_attr_24_slew_rate_24_qs;
logic [1:0] mio_pad_attr_24_slew_rate_24_wd;
logic [3:0] mio_pad_attr_24_drive_strength_24_qs;
logic [3:0] mio_pad_attr_24_drive_strength_24_wd;
logic mio_pad_attr_25_re;
logic mio_pad_attr_25_we;
logic mio_pad_attr_25_invert_25_qs;
logic mio_pad_attr_25_invert_25_wd;
logic mio_pad_attr_25_virtual_od_en_25_qs;
logic mio_pad_attr_25_virtual_od_en_25_wd;
logic mio_pad_attr_25_pull_en_25_qs;
logic mio_pad_attr_25_pull_en_25_wd;
logic mio_pad_attr_25_pull_select_25_qs;
logic mio_pad_attr_25_pull_select_25_wd;
logic mio_pad_attr_25_keeper_en_25_qs;
logic mio_pad_attr_25_keeper_en_25_wd;
logic mio_pad_attr_25_schmitt_en_25_qs;
logic mio_pad_attr_25_schmitt_en_25_wd;
logic mio_pad_attr_25_od_en_25_qs;
logic mio_pad_attr_25_od_en_25_wd;
logic [1:0] mio_pad_attr_25_slew_rate_25_qs;
logic [1:0] mio_pad_attr_25_slew_rate_25_wd;
logic [3:0] mio_pad_attr_25_drive_strength_25_qs;
logic [3:0] mio_pad_attr_25_drive_strength_25_wd;
logic mio_pad_attr_26_re;
logic mio_pad_attr_26_we;
logic mio_pad_attr_26_invert_26_qs;
logic mio_pad_attr_26_invert_26_wd;
logic mio_pad_attr_26_virtual_od_en_26_qs;
logic mio_pad_attr_26_virtual_od_en_26_wd;
logic mio_pad_attr_26_pull_en_26_qs;
logic mio_pad_attr_26_pull_en_26_wd;
logic mio_pad_attr_26_pull_select_26_qs;
logic mio_pad_attr_26_pull_select_26_wd;
logic mio_pad_attr_26_keeper_en_26_qs;
logic mio_pad_attr_26_keeper_en_26_wd;
logic mio_pad_attr_26_schmitt_en_26_qs;
logic mio_pad_attr_26_schmitt_en_26_wd;
logic mio_pad_attr_26_od_en_26_qs;
logic mio_pad_attr_26_od_en_26_wd;
logic [1:0] mio_pad_attr_26_slew_rate_26_qs;
logic [1:0] mio_pad_attr_26_slew_rate_26_wd;
logic [3:0] mio_pad_attr_26_drive_strength_26_qs;
logic [3:0] mio_pad_attr_26_drive_strength_26_wd;
logic mio_pad_attr_27_re;
logic mio_pad_attr_27_we;
logic mio_pad_attr_27_invert_27_qs;
logic mio_pad_attr_27_invert_27_wd;
logic mio_pad_attr_27_virtual_od_en_27_qs;
logic mio_pad_attr_27_virtual_od_en_27_wd;
logic mio_pad_attr_27_pull_en_27_qs;
logic mio_pad_attr_27_pull_en_27_wd;
logic mio_pad_attr_27_pull_select_27_qs;
logic mio_pad_attr_27_pull_select_27_wd;
logic mio_pad_attr_27_keeper_en_27_qs;
logic mio_pad_attr_27_keeper_en_27_wd;
logic mio_pad_attr_27_schmitt_en_27_qs;
logic mio_pad_attr_27_schmitt_en_27_wd;
logic mio_pad_attr_27_od_en_27_qs;
logic mio_pad_attr_27_od_en_27_wd;
logic [1:0] mio_pad_attr_27_slew_rate_27_qs;
logic [1:0] mio_pad_attr_27_slew_rate_27_wd;
logic [3:0] mio_pad_attr_27_drive_strength_27_qs;
logic [3:0] mio_pad_attr_27_drive_strength_27_wd;
logic mio_pad_attr_28_re;
logic mio_pad_attr_28_we;
logic mio_pad_attr_28_invert_28_qs;
logic mio_pad_attr_28_invert_28_wd;
logic mio_pad_attr_28_virtual_od_en_28_qs;
logic mio_pad_attr_28_virtual_od_en_28_wd;
logic mio_pad_attr_28_pull_en_28_qs;
logic mio_pad_attr_28_pull_en_28_wd;
logic mio_pad_attr_28_pull_select_28_qs;
logic mio_pad_attr_28_pull_select_28_wd;
logic mio_pad_attr_28_keeper_en_28_qs;
logic mio_pad_attr_28_keeper_en_28_wd;
logic mio_pad_attr_28_schmitt_en_28_qs;
logic mio_pad_attr_28_schmitt_en_28_wd;
logic mio_pad_attr_28_od_en_28_qs;
logic mio_pad_attr_28_od_en_28_wd;
logic [1:0] mio_pad_attr_28_slew_rate_28_qs;
logic [1:0] mio_pad_attr_28_slew_rate_28_wd;
logic [3:0] mio_pad_attr_28_drive_strength_28_qs;
logic [3:0] mio_pad_attr_28_drive_strength_28_wd;
logic mio_pad_attr_29_re;
logic mio_pad_attr_29_we;
logic mio_pad_attr_29_invert_29_qs;
logic mio_pad_attr_29_invert_29_wd;
logic mio_pad_attr_29_virtual_od_en_29_qs;
logic mio_pad_attr_29_virtual_od_en_29_wd;
logic mio_pad_attr_29_pull_en_29_qs;
logic mio_pad_attr_29_pull_en_29_wd;
logic mio_pad_attr_29_pull_select_29_qs;
logic mio_pad_attr_29_pull_select_29_wd;
logic mio_pad_attr_29_keeper_en_29_qs;
logic mio_pad_attr_29_keeper_en_29_wd;
logic mio_pad_attr_29_schmitt_en_29_qs;
logic mio_pad_attr_29_schmitt_en_29_wd;
logic mio_pad_attr_29_od_en_29_qs;
logic mio_pad_attr_29_od_en_29_wd;
logic [1:0] mio_pad_attr_29_slew_rate_29_qs;
logic [1:0] mio_pad_attr_29_slew_rate_29_wd;
logic [3:0] mio_pad_attr_29_drive_strength_29_qs;
logic [3:0] mio_pad_attr_29_drive_strength_29_wd;
logic mio_pad_attr_30_re;
logic mio_pad_attr_30_we;
logic mio_pad_attr_30_invert_30_qs;
logic mio_pad_attr_30_invert_30_wd;
logic mio_pad_attr_30_virtual_od_en_30_qs;
logic mio_pad_attr_30_virtual_od_en_30_wd;
logic mio_pad_attr_30_pull_en_30_qs;
logic mio_pad_attr_30_pull_en_30_wd;
logic mio_pad_attr_30_pull_select_30_qs;
logic mio_pad_attr_30_pull_select_30_wd;
logic mio_pad_attr_30_keeper_en_30_qs;
logic mio_pad_attr_30_keeper_en_30_wd;
logic mio_pad_attr_30_schmitt_en_30_qs;
logic mio_pad_attr_30_schmitt_en_30_wd;
logic mio_pad_attr_30_od_en_30_qs;
logic mio_pad_attr_30_od_en_30_wd;
logic [1:0] mio_pad_attr_30_slew_rate_30_qs;
logic [1:0] mio_pad_attr_30_slew_rate_30_wd;
logic [3:0] mio_pad_attr_30_drive_strength_30_qs;
logic [3:0] mio_pad_attr_30_drive_strength_30_wd;
logic mio_pad_attr_31_re;
logic mio_pad_attr_31_we;
logic mio_pad_attr_31_invert_31_qs;
logic mio_pad_attr_31_invert_31_wd;
logic mio_pad_attr_31_virtual_od_en_31_qs;
logic mio_pad_attr_31_virtual_od_en_31_wd;
logic mio_pad_attr_31_pull_en_31_qs;
logic mio_pad_attr_31_pull_en_31_wd;
logic mio_pad_attr_31_pull_select_31_qs;
logic mio_pad_attr_31_pull_select_31_wd;
logic mio_pad_attr_31_keeper_en_31_qs;
logic mio_pad_attr_31_keeper_en_31_wd;
logic mio_pad_attr_31_schmitt_en_31_qs;
logic mio_pad_attr_31_schmitt_en_31_wd;
logic mio_pad_attr_31_od_en_31_qs;
logic mio_pad_attr_31_od_en_31_wd;
logic [1:0] mio_pad_attr_31_slew_rate_31_qs;
logic [1:0] mio_pad_attr_31_slew_rate_31_wd;
logic [3:0] mio_pad_attr_31_drive_strength_31_qs;
logic [3:0] mio_pad_attr_31_drive_strength_31_wd;
logic dio_pad_attr_regwen_0_we;
logic dio_pad_attr_regwen_0_qs;
logic dio_pad_attr_regwen_0_wd;
logic dio_pad_attr_regwen_1_we;
logic dio_pad_attr_regwen_1_qs;
logic dio_pad_attr_regwen_1_wd;
logic dio_pad_attr_regwen_2_we;
logic dio_pad_attr_regwen_2_qs;
logic dio_pad_attr_regwen_2_wd;
logic dio_pad_attr_regwen_3_we;
logic dio_pad_attr_regwen_3_qs;
logic dio_pad_attr_regwen_3_wd;
logic dio_pad_attr_regwen_4_we;
logic dio_pad_attr_regwen_4_qs;
logic dio_pad_attr_regwen_4_wd;
logic dio_pad_attr_regwen_5_we;
logic dio_pad_attr_regwen_5_qs;
logic dio_pad_attr_regwen_5_wd;
logic dio_pad_attr_regwen_6_we;
logic dio_pad_attr_regwen_6_qs;
logic dio_pad_attr_regwen_6_wd;
logic dio_pad_attr_regwen_7_we;
logic dio_pad_attr_regwen_7_qs;
logic dio_pad_attr_regwen_7_wd;
logic dio_pad_attr_regwen_8_we;
logic dio_pad_attr_regwen_8_qs;
logic dio_pad_attr_regwen_8_wd;
logic dio_pad_attr_regwen_9_we;
logic dio_pad_attr_regwen_9_qs;
logic dio_pad_attr_regwen_9_wd;
logic dio_pad_attr_regwen_10_we;
logic dio_pad_attr_regwen_10_qs;
logic dio_pad_attr_regwen_10_wd;
logic dio_pad_attr_regwen_11_we;
logic dio_pad_attr_regwen_11_qs;
logic dio_pad_attr_regwen_11_wd;
logic dio_pad_attr_regwen_12_we;
logic dio_pad_attr_regwen_12_qs;
logic dio_pad_attr_regwen_12_wd;
logic dio_pad_attr_regwen_13_we;
logic dio_pad_attr_regwen_13_qs;
logic dio_pad_attr_regwen_13_wd;
logic dio_pad_attr_regwen_14_we;
logic dio_pad_attr_regwen_14_qs;
logic dio_pad_attr_regwen_14_wd;
logic dio_pad_attr_regwen_15_we;
logic dio_pad_attr_regwen_15_qs;
logic dio_pad_attr_regwen_15_wd;
logic dio_pad_attr_0_re;
logic dio_pad_attr_0_we;
logic dio_pad_attr_0_invert_0_qs;
logic dio_pad_attr_0_invert_0_wd;
logic dio_pad_attr_0_virtual_od_en_0_qs;
logic dio_pad_attr_0_virtual_od_en_0_wd;
logic dio_pad_attr_0_pull_en_0_qs;
logic dio_pad_attr_0_pull_en_0_wd;
logic dio_pad_attr_0_pull_select_0_qs;
logic dio_pad_attr_0_pull_select_0_wd;
logic dio_pad_attr_0_keeper_en_0_qs;
logic dio_pad_attr_0_keeper_en_0_wd;
logic dio_pad_attr_0_schmitt_en_0_qs;
logic dio_pad_attr_0_schmitt_en_0_wd;
logic dio_pad_attr_0_od_en_0_qs;
logic dio_pad_attr_0_od_en_0_wd;
logic [1:0] dio_pad_attr_0_slew_rate_0_qs;
logic [1:0] dio_pad_attr_0_slew_rate_0_wd;
logic [3:0] dio_pad_attr_0_drive_strength_0_qs;
logic [3:0] dio_pad_attr_0_drive_strength_0_wd;
logic dio_pad_attr_1_re;
logic dio_pad_attr_1_we;
logic dio_pad_attr_1_invert_1_qs;
logic dio_pad_attr_1_invert_1_wd;
logic dio_pad_attr_1_virtual_od_en_1_qs;
logic dio_pad_attr_1_virtual_od_en_1_wd;
logic dio_pad_attr_1_pull_en_1_qs;
logic dio_pad_attr_1_pull_en_1_wd;
logic dio_pad_attr_1_pull_select_1_qs;
logic dio_pad_attr_1_pull_select_1_wd;
logic dio_pad_attr_1_keeper_en_1_qs;
logic dio_pad_attr_1_keeper_en_1_wd;
logic dio_pad_attr_1_schmitt_en_1_qs;
logic dio_pad_attr_1_schmitt_en_1_wd;
logic dio_pad_attr_1_od_en_1_qs;
logic dio_pad_attr_1_od_en_1_wd;
logic [1:0] dio_pad_attr_1_slew_rate_1_qs;
logic [1:0] dio_pad_attr_1_slew_rate_1_wd;
logic [3:0] dio_pad_attr_1_drive_strength_1_qs;
logic [3:0] dio_pad_attr_1_drive_strength_1_wd;
logic dio_pad_attr_2_re;
logic dio_pad_attr_2_we;
logic dio_pad_attr_2_invert_2_qs;
logic dio_pad_attr_2_invert_2_wd;
logic dio_pad_attr_2_virtual_od_en_2_qs;
logic dio_pad_attr_2_virtual_od_en_2_wd;
logic dio_pad_attr_2_pull_en_2_qs;
logic dio_pad_attr_2_pull_en_2_wd;
logic dio_pad_attr_2_pull_select_2_qs;
logic dio_pad_attr_2_pull_select_2_wd;
logic dio_pad_attr_2_keeper_en_2_qs;
logic dio_pad_attr_2_keeper_en_2_wd;
logic dio_pad_attr_2_schmitt_en_2_qs;
logic dio_pad_attr_2_schmitt_en_2_wd;
logic dio_pad_attr_2_od_en_2_qs;
logic dio_pad_attr_2_od_en_2_wd;
logic [1:0] dio_pad_attr_2_slew_rate_2_qs;
logic [1:0] dio_pad_attr_2_slew_rate_2_wd;
logic [3:0] dio_pad_attr_2_drive_strength_2_qs;
logic [3:0] dio_pad_attr_2_drive_strength_2_wd;
logic dio_pad_attr_3_re;
logic dio_pad_attr_3_we;
logic dio_pad_attr_3_invert_3_qs;
logic dio_pad_attr_3_invert_3_wd;
logic dio_pad_attr_3_virtual_od_en_3_qs;
logic dio_pad_attr_3_virtual_od_en_3_wd;
logic dio_pad_attr_3_pull_en_3_qs;
logic dio_pad_attr_3_pull_en_3_wd;
logic dio_pad_attr_3_pull_select_3_qs;
logic dio_pad_attr_3_pull_select_3_wd;
logic dio_pad_attr_3_keeper_en_3_qs;
logic dio_pad_attr_3_keeper_en_3_wd;
logic dio_pad_attr_3_schmitt_en_3_qs;
logic dio_pad_attr_3_schmitt_en_3_wd;
logic dio_pad_attr_3_od_en_3_qs;
logic dio_pad_attr_3_od_en_3_wd;
logic [1:0] dio_pad_attr_3_slew_rate_3_qs;
logic [1:0] dio_pad_attr_3_slew_rate_3_wd;
logic [3:0] dio_pad_attr_3_drive_strength_3_qs;
logic [3:0] dio_pad_attr_3_drive_strength_3_wd;
logic dio_pad_attr_4_re;
logic dio_pad_attr_4_we;
logic dio_pad_attr_4_invert_4_qs;
logic dio_pad_attr_4_invert_4_wd;
logic dio_pad_attr_4_virtual_od_en_4_qs;
logic dio_pad_attr_4_virtual_od_en_4_wd;
logic dio_pad_attr_4_pull_en_4_qs;
logic dio_pad_attr_4_pull_en_4_wd;
logic dio_pad_attr_4_pull_select_4_qs;
logic dio_pad_attr_4_pull_select_4_wd;
logic dio_pad_attr_4_keeper_en_4_qs;
logic dio_pad_attr_4_keeper_en_4_wd;
logic dio_pad_attr_4_schmitt_en_4_qs;
logic dio_pad_attr_4_schmitt_en_4_wd;
logic dio_pad_attr_4_od_en_4_qs;
logic dio_pad_attr_4_od_en_4_wd;
logic [1:0] dio_pad_attr_4_slew_rate_4_qs;
logic [1:0] dio_pad_attr_4_slew_rate_4_wd;
logic [3:0] dio_pad_attr_4_drive_strength_4_qs;
logic [3:0] dio_pad_attr_4_drive_strength_4_wd;
logic dio_pad_attr_5_re;
logic dio_pad_attr_5_we;
logic dio_pad_attr_5_invert_5_qs;
logic dio_pad_attr_5_invert_5_wd;
logic dio_pad_attr_5_virtual_od_en_5_qs;
logic dio_pad_attr_5_virtual_od_en_5_wd;
logic dio_pad_attr_5_pull_en_5_qs;
logic dio_pad_attr_5_pull_en_5_wd;
logic dio_pad_attr_5_pull_select_5_qs;
logic dio_pad_attr_5_pull_select_5_wd;
logic dio_pad_attr_5_keeper_en_5_qs;
logic dio_pad_attr_5_keeper_en_5_wd;
logic dio_pad_attr_5_schmitt_en_5_qs;
logic dio_pad_attr_5_schmitt_en_5_wd;
logic dio_pad_attr_5_od_en_5_qs;
logic dio_pad_attr_5_od_en_5_wd;
logic [1:0] dio_pad_attr_5_slew_rate_5_qs;
logic [1:0] dio_pad_attr_5_slew_rate_5_wd;
logic [3:0] dio_pad_attr_5_drive_strength_5_qs;
logic [3:0] dio_pad_attr_5_drive_strength_5_wd;
logic dio_pad_attr_6_re;
logic dio_pad_attr_6_we;
logic dio_pad_attr_6_invert_6_qs;
logic dio_pad_attr_6_invert_6_wd;
logic dio_pad_attr_6_virtual_od_en_6_qs;
logic dio_pad_attr_6_virtual_od_en_6_wd;
logic dio_pad_attr_6_pull_en_6_qs;
logic dio_pad_attr_6_pull_en_6_wd;
logic dio_pad_attr_6_pull_select_6_qs;
logic dio_pad_attr_6_pull_select_6_wd;
logic dio_pad_attr_6_keeper_en_6_qs;
logic dio_pad_attr_6_keeper_en_6_wd;
logic dio_pad_attr_6_schmitt_en_6_qs;
logic dio_pad_attr_6_schmitt_en_6_wd;
logic dio_pad_attr_6_od_en_6_qs;
logic dio_pad_attr_6_od_en_6_wd;
logic [1:0] dio_pad_attr_6_slew_rate_6_qs;
logic [1:0] dio_pad_attr_6_slew_rate_6_wd;
logic [3:0] dio_pad_attr_6_drive_strength_6_qs;
logic [3:0] dio_pad_attr_6_drive_strength_6_wd;
logic dio_pad_attr_7_re;
logic dio_pad_attr_7_we;
logic dio_pad_attr_7_invert_7_qs;
logic dio_pad_attr_7_invert_7_wd;
logic dio_pad_attr_7_virtual_od_en_7_qs;
logic dio_pad_attr_7_virtual_od_en_7_wd;
logic dio_pad_attr_7_pull_en_7_qs;
logic dio_pad_attr_7_pull_en_7_wd;
logic dio_pad_attr_7_pull_select_7_qs;
logic dio_pad_attr_7_pull_select_7_wd;
logic dio_pad_attr_7_keeper_en_7_qs;
logic dio_pad_attr_7_keeper_en_7_wd;
logic dio_pad_attr_7_schmitt_en_7_qs;
logic dio_pad_attr_7_schmitt_en_7_wd;
logic dio_pad_attr_7_od_en_7_qs;
logic dio_pad_attr_7_od_en_7_wd;
logic [1:0] dio_pad_attr_7_slew_rate_7_qs;
logic [1:0] dio_pad_attr_7_slew_rate_7_wd;
logic [3:0] dio_pad_attr_7_drive_strength_7_qs;
logic [3:0] dio_pad_attr_7_drive_strength_7_wd;
logic dio_pad_attr_8_re;
logic dio_pad_attr_8_we;
logic dio_pad_attr_8_invert_8_qs;
logic dio_pad_attr_8_invert_8_wd;
logic dio_pad_attr_8_virtual_od_en_8_qs;
logic dio_pad_attr_8_virtual_od_en_8_wd;
logic dio_pad_attr_8_pull_en_8_qs;
logic dio_pad_attr_8_pull_en_8_wd;
logic dio_pad_attr_8_pull_select_8_qs;
logic dio_pad_attr_8_pull_select_8_wd;
logic dio_pad_attr_8_keeper_en_8_qs;
logic dio_pad_attr_8_keeper_en_8_wd;
logic dio_pad_attr_8_schmitt_en_8_qs;
logic dio_pad_attr_8_schmitt_en_8_wd;
logic dio_pad_attr_8_od_en_8_qs;
logic dio_pad_attr_8_od_en_8_wd;
logic [1:0] dio_pad_attr_8_slew_rate_8_qs;
logic [1:0] dio_pad_attr_8_slew_rate_8_wd;
logic [3:0] dio_pad_attr_8_drive_strength_8_qs;
logic [3:0] dio_pad_attr_8_drive_strength_8_wd;
logic dio_pad_attr_9_re;
logic dio_pad_attr_9_we;
logic dio_pad_attr_9_invert_9_qs;
logic dio_pad_attr_9_invert_9_wd;
logic dio_pad_attr_9_virtual_od_en_9_qs;
logic dio_pad_attr_9_virtual_od_en_9_wd;
logic dio_pad_attr_9_pull_en_9_qs;
logic dio_pad_attr_9_pull_en_9_wd;
logic dio_pad_attr_9_pull_select_9_qs;
logic dio_pad_attr_9_pull_select_9_wd;
logic dio_pad_attr_9_keeper_en_9_qs;
logic dio_pad_attr_9_keeper_en_9_wd;
logic dio_pad_attr_9_schmitt_en_9_qs;
logic dio_pad_attr_9_schmitt_en_9_wd;
logic dio_pad_attr_9_od_en_9_qs;
logic dio_pad_attr_9_od_en_9_wd;
logic [1:0] dio_pad_attr_9_slew_rate_9_qs;
logic [1:0] dio_pad_attr_9_slew_rate_9_wd;
logic [3:0] dio_pad_attr_9_drive_strength_9_qs;
logic [3:0] dio_pad_attr_9_drive_strength_9_wd;
logic dio_pad_attr_10_re;
logic dio_pad_attr_10_we;
logic dio_pad_attr_10_invert_10_qs;
logic dio_pad_attr_10_invert_10_wd;
logic dio_pad_attr_10_virtual_od_en_10_qs;
logic dio_pad_attr_10_virtual_od_en_10_wd;
logic dio_pad_attr_10_pull_en_10_qs;
logic dio_pad_attr_10_pull_en_10_wd;
logic dio_pad_attr_10_pull_select_10_qs;
logic dio_pad_attr_10_pull_select_10_wd;
logic dio_pad_attr_10_keeper_en_10_qs;
logic dio_pad_attr_10_keeper_en_10_wd;
logic dio_pad_attr_10_schmitt_en_10_qs;
logic dio_pad_attr_10_schmitt_en_10_wd;
logic dio_pad_attr_10_od_en_10_qs;
logic dio_pad_attr_10_od_en_10_wd;
logic [1:0] dio_pad_attr_10_slew_rate_10_qs;
logic [1:0] dio_pad_attr_10_slew_rate_10_wd;
logic [3:0] dio_pad_attr_10_drive_strength_10_qs;
logic [3:0] dio_pad_attr_10_drive_strength_10_wd;
logic dio_pad_attr_11_re;
logic dio_pad_attr_11_we;
logic dio_pad_attr_11_invert_11_qs;
logic dio_pad_attr_11_invert_11_wd;
logic dio_pad_attr_11_virtual_od_en_11_qs;
logic dio_pad_attr_11_virtual_od_en_11_wd;
logic dio_pad_attr_11_pull_en_11_qs;
logic dio_pad_attr_11_pull_en_11_wd;
logic dio_pad_attr_11_pull_select_11_qs;
logic dio_pad_attr_11_pull_select_11_wd;
logic dio_pad_attr_11_keeper_en_11_qs;
logic dio_pad_attr_11_keeper_en_11_wd;
logic dio_pad_attr_11_schmitt_en_11_qs;
logic dio_pad_attr_11_schmitt_en_11_wd;
logic dio_pad_attr_11_od_en_11_qs;
logic dio_pad_attr_11_od_en_11_wd;
logic [1:0] dio_pad_attr_11_slew_rate_11_qs;
logic [1:0] dio_pad_attr_11_slew_rate_11_wd;
logic [3:0] dio_pad_attr_11_drive_strength_11_qs;
logic [3:0] dio_pad_attr_11_drive_strength_11_wd;
logic dio_pad_attr_12_re;
logic dio_pad_attr_12_we;
logic dio_pad_attr_12_invert_12_qs;
logic dio_pad_attr_12_invert_12_wd;
logic dio_pad_attr_12_virtual_od_en_12_qs;
logic dio_pad_attr_12_virtual_od_en_12_wd;
logic dio_pad_attr_12_pull_en_12_qs;
logic dio_pad_attr_12_pull_en_12_wd;
logic dio_pad_attr_12_pull_select_12_qs;
logic dio_pad_attr_12_pull_select_12_wd;
logic dio_pad_attr_12_keeper_en_12_qs;
logic dio_pad_attr_12_keeper_en_12_wd;
logic dio_pad_attr_12_schmitt_en_12_qs;
logic dio_pad_attr_12_schmitt_en_12_wd;
logic dio_pad_attr_12_od_en_12_qs;
logic dio_pad_attr_12_od_en_12_wd;
logic [1:0] dio_pad_attr_12_slew_rate_12_qs;
logic [1:0] dio_pad_attr_12_slew_rate_12_wd;
logic [3:0] dio_pad_attr_12_drive_strength_12_qs;
logic [3:0] dio_pad_attr_12_drive_strength_12_wd;
logic dio_pad_attr_13_re;
logic dio_pad_attr_13_we;
logic dio_pad_attr_13_invert_13_qs;
logic dio_pad_attr_13_invert_13_wd;
logic dio_pad_attr_13_virtual_od_en_13_qs;
logic dio_pad_attr_13_virtual_od_en_13_wd;
logic dio_pad_attr_13_pull_en_13_qs;
logic dio_pad_attr_13_pull_en_13_wd;
logic dio_pad_attr_13_pull_select_13_qs;
logic dio_pad_attr_13_pull_select_13_wd;
logic dio_pad_attr_13_keeper_en_13_qs;
logic dio_pad_attr_13_keeper_en_13_wd;
logic dio_pad_attr_13_schmitt_en_13_qs;
logic dio_pad_attr_13_schmitt_en_13_wd;
logic dio_pad_attr_13_od_en_13_qs;
logic dio_pad_attr_13_od_en_13_wd;
logic [1:0] dio_pad_attr_13_slew_rate_13_qs;
logic [1:0] dio_pad_attr_13_slew_rate_13_wd;
logic [3:0] dio_pad_attr_13_drive_strength_13_qs;
logic [3:0] dio_pad_attr_13_drive_strength_13_wd;
logic dio_pad_attr_14_re;
logic dio_pad_attr_14_we;
logic dio_pad_attr_14_invert_14_qs;
logic dio_pad_attr_14_invert_14_wd;
logic dio_pad_attr_14_virtual_od_en_14_qs;
logic dio_pad_attr_14_virtual_od_en_14_wd;
logic dio_pad_attr_14_pull_en_14_qs;
logic dio_pad_attr_14_pull_en_14_wd;
logic dio_pad_attr_14_pull_select_14_qs;
logic dio_pad_attr_14_pull_select_14_wd;
logic dio_pad_attr_14_keeper_en_14_qs;
logic dio_pad_attr_14_keeper_en_14_wd;
logic dio_pad_attr_14_schmitt_en_14_qs;
logic dio_pad_attr_14_schmitt_en_14_wd;
logic dio_pad_attr_14_od_en_14_qs;
logic dio_pad_attr_14_od_en_14_wd;
logic [1:0] dio_pad_attr_14_slew_rate_14_qs;
logic [1:0] dio_pad_attr_14_slew_rate_14_wd;
logic [3:0] dio_pad_attr_14_drive_strength_14_qs;
logic [3:0] dio_pad_attr_14_drive_strength_14_wd;
logic dio_pad_attr_15_re;
logic dio_pad_attr_15_we;
logic dio_pad_attr_15_invert_15_qs;
logic dio_pad_attr_15_invert_15_wd;
logic dio_pad_attr_15_virtual_od_en_15_qs;
logic dio_pad_attr_15_virtual_od_en_15_wd;
logic dio_pad_attr_15_pull_en_15_qs;
logic dio_pad_attr_15_pull_en_15_wd;
logic dio_pad_attr_15_pull_select_15_qs;
logic dio_pad_attr_15_pull_select_15_wd;
logic dio_pad_attr_15_keeper_en_15_qs;
logic dio_pad_attr_15_keeper_en_15_wd;
logic dio_pad_attr_15_schmitt_en_15_qs;
logic dio_pad_attr_15_schmitt_en_15_wd;
logic dio_pad_attr_15_od_en_15_qs;
logic dio_pad_attr_15_od_en_15_wd;
logic [1:0] dio_pad_attr_15_slew_rate_15_qs;
logic [1:0] dio_pad_attr_15_slew_rate_15_wd;
logic [3:0] dio_pad_attr_15_drive_strength_15_qs;
logic [3:0] dio_pad_attr_15_drive_strength_15_wd;
logic mio_pad_sleep_status_we;
logic mio_pad_sleep_status_en_0_qs;
logic mio_pad_sleep_status_en_0_wd;
logic mio_pad_sleep_status_en_1_qs;
logic mio_pad_sleep_status_en_1_wd;
logic mio_pad_sleep_status_en_2_qs;
logic mio_pad_sleep_status_en_2_wd;
logic mio_pad_sleep_status_en_3_qs;
logic mio_pad_sleep_status_en_3_wd;
logic mio_pad_sleep_status_en_4_qs;
logic mio_pad_sleep_status_en_4_wd;
logic mio_pad_sleep_status_en_5_qs;
logic mio_pad_sleep_status_en_5_wd;
logic mio_pad_sleep_status_en_6_qs;
logic mio_pad_sleep_status_en_6_wd;
logic mio_pad_sleep_status_en_7_qs;
logic mio_pad_sleep_status_en_7_wd;
logic mio_pad_sleep_status_en_8_qs;
logic mio_pad_sleep_status_en_8_wd;
logic mio_pad_sleep_status_en_9_qs;
logic mio_pad_sleep_status_en_9_wd;
logic mio_pad_sleep_status_en_10_qs;
logic mio_pad_sleep_status_en_10_wd;
logic mio_pad_sleep_status_en_11_qs;
logic mio_pad_sleep_status_en_11_wd;
logic mio_pad_sleep_status_en_12_qs;
logic mio_pad_sleep_status_en_12_wd;
logic mio_pad_sleep_status_en_13_qs;
logic mio_pad_sleep_status_en_13_wd;
logic mio_pad_sleep_status_en_14_qs;
logic mio_pad_sleep_status_en_14_wd;
logic mio_pad_sleep_status_en_15_qs;
logic mio_pad_sleep_status_en_15_wd;
logic mio_pad_sleep_status_en_16_qs;
logic mio_pad_sleep_status_en_16_wd;
logic mio_pad_sleep_status_en_17_qs;
logic mio_pad_sleep_status_en_17_wd;
logic mio_pad_sleep_status_en_18_qs;
logic mio_pad_sleep_status_en_18_wd;
logic mio_pad_sleep_status_en_19_qs;
logic mio_pad_sleep_status_en_19_wd;
logic mio_pad_sleep_status_en_20_qs;
logic mio_pad_sleep_status_en_20_wd;
logic mio_pad_sleep_status_en_21_qs;
logic mio_pad_sleep_status_en_21_wd;
logic mio_pad_sleep_status_en_22_qs;
logic mio_pad_sleep_status_en_22_wd;
logic mio_pad_sleep_status_en_23_qs;
logic mio_pad_sleep_status_en_23_wd;
logic mio_pad_sleep_status_en_24_qs;
logic mio_pad_sleep_status_en_24_wd;
logic mio_pad_sleep_status_en_25_qs;
logic mio_pad_sleep_status_en_25_wd;
logic mio_pad_sleep_status_en_26_qs;
logic mio_pad_sleep_status_en_26_wd;
logic mio_pad_sleep_status_en_27_qs;
logic mio_pad_sleep_status_en_27_wd;
logic mio_pad_sleep_status_en_28_qs;
logic mio_pad_sleep_status_en_28_wd;
logic mio_pad_sleep_status_en_29_qs;
logic mio_pad_sleep_status_en_29_wd;
logic mio_pad_sleep_status_en_30_qs;
logic mio_pad_sleep_status_en_30_wd;
logic mio_pad_sleep_status_en_31_qs;
logic mio_pad_sleep_status_en_31_wd;
logic mio_pad_sleep_regwen_0_we;
logic mio_pad_sleep_regwen_0_qs;
logic mio_pad_sleep_regwen_0_wd;
logic mio_pad_sleep_regwen_1_we;
logic mio_pad_sleep_regwen_1_qs;
logic mio_pad_sleep_regwen_1_wd;
logic mio_pad_sleep_regwen_2_we;
logic mio_pad_sleep_regwen_2_qs;
logic mio_pad_sleep_regwen_2_wd;
logic mio_pad_sleep_regwen_3_we;
logic mio_pad_sleep_regwen_3_qs;
logic mio_pad_sleep_regwen_3_wd;
logic mio_pad_sleep_regwen_4_we;
logic mio_pad_sleep_regwen_4_qs;
logic mio_pad_sleep_regwen_4_wd;
logic mio_pad_sleep_regwen_5_we;
logic mio_pad_sleep_regwen_5_qs;
logic mio_pad_sleep_regwen_5_wd;
logic mio_pad_sleep_regwen_6_we;
logic mio_pad_sleep_regwen_6_qs;
logic mio_pad_sleep_regwen_6_wd;
logic mio_pad_sleep_regwen_7_we;
logic mio_pad_sleep_regwen_7_qs;
logic mio_pad_sleep_regwen_7_wd;
logic mio_pad_sleep_regwen_8_we;
logic mio_pad_sleep_regwen_8_qs;
logic mio_pad_sleep_regwen_8_wd;
logic mio_pad_sleep_regwen_9_we;
logic mio_pad_sleep_regwen_9_qs;
logic mio_pad_sleep_regwen_9_wd;
logic mio_pad_sleep_regwen_10_we;
logic mio_pad_sleep_regwen_10_qs;
logic mio_pad_sleep_regwen_10_wd;
logic mio_pad_sleep_regwen_11_we;
logic mio_pad_sleep_regwen_11_qs;
logic mio_pad_sleep_regwen_11_wd;
logic mio_pad_sleep_regwen_12_we;
logic mio_pad_sleep_regwen_12_qs;
logic mio_pad_sleep_regwen_12_wd;
logic mio_pad_sleep_regwen_13_we;
logic mio_pad_sleep_regwen_13_qs;
logic mio_pad_sleep_regwen_13_wd;
logic mio_pad_sleep_regwen_14_we;
logic mio_pad_sleep_regwen_14_qs;
logic mio_pad_sleep_regwen_14_wd;
logic mio_pad_sleep_regwen_15_we;
logic mio_pad_sleep_regwen_15_qs;
logic mio_pad_sleep_regwen_15_wd;
logic mio_pad_sleep_regwen_16_we;
logic mio_pad_sleep_regwen_16_qs;
logic mio_pad_sleep_regwen_16_wd;
logic mio_pad_sleep_regwen_17_we;
logic mio_pad_sleep_regwen_17_qs;
logic mio_pad_sleep_regwen_17_wd;
logic mio_pad_sleep_regwen_18_we;
logic mio_pad_sleep_regwen_18_qs;
logic mio_pad_sleep_regwen_18_wd;
logic mio_pad_sleep_regwen_19_we;
logic mio_pad_sleep_regwen_19_qs;
logic mio_pad_sleep_regwen_19_wd;
logic mio_pad_sleep_regwen_20_we;
logic mio_pad_sleep_regwen_20_qs;
logic mio_pad_sleep_regwen_20_wd;
logic mio_pad_sleep_regwen_21_we;
logic mio_pad_sleep_regwen_21_qs;
logic mio_pad_sleep_regwen_21_wd;
logic mio_pad_sleep_regwen_22_we;
logic mio_pad_sleep_regwen_22_qs;
logic mio_pad_sleep_regwen_22_wd;
logic mio_pad_sleep_regwen_23_we;
logic mio_pad_sleep_regwen_23_qs;
logic mio_pad_sleep_regwen_23_wd;
logic mio_pad_sleep_regwen_24_we;
logic mio_pad_sleep_regwen_24_qs;
logic mio_pad_sleep_regwen_24_wd;
logic mio_pad_sleep_regwen_25_we;
logic mio_pad_sleep_regwen_25_qs;
logic mio_pad_sleep_regwen_25_wd;
logic mio_pad_sleep_regwen_26_we;
logic mio_pad_sleep_regwen_26_qs;
logic mio_pad_sleep_regwen_26_wd;
logic mio_pad_sleep_regwen_27_we;
logic mio_pad_sleep_regwen_27_qs;
logic mio_pad_sleep_regwen_27_wd;
logic mio_pad_sleep_regwen_28_we;
logic mio_pad_sleep_regwen_28_qs;
logic mio_pad_sleep_regwen_28_wd;
logic mio_pad_sleep_regwen_29_we;
logic mio_pad_sleep_regwen_29_qs;
logic mio_pad_sleep_regwen_29_wd;
logic mio_pad_sleep_regwen_30_we;
logic mio_pad_sleep_regwen_30_qs;
logic mio_pad_sleep_regwen_30_wd;
logic mio_pad_sleep_regwen_31_we;
logic mio_pad_sleep_regwen_31_qs;
logic mio_pad_sleep_regwen_31_wd;
logic mio_pad_sleep_en_0_we;
logic mio_pad_sleep_en_0_qs;
logic mio_pad_sleep_en_0_wd;
logic mio_pad_sleep_en_1_we;
logic mio_pad_sleep_en_1_qs;
logic mio_pad_sleep_en_1_wd;
logic mio_pad_sleep_en_2_we;
logic mio_pad_sleep_en_2_qs;
logic mio_pad_sleep_en_2_wd;
logic mio_pad_sleep_en_3_we;
logic mio_pad_sleep_en_3_qs;
logic mio_pad_sleep_en_3_wd;
logic mio_pad_sleep_en_4_we;
logic mio_pad_sleep_en_4_qs;
logic mio_pad_sleep_en_4_wd;
logic mio_pad_sleep_en_5_we;
logic mio_pad_sleep_en_5_qs;
logic mio_pad_sleep_en_5_wd;
logic mio_pad_sleep_en_6_we;
logic mio_pad_sleep_en_6_qs;
logic mio_pad_sleep_en_6_wd;
logic mio_pad_sleep_en_7_we;
logic mio_pad_sleep_en_7_qs;
logic mio_pad_sleep_en_7_wd;
logic mio_pad_sleep_en_8_we;
logic mio_pad_sleep_en_8_qs;
logic mio_pad_sleep_en_8_wd;
logic mio_pad_sleep_en_9_we;
logic mio_pad_sleep_en_9_qs;
logic mio_pad_sleep_en_9_wd;
logic mio_pad_sleep_en_10_we;
logic mio_pad_sleep_en_10_qs;
logic mio_pad_sleep_en_10_wd;
logic mio_pad_sleep_en_11_we;
logic mio_pad_sleep_en_11_qs;
logic mio_pad_sleep_en_11_wd;
logic mio_pad_sleep_en_12_we;
logic mio_pad_sleep_en_12_qs;
logic mio_pad_sleep_en_12_wd;
logic mio_pad_sleep_en_13_we;
logic mio_pad_sleep_en_13_qs;
logic mio_pad_sleep_en_13_wd;
logic mio_pad_sleep_en_14_we;
logic mio_pad_sleep_en_14_qs;
logic mio_pad_sleep_en_14_wd;
logic mio_pad_sleep_en_15_we;
logic mio_pad_sleep_en_15_qs;
logic mio_pad_sleep_en_15_wd;
logic mio_pad_sleep_en_16_we;
logic mio_pad_sleep_en_16_qs;
logic mio_pad_sleep_en_16_wd;
logic mio_pad_sleep_en_17_we;
logic mio_pad_sleep_en_17_qs;
logic mio_pad_sleep_en_17_wd;
logic mio_pad_sleep_en_18_we;
logic mio_pad_sleep_en_18_qs;
logic mio_pad_sleep_en_18_wd;
logic mio_pad_sleep_en_19_we;
logic mio_pad_sleep_en_19_qs;
logic mio_pad_sleep_en_19_wd;
logic mio_pad_sleep_en_20_we;
logic mio_pad_sleep_en_20_qs;
logic mio_pad_sleep_en_20_wd;
logic mio_pad_sleep_en_21_we;
logic mio_pad_sleep_en_21_qs;
logic mio_pad_sleep_en_21_wd;
logic mio_pad_sleep_en_22_we;
logic mio_pad_sleep_en_22_qs;
logic mio_pad_sleep_en_22_wd;
logic mio_pad_sleep_en_23_we;
logic mio_pad_sleep_en_23_qs;
logic mio_pad_sleep_en_23_wd;
logic mio_pad_sleep_en_24_we;
logic mio_pad_sleep_en_24_qs;
logic mio_pad_sleep_en_24_wd;
logic mio_pad_sleep_en_25_we;
logic mio_pad_sleep_en_25_qs;
logic mio_pad_sleep_en_25_wd;
logic mio_pad_sleep_en_26_we;
logic mio_pad_sleep_en_26_qs;
logic mio_pad_sleep_en_26_wd;
logic mio_pad_sleep_en_27_we;
logic mio_pad_sleep_en_27_qs;
logic mio_pad_sleep_en_27_wd;
logic mio_pad_sleep_en_28_we;
logic mio_pad_sleep_en_28_qs;
logic mio_pad_sleep_en_28_wd;
logic mio_pad_sleep_en_29_we;
logic mio_pad_sleep_en_29_qs;
logic mio_pad_sleep_en_29_wd;
logic mio_pad_sleep_en_30_we;
logic mio_pad_sleep_en_30_qs;
logic mio_pad_sleep_en_30_wd;
logic mio_pad_sleep_en_31_we;
logic mio_pad_sleep_en_31_qs;
logic mio_pad_sleep_en_31_wd;
logic mio_pad_sleep_mode_0_we;
logic [1:0] mio_pad_sleep_mode_0_qs;
logic [1:0] mio_pad_sleep_mode_0_wd;
logic mio_pad_sleep_mode_1_we;
logic [1:0] mio_pad_sleep_mode_1_qs;
logic [1:0] mio_pad_sleep_mode_1_wd;
logic mio_pad_sleep_mode_2_we;
logic [1:0] mio_pad_sleep_mode_2_qs;
logic [1:0] mio_pad_sleep_mode_2_wd;
logic mio_pad_sleep_mode_3_we;
logic [1:0] mio_pad_sleep_mode_3_qs;
logic [1:0] mio_pad_sleep_mode_3_wd;
logic mio_pad_sleep_mode_4_we;
logic [1:0] mio_pad_sleep_mode_4_qs;
logic [1:0] mio_pad_sleep_mode_4_wd;
logic mio_pad_sleep_mode_5_we;
logic [1:0] mio_pad_sleep_mode_5_qs;
logic [1:0] mio_pad_sleep_mode_5_wd;
logic mio_pad_sleep_mode_6_we;
logic [1:0] mio_pad_sleep_mode_6_qs;
logic [1:0] mio_pad_sleep_mode_6_wd;
logic mio_pad_sleep_mode_7_we;
logic [1:0] mio_pad_sleep_mode_7_qs;
logic [1:0] mio_pad_sleep_mode_7_wd;
logic mio_pad_sleep_mode_8_we;
logic [1:0] mio_pad_sleep_mode_8_qs;
logic [1:0] mio_pad_sleep_mode_8_wd;
logic mio_pad_sleep_mode_9_we;
logic [1:0] mio_pad_sleep_mode_9_qs;
logic [1:0] mio_pad_sleep_mode_9_wd;
logic mio_pad_sleep_mode_10_we;
logic [1:0] mio_pad_sleep_mode_10_qs;
logic [1:0] mio_pad_sleep_mode_10_wd;
logic mio_pad_sleep_mode_11_we;
logic [1:0] mio_pad_sleep_mode_11_qs;
logic [1:0] mio_pad_sleep_mode_11_wd;
logic mio_pad_sleep_mode_12_we;
logic [1:0] mio_pad_sleep_mode_12_qs;
logic [1:0] mio_pad_sleep_mode_12_wd;
logic mio_pad_sleep_mode_13_we;
logic [1:0] mio_pad_sleep_mode_13_qs;
logic [1:0] mio_pad_sleep_mode_13_wd;
logic mio_pad_sleep_mode_14_we;
logic [1:0] mio_pad_sleep_mode_14_qs;
logic [1:0] mio_pad_sleep_mode_14_wd;
logic mio_pad_sleep_mode_15_we;
logic [1:0] mio_pad_sleep_mode_15_qs;
logic [1:0] mio_pad_sleep_mode_15_wd;
logic mio_pad_sleep_mode_16_we;
logic [1:0] mio_pad_sleep_mode_16_qs;
logic [1:0] mio_pad_sleep_mode_16_wd;
logic mio_pad_sleep_mode_17_we;
logic [1:0] mio_pad_sleep_mode_17_qs;
logic [1:0] mio_pad_sleep_mode_17_wd;
logic mio_pad_sleep_mode_18_we;
logic [1:0] mio_pad_sleep_mode_18_qs;
logic [1:0] mio_pad_sleep_mode_18_wd;
logic mio_pad_sleep_mode_19_we;
logic [1:0] mio_pad_sleep_mode_19_qs;
logic [1:0] mio_pad_sleep_mode_19_wd;
logic mio_pad_sleep_mode_20_we;
logic [1:0] mio_pad_sleep_mode_20_qs;
logic [1:0] mio_pad_sleep_mode_20_wd;
logic mio_pad_sleep_mode_21_we;
logic [1:0] mio_pad_sleep_mode_21_qs;
logic [1:0] mio_pad_sleep_mode_21_wd;
logic mio_pad_sleep_mode_22_we;
logic [1:0] mio_pad_sleep_mode_22_qs;
logic [1:0] mio_pad_sleep_mode_22_wd;
logic mio_pad_sleep_mode_23_we;
logic [1:0] mio_pad_sleep_mode_23_qs;
logic [1:0] mio_pad_sleep_mode_23_wd;
logic mio_pad_sleep_mode_24_we;
logic [1:0] mio_pad_sleep_mode_24_qs;
logic [1:0] mio_pad_sleep_mode_24_wd;
logic mio_pad_sleep_mode_25_we;
logic [1:0] mio_pad_sleep_mode_25_qs;
logic [1:0] mio_pad_sleep_mode_25_wd;
logic mio_pad_sleep_mode_26_we;
logic [1:0] mio_pad_sleep_mode_26_qs;
logic [1:0] mio_pad_sleep_mode_26_wd;
logic mio_pad_sleep_mode_27_we;
logic [1:0] mio_pad_sleep_mode_27_qs;
logic [1:0] mio_pad_sleep_mode_27_wd;
logic mio_pad_sleep_mode_28_we;
logic [1:0] mio_pad_sleep_mode_28_qs;
logic [1:0] mio_pad_sleep_mode_28_wd;
logic mio_pad_sleep_mode_29_we;
logic [1:0] mio_pad_sleep_mode_29_qs;
logic [1:0] mio_pad_sleep_mode_29_wd;
logic mio_pad_sleep_mode_30_we;
logic [1:0] mio_pad_sleep_mode_30_qs;
logic [1:0] mio_pad_sleep_mode_30_wd;
logic mio_pad_sleep_mode_31_we;
logic [1:0] mio_pad_sleep_mode_31_qs;
logic [1:0] mio_pad_sleep_mode_31_wd;
logic dio_pad_sleep_status_we;
logic dio_pad_sleep_status_en_0_qs;
logic dio_pad_sleep_status_en_0_wd;
logic dio_pad_sleep_status_en_1_qs;
logic dio_pad_sleep_status_en_1_wd;
logic dio_pad_sleep_status_en_2_qs;
logic dio_pad_sleep_status_en_2_wd;
logic dio_pad_sleep_status_en_3_qs;
logic dio_pad_sleep_status_en_3_wd;
logic dio_pad_sleep_status_en_4_qs;
logic dio_pad_sleep_status_en_4_wd;
logic dio_pad_sleep_status_en_5_qs;
logic dio_pad_sleep_status_en_5_wd;
logic dio_pad_sleep_status_en_6_qs;
logic dio_pad_sleep_status_en_6_wd;
logic dio_pad_sleep_status_en_7_qs;
logic dio_pad_sleep_status_en_7_wd;
logic dio_pad_sleep_status_en_8_qs;
logic dio_pad_sleep_status_en_8_wd;
logic dio_pad_sleep_status_en_9_qs;
logic dio_pad_sleep_status_en_9_wd;
logic dio_pad_sleep_status_en_10_qs;
logic dio_pad_sleep_status_en_10_wd;
logic dio_pad_sleep_status_en_11_qs;
logic dio_pad_sleep_status_en_11_wd;
logic dio_pad_sleep_status_en_12_qs;
logic dio_pad_sleep_status_en_12_wd;
logic dio_pad_sleep_status_en_13_qs;
logic dio_pad_sleep_status_en_13_wd;
logic dio_pad_sleep_status_en_14_qs;
logic dio_pad_sleep_status_en_14_wd;
logic dio_pad_sleep_status_en_15_qs;
logic dio_pad_sleep_status_en_15_wd;
logic dio_pad_sleep_regwen_0_we;
logic dio_pad_sleep_regwen_0_qs;
logic dio_pad_sleep_regwen_0_wd;
logic dio_pad_sleep_regwen_1_we;
logic dio_pad_sleep_regwen_1_qs;
logic dio_pad_sleep_regwen_1_wd;
logic dio_pad_sleep_regwen_2_we;
logic dio_pad_sleep_regwen_2_qs;
logic dio_pad_sleep_regwen_2_wd;
logic dio_pad_sleep_regwen_3_we;
logic dio_pad_sleep_regwen_3_qs;
logic dio_pad_sleep_regwen_3_wd;
logic dio_pad_sleep_regwen_4_we;
logic dio_pad_sleep_regwen_4_qs;
logic dio_pad_sleep_regwen_4_wd;
logic dio_pad_sleep_regwen_5_we;
logic dio_pad_sleep_regwen_5_qs;
logic dio_pad_sleep_regwen_5_wd;
logic dio_pad_sleep_regwen_6_we;
logic dio_pad_sleep_regwen_6_qs;
logic dio_pad_sleep_regwen_6_wd;
logic dio_pad_sleep_regwen_7_we;
logic dio_pad_sleep_regwen_7_qs;
logic dio_pad_sleep_regwen_7_wd;
logic dio_pad_sleep_regwen_8_we;
logic dio_pad_sleep_regwen_8_qs;
logic dio_pad_sleep_regwen_8_wd;
logic dio_pad_sleep_regwen_9_we;
logic dio_pad_sleep_regwen_9_qs;
logic dio_pad_sleep_regwen_9_wd;
logic dio_pad_sleep_regwen_10_we;
logic dio_pad_sleep_regwen_10_qs;
logic dio_pad_sleep_regwen_10_wd;
logic dio_pad_sleep_regwen_11_we;
logic dio_pad_sleep_regwen_11_qs;
logic dio_pad_sleep_regwen_11_wd;
logic dio_pad_sleep_regwen_12_we;
logic dio_pad_sleep_regwen_12_qs;
logic dio_pad_sleep_regwen_12_wd;
logic dio_pad_sleep_regwen_13_we;
logic dio_pad_sleep_regwen_13_qs;
logic dio_pad_sleep_regwen_13_wd;
logic dio_pad_sleep_regwen_14_we;
logic dio_pad_sleep_regwen_14_qs;
logic dio_pad_sleep_regwen_14_wd;
logic dio_pad_sleep_regwen_15_we;
logic dio_pad_sleep_regwen_15_qs;
logic dio_pad_sleep_regwen_15_wd;
logic dio_pad_sleep_en_0_we;
logic dio_pad_sleep_en_0_qs;
logic dio_pad_sleep_en_0_wd;
logic dio_pad_sleep_en_1_we;
logic dio_pad_sleep_en_1_qs;
logic dio_pad_sleep_en_1_wd;
logic dio_pad_sleep_en_2_we;
logic dio_pad_sleep_en_2_qs;
logic dio_pad_sleep_en_2_wd;
logic dio_pad_sleep_en_3_we;
logic dio_pad_sleep_en_3_qs;
logic dio_pad_sleep_en_3_wd;
logic dio_pad_sleep_en_4_we;
logic dio_pad_sleep_en_4_qs;
logic dio_pad_sleep_en_4_wd;
logic dio_pad_sleep_en_5_we;
logic dio_pad_sleep_en_5_qs;
logic dio_pad_sleep_en_5_wd;
logic dio_pad_sleep_en_6_we;
logic dio_pad_sleep_en_6_qs;
logic dio_pad_sleep_en_6_wd;
logic dio_pad_sleep_en_7_we;
logic dio_pad_sleep_en_7_qs;
logic dio_pad_sleep_en_7_wd;
logic dio_pad_sleep_en_8_we;
logic dio_pad_sleep_en_8_qs;
logic dio_pad_sleep_en_8_wd;
logic dio_pad_sleep_en_9_we;
logic dio_pad_sleep_en_9_qs;
logic dio_pad_sleep_en_9_wd;
logic dio_pad_sleep_en_10_we;
logic dio_pad_sleep_en_10_qs;
logic dio_pad_sleep_en_10_wd;
logic dio_pad_sleep_en_11_we;
logic dio_pad_sleep_en_11_qs;
logic dio_pad_sleep_en_11_wd;
logic dio_pad_sleep_en_12_we;
logic dio_pad_sleep_en_12_qs;
logic dio_pad_sleep_en_12_wd;
logic dio_pad_sleep_en_13_we;
logic dio_pad_sleep_en_13_qs;
logic dio_pad_sleep_en_13_wd;
logic dio_pad_sleep_en_14_we;
logic dio_pad_sleep_en_14_qs;
logic dio_pad_sleep_en_14_wd;
logic dio_pad_sleep_en_15_we;
logic dio_pad_sleep_en_15_qs;
logic dio_pad_sleep_en_15_wd;
logic dio_pad_sleep_mode_0_we;
logic [1:0] dio_pad_sleep_mode_0_qs;
logic [1:0] dio_pad_sleep_mode_0_wd;
logic dio_pad_sleep_mode_1_we;
logic [1:0] dio_pad_sleep_mode_1_qs;
logic [1:0] dio_pad_sleep_mode_1_wd;
logic dio_pad_sleep_mode_2_we;
logic [1:0] dio_pad_sleep_mode_2_qs;
logic [1:0] dio_pad_sleep_mode_2_wd;
logic dio_pad_sleep_mode_3_we;
logic [1:0] dio_pad_sleep_mode_3_qs;
logic [1:0] dio_pad_sleep_mode_3_wd;
logic dio_pad_sleep_mode_4_we;
logic [1:0] dio_pad_sleep_mode_4_qs;
logic [1:0] dio_pad_sleep_mode_4_wd;
logic dio_pad_sleep_mode_5_we;
logic [1:0] dio_pad_sleep_mode_5_qs;
logic [1:0] dio_pad_sleep_mode_5_wd;
logic dio_pad_sleep_mode_6_we;
logic [1:0] dio_pad_sleep_mode_6_qs;
logic [1:0] dio_pad_sleep_mode_6_wd;
logic dio_pad_sleep_mode_7_we;
logic [1:0] dio_pad_sleep_mode_7_qs;
logic [1:0] dio_pad_sleep_mode_7_wd;
logic dio_pad_sleep_mode_8_we;
logic [1:0] dio_pad_sleep_mode_8_qs;
logic [1:0] dio_pad_sleep_mode_8_wd;
logic dio_pad_sleep_mode_9_we;
logic [1:0] dio_pad_sleep_mode_9_qs;
logic [1:0] dio_pad_sleep_mode_9_wd;
logic dio_pad_sleep_mode_10_we;
logic [1:0] dio_pad_sleep_mode_10_qs;
logic [1:0] dio_pad_sleep_mode_10_wd;
logic dio_pad_sleep_mode_11_we;
logic [1:0] dio_pad_sleep_mode_11_qs;
logic [1:0] dio_pad_sleep_mode_11_wd;
logic dio_pad_sleep_mode_12_we;
logic [1:0] dio_pad_sleep_mode_12_qs;
logic [1:0] dio_pad_sleep_mode_12_wd;
logic dio_pad_sleep_mode_13_we;
logic [1:0] dio_pad_sleep_mode_13_qs;
logic [1:0] dio_pad_sleep_mode_13_wd;
logic dio_pad_sleep_mode_14_we;
logic [1:0] dio_pad_sleep_mode_14_qs;
logic [1:0] dio_pad_sleep_mode_14_wd;
logic dio_pad_sleep_mode_15_we;
logic [1:0] dio_pad_sleep_mode_15_qs;
logic [1:0] dio_pad_sleep_mode_15_wd;
logic wkup_detector_regwen_0_we;
logic wkup_detector_regwen_0_qs;
logic wkup_detector_regwen_0_wd;
logic wkup_detector_regwen_1_we;
logic wkup_detector_regwen_1_qs;
logic wkup_detector_regwen_1_wd;
logic wkup_detector_regwen_2_we;
logic wkup_detector_regwen_2_qs;
logic wkup_detector_regwen_2_wd;
logic wkup_detector_regwen_3_we;
logic wkup_detector_regwen_3_qs;
logic wkup_detector_regwen_3_wd;
logic wkup_detector_regwen_4_we;
logic wkup_detector_regwen_4_qs;
logic wkup_detector_regwen_4_wd;
logic wkup_detector_regwen_5_we;
logic wkup_detector_regwen_5_qs;
logic wkup_detector_regwen_5_wd;
logic wkup_detector_regwen_6_we;
logic wkup_detector_regwen_6_qs;
logic wkup_detector_regwen_6_wd;
logic wkup_detector_regwen_7_we;
logic wkup_detector_regwen_7_qs;
logic wkup_detector_regwen_7_wd;
logic wkup_detector_en_0_we;
logic [0:0] wkup_detector_en_0_qs;
logic wkup_detector_en_0_busy;
logic wkup_detector_en_1_we;
logic [0:0] wkup_detector_en_1_qs;
logic wkup_detector_en_1_busy;
logic wkup_detector_en_2_we;
logic [0:0] wkup_detector_en_2_qs;
logic wkup_detector_en_2_busy;
logic wkup_detector_en_3_we;
logic [0:0] wkup_detector_en_3_qs;
logic wkup_detector_en_3_busy;
logic wkup_detector_en_4_we;
logic [0:0] wkup_detector_en_4_qs;
logic wkup_detector_en_4_busy;
logic wkup_detector_en_5_we;
logic [0:0] wkup_detector_en_5_qs;
logic wkup_detector_en_5_busy;
logic wkup_detector_en_6_we;
logic [0:0] wkup_detector_en_6_qs;
logic wkup_detector_en_6_busy;
logic wkup_detector_en_7_we;
logic [0:0] wkup_detector_en_7_qs;
logic wkup_detector_en_7_busy;
logic wkup_detector_0_we;
logic [4:0] wkup_detector_0_qs;
logic wkup_detector_0_busy;
logic wkup_detector_1_we;
logic [4:0] wkup_detector_1_qs;
logic wkup_detector_1_busy;
logic wkup_detector_2_we;
logic [4:0] wkup_detector_2_qs;
logic wkup_detector_2_busy;
logic wkup_detector_3_we;
logic [4:0] wkup_detector_3_qs;
logic wkup_detector_3_busy;
logic wkup_detector_4_we;
logic [4:0] wkup_detector_4_qs;
logic wkup_detector_4_busy;
logic wkup_detector_5_we;
logic [4:0] wkup_detector_5_qs;
logic wkup_detector_5_busy;
logic wkup_detector_6_we;
logic [4:0] wkup_detector_6_qs;
logic wkup_detector_6_busy;
logic wkup_detector_7_we;
logic [4:0] wkup_detector_7_qs;
logic wkup_detector_7_busy;
logic wkup_detector_cnt_th_0_we;
logic [7:0] wkup_detector_cnt_th_0_qs;
logic wkup_detector_cnt_th_0_busy;
logic wkup_detector_cnt_th_1_we;
logic [7:0] wkup_detector_cnt_th_1_qs;
logic wkup_detector_cnt_th_1_busy;
logic wkup_detector_cnt_th_2_we;
logic [7:0] wkup_detector_cnt_th_2_qs;
logic wkup_detector_cnt_th_2_busy;
logic wkup_detector_cnt_th_3_we;
logic [7:0] wkup_detector_cnt_th_3_qs;
logic wkup_detector_cnt_th_3_busy;
logic wkup_detector_cnt_th_4_we;
logic [7:0] wkup_detector_cnt_th_4_qs;
logic wkup_detector_cnt_th_4_busy;
logic wkup_detector_cnt_th_5_we;
logic [7:0] wkup_detector_cnt_th_5_qs;
logic wkup_detector_cnt_th_5_busy;
logic wkup_detector_cnt_th_6_we;
logic [7:0] wkup_detector_cnt_th_6_qs;
logic wkup_detector_cnt_th_6_busy;
logic wkup_detector_cnt_th_7_we;
logic [7:0] wkup_detector_cnt_th_7_qs;
logic wkup_detector_cnt_th_7_busy;
logic wkup_detector_padsel_0_we;
logic [5:0] wkup_detector_padsel_0_qs;
logic [5:0] wkup_detector_padsel_0_wd;
logic wkup_detector_padsel_1_we;
logic [5:0] wkup_detector_padsel_1_qs;
logic [5:0] wkup_detector_padsel_1_wd;
logic wkup_detector_padsel_2_we;
logic [5:0] wkup_detector_padsel_2_qs;
logic [5:0] wkup_detector_padsel_2_wd;
logic wkup_detector_padsel_3_we;
logic [5:0] wkup_detector_padsel_3_qs;
logic [5:0] wkup_detector_padsel_3_wd;
logic wkup_detector_padsel_4_we;
logic [5:0] wkup_detector_padsel_4_qs;
logic [5:0] wkup_detector_padsel_4_wd;
logic wkup_detector_padsel_5_we;
logic [5:0] wkup_detector_padsel_5_qs;
logic [5:0] wkup_detector_padsel_5_wd;
logic wkup_detector_padsel_6_we;
logic [5:0] wkup_detector_padsel_6_qs;
logic [5:0] wkup_detector_padsel_6_wd;
logic wkup_detector_padsel_7_we;
logic [5:0] wkup_detector_padsel_7_qs;
logic [5:0] wkup_detector_padsel_7_wd;
logic wkup_cause_we;
logic [7:0] wkup_cause_qs;
logic wkup_cause_busy;
// Define register CDC handling.
// CDC handling is done on a per-reg instead of per-field boundary.
logic aon_wkup_detector_en_0_qs_int;
logic [0:0] aon_wkup_detector_en_0_qs;
logic [0:0] aon_wkup_detector_en_0_wdata;
logic aon_wkup_detector_en_0_we;
logic unused_aon_wkup_detector_en_0_wdata;
logic aon_wkup_detector_en_0_regwen;
always_comb begin
aon_wkup_detector_en_0_qs = 1'h0;
aon_wkup_detector_en_0_qs = aon_wkup_detector_en_0_qs_int;
end
prim_reg_cdc #(
.DataWidth(1),
.ResetVal(1'h0),
.BitMask(1'h1),
.DstWrReq(0)
) u_wkup_detector_en_0_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_0_qs),
.src_we_i (wkup_detector_en_0_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[0:0]),
.src_busy_o (wkup_detector_en_0_busy),
.src_qs_o (wkup_detector_en_0_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_en_0_qs),
.dst_we_o (aon_wkup_detector_en_0_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_en_0_regwen),
.dst_wd_o (aon_wkup_detector_en_0_wdata)
);
assign unused_aon_wkup_detector_en_0_wdata =
^aon_wkup_detector_en_0_wdata;
logic aon_wkup_detector_en_1_qs_int;
logic [0:0] aon_wkup_detector_en_1_qs;
logic [0:0] aon_wkup_detector_en_1_wdata;
logic aon_wkup_detector_en_1_we;
logic unused_aon_wkup_detector_en_1_wdata;
logic aon_wkup_detector_en_1_regwen;
always_comb begin
aon_wkup_detector_en_1_qs = 1'h0;
aon_wkup_detector_en_1_qs = aon_wkup_detector_en_1_qs_int;
end
prim_reg_cdc #(
.DataWidth(1),
.ResetVal(1'h0),
.BitMask(1'h1),
.DstWrReq(0)
) u_wkup_detector_en_1_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_1_qs),
.src_we_i (wkup_detector_en_1_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[0:0]),
.src_busy_o (wkup_detector_en_1_busy),
.src_qs_o (wkup_detector_en_1_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_en_1_qs),
.dst_we_o (aon_wkup_detector_en_1_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_en_1_regwen),
.dst_wd_o (aon_wkup_detector_en_1_wdata)
);
assign unused_aon_wkup_detector_en_1_wdata =
^aon_wkup_detector_en_1_wdata;
logic aon_wkup_detector_en_2_qs_int;
logic [0:0] aon_wkup_detector_en_2_qs;
logic [0:0] aon_wkup_detector_en_2_wdata;
logic aon_wkup_detector_en_2_we;
logic unused_aon_wkup_detector_en_2_wdata;
logic aon_wkup_detector_en_2_regwen;
always_comb begin
aon_wkup_detector_en_2_qs = 1'h0;
aon_wkup_detector_en_2_qs = aon_wkup_detector_en_2_qs_int;
end
prim_reg_cdc #(
.DataWidth(1),
.ResetVal(1'h0),
.BitMask(1'h1),
.DstWrReq(0)
) u_wkup_detector_en_2_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_2_qs),
.src_we_i (wkup_detector_en_2_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[0:0]),
.src_busy_o (wkup_detector_en_2_busy),
.src_qs_o (wkup_detector_en_2_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_en_2_qs),
.dst_we_o (aon_wkup_detector_en_2_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_en_2_regwen),
.dst_wd_o (aon_wkup_detector_en_2_wdata)
);
assign unused_aon_wkup_detector_en_2_wdata =
^aon_wkup_detector_en_2_wdata;
logic aon_wkup_detector_en_3_qs_int;
logic [0:0] aon_wkup_detector_en_3_qs;
logic [0:0] aon_wkup_detector_en_3_wdata;
logic aon_wkup_detector_en_3_we;
logic unused_aon_wkup_detector_en_3_wdata;
logic aon_wkup_detector_en_3_regwen;
always_comb begin
aon_wkup_detector_en_3_qs = 1'h0;
aon_wkup_detector_en_3_qs = aon_wkup_detector_en_3_qs_int;
end
prim_reg_cdc #(
.DataWidth(1),
.ResetVal(1'h0),
.BitMask(1'h1),
.DstWrReq(0)
) u_wkup_detector_en_3_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_3_qs),
.src_we_i (wkup_detector_en_3_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[0:0]),
.src_busy_o (wkup_detector_en_3_busy),
.src_qs_o (wkup_detector_en_3_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_en_3_qs),
.dst_we_o (aon_wkup_detector_en_3_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_en_3_regwen),
.dst_wd_o (aon_wkup_detector_en_3_wdata)
);
assign unused_aon_wkup_detector_en_3_wdata =
^aon_wkup_detector_en_3_wdata;
logic aon_wkup_detector_en_4_qs_int;
logic [0:0] aon_wkup_detector_en_4_qs;
logic [0:0] aon_wkup_detector_en_4_wdata;
logic aon_wkup_detector_en_4_we;
logic unused_aon_wkup_detector_en_4_wdata;
logic aon_wkup_detector_en_4_regwen;
always_comb begin
aon_wkup_detector_en_4_qs = 1'h0;
aon_wkup_detector_en_4_qs = aon_wkup_detector_en_4_qs_int;
end
prim_reg_cdc #(
.DataWidth(1),
.ResetVal(1'h0),
.BitMask(1'h1),
.DstWrReq(0)
) u_wkup_detector_en_4_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_4_qs),
.src_we_i (wkup_detector_en_4_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[0:0]),
.src_busy_o (wkup_detector_en_4_busy),
.src_qs_o (wkup_detector_en_4_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_en_4_qs),
.dst_we_o (aon_wkup_detector_en_4_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_en_4_regwen),
.dst_wd_o (aon_wkup_detector_en_4_wdata)
);
assign unused_aon_wkup_detector_en_4_wdata =
^aon_wkup_detector_en_4_wdata;
logic aon_wkup_detector_en_5_qs_int;
logic [0:0] aon_wkup_detector_en_5_qs;
logic [0:0] aon_wkup_detector_en_5_wdata;
logic aon_wkup_detector_en_5_we;
logic unused_aon_wkup_detector_en_5_wdata;
logic aon_wkup_detector_en_5_regwen;
always_comb begin
aon_wkup_detector_en_5_qs = 1'h0;
aon_wkup_detector_en_5_qs = aon_wkup_detector_en_5_qs_int;
end
prim_reg_cdc #(
.DataWidth(1),
.ResetVal(1'h0),
.BitMask(1'h1),
.DstWrReq(0)
) u_wkup_detector_en_5_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_5_qs),
.src_we_i (wkup_detector_en_5_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[0:0]),
.src_busy_o (wkup_detector_en_5_busy),
.src_qs_o (wkup_detector_en_5_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_en_5_qs),
.dst_we_o (aon_wkup_detector_en_5_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_en_5_regwen),
.dst_wd_o (aon_wkup_detector_en_5_wdata)
);
assign unused_aon_wkup_detector_en_5_wdata =
^aon_wkup_detector_en_5_wdata;
logic aon_wkup_detector_en_6_qs_int;
logic [0:0] aon_wkup_detector_en_6_qs;
logic [0:0] aon_wkup_detector_en_6_wdata;
logic aon_wkup_detector_en_6_we;
logic unused_aon_wkup_detector_en_6_wdata;
logic aon_wkup_detector_en_6_regwen;
always_comb begin
aon_wkup_detector_en_6_qs = 1'h0;
aon_wkup_detector_en_6_qs = aon_wkup_detector_en_6_qs_int;
end
prim_reg_cdc #(
.DataWidth(1),
.ResetVal(1'h0),
.BitMask(1'h1),
.DstWrReq(0)
) u_wkup_detector_en_6_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_6_qs),
.src_we_i (wkup_detector_en_6_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[0:0]),
.src_busy_o (wkup_detector_en_6_busy),
.src_qs_o (wkup_detector_en_6_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_en_6_qs),
.dst_we_o (aon_wkup_detector_en_6_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_en_6_regwen),
.dst_wd_o (aon_wkup_detector_en_6_wdata)
);
assign unused_aon_wkup_detector_en_6_wdata =
^aon_wkup_detector_en_6_wdata;
logic aon_wkup_detector_en_7_qs_int;
logic [0:0] aon_wkup_detector_en_7_qs;
logic [0:0] aon_wkup_detector_en_7_wdata;
logic aon_wkup_detector_en_7_we;
logic unused_aon_wkup_detector_en_7_wdata;
logic aon_wkup_detector_en_7_regwen;
always_comb begin
aon_wkup_detector_en_7_qs = 1'h0;
aon_wkup_detector_en_7_qs = aon_wkup_detector_en_7_qs_int;
end
prim_reg_cdc #(
.DataWidth(1),
.ResetVal(1'h0),
.BitMask(1'h1),
.DstWrReq(0)
) u_wkup_detector_en_7_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_7_qs),
.src_we_i (wkup_detector_en_7_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[0:0]),
.src_busy_o (wkup_detector_en_7_busy),
.src_qs_o (wkup_detector_en_7_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_en_7_qs),
.dst_we_o (aon_wkup_detector_en_7_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_en_7_regwen),
.dst_wd_o (aon_wkup_detector_en_7_wdata)
);
assign unused_aon_wkup_detector_en_7_wdata =
^aon_wkup_detector_en_7_wdata;
logic [2:0] aon_wkup_detector_0_mode_0_qs_int;
logic aon_wkup_detector_0_filter_0_qs_int;
logic aon_wkup_detector_0_miodio_0_qs_int;
logic [4:0] aon_wkup_detector_0_qs;
logic [4:0] aon_wkup_detector_0_wdata;
logic aon_wkup_detector_0_we;
logic unused_aon_wkup_detector_0_wdata;
logic aon_wkup_detector_0_regwen;
always_comb begin
aon_wkup_detector_0_qs = 5'h0;
aon_wkup_detector_0_qs[2:0] = aon_wkup_detector_0_mode_0_qs_int;
aon_wkup_detector_0_qs[3] = aon_wkup_detector_0_filter_0_qs_int;
aon_wkup_detector_0_qs[4] = aon_wkup_detector_0_miodio_0_qs_int;
end
prim_reg_cdc #(
.DataWidth(5),
.ResetVal(5'h0),
.BitMask(5'h1f),
.DstWrReq(0)
) u_wkup_detector_0_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_0_qs),
.src_we_i (wkup_detector_0_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[4:0]),
.src_busy_o (wkup_detector_0_busy),
.src_qs_o (wkup_detector_0_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_0_qs),
.dst_we_o (aon_wkup_detector_0_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_0_regwen),
.dst_wd_o (aon_wkup_detector_0_wdata)
);
assign unused_aon_wkup_detector_0_wdata =
^aon_wkup_detector_0_wdata;
logic [2:0] aon_wkup_detector_1_mode_1_qs_int;
logic aon_wkup_detector_1_filter_1_qs_int;
logic aon_wkup_detector_1_miodio_1_qs_int;
logic [4:0] aon_wkup_detector_1_qs;
logic [4:0] aon_wkup_detector_1_wdata;
logic aon_wkup_detector_1_we;
logic unused_aon_wkup_detector_1_wdata;
logic aon_wkup_detector_1_regwen;
always_comb begin
aon_wkup_detector_1_qs = 5'h0;
aon_wkup_detector_1_qs[2:0] = aon_wkup_detector_1_mode_1_qs_int;
aon_wkup_detector_1_qs[3] = aon_wkup_detector_1_filter_1_qs_int;
aon_wkup_detector_1_qs[4] = aon_wkup_detector_1_miodio_1_qs_int;
end
prim_reg_cdc #(
.DataWidth(5),
.ResetVal(5'h0),
.BitMask(5'h1f),
.DstWrReq(0)
) u_wkup_detector_1_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_1_qs),
.src_we_i (wkup_detector_1_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[4:0]),
.src_busy_o (wkup_detector_1_busy),
.src_qs_o (wkup_detector_1_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_1_qs),
.dst_we_o (aon_wkup_detector_1_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_1_regwen),
.dst_wd_o (aon_wkup_detector_1_wdata)
);
assign unused_aon_wkup_detector_1_wdata =
^aon_wkup_detector_1_wdata;
logic [2:0] aon_wkup_detector_2_mode_2_qs_int;
logic aon_wkup_detector_2_filter_2_qs_int;
logic aon_wkup_detector_2_miodio_2_qs_int;
logic [4:0] aon_wkup_detector_2_qs;
logic [4:0] aon_wkup_detector_2_wdata;
logic aon_wkup_detector_2_we;
logic unused_aon_wkup_detector_2_wdata;
logic aon_wkup_detector_2_regwen;
always_comb begin
aon_wkup_detector_2_qs = 5'h0;
aon_wkup_detector_2_qs[2:0] = aon_wkup_detector_2_mode_2_qs_int;
aon_wkup_detector_2_qs[3] = aon_wkup_detector_2_filter_2_qs_int;
aon_wkup_detector_2_qs[4] = aon_wkup_detector_2_miodio_2_qs_int;
end
prim_reg_cdc #(
.DataWidth(5),
.ResetVal(5'h0),
.BitMask(5'h1f),
.DstWrReq(0)
) u_wkup_detector_2_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_2_qs),
.src_we_i (wkup_detector_2_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[4:0]),
.src_busy_o (wkup_detector_2_busy),
.src_qs_o (wkup_detector_2_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_2_qs),
.dst_we_o (aon_wkup_detector_2_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_2_regwen),
.dst_wd_o (aon_wkup_detector_2_wdata)
);
assign unused_aon_wkup_detector_2_wdata =
^aon_wkup_detector_2_wdata;
logic [2:0] aon_wkup_detector_3_mode_3_qs_int;
logic aon_wkup_detector_3_filter_3_qs_int;
logic aon_wkup_detector_3_miodio_3_qs_int;
logic [4:0] aon_wkup_detector_3_qs;
logic [4:0] aon_wkup_detector_3_wdata;
logic aon_wkup_detector_3_we;
logic unused_aon_wkup_detector_3_wdata;
logic aon_wkup_detector_3_regwen;
always_comb begin
aon_wkup_detector_3_qs = 5'h0;
aon_wkup_detector_3_qs[2:0] = aon_wkup_detector_3_mode_3_qs_int;
aon_wkup_detector_3_qs[3] = aon_wkup_detector_3_filter_3_qs_int;
aon_wkup_detector_3_qs[4] = aon_wkup_detector_3_miodio_3_qs_int;
end
prim_reg_cdc #(
.DataWidth(5),
.ResetVal(5'h0),
.BitMask(5'h1f),
.DstWrReq(0)
) u_wkup_detector_3_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_3_qs),
.src_we_i (wkup_detector_3_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[4:0]),
.src_busy_o (wkup_detector_3_busy),
.src_qs_o (wkup_detector_3_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_3_qs),
.dst_we_o (aon_wkup_detector_3_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_3_regwen),
.dst_wd_o (aon_wkup_detector_3_wdata)
);
assign unused_aon_wkup_detector_3_wdata =
^aon_wkup_detector_3_wdata;
logic [2:0] aon_wkup_detector_4_mode_4_qs_int;
logic aon_wkup_detector_4_filter_4_qs_int;
logic aon_wkup_detector_4_miodio_4_qs_int;
logic [4:0] aon_wkup_detector_4_qs;
logic [4:0] aon_wkup_detector_4_wdata;
logic aon_wkup_detector_4_we;
logic unused_aon_wkup_detector_4_wdata;
logic aon_wkup_detector_4_regwen;
always_comb begin
aon_wkup_detector_4_qs = 5'h0;
aon_wkup_detector_4_qs[2:0] = aon_wkup_detector_4_mode_4_qs_int;
aon_wkup_detector_4_qs[3] = aon_wkup_detector_4_filter_4_qs_int;
aon_wkup_detector_4_qs[4] = aon_wkup_detector_4_miodio_4_qs_int;
end
prim_reg_cdc #(
.DataWidth(5),
.ResetVal(5'h0),
.BitMask(5'h1f),
.DstWrReq(0)
) u_wkup_detector_4_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_4_qs),
.src_we_i (wkup_detector_4_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[4:0]),
.src_busy_o (wkup_detector_4_busy),
.src_qs_o (wkup_detector_4_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_4_qs),
.dst_we_o (aon_wkup_detector_4_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_4_regwen),
.dst_wd_o (aon_wkup_detector_4_wdata)
);
assign unused_aon_wkup_detector_4_wdata =
^aon_wkup_detector_4_wdata;
logic [2:0] aon_wkup_detector_5_mode_5_qs_int;
logic aon_wkup_detector_5_filter_5_qs_int;
logic aon_wkup_detector_5_miodio_5_qs_int;
logic [4:0] aon_wkup_detector_5_qs;
logic [4:0] aon_wkup_detector_5_wdata;
logic aon_wkup_detector_5_we;
logic unused_aon_wkup_detector_5_wdata;
logic aon_wkup_detector_5_regwen;
always_comb begin
aon_wkup_detector_5_qs = 5'h0;
aon_wkup_detector_5_qs[2:0] = aon_wkup_detector_5_mode_5_qs_int;
aon_wkup_detector_5_qs[3] = aon_wkup_detector_5_filter_5_qs_int;
aon_wkup_detector_5_qs[4] = aon_wkup_detector_5_miodio_5_qs_int;
end
prim_reg_cdc #(
.DataWidth(5),
.ResetVal(5'h0),
.BitMask(5'h1f),
.DstWrReq(0)
) u_wkup_detector_5_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_5_qs),
.src_we_i (wkup_detector_5_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[4:0]),
.src_busy_o (wkup_detector_5_busy),
.src_qs_o (wkup_detector_5_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_5_qs),
.dst_we_o (aon_wkup_detector_5_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_5_regwen),
.dst_wd_o (aon_wkup_detector_5_wdata)
);
assign unused_aon_wkup_detector_5_wdata =
^aon_wkup_detector_5_wdata;
logic [2:0] aon_wkup_detector_6_mode_6_qs_int;
logic aon_wkup_detector_6_filter_6_qs_int;
logic aon_wkup_detector_6_miodio_6_qs_int;
logic [4:0] aon_wkup_detector_6_qs;
logic [4:0] aon_wkup_detector_6_wdata;
logic aon_wkup_detector_6_we;
logic unused_aon_wkup_detector_6_wdata;
logic aon_wkup_detector_6_regwen;
always_comb begin
aon_wkup_detector_6_qs = 5'h0;
aon_wkup_detector_6_qs[2:0] = aon_wkup_detector_6_mode_6_qs_int;
aon_wkup_detector_6_qs[3] = aon_wkup_detector_6_filter_6_qs_int;
aon_wkup_detector_6_qs[4] = aon_wkup_detector_6_miodio_6_qs_int;
end
prim_reg_cdc #(
.DataWidth(5),
.ResetVal(5'h0),
.BitMask(5'h1f),
.DstWrReq(0)
) u_wkup_detector_6_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_6_qs),
.src_we_i (wkup_detector_6_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[4:0]),
.src_busy_o (wkup_detector_6_busy),
.src_qs_o (wkup_detector_6_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_6_qs),
.dst_we_o (aon_wkup_detector_6_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_6_regwen),
.dst_wd_o (aon_wkup_detector_6_wdata)
);
assign unused_aon_wkup_detector_6_wdata =
^aon_wkup_detector_6_wdata;
logic [2:0] aon_wkup_detector_7_mode_7_qs_int;
logic aon_wkup_detector_7_filter_7_qs_int;
logic aon_wkup_detector_7_miodio_7_qs_int;
logic [4:0] aon_wkup_detector_7_qs;
logic [4:0] aon_wkup_detector_7_wdata;
logic aon_wkup_detector_7_we;
logic unused_aon_wkup_detector_7_wdata;
logic aon_wkup_detector_7_regwen;
always_comb begin
aon_wkup_detector_7_qs = 5'h0;
aon_wkup_detector_7_qs[2:0] = aon_wkup_detector_7_mode_7_qs_int;
aon_wkup_detector_7_qs[3] = aon_wkup_detector_7_filter_7_qs_int;
aon_wkup_detector_7_qs[4] = aon_wkup_detector_7_miodio_7_qs_int;
end
prim_reg_cdc #(
.DataWidth(5),
.ResetVal(5'h0),
.BitMask(5'h1f),
.DstWrReq(0)
) u_wkup_detector_7_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_7_qs),
.src_we_i (wkup_detector_7_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[4:0]),
.src_busy_o (wkup_detector_7_busy),
.src_qs_o (wkup_detector_7_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_7_qs),
.dst_we_o (aon_wkup_detector_7_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_7_regwen),
.dst_wd_o (aon_wkup_detector_7_wdata)
);
assign unused_aon_wkup_detector_7_wdata =
^aon_wkup_detector_7_wdata;
logic [7:0] aon_wkup_detector_cnt_th_0_qs_int;
logic [7:0] aon_wkup_detector_cnt_th_0_qs;
logic [7:0] aon_wkup_detector_cnt_th_0_wdata;
logic aon_wkup_detector_cnt_th_0_we;
logic unused_aon_wkup_detector_cnt_th_0_wdata;
logic aon_wkup_detector_cnt_th_0_regwen;
always_comb begin
aon_wkup_detector_cnt_th_0_qs = 8'h0;
aon_wkup_detector_cnt_th_0_qs = aon_wkup_detector_cnt_th_0_qs_int;
end
prim_reg_cdc #(
.DataWidth(8),
.ResetVal(8'h0),
.BitMask(8'hff),
.DstWrReq(0)
) u_wkup_detector_cnt_th_0_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_0_qs),
.src_we_i (wkup_detector_cnt_th_0_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[7:0]),
.src_busy_o (wkup_detector_cnt_th_0_busy),
.src_qs_o (wkup_detector_cnt_th_0_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_cnt_th_0_qs),
.dst_we_o (aon_wkup_detector_cnt_th_0_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_cnt_th_0_regwen),
.dst_wd_o (aon_wkup_detector_cnt_th_0_wdata)
);
assign unused_aon_wkup_detector_cnt_th_0_wdata =
^aon_wkup_detector_cnt_th_0_wdata;
logic [7:0] aon_wkup_detector_cnt_th_1_qs_int;
logic [7:0] aon_wkup_detector_cnt_th_1_qs;
logic [7:0] aon_wkup_detector_cnt_th_1_wdata;
logic aon_wkup_detector_cnt_th_1_we;
logic unused_aon_wkup_detector_cnt_th_1_wdata;
logic aon_wkup_detector_cnt_th_1_regwen;
always_comb begin
aon_wkup_detector_cnt_th_1_qs = 8'h0;
aon_wkup_detector_cnt_th_1_qs = aon_wkup_detector_cnt_th_1_qs_int;
end
prim_reg_cdc #(
.DataWidth(8),
.ResetVal(8'h0),
.BitMask(8'hff),
.DstWrReq(0)
) u_wkup_detector_cnt_th_1_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_1_qs),
.src_we_i (wkup_detector_cnt_th_1_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[7:0]),
.src_busy_o (wkup_detector_cnt_th_1_busy),
.src_qs_o (wkup_detector_cnt_th_1_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_cnt_th_1_qs),
.dst_we_o (aon_wkup_detector_cnt_th_1_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_cnt_th_1_regwen),
.dst_wd_o (aon_wkup_detector_cnt_th_1_wdata)
);
assign unused_aon_wkup_detector_cnt_th_1_wdata =
^aon_wkup_detector_cnt_th_1_wdata;
logic [7:0] aon_wkup_detector_cnt_th_2_qs_int;
logic [7:0] aon_wkup_detector_cnt_th_2_qs;
logic [7:0] aon_wkup_detector_cnt_th_2_wdata;
logic aon_wkup_detector_cnt_th_2_we;
logic unused_aon_wkup_detector_cnt_th_2_wdata;
logic aon_wkup_detector_cnt_th_2_regwen;
always_comb begin
aon_wkup_detector_cnt_th_2_qs = 8'h0;
aon_wkup_detector_cnt_th_2_qs = aon_wkup_detector_cnt_th_2_qs_int;
end
prim_reg_cdc #(
.DataWidth(8),
.ResetVal(8'h0),
.BitMask(8'hff),
.DstWrReq(0)
) u_wkup_detector_cnt_th_2_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_2_qs),
.src_we_i (wkup_detector_cnt_th_2_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[7:0]),
.src_busy_o (wkup_detector_cnt_th_2_busy),
.src_qs_o (wkup_detector_cnt_th_2_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_cnt_th_2_qs),
.dst_we_o (aon_wkup_detector_cnt_th_2_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_cnt_th_2_regwen),
.dst_wd_o (aon_wkup_detector_cnt_th_2_wdata)
);
assign unused_aon_wkup_detector_cnt_th_2_wdata =
^aon_wkup_detector_cnt_th_2_wdata;
logic [7:0] aon_wkup_detector_cnt_th_3_qs_int;
logic [7:0] aon_wkup_detector_cnt_th_3_qs;
logic [7:0] aon_wkup_detector_cnt_th_3_wdata;
logic aon_wkup_detector_cnt_th_3_we;
logic unused_aon_wkup_detector_cnt_th_3_wdata;
logic aon_wkup_detector_cnt_th_3_regwen;
always_comb begin
aon_wkup_detector_cnt_th_3_qs = 8'h0;
aon_wkup_detector_cnt_th_3_qs = aon_wkup_detector_cnt_th_3_qs_int;
end
prim_reg_cdc #(
.DataWidth(8),
.ResetVal(8'h0),
.BitMask(8'hff),
.DstWrReq(0)
) u_wkup_detector_cnt_th_3_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_3_qs),
.src_we_i (wkup_detector_cnt_th_3_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[7:0]),
.src_busy_o (wkup_detector_cnt_th_3_busy),
.src_qs_o (wkup_detector_cnt_th_3_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_cnt_th_3_qs),
.dst_we_o (aon_wkup_detector_cnt_th_3_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_cnt_th_3_regwen),
.dst_wd_o (aon_wkup_detector_cnt_th_3_wdata)
);
assign unused_aon_wkup_detector_cnt_th_3_wdata =
^aon_wkup_detector_cnt_th_3_wdata;
logic [7:0] aon_wkup_detector_cnt_th_4_qs_int;
logic [7:0] aon_wkup_detector_cnt_th_4_qs;
logic [7:0] aon_wkup_detector_cnt_th_4_wdata;
logic aon_wkup_detector_cnt_th_4_we;
logic unused_aon_wkup_detector_cnt_th_4_wdata;
logic aon_wkup_detector_cnt_th_4_regwen;
always_comb begin
aon_wkup_detector_cnt_th_4_qs = 8'h0;
aon_wkup_detector_cnt_th_4_qs = aon_wkup_detector_cnt_th_4_qs_int;
end
prim_reg_cdc #(
.DataWidth(8),
.ResetVal(8'h0),
.BitMask(8'hff),
.DstWrReq(0)
) u_wkup_detector_cnt_th_4_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_4_qs),
.src_we_i (wkup_detector_cnt_th_4_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[7:0]),
.src_busy_o (wkup_detector_cnt_th_4_busy),
.src_qs_o (wkup_detector_cnt_th_4_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_cnt_th_4_qs),
.dst_we_o (aon_wkup_detector_cnt_th_4_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_cnt_th_4_regwen),
.dst_wd_o (aon_wkup_detector_cnt_th_4_wdata)
);
assign unused_aon_wkup_detector_cnt_th_4_wdata =
^aon_wkup_detector_cnt_th_4_wdata;
logic [7:0] aon_wkup_detector_cnt_th_5_qs_int;
logic [7:0] aon_wkup_detector_cnt_th_5_qs;
logic [7:0] aon_wkup_detector_cnt_th_5_wdata;
logic aon_wkup_detector_cnt_th_5_we;
logic unused_aon_wkup_detector_cnt_th_5_wdata;
logic aon_wkup_detector_cnt_th_5_regwen;
always_comb begin
aon_wkup_detector_cnt_th_5_qs = 8'h0;
aon_wkup_detector_cnt_th_5_qs = aon_wkup_detector_cnt_th_5_qs_int;
end
prim_reg_cdc #(
.DataWidth(8),
.ResetVal(8'h0),
.BitMask(8'hff),
.DstWrReq(0)
) u_wkup_detector_cnt_th_5_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_5_qs),
.src_we_i (wkup_detector_cnt_th_5_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[7:0]),
.src_busy_o (wkup_detector_cnt_th_5_busy),
.src_qs_o (wkup_detector_cnt_th_5_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_cnt_th_5_qs),
.dst_we_o (aon_wkup_detector_cnt_th_5_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_cnt_th_5_regwen),
.dst_wd_o (aon_wkup_detector_cnt_th_5_wdata)
);
assign unused_aon_wkup_detector_cnt_th_5_wdata =
^aon_wkup_detector_cnt_th_5_wdata;
logic [7:0] aon_wkup_detector_cnt_th_6_qs_int;
logic [7:0] aon_wkup_detector_cnt_th_6_qs;
logic [7:0] aon_wkup_detector_cnt_th_6_wdata;
logic aon_wkup_detector_cnt_th_6_we;
logic unused_aon_wkup_detector_cnt_th_6_wdata;
logic aon_wkup_detector_cnt_th_6_regwen;
always_comb begin
aon_wkup_detector_cnt_th_6_qs = 8'h0;
aon_wkup_detector_cnt_th_6_qs = aon_wkup_detector_cnt_th_6_qs_int;
end
prim_reg_cdc #(
.DataWidth(8),
.ResetVal(8'h0),
.BitMask(8'hff),
.DstWrReq(0)
) u_wkup_detector_cnt_th_6_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_6_qs),
.src_we_i (wkup_detector_cnt_th_6_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[7:0]),
.src_busy_o (wkup_detector_cnt_th_6_busy),
.src_qs_o (wkup_detector_cnt_th_6_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_cnt_th_6_qs),
.dst_we_o (aon_wkup_detector_cnt_th_6_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_cnt_th_6_regwen),
.dst_wd_o (aon_wkup_detector_cnt_th_6_wdata)
);
assign unused_aon_wkup_detector_cnt_th_6_wdata =
^aon_wkup_detector_cnt_th_6_wdata;
logic [7:0] aon_wkup_detector_cnt_th_7_qs_int;
logic [7:0] aon_wkup_detector_cnt_th_7_qs;
logic [7:0] aon_wkup_detector_cnt_th_7_wdata;
logic aon_wkup_detector_cnt_th_7_we;
logic unused_aon_wkup_detector_cnt_th_7_wdata;
logic aon_wkup_detector_cnt_th_7_regwen;
always_comb begin
aon_wkup_detector_cnt_th_7_qs = 8'h0;
aon_wkup_detector_cnt_th_7_qs = aon_wkup_detector_cnt_th_7_qs_int;
end
prim_reg_cdc #(
.DataWidth(8),
.ResetVal(8'h0),
.BitMask(8'hff),
.DstWrReq(0)
) u_wkup_detector_cnt_th_7_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i (wkup_detector_regwen_7_qs),
.src_we_i (wkup_detector_cnt_th_7_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[7:0]),
.src_busy_o (wkup_detector_cnt_th_7_busy),
.src_qs_o (wkup_detector_cnt_th_7_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (aon_wkup_detector_cnt_th_7_qs),
.dst_we_o (aon_wkup_detector_cnt_th_7_we),
.dst_re_o (),
.dst_regwen_o (aon_wkup_detector_cnt_th_7_regwen),
.dst_wd_o (aon_wkup_detector_cnt_th_7_wdata)
);
assign unused_aon_wkup_detector_cnt_th_7_wdata =
^aon_wkup_detector_cnt_th_7_wdata;
logic aon_wkup_cause_cause_0_ds_int;
logic aon_wkup_cause_cause_0_qs_int;
logic aon_wkup_cause_cause_1_ds_int;
logic aon_wkup_cause_cause_1_qs_int;
logic aon_wkup_cause_cause_2_ds_int;
logic aon_wkup_cause_cause_2_qs_int;
logic aon_wkup_cause_cause_3_ds_int;
logic aon_wkup_cause_cause_3_qs_int;
logic aon_wkup_cause_cause_4_ds_int;
logic aon_wkup_cause_cause_4_qs_int;
logic aon_wkup_cause_cause_5_ds_int;
logic aon_wkup_cause_cause_5_qs_int;
logic aon_wkup_cause_cause_6_ds_int;
logic aon_wkup_cause_cause_6_qs_int;
logic aon_wkup_cause_cause_7_ds_int;
logic aon_wkup_cause_cause_7_qs_int;
logic [7:0] aon_wkup_cause_ds;
logic aon_wkup_cause_qe;
logic [7:0] aon_wkup_cause_qs;
logic [7:0] aon_wkup_cause_wdata;
logic aon_wkup_cause_we;
logic unused_aon_wkup_cause_wdata;
always_comb begin
aon_wkup_cause_qs = 8'h0;
aon_wkup_cause_ds = 8'h0;
aon_wkup_cause_ds[0] = aon_wkup_cause_cause_0_ds_int;
aon_wkup_cause_qs[0] = aon_wkup_cause_cause_0_qs_int;
aon_wkup_cause_ds[1] = aon_wkup_cause_cause_1_ds_int;
aon_wkup_cause_qs[1] = aon_wkup_cause_cause_1_qs_int;
aon_wkup_cause_ds[2] = aon_wkup_cause_cause_2_ds_int;
aon_wkup_cause_qs[2] = aon_wkup_cause_cause_2_qs_int;
aon_wkup_cause_ds[3] = aon_wkup_cause_cause_3_ds_int;
aon_wkup_cause_qs[3] = aon_wkup_cause_cause_3_qs_int;
aon_wkup_cause_ds[4] = aon_wkup_cause_cause_4_ds_int;
aon_wkup_cause_qs[4] = aon_wkup_cause_cause_4_qs_int;
aon_wkup_cause_ds[5] = aon_wkup_cause_cause_5_ds_int;
aon_wkup_cause_qs[5] = aon_wkup_cause_cause_5_qs_int;
aon_wkup_cause_ds[6] = aon_wkup_cause_cause_6_ds_int;
aon_wkup_cause_qs[6] = aon_wkup_cause_cause_6_qs_int;
aon_wkup_cause_ds[7] = aon_wkup_cause_cause_7_ds_int;
aon_wkup_cause_qs[7] = aon_wkup_cause_cause_7_qs_int;
end
prim_reg_cdc #(
.DataWidth(8),
.ResetVal(8'h0),
.BitMask(8'hff),
.DstWrReq(1)
) u_wkup_cause_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_aon_i),
.rst_dst_ni (rst_aon_ni),
.src_regwen_i ('0),
.src_we_i (wkup_cause_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[7:0]),
.src_busy_o (wkup_cause_busy),
.src_qs_o (wkup_cause_qs), // for software read back
.dst_update_i (aon_wkup_cause_qe),
.dst_ds_i (aon_wkup_cause_ds),
.dst_qs_i (aon_wkup_cause_qs),
.dst_we_o (aon_wkup_cause_we),
.dst_re_o (),
.dst_regwen_o (),
.dst_wd_o (aon_wkup_cause_wdata)
);
assign unused_aon_wkup_cause_wdata =
^aon_wkup_cause_wdata;
// Register instances
// R[alert_test]: V(True)
logic alert_test_qe;
logic [0:0] alert_test_flds_we;
assign alert_test_qe = &alert_test_flds_we;
prim_subreg_ext #(
.DW (1)
) u_alert_test (
.re (1'b0),
.we (alert_test_we),
.wd (alert_test_wd),
.d ('0),
.qre (),
.qe (alert_test_flds_we[0]),
.q (reg2hw.alert_test.q),
.ds (),
.qs ()
);
assign reg2hw.alert_test.qe = alert_test_qe;
// Subregister 0 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_0]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_0 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_0_we),
.wd (mio_periph_insel_regwen_0_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_0_qs)
);
// Subregister 1 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_1]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_1 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_1_we),
.wd (mio_periph_insel_regwen_1_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_1_qs)
);
// Subregister 2 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_2]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_2 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_2_we),
.wd (mio_periph_insel_regwen_2_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_2_qs)
);
// Subregister 3 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_3]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_3 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_3_we),
.wd (mio_periph_insel_regwen_3_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_3_qs)
);
// Subregister 4 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_4]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_4 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_4_we),
.wd (mio_periph_insel_regwen_4_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_4_qs)
);
// Subregister 5 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_5]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_5 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_5_we),
.wd (mio_periph_insel_regwen_5_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_5_qs)
);
// Subregister 6 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_6]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_6 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_6_we),
.wd (mio_periph_insel_regwen_6_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_6_qs)
);
// Subregister 7 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_7]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_7 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_7_we),
.wd (mio_periph_insel_regwen_7_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_7_qs)
);
// Subregister 8 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_8]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_8 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_8_we),
.wd (mio_periph_insel_regwen_8_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_8_qs)
);
// Subregister 9 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_9]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_9 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_9_we),
.wd (mio_periph_insel_regwen_9_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_9_qs)
);
// Subregister 10 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_10]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_10 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_10_we),
.wd (mio_periph_insel_regwen_10_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_10_qs)
);
// Subregister 11 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_11]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_11 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_11_we),
.wd (mio_periph_insel_regwen_11_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_11_qs)
);
// Subregister 12 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_12]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_12 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_12_we),
.wd (mio_periph_insel_regwen_12_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_12_qs)
);
// Subregister 13 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_13]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_13 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_13_we),
.wd (mio_periph_insel_regwen_13_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_13_qs)
);
// Subregister 14 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_14]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_14 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_14_we),
.wd (mio_periph_insel_regwen_14_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_14_qs)
);
// Subregister 15 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_15]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_15 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_15_we),
.wd (mio_periph_insel_regwen_15_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_15_qs)
);
// Subregister 16 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_16]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_16 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_16_we),
.wd (mio_periph_insel_regwen_16_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_16_qs)
);
// Subregister 17 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_17]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_17 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_17_we),
.wd (mio_periph_insel_regwen_17_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_17_qs)
);
// Subregister 18 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_18]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_18 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_18_we),
.wd (mio_periph_insel_regwen_18_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_18_qs)
);
// Subregister 19 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_19]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_19 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_19_we),
.wd (mio_periph_insel_regwen_19_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_19_qs)
);
// Subregister 20 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_20]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_20 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_20_we),
.wd (mio_periph_insel_regwen_20_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_20_qs)
);
// Subregister 21 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_21]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_21 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_21_we),
.wd (mio_periph_insel_regwen_21_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_21_qs)
);
// Subregister 22 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_22]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_22 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_22_we),
.wd (mio_periph_insel_regwen_22_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_22_qs)
);
// Subregister 23 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_23]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_23 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_23_we),
.wd (mio_periph_insel_regwen_23_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_23_qs)
);
// Subregister 24 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_24]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_24 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_24_we),
.wd (mio_periph_insel_regwen_24_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_24_qs)
);
// Subregister 25 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_25]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_25 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_25_we),
.wd (mio_periph_insel_regwen_25_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_25_qs)
);
// Subregister 26 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_26]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_26 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_26_we),
.wd (mio_periph_insel_regwen_26_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_26_qs)
);
// Subregister 27 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_27]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_27 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_27_we),
.wd (mio_periph_insel_regwen_27_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_27_qs)
);
// Subregister 28 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_28]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_28 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_28_we),
.wd (mio_periph_insel_regwen_28_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_28_qs)
);
// Subregister 29 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_29]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_29 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_29_we),
.wd (mio_periph_insel_regwen_29_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_29_qs)
);
// Subregister 30 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_30]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_30 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_30_we),
.wd (mio_periph_insel_regwen_30_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_30_qs)
);
// Subregister 31 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_31]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_31 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_31_we),
.wd (mio_periph_insel_regwen_31_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_31_qs)
);
// Subregister 32 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_32]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_32 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_32_we),
.wd (mio_periph_insel_regwen_32_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_regwen_32_qs)
);
// Subregister 0 of Multireg mio_periph_insel
// R[mio_periph_insel_0]: V(False)
// Create REGWEN-gated WE signal
logic mio_periph_insel_0_gated_we;
assign mio_periph_insel_0_gated_we = mio_periph_insel_0_we & mio_periph_insel_regwen_0_qs;
prim_subreg #(
.DW (6),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (6'h0)
) u_mio_periph_insel_0 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_0_gated_we),
.wd (mio_periph_insel_0_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.mio_periph_insel[0].q),
.ds (),
// to register interface (read)
.qs (mio_periph_insel_0_qs)
);