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opensecura / 3p / lowrisc / opentitan / 5a1c665a50f3c920862f9eb4aa4d2c8b8038ab52 / . / hw / ip / keymgr / rtl / keymgr_reg_top.sv
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Top module auto-generated by `reggen`
`include "prim_assert.sv"
module keymgr_reg_top (
input clk_i,
input rst_ni,
input rst_shadowed_ni,
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
// To HW
output keymgr_reg_pkg::keymgr_reg2hw_t reg2hw, // Write
input keymgr_reg_pkg::keymgr_hw2reg_t hw2reg, // Read
output logic shadowed_storage_err_o,
output logic shadowed_update_err_o,
// Integrity check errors
output logic intg_err_o,
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
import keymgr_reg_pkg::* ;
localparam int AW = 8;
localparam int DW = 32;
localparam int DBW = DW/8; // Byte Width
// register signals
logic reg_we;
logic reg_re;
logic [AW-1:0] reg_addr;
logic [DW-1:0] reg_wdata;
logic [DBW-1:0] reg_be;
logic [DW-1:0] reg_rdata;
logic reg_error;
logic addrmiss, wr_err;
logic [DW-1:0] reg_rdata_next;
logic reg_busy;
tlul_pkg::tl_h2d_t tl_reg_h2d;
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
logic intg_err;
tlul_cmd_intg_chk u_chk (
.tl_i(tl_i),
.err_o(intg_err)
);
// also check for spurious write enables
logic reg_we_err;
logic [62:0] reg_we_check;
prim_reg_we_check #(
.OneHotWidth(63)
) u_prim_reg_we_check (
.clk_i(clk_i),
.rst_ni(rst_ni),
.oh_i (reg_we_check),
.en_i (reg_we && !addrmiss),
.err_o (reg_we_err)
);
logic err_q;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
err_q <= '0;
end else if (intg_err || reg_we_err) begin
err_q <= 1'b1;
end
end
// integrity error output is permanent and should be used for alert generation
// register errors are transactional
assign intg_err_o = err_q | intg_err | reg_we_err;
// outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
tlul_rsp_intg_gen #(
.EnableRspIntgGen(1),
.EnableDataIntgGen(1)
) u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o(tl_o)
);
assign tl_reg_h2d = tl_i;
assign tl_o_pre = tl_reg_d2h;
tlul_adapter_reg #(
.RegAw(AW),
.RegDw(DW),
.EnableDataIntgGen(0)
) u_reg_if (
.clk_i (clk_i),
.rst_ni (rst_ni),
.tl_i (tl_reg_h2d),
.tl_o (tl_reg_d2h),
.en_ifetch_i(prim_mubi_pkg::MuBi4False),
.intg_error_o(),
.we_o (reg_we),
.re_o (reg_re),
.addr_o (reg_addr),
.wdata_o (reg_wdata),
.be_o (reg_be),
.busy_i (reg_busy),
.rdata_i (reg_rdata),
.error_i (reg_error)
);
// cdc oversampling signals
assign reg_rdata = reg_rdata_next ;
assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
// or <reg>_{wd|we|qs} if field == 1 or 0
logic intr_state_we;
logic intr_state_qs;
logic intr_state_wd;
logic intr_enable_we;
logic intr_enable_qs;
logic intr_enable_wd;
logic intr_test_we;
logic intr_test_wd;
logic alert_test_we;
logic alert_test_recov_operation_err_wd;
logic alert_test_fatal_fault_err_wd;
logic cfg_regwen_re;
logic cfg_regwen_qs;
logic start_we;
logic start_qs;
logic start_wd;
logic control_shadowed_re;
logic control_shadowed_we;
logic [2:0] control_shadowed_operation_qs;
logic [2:0] control_shadowed_operation_wd;
logic control_shadowed_operation_storage_err;
logic control_shadowed_operation_update_err;
logic control_shadowed_cdi_sel_qs;
logic control_shadowed_cdi_sel_wd;
logic control_shadowed_cdi_sel_storage_err;
logic control_shadowed_cdi_sel_update_err;
logic [1:0] control_shadowed_dest_sel_qs;
logic [1:0] control_shadowed_dest_sel_wd;
logic control_shadowed_dest_sel_storage_err;
logic control_shadowed_dest_sel_update_err;
logic sideload_clear_we;
logic [2:0] sideload_clear_qs;
logic [2:0] sideload_clear_wd;
logic reseed_interval_regwen_we;
logic reseed_interval_regwen_qs;
logic reseed_interval_regwen_wd;
logic reseed_interval_shadowed_re;
logic reseed_interval_shadowed_we;
logic [15:0] reseed_interval_shadowed_qs;
logic [15:0] reseed_interval_shadowed_wd;
logic reseed_interval_shadowed_storage_err;
logic reseed_interval_shadowed_update_err;
logic sw_binding_regwen_re;
logic sw_binding_regwen_we;
logic sw_binding_regwen_qs;
logic sw_binding_regwen_wd;
logic sealing_sw_binding_0_we;
logic [31:0] sealing_sw_binding_0_qs;
logic [31:0] sealing_sw_binding_0_wd;
logic sealing_sw_binding_1_we;
logic [31:0] sealing_sw_binding_1_qs;
logic [31:0] sealing_sw_binding_1_wd;
logic sealing_sw_binding_2_we;
logic [31:0] sealing_sw_binding_2_qs;
logic [31:0] sealing_sw_binding_2_wd;
logic sealing_sw_binding_3_we;
logic [31:0] sealing_sw_binding_3_qs;
logic [31:0] sealing_sw_binding_3_wd;
logic sealing_sw_binding_4_we;
logic [31:0] sealing_sw_binding_4_qs;
logic [31:0] sealing_sw_binding_4_wd;
logic sealing_sw_binding_5_we;
logic [31:0] sealing_sw_binding_5_qs;
logic [31:0] sealing_sw_binding_5_wd;
logic sealing_sw_binding_6_we;
logic [31:0] sealing_sw_binding_6_qs;
logic [31:0] sealing_sw_binding_6_wd;
logic sealing_sw_binding_7_we;
logic [31:0] sealing_sw_binding_7_qs;
logic [31:0] sealing_sw_binding_7_wd;
logic attest_sw_binding_0_we;
logic [31:0] attest_sw_binding_0_qs;
logic [31:0] attest_sw_binding_0_wd;
logic attest_sw_binding_1_we;
logic [31:0] attest_sw_binding_1_qs;
logic [31:0] attest_sw_binding_1_wd;
logic attest_sw_binding_2_we;
logic [31:0] attest_sw_binding_2_qs;
logic [31:0] attest_sw_binding_2_wd;
logic attest_sw_binding_3_we;
logic [31:0] attest_sw_binding_3_qs;
logic [31:0] attest_sw_binding_3_wd;
logic attest_sw_binding_4_we;
logic [31:0] attest_sw_binding_4_qs;
logic [31:0] attest_sw_binding_4_wd;
logic attest_sw_binding_5_we;
logic [31:0] attest_sw_binding_5_qs;
logic [31:0] attest_sw_binding_5_wd;
logic attest_sw_binding_6_we;
logic [31:0] attest_sw_binding_6_qs;
logic [31:0] attest_sw_binding_6_wd;
logic attest_sw_binding_7_we;
logic [31:0] attest_sw_binding_7_qs;
logic [31:0] attest_sw_binding_7_wd;
logic salt_0_we;
logic [31:0] salt_0_qs;
logic [31:0] salt_0_wd;
logic salt_1_we;
logic [31:0] salt_1_qs;
logic [31:0] salt_1_wd;
logic salt_2_we;
logic [31:0] salt_2_qs;
logic [31:0] salt_2_wd;
logic salt_3_we;
logic [31:0] salt_3_qs;
logic [31:0] salt_3_wd;
logic salt_4_we;
logic [31:0] salt_4_qs;
logic [31:0] salt_4_wd;
logic salt_5_we;
logic [31:0] salt_5_qs;
logic [31:0] salt_5_wd;
logic salt_6_we;
logic [31:0] salt_6_qs;
logic [31:0] salt_6_wd;
logic salt_7_we;
logic [31:0] salt_7_qs;
logic [31:0] salt_7_wd;
logic key_version_we;
logic [31:0] key_version_qs;
logic [31:0] key_version_wd;
logic max_creator_key_ver_regwen_we;
logic max_creator_key_ver_regwen_qs;
logic max_creator_key_ver_regwen_wd;
logic max_creator_key_ver_shadowed_re;
logic max_creator_key_ver_shadowed_we;
logic [31:0] max_creator_key_ver_shadowed_qs;
logic [31:0] max_creator_key_ver_shadowed_wd;
logic max_creator_key_ver_shadowed_storage_err;
logic max_creator_key_ver_shadowed_update_err;
logic max_owner_int_key_ver_regwen_we;
logic max_owner_int_key_ver_regwen_qs;
logic max_owner_int_key_ver_regwen_wd;
logic max_owner_int_key_ver_shadowed_re;
logic max_owner_int_key_ver_shadowed_we;
logic [31:0] max_owner_int_key_ver_shadowed_qs;
logic [31:0] max_owner_int_key_ver_shadowed_wd;
logic max_owner_int_key_ver_shadowed_storage_err;
logic max_owner_int_key_ver_shadowed_update_err;
logic max_owner_key_ver_regwen_we;
logic max_owner_key_ver_regwen_qs;
logic max_owner_key_ver_regwen_wd;
logic max_owner_key_ver_shadowed_re;
logic max_owner_key_ver_shadowed_we;
logic [31:0] max_owner_key_ver_shadowed_qs;
logic [31:0] max_owner_key_ver_shadowed_wd;
logic max_owner_key_ver_shadowed_storage_err;
logic max_owner_key_ver_shadowed_update_err;
logic sw_share0_output_0_re;
logic [31:0] sw_share0_output_0_qs;
logic [31:0] sw_share0_output_0_wd;
logic sw_share0_output_1_re;
logic [31:0] sw_share0_output_1_qs;
logic [31:0] sw_share0_output_1_wd;
logic sw_share0_output_2_re;
logic [31:0] sw_share0_output_2_qs;
logic [31:0] sw_share0_output_2_wd;
logic sw_share0_output_3_re;
logic [31:0] sw_share0_output_3_qs;
logic [31:0] sw_share0_output_3_wd;
logic sw_share0_output_4_re;
logic [31:0] sw_share0_output_4_qs;
logic [31:0] sw_share0_output_4_wd;
logic sw_share0_output_5_re;
logic [31:0] sw_share0_output_5_qs;
logic [31:0] sw_share0_output_5_wd;
logic sw_share0_output_6_re;
logic [31:0] sw_share0_output_6_qs;
logic [31:0] sw_share0_output_6_wd;
logic sw_share0_output_7_re;
logic [31:0] sw_share0_output_7_qs;
logic [31:0] sw_share0_output_7_wd;
logic sw_share1_output_0_re;
logic [31:0] sw_share1_output_0_qs;
logic [31:0] sw_share1_output_0_wd;
logic sw_share1_output_1_re;
logic [31:0] sw_share1_output_1_qs;
logic [31:0] sw_share1_output_1_wd;
logic sw_share1_output_2_re;
logic [31:0] sw_share1_output_2_qs;
logic [31:0] sw_share1_output_2_wd;
logic sw_share1_output_3_re;
logic [31:0] sw_share1_output_3_qs;
logic [31:0] sw_share1_output_3_wd;
logic sw_share1_output_4_re;
logic [31:0] sw_share1_output_4_qs;
logic [31:0] sw_share1_output_4_wd;
logic sw_share1_output_5_re;
logic [31:0] sw_share1_output_5_qs;
logic [31:0] sw_share1_output_5_wd;
logic sw_share1_output_6_re;
logic [31:0] sw_share1_output_6_qs;
logic [31:0] sw_share1_output_6_wd;
logic sw_share1_output_7_re;
logic [31:0] sw_share1_output_7_qs;
logic [31:0] sw_share1_output_7_wd;
logic [2:0] working_state_qs;
logic op_status_we;
logic [1:0] op_status_qs;
logic [1:0] op_status_wd;
logic err_code_we;
logic err_code_invalid_op_qs;
logic err_code_invalid_op_wd;
logic err_code_invalid_kmac_input_qs;
logic err_code_invalid_kmac_input_wd;
logic err_code_invalid_shadow_update_qs;
logic err_code_invalid_shadow_update_wd;
logic fault_status_cmd_qs;
logic fault_status_kmac_fsm_qs;
logic fault_status_kmac_done_qs;
logic fault_status_kmac_op_qs;
logic fault_status_kmac_out_qs;
logic fault_status_regfile_intg_qs;
logic fault_status_shadow_qs;
logic fault_status_ctrl_fsm_intg_qs;
logic fault_status_ctrl_fsm_chk_qs;
logic fault_status_ctrl_fsm_cnt_qs;
logic fault_status_reseed_cnt_qs;
logic fault_status_side_ctrl_fsm_qs;
logic fault_status_side_ctrl_sel_qs;
logic fault_status_key_ecc_qs;
logic debug_we;
logic debug_invalid_creator_seed_qs;
logic debug_invalid_creator_seed_wd;
logic debug_invalid_owner_seed_qs;
logic debug_invalid_owner_seed_wd;
logic debug_invalid_dev_id_qs;
logic debug_invalid_dev_id_wd;
logic debug_invalid_health_state_qs;
logic debug_invalid_health_state_wd;
logic debug_invalid_key_version_qs;
logic debug_invalid_key_version_wd;
logic debug_invalid_key_qs;
logic debug_invalid_key_wd;
logic debug_invalid_digest_qs;
logic debug_invalid_digest_wd;
// Register instances
// R[intr_state]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_intr_state (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
.wd (intr_state_wd),
// from internal hardware
.de (hw2reg.intr_state.de),
.d (hw2reg.intr_state.d),
// to internal hardware
.qe (),
.q (reg2hw.intr_state.q),
.ds (),
// to register interface (read)
.qs (intr_state_qs)
);
// R[intr_enable]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_intr_enable (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
.wd (intr_enable_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.intr_enable.q),
.ds (),
// to register interface (read)
.qs (intr_enable_qs)
);
// R[intr_test]: V(True)
logic intr_test_qe;
logic [0:0] intr_test_flds_we;
assign intr_test_qe = &intr_test_flds_we;
prim_subreg_ext #(
.DW (1)
) u_intr_test (
.re (1'b0),
.we (intr_test_we),
.wd (intr_test_wd),
.d ('0),
.qre (),
.qe (intr_test_flds_we[0]),
.q (reg2hw.intr_test.q),
.ds (),
.qs ()
);
assign reg2hw.intr_test.qe = intr_test_qe;
// R[alert_test]: V(True)
logic alert_test_qe;
logic [1:0] alert_test_flds_we;
assign alert_test_qe = &alert_test_flds_we;
// F[recov_operation_err]: 0:0
prim_subreg_ext #(
.DW (1)
) u_alert_test_recov_operation_err (
.re (1'b0),
.we (alert_test_we),
.wd (alert_test_recov_operation_err_wd),
.d ('0),
.qre (),
.qe (alert_test_flds_we[0]),
.q (reg2hw.alert_test.recov_operation_err.q),
.ds (),
.qs ()
);
assign reg2hw.alert_test.recov_operation_err.qe = alert_test_qe;
// F[fatal_fault_err]: 1:1
prim_subreg_ext #(
.DW (1)
) u_alert_test_fatal_fault_err (
.re (1'b0),
.we (alert_test_we),
.wd (alert_test_fatal_fault_err_wd),
.d ('0),
.qre (),
.qe (alert_test_flds_we[1]),
.q (reg2hw.alert_test.fatal_fault_err.q),
.ds (),
.qs ()
);
assign reg2hw.alert_test.fatal_fault_err.qe = alert_test_qe;
// R[cfg_regwen]: V(True)
prim_subreg_ext #(
.DW (1)
) u_cfg_regwen (
.re (cfg_regwen_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.cfg_regwen.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (cfg_regwen_qs)
);
// R[start]: V(False)
// Create REGWEN-gated WE signal
logic start_gated_we;
assign start_gated_we = start_we & cfg_regwen_qs;
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_start (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (start_gated_we),
.wd (start_wd),
// from internal hardware
.de (hw2reg.start.de),
.d (hw2reg.start.d),
// to internal hardware
.qe (),
.q (reg2hw.start.q),
.ds (),
// to register interface (read)
.qs (start_qs)
);
// R[control_shadowed]: V(False)
// Create REGWEN-gated WE signal
logic control_shadowed_gated_we;
assign control_shadowed_gated_we = control_shadowed_we & cfg_regwen_qs;
// F[operation]: 6:4
prim_subreg_shadow #(
.DW (3),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (3'h1)
) u_control_shadowed_operation (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (control_shadowed_re),
.we (control_shadowed_gated_we),
.wd (control_shadowed_operation_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.control_shadowed.operation.q),
.ds (),
// to register interface (read)
.qs (control_shadowed_operation_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (control_shadowed_operation_update_err),
.err_storage (control_shadowed_operation_storage_err)
);
// F[cdi_sel]: 7:7
prim_subreg_shadow #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_control_shadowed_cdi_sel (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (control_shadowed_re),
.we (control_shadowed_gated_we),
.wd (control_shadowed_cdi_sel_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.control_shadowed.cdi_sel.q),
.ds (),
// to register interface (read)
.qs (control_shadowed_cdi_sel_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (control_shadowed_cdi_sel_update_err),
.err_storage (control_shadowed_cdi_sel_storage_err)
);
// F[dest_sel]: 13:12
prim_subreg_shadow #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_control_shadowed_dest_sel (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (control_shadowed_re),
.we (control_shadowed_gated_we),
.wd (control_shadowed_dest_sel_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.control_shadowed.dest_sel.q),
.ds (),
// to register interface (read)
.qs (control_shadowed_dest_sel_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (control_shadowed_dest_sel_update_err),
.err_storage (control_shadowed_dest_sel_storage_err)
);
// R[sideload_clear]: V(False)
// Create REGWEN-gated WE signal
logic sideload_clear_gated_we;
assign sideload_clear_gated_we = sideload_clear_we & cfg_regwen_qs;
prim_subreg #(
.DW (3),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (3'h0)
) u_sideload_clear (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sideload_clear_gated_we),
.wd (sideload_clear_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.sideload_clear.q),
.ds (),
// to register interface (read)
.qs (sideload_clear_qs)
);
// R[reseed_interval_regwen]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_reseed_interval_regwen (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (reseed_interval_regwen_we),
.wd (reseed_interval_regwen_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (reseed_interval_regwen_qs)
);
// R[reseed_interval_shadowed]: V(False)
// Create REGWEN-gated WE signal
logic reseed_interval_shadowed_gated_we;
assign reseed_interval_shadowed_gated_we =
reseed_interval_shadowed_we & reseed_interval_regwen_qs;
prim_subreg_shadow #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h100)
) u_reseed_interval_shadowed (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (reseed_interval_shadowed_re),
.we (reseed_interval_shadowed_gated_we),
.wd (reseed_interval_shadowed_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.reseed_interval_shadowed.q),
.ds (),
// to register interface (read)
.qs (reseed_interval_shadowed_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (reseed_interval_shadowed_update_err),
.err_storage (reseed_interval_shadowed_storage_err)
);
// R[sw_binding_regwen]: V(True)
logic sw_binding_regwen_qe;
logic [0:0] sw_binding_regwen_flds_we;
assign sw_binding_regwen_qe = &sw_binding_regwen_flds_we;
prim_subreg_ext #(
.DW (1)
) u_sw_binding_regwen (
.re (sw_binding_regwen_re),
.we (sw_binding_regwen_we),
.wd (sw_binding_regwen_wd),
.d (hw2reg.sw_binding_regwen.d),
.qre (),
.qe (sw_binding_regwen_flds_we[0]),
.q (reg2hw.sw_binding_regwen.q),
.ds (),
.qs (sw_binding_regwen_qs)
);
assign reg2hw.sw_binding_regwen.qe = sw_binding_regwen_qe;
// Subregister 0 of Multireg sealing_sw_binding
// R[sealing_sw_binding_0]: V(False)
// Create REGWEN-gated WE signal
logic sealing_sw_binding_0_gated_we;
assign sealing_sw_binding_0_gated_we = sealing_sw_binding_0_we & sw_binding_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_sealing_sw_binding_0 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sealing_sw_binding_0_gated_we),
.wd (sealing_sw_binding_0_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.sealing_sw_binding[0].q),
.ds (),
// to register interface (read)
.qs (sealing_sw_binding_0_qs)
);
// Subregister 1 of Multireg sealing_sw_binding
// R[sealing_sw_binding_1]: V(False)
// Create REGWEN-gated WE signal
logic sealing_sw_binding_1_gated_we;
assign sealing_sw_binding_1_gated_we = sealing_sw_binding_1_we & sw_binding_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_sealing_sw_binding_1 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sealing_sw_binding_1_gated_we),
.wd (sealing_sw_binding_1_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.sealing_sw_binding[1].q),
.ds (),
// to register interface (read)
.qs (sealing_sw_binding_1_qs)
);
// Subregister 2 of Multireg sealing_sw_binding
// R[sealing_sw_binding_2]: V(False)
// Create REGWEN-gated WE signal
logic sealing_sw_binding_2_gated_we;
assign sealing_sw_binding_2_gated_we = sealing_sw_binding_2_we & sw_binding_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_sealing_sw_binding_2 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sealing_sw_binding_2_gated_we),
.wd (sealing_sw_binding_2_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.sealing_sw_binding[2].q),
.ds (),
// to register interface (read)
.qs (sealing_sw_binding_2_qs)
);
// Subregister 3 of Multireg sealing_sw_binding
// R[sealing_sw_binding_3]: V(False)
// Create REGWEN-gated WE signal
logic sealing_sw_binding_3_gated_we;
assign sealing_sw_binding_3_gated_we = sealing_sw_binding_3_we & sw_binding_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_sealing_sw_binding_3 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sealing_sw_binding_3_gated_we),
.wd (sealing_sw_binding_3_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.sealing_sw_binding[3].q),
.ds (),
// to register interface (read)
.qs (sealing_sw_binding_3_qs)
);
// Subregister 4 of Multireg sealing_sw_binding
// R[sealing_sw_binding_4]: V(False)
// Create REGWEN-gated WE signal
logic sealing_sw_binding_4_gated_we;
assign sealing_sw_binding_4_gated_we = sealing_sw_binding_4_we & sw_binding_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_sealing_sw_binding_4 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sealing_sw_binding_4_gated_we),
.wd (sealing_sw_binding_4_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.sealing_sw_binding[4].q),
.ds (),
// to register interface (read)
.qs (sealing_sw_binding_4_qs)
);
// Subregister 5 of Multireg sealing_sw_binding
// R[sealing_sw_binding_5]: V(False)
// Create REGWEN-gated WE signal
logic sealing_sw_binding_5_gated_we;
assign sealing_sw_binding_5_gated_we = sealing_sw_binding_5_we & sw_binding_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_sealing_sw_binding_5 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sealing_sw_binding_5_gated_we),
.wd (sealing_sw_binding_5_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.sealing_sw_binding[5].q),
.ds (),
// to register interface (read)
.qs (sealing_sw_binding_5_qs)
);
// Subregister 6 of Multireg sealing_sw_binding
// R[sealing_sw_binding_6]: V(False)
// Create REGWEN-gated WE signal
logic sealing_sw_binding_6_gated_we;
assign sealing_sw_binding_6_gated_we = sealing_sw_binding_6_we & sw_binding_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_sealing_sw_binding_6 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sealing_sw_binding_6_gated_we),
.wd (sealing_sw_binding_6_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.sealing_sw_binding[6].q),
.ds (),
// to register interface (read)
.qs (sealing_sw_binding_6_qs)
);
// Subregister 7 of Multireg sealing_sw_binding
// R[sealing_sw_binding_7]: V(False)
// Create REGWEN-gated WE signal
logic sealing_sw_binding_7_gated_we;
assign sealing_sw_binding_7_gated_we = sealing_sw_binding_7_we & sw_binding_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_sealing_sw_binding_7 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sealing_sw_binding_7_gated_we),
.wd (sealing_sw_binding_7_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.sealing_sw_binding[7].q),
.ds (),
// to register interface (read)
.qs (sealing_sw_binding_7_qs)
);
// Subregister 0 of Multireg attest_sw_binding
// R[attest_sw_binding_0]: V(False)
// Create REGWEN-gated WE signal
logic attest_sw_binding_0_gated_we;
assign attest_sw_binding_0_gated_we = attest_sw_binding_0_we & sw_binding_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_attest_sw_binding_0 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (attest_sw_binding_0_gated_we),
.wd (attest_sw_binding_0_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.attest_sw_binding[0].q),
.ds (),
// to register interface (read)
.qs (attest_sw_binding_0_qs)
);
// Subregister 1 of Multireg attest_sw_binding
// R[attest_sw_binding_1]: V(False)
// Create REGWEN-gated WE signal
logic attest_sw_binding_1_gated_we;
assign attest_sw_binding_1_gated_we = attest_sw_binding_1_we & sw_binding_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_attest_sw_binding_1 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (attest_sw_binding_1_gated_we),
.wd (attest_sw_binding_1_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.attest_sw_binding[1].q),
.ds (),
// to register interface (read)
.qs (attest_sw_binding_1_qs)
);
// Subregister 2 of Multireg attest_sw_binding
// R[attest_sw_binding_2]: V(False)
// Create REGWEN-gated WE signal
logic attest_sw_binding_2_gated_we;
assign attest_sw_binding_2_gated_we = attest_sw_binding_2_we & sw_binding_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_attest_sw_binding_2 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (attest_sw_binding_2_gated_we),
.wd (attest_sw_binding_2_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.attest_sw_binding[2].q),
.ds (),
// to register interface (read)
.qs (attest_sw_binding_2_qs)
);
// Subregister 3 of Multireg attest_sw_binding
// R[attest_sw_binding_3]: V(False)
// Create REGWEN-gated WE signal
logic attest_sw_binding_3_gated_we;
assign attest_sw_binding_3_gated_we = attest_sw_binding_3_we & sw_binding_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_attest_sw_binding_3 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (attest_sw_binding_3_gated_we),
.wd (attest_sw_binding_3_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.attest_sw_binding[3].q),
.ds (),
// to register interface (read)
.qs (attest_sw_binding_3_qs)
);
// Subregister 4 of Multireg attest_sw_binding
// R[attest_sw_binding_4]: V(False)
// Create REGWEN-gated WE signal
logic attest_sw_binding_4_gated_we;
assign attest_sw_binding_4_gated_we = attest_sw_binding_4_we & sw_binding_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_attest_sw_binding_4 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (attest_sw_binding_4_gated_we),
.wd (attest_sw_binding_4_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.attest_sw_binding[4].q),
.ds (),
// to register interface (read)
.qs (attest_sw_binding_4_qs)
);
// Subregister 5 of Multireg attest_sw_binding
// R[attest_sw_binding_5]: V(False)
// Create REGWEN-gated WE signal
logic attest_sw_binding_5_gated_we;
assign attest_sw_binding_5_gated_we = attest_sw_binding_5_we & sw_binding_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_attest_sw_binding_5 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (attest_sw_binding_5_gated_we),
.wd (attest_sw_binding_5_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.attest_sw_binding[5].q),
.ds (),
// to register interface (read)
.qs (attest_sw_binding_5_qs)
);
// Subregister 6 of Multireg attest_sw_binding
// R[attest_sw_binding_6]: V(False)
// Create REGWEN-gated WE signal
logic attest_sw_binding_6_gated_we;
assign attest_sw_binding_6_gated_we = attest_sw_binding_6_we & sw_binding_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_attest_sw_binding_6 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (attest_sw_binding_6_gated_we),
.wd (attest_sw_binding_6_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.attest_sw_binding[6].q),
.ds (),
// to register interface (read)
.qs (attest_sw_binding_6_qs)
);
// Subregister 7 of Multireg attest_sw_binding
// R[attest_sw_binding_7]: V(False)
// Create REGWEN-gated WE signal
logic attest_sw_binding_7_gated_we;
assign attest_sw_binding_7_gated_we = attest_sw_binding_7_we & sw_binding_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_attest_sw_binding_7 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (attest_sw_binding_7_gated_we),
.wd (attest_sw_binding_7_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.attest_sw_binding[7].q),
.ds (),
// to register interface (read)
.qs (attest_sw_binding_7_qs)
);
// Subregister 0 of Multireg salt
// R[salt_0]: V(False)
// Create REGWEN-gated WE signal
logic salt_0_gated_we;
assign salt_0_gated_we = salt_0_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_salt_0 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (salt_0_gated_we),
.wd (salt_0_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.salt[0].q),
.ds (),
// to register interface (read)
.qs (salt_0_qs)
);
// Subregister 1 of Multireg salt
// R[salt_1]: V(False)
// Create REGWEN-gated WE signal
logic salt_1_gated_we;
assign salt_1_gated_we = salt_1_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_salt_1 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (salt_1_gated_we),
.wd (salt_1_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.salt[1].q),
.ds (),
// to register interface (read)
.qs (salt_1_qs)
);
// Subregister 2 of Multireg salt
// R[salt_2]: V(False)
// Create REGWEN-gated WE signal
logic salt_2_gated_we;
assign salt_2_gated_we = salt_2_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_salt_2 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (salt_2_gated_we),
.wd (salt_2_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.salt[2].q),
.ds (),
// to register interface (read)
.qs (salt_2_qs)
);
// Subregister 3 of Multireg salt
// R[salt_3]: V(False)
// Create REGWEN-gated WE signal
logic salt_3_gated_we;
assign salt_3_gated_we = salt_3_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_salt_3 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (salt_3_gated_we),
.wd (salt_3_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.salt[3].q),
.ds (),
// to register interface (read)
.qs (salt_3_qs)
);
// Subregister 4 of Multireg salt
// R[salt_4]: V(False)
// Create REGWEN-gated WE signal
logic salt_4_gated_we;
assign salt_4_gated_we = salt_4_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_salt_4 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (salt_4_gated_we),
.wd (salt_4_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.salt[4].q),
.ds (),
// to register interface (read)
.qs (salt_4_qs)
);
// Subregister 5 of Multireg salt
// R[salt_5]: V(False)
// Create REGWEN-gated WE signal
logic salt_5_gated_we;
assign salt_5_gated_we = salt_5_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_salt_5 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (salt_5_gated_we),
.wd (salt_5_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.salt[5].q),
.ds (),
// to register interface (read)
.qs (salt_5_qs)
);
// Subregister 6 of Multireg salt
// R[salt_6]: V(False)
// Create REGWEN-gated WE signal
logic salt_6_gated_we;
assign salt_6_gated_we = salt_6_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_salt_6 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (salt_6_gated_we),
.wd (salt_6_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.salt[6].q),
.ds (),
// to register interface (read)
.qs (salt_6_qs)
);
// Subregister 7 of Multireg salt
// R[salt_7]: V(False)
// Create REGWEN-gated WE signal
logic salt_7_gated_we;
assign salt_7_gated_we = salt_7_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_salt_7 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (salt_7_gated_we),
.wd (salt_7_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.salt[7].q),
.ds (),
// to register interface (read)
.qs (salt_7_qs)
);
// Subregister 0 of Multireg key_version
// R[key_version]: V(False)
// Create REGWEN-gated WE signal
logic key_version_gated_we;
assign key_version_gated_we = key_version_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_key_version (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (key_version_gated_we),
.wd (key_version_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.key_version[0].q),
.ds (),
// to register interface (read)
.qs (key_version_qs)
);
// R[max_creator_key_ver_regwen]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_max_creator_key_ver_regwen (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (max_creator_key_ver_regwen_we),
.wd (max_creator_key_ver_regwen_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (max_creator_key_ver_regwen_qs)
);
// R[max_creator_key_ver_shadowed]: V(False)
// Create REGWEN-gated WE signal
logic max_creator_key_ver_shadowed_gated_we;
assign max_creator_key_ver_shadowed_gated_we =
max_creator_key_ver_shadowed_we & max_creator_key_ver_regwen_qs;
prim_subreg_shadow #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_max_creator_key_ver_shadowed (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (max_creator_key_ver_shadowed_re),
.we (max_creator_key_ver_shadowed_gated_we),
.wd (max_creator_key_ver_shadowed_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.max_creator_key_ver_shadowed.q),
.ds (),
// to register interface (read)
.qs (max_creator_key_ver_shadowed_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (max_creator_key_ver_shadowed_update_err),
.err_storage (max_creator_key_ver_shadowed_storage_err)
);
// R[max_owner_int_key_ver_regwen]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_max_owner_int_key_ver_regwen (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (max_owner_int_key_ver_regwen_we),
.wd (max_owner_int_key_ver_regwen_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (max_owner_int_key_ver_regwen_qs)
);
// R[max_owner_int_key_ver_shadowed]: V(False)
// Create REGWEN-gated WE signal
logic max_owner_int_key_ver_shadowed_gated_we;
assign max_owner_int_key_ver_shadowed_gated_we =
max_owner_int_key_ver_shadowed_we & max_owner_int_key_ver_regwen_qs;
prim_subreg_shadow #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h1)
) u_max_owner_int_key_ver_shadowed (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (max_owner_int_key_ver_shadowed_re),
.we (max_owner_int_key_ver_shadowed_gated_we),
.wd (max_owner_int_key_ver_shadowed_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.max_owner_int_key_ver_shadowed.q),
.ds (),
// to register interface (read)
.qs (max_owner_int_key_ver_shadowed_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (max_owner_int_key_ver_shadowed_update_err),
.err_storage (max_owner_int_key_ver_shadowed_storage_err)
);
// R[max_owner_key_ver_regwen]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_max_owner_key_ver_regwen (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (max_owner_key_ver_regwen_we),
.wd (max_owner_key_ver_regwen_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (max_owner_key_ver_regwen_qs)
);
// R[max_owner_key_ver_shadowed]: V(False)
// Create REGWEN-gated WE signal
logic max_owner_key_ver_shadowed_gated_we;
assign max_owner_key_ver_shadowed_gated_we =
max_owner_key_ver_shadowed_we & max_owner_key_ver_regwen_qs;
prim_subreg_shadow #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_max_owner_key_ver_shadowed (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (max_owner_key_ver_shadowed_re),
.we (max_owner_key_ver_shadowed_gated_we),
.wd (max_owner_key_ver_shadowed_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.max_owner_key_ver_shadowed.q),
.ds (),
// to register interface (read)
.qs (max_owner_key_ver_shadowed_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (max_owner_key_ver_shadowed_update_err),
.err_storage (max_owner_key_ver_shadowed_storage_err)
);
// Subregister 0 of Multireg sw_share0_output
// R[sw_share0_output_0]: V(False)
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRC),
.RESVAL (32'h0)
) u_sw_share0_output_0 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sw_share0_output_0_re),
.wd (sw_share0_output_0_wd),
// from internal hardware
.de (hw2reg.sw_share0_output[0].de),
.d (hw2reg.sw_share0_output[0].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (sw_share0_output_0_qs)
);
// Subregister 1 of Multireg sw_share0_output
// R[sw_share0_output_1]: V(False)
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRC),
.RESVAL (32'h0)
) u_sw_share0_output_1 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sw_share0_output_1_re),
.wd (sw_share0_output_1_wd),
// from internal hardware
.de (hw2reg.sw_share0_output[1].de),
.d (hw2reg.sw_share0_output[1].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (sw_share0_output_1_qs)
);
// Subregister 2 of Multireg sw_share0_output
// R[sw_share0_output_2]: V(False)
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRC),
.RESVAL (32'h0)
) u_sw_share0_output_2 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sw_share0_output_2_re),
.wd (sw_share0_output_2_wd),
// from internal hardware
.de (hw2reg.sw_share0_output[2].de),
.d (hw2reg.sw_share0_output[2].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (sw_share0_output_2_qs)
);
// Subregister 3 of Multireg sw_share0_output
// R[sw_share0_output_3]: V(False)
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRC),
.RESVAL (32'h0)
) u_sw_share0_output_3 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sw_share0_output_3_re),
.wd (sw_share0_output_3_wd),
// from internal hardware
.de (hw2reg.sw_share0_output[3].de),
.d (hw2reg.sw_share0_output[3].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (sw_share0_output_3_qs)
);
// Subregister 4 of Multireg sw_share0_output
// R[sw_share0_output_4]: V(False)
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRC),
.RESVAL (32'h0)
) u_sw_share0_output_4 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sw_share0_output_4_re),
.wd (sw_share0_output_4_wd),
// from internal hardware
.de (hw2reg.sw_share0_output[4].de),
.d (hw2reg.sw_share0_output[4].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (sw_share0_output_4_qs)
);
// Subregister 5 of Multireg sw_share0_output
// R[sw_share0_output_5]: V(False)
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRC),
.RESVAL (32'h0)
) u_sw_share0_output_5 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sw_share0_output_5_re),
.wd (sw_share0_output_5_wd),
// from internal hardware
.de (hw2reg.sw_share0_output[5].de),
.d (hw2reg.sw_share0_output[5].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (sw_share0_output_5_qs)
);
// Subregister 6 of Multireg sw_share0_output
// R[sw_share0_output_6]: V(False)
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRC),
.RESVAL (32'h0)
) u_sw_share0_output_6 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sw_share0_output_6_re),
.wd (sw_share0_output_6_wd),
// from internal hardware
.de (hw2reg.sw_share0_output[6].de),
.d (hw2reg.sw_share0_output[6].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (sw_share0_output_6_qs)
);
// Subregister 7 of Multireg sw_share0_output
// R[sw_share0_output_7]: V(False)
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRC),
.RESVAL (32'h0)
) u_sw_share0_output_7 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sw_share0_output_7_re),
.wd (sw_share0_output_7_wd),
// from internal hardware
.de (hw2reg.sw_share0_output[7].de),
.d (hw2reg.sw_share0_output[7].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (sw_share0_output_7_qs)
);
// Subregister 0 of Multireg sw_share1_output
// R[sw_share1_output_0]: V(False)
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRC),
.RESVAL (32'h0)
) u_sw_share1_output_0 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sw_share1_output_0_re),
.wd (sw_share1_output_0_wd),
// from internal hardware
.de (hw2reg.sw_share1_output[0].de),
.d (hw2reg.sw_share1_output[0].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (sw_share1_output_0_qs)
);
// Subregister 1 of Multireg sw_share1_output
// R[sw_share1_output_1]: V(False)
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRC),
.RESVAL (32'h0)
) u_sw_share1_output_1 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sw_share1_output_1_re),
.wd (sw_share1_output_1_wd),
// from internal hardware
.de (hw2reg.sw_share1_output[1].de),
.d (hw2reg.sw_share1_output[1].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (sw_share1_output_1_qs)
);
// Subregister 2 of Multireg sw_share1_output
// R[sw_share1_output_2]: V(False)
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRC),
.RESVAL (32'h0)
) u_sw_share1_output_2 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sw_share1_output_2_re),
.wd (sw_share1_output_2_wd),
// from internal hardware
.de (hw2reg.sw_share1_output[2].de),
.d (hw2reg.sw_share1_output[2].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (sw_share1_output_2_qs)
);
// Subregister 3 of Multireg sw_share1_output
// R[sw_share1_output_3]: V(False)
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRC),
.RESVAL (32'h0)
) u_sw_share1_output_3 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sw_share1_output_3_re),
.wd (sw_share1_output_3_wd),
// from internal hardware
.de (hw2reg.sw_share1_output[3].de),
.d (hw2reg.sw_share1_output[3].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (sw_share1_output_3_qs)
);
// Subregister 4 of Multireg sw_share1_output
// R[sw_share1_output_4]: V(False)
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRC),
.RESVAL (32'h0)
) u_sw_share1_output_4 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sw_share1_output_4_re),
.wd (sw_share1_output_4_wd),
// from internal hardware
.de (hw2reg.sw_share1_output[4].de),
.d (hw2reg.sw_share1_output[4].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (sw_share1_output_4_qs)
);
// Subregister 5 of Multireg sw_share1_output
// R[sw_share1_output_5]: V(False)
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRC),
.RESVAL (32'h0)
) u_sw_share1_output_5 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sw_share1_output_5_re),
.wd (sw_share1_output_5_wd),
// from internal hardware
.de (hw2reg.sw_share1_output[5].de),
.d (hw2reg.sw_share1_output[5].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (sw_share1_output_5_qs)
);
// Subregister 6 of Multireg sw_share1_output
// R[sw_share1_output_6]: V(False)
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRC),
.RESVAL (32'h0)
) u_sw_share1_output_6 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sw_share1_output_6_re),
.wd (sw_share1_output_6_wd),
// from internal hardware
.de (hw2reg.sw_share1_output[6].de),
.d (hw2reg.sw_share1_output[6].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (sw_share1_output_6_qs)
);
// Subregister 7 of Multireg sw_share1_output
// R[sw_share1_output_7]: V(False)
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRC),
.RESVAL (32'h0)
) u_sw_share1_output_7 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sw_share1_output_7_re),
.wd (sw_share1_output_7_wd),
// from internal hardware
.de (hw2reg.sw_share1_output[7].de),
.d (hw2reg.sw_share1_output[7].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (sw_share1_output_7_qs)
);
// R[working_state]: V(False)
prim_subreg #(
.DW (3),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (3'h0)
) u_working_state (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.working_state.de),
.d (hw2reg.working_state.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (working_state_qs)
);
// R[op_status]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (2'h0)
) u_op_status (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (op_status_we),
.wd (op_status_wd),
// from internal hardware
.de (hw2reg.op_status.de),
.d (hw2reg.op_status.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (op_status_qs)
);
// R[err_code]: V(False)
// F[invalid_op]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_err_code_invalid_op (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (err_code_we),
.wd (err_code_invalid_op_wd),
// from internal hardware
.de (hw2reg.err_code.invalid_op.de),
.d (hw2reg.err_code.invalid_op.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (err_code_invalid_op_qs)
);
// F[invalid_kmac_input]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_err_code_invalid_kmac_input (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (err_code_we),
.wd (err_code_invalid_kmac_input_wd),
// from internal hardware
.de (hw2reg.err_code.invalid_kmac_input.de),
.d (hw2reg.err_code.invalid_kmac_input.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (err_code_invalid_kmac_input_qs)
);
// F[invalid_shadow_update]: 2:2
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_err_code_invalid_shadow_update (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (err_code_we),
.wd (err_code_invalid_shadow_update_wd),
// from internal hardware
.de (hw2reg.err_code.invalid_shadow_update.de),
.d (hw2reg.err_code.invalid_shadow_update.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (err_code_invalid_shadow_update_qs)
);
// R[fault_status]: V(False)
// F[cmd]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_fault_status_cmd (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.fault_status.cmd.de),
.d (hw2reg.fault_status.cmd.d),
// to internal hardware
.qe (),
.q (reg2hw.fault_status.cmd.q),
.ds (),
// to register interface (read)
.qs (fault_status_cmd_qs)
);
// F[kmac_fsm]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_fault_status_kmac_fsm (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.fault_status.kmac_fsm.de),
.d (hw2reg.fault_status.kmac_fsm.d),
// to internal hardware
.qe (),
.q (reg2hw.fault_status.kmac_fsm.q),
.ds (),
// to register interface (read)
.qs (fault_status_kmac_fsm_qs)
);
// F[kmac_done]: 2:2
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_fault_status_kmac_done (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.fault_status.kmac_done.de),
.d (hw2reg.fault_status.kmac_done.d),
// to internal hardware
.qe (),
.q (reg2hw.fault_status.kmac_done.q),
.ds (),
// to register interface (read)
.qs (fault_status_kmac_done_qs)
);
// F[kmac_op]: 3:3
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_fault_status_kmac_op (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.fault_status.kmac_op.de),
.d (hw2reg.fault_status.kmac_op.d),
// to internal hardware
.qe (),
.q (reg2hw.fault_status.kmac_op.q),
.ds (),
// to register interface (read)
.qs (fault_status_kmac_op_qs)
);
// F[kmac_out]: 4:4
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_fault_status_kmac_out (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.fault_status.kmac_out.de),
.d (hw2reg.fault_status.kmac_out.d),
// to internal hardware
.qe (),
.q (reg2hw.fault_status.kmac_out.q),
.ds (),
// to register interface (read)
.qs (fault_status_kmac_out_qs)
);
// F[regfile_intg]: 5:5
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_fault_status_regfile_intg (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.fault_status.regfile_intg.de),
.d (hw2reg.fault_status.regfile_intg.d),
// to internal hardware
.qe (),
.q (reg2hw.fault_status.regfile_intg.q),
.ds (),
// to register interface (read)
.qs (fault_status_regfile_intg_qs)
);
// F[shadow]: 6:6
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_fault_status_shadow (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.fault_status.shadow.de),
.d (hw2reg.fault_status.shadow.d),
// to internal hardware
.qe (),
.q (reg2hw.fault_status.shadow.q),
.ds (),
// to register interface (read)
.qs (fault_status_shadow_qs)
);
// F[ctrl_fsm_intg]: 7:7
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_fault_status_ctrl_fsm_intg (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.fault_status.ctrl_fsm_intg.de),
.d (hw2reg.fault_status.ctrl_fsm_intg.d),
// to internal hardware
.qe (),
.q (reg2hw.fault_status.ctrl_fsm_intg.q),
.ds (),
// to register interface (read)
.qs (fault_status_ctrl_fsm_intg_qs)
);
// F[ctrl_fsm_chk]: 8:8
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_fault_status_ctrl_fsm_chk (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.fault_status.ctrl_fsm_chk.de),
.d (hw2reg.fault_status.ctrl_fsm_chk.d),
// to internal hardware
.qe (),
.q (reg2hw.fault_status.ctrl_fsm_chk.q),
.ds (),
// to register interface (read)
.qs (fault_status_ctrl_fsm_chk_qs)
);
// F[ctrl_fsm_cnt]: 9:9
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_fault_status_ctrl_fsm_cnt (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.fault_status.ctrl_fsm_cnt.de),
.d (hw2reg.fault_status.ctrl_fsm_cnt.d),
// to internal hardware
.qe (),
.q (reg2hw.fault_status.ctrl_fsm_cnt.q),
.ds (),
// to register interface (read)
.qs (fault_status_ctrl_fsm_cnt_qs)
);
// F[reseed_cnt]: 10:10
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_fault_status_reseed_cnt (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.fault_status.reseed_cnt.de),
.d (hw2reg.fault_status.reseed_cnt.d),
// to internal hardware
.qe (),
.q (reg2hw.fault_status.reseed_cnt.q),
.ds (),
// to register interface (read)
.qs (fault_status_reseed_cnt_qs)
);
// F[side_ctrl_fsm]: 11:11
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_fault_status_side_ctrl_fsm (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.fault_status.side_ctrl_fsm.de),
.d (hw2reg.fault_status.side_ctrl_fsm.d),
// to internal hardware
.qe (),
.q (reg2hw.fault_status.side_ctrl_fsm.q),
.ds (),
// to register interface (read)
.qs (fault_status_side_ctrl_fsm_qs)
);
// F[side_ctrl_sel]: 12:12
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_fault_status_side_ctrl_sel (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.fault_status.side_ctrl_sel.de),
.d (hw2reg.fault_status.side_ctrl_sel.d),
// to internal hardware
.qe (),
.q (reg2hw.fault_status.side_ctrl_sel.q),
.ds (),
// to register interface (read)
.qs (fault_status_side_ctrl_sel_qs)
);
// F[key_ecc]: 13:13
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_fault_status_key_ecc (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.fault_status.key_ecc.de),
.d (hw2reg.fault_status.key_ecc.d),
// to internal hardware
.qe (),
.q (reg2hw.fault_status.key_ecc.q),
.ds (),
// to register interface (read)
.qs (fault_status_key_ecc_qs)
);
// R[debug]: V(False)
// F[invalid_creator_seed]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_debug_invalid_creator_seed (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (debug_we),
.wd (debug_invalid_creator_seed_wd),
// from internal hardware
.de (hw2reg.debug.invalid_creator_seed.de),
.d (hw2reg.debug.invalid_creator_seed.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (debug_invalid_creator_seed_qs)
);
// F[invalid_owner_seed]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_debug_invalid_owner_seed (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (debug_we),
.wd (debug_invalid_owner_seed_wd),
// from internal hardware
.de (hw2reg.debug.invalid_owner_seed.de),
.d (hw2reg.debug.invalid_owner_seed.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (debug_invalid_owner_seed_qs)
);
// F[invalid_dev_id]: 2:2
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_debug_invalid_dev_id (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (debug_we),
.wd (debug_invalid_dev_id_wd),
// from internal hardware
.de (hw2reg.debug.invalid_dev_id.de),
.d (hw2reg.debug.invalid_dev_id.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (debug_invalid_dev_id_qs)
);
// F[invalid_health_state]: 3:3
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_debug_invalid_health_state (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (debug_we),
.wd (debug_invalid_health_state_wd),
// from internal hardware
.de (hw2reg.debug.invalid_health_state.de),
.d (hw2reg.debug.invalid_health_state.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (debug_invalid_health_state_qs)
);
// F[invalid_key_version]: 4:4
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_debug_invalid_key_version (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (debug_we),
.wd (debug_invalid_key_version_wd),
// from internal hardware
.de (hw2reg.debug.invalid_key_version.de),
.d (hw2reg.debug.invalid_key_version.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (debug_invalid_key_version_qs)
);
// F[invalid_key]: 5:5
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_debug_invalid_key (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (debug_we),
.wd (debug_invalid_key_wd),
// from internal hardware
.de (hw2reg.debug.invalid_key.de),
.d (hw2reg.debug.invalid_key.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (debug_invalid_key_qs)
);
// F[invalid_digest]: 6:6
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_debug_invalid_digest (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (debug_we),
.wd (debug_invalid_digest_wd),
// from internal hardware
.de (hw2reg.debug.invalid_digest.de),
.d (hw2reg.debug.invalid_digest.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (debug_invalid_digest_qs)
);
logic [62:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == KEYMGR_INTR_STATE_OFFSET);
addr_hit[ 1] = (reg_addr == KEYMGR_INTR_ENABLE_OFFSET);
addr_hit[ 2] = (reg_addr == KEYMGR_INTR_TEST_OFFSET);
addr_hit[ 3] = (reg_addr == KEYMGR_ALERT_TEST_OFFSET);
addr_hit[ 4] = (reg_addr == KEYMGR_CFG_REGWEN_OFFSET);
addr_hit[ 5] = (reg_addr == KEYMGR_START_OFFSET);
addr_hit[ 6] = (reg_addr == KEYMGR_CONTROL_SHADOWED_OFFSET);
addr_hit[ 7] = (reg_addr == KEYMGR_SIDELOAD_CLEAR_OFFSET);
addr_hit[ 8] = (reg_addr == KEYMGR_RESEED_INTERVAL_REGWEN_OFFSET);
addr_hit[ 9] = (reg_addr == KEYMGR_RESEED_INTERVAL_SHADOWED_OFFSET);
addr_hit[10] = (reg_addr == KEYMGR_SW_BINDING_REGWEN_OFFSET);
addr_hit[11] = (reg_addr == KEYMGR_SEALING_SW_BINDING_0_OFFSET);
addr_hit[12] = (reg_addr == KEYMGR_SEALING_SW_BINDING_1_OFFSET);
addr_hit[13] = (reg_addr == KEYMGR_SEALING_SW_BINDING_2_OFFSET);
addr_hit[14] = (reg_addr == KEYMGR_SEALING_SW_BINDING_3_OFFSET);
addr_hit[15] = (reg_addr == KEYMGR_SEALING_SW_BINDING_4_OFFSET);
addr_hit[16] = (reg_addr == KEYMGR_SEALING_SW_BINDING_5_OFFSET);
addr_hit[17] = (reg_addr == KEYMGR_SEALING_SW_BINDING_6_OFFSET);
addr_hit[18] = (reg_addr == KEYMGR_SEALING_SW_BINDING_7_OFFSET);
addr_hit[19] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_0_OFFSET);
addr_hit[20] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_1_OFFSET);
addr_hit[21] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_2_OFFSET);
addr_hit[22] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_3_OFFSET);
addr_hit[23] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_4_OFFSET);
addr_hit[24] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_5_OFFSET);
addr_hit[25] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_6_OFFSET);
addr_hit[26] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_7_OFFSET);
addr_hit[27] = (reg_addr == KEYMGR_SALT_0_OFFSET);
addr_hit[28] = (reg_addr == KEYMGR_SALT_1_OFFSET);
addr_hit[29] = (reg_addr == KEYMGR_SALT_2_OFFSET);
addr_hit[30] = (reg_addr == KEYMGR_SALT_3_OFFSET);
addr_hit[31] = (reg_addr == KEYMGR_SALT_4_OFFSET);
addr_hit[32] = (reg_addr == KEYMGR_SALT_5_OFFSET);
addr_hit[33] = (reg_addr == KEYMGR_SALT_6_OFFSET);
addr_hit[34] = (reg_addr == KEYMGR_SALT_7_OFFSET);
addr_hit[35] = (reg_addr == KEYMGR_KEY_VERSION_OFFSET);
addr_hit[36] = (reg_addr == KEYMGR_MAX_CREATOR_KEY_VER_REGWEN_OFFSET);
addr_hit[37] = (reg_addr == KEYMGR_MAX_CREATOR_KEY_VER_SHADOWED_OFFSET);
addr_hit[38] = (reg_addr == KEYMGR_MAX_OWNER_INT_KEY_VER_REGWEN_OFFSET);
addr_hit[39] = (reg_addr == KEYMGR_MAX_OWNER_INT_KEY_VER_SHADOWED_OFFSET);
addr_hit[40] = (reg_addr == KEYMGR_MAX_OWNER_KEY_VER_REGWEN_OFFSET);
addr_hit[41] = (reg_addr == KEYMGR_MAX_OWNER_KEY_VER_SHADOWED_OFFSET);
addr_hit[42] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_0_OFFSET);
addr_hit[43] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_1_OFFSET);
addr_hit[44] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_2_OFFSET);
addr_hit[45] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_3_OFFSET);
addr_hit[46] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_4_OFFSET);
addr_hit[47] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_5_OFFSET);
addr_hit[48] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_6_OFFSET);
addr_hit[49] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_7_OFFSET);
addr_hit[50] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_0_OFFSET);
addr_hit[51] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_1_OFFSET);
addr_hit[52] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_2_OFFSET);
addr_hit[53] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_3_OFFSET);
addr_hit[54] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_4_OFFSET);
addr_hit[55] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_5_OFFSET);
addr_hit[56] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_6_OFFSET);
addr_hit[57] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_7_OFFSET);
addr_hit[58] = (reg_addr == KEYMGR_WORKING_STATE_OFFSET);
addr_hit[59] = (reg_addr == KEYMGR_OP_STATUS_OFFSET);
addr_hit[60] = (reg_addr == KEYMGR_ERR_CODE_OFFSET);
addr_hit[61] = (reg_addr == KEYMGR_FAULT_STATUS_OFFSET);
addr_hit[62] = (reg_addr == KEYMGR_DEBUG_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
// Check sub-word write is permitted
always_comb begin
wr_err = (reg_we &
((addr_hit[ 0] & (|(KEYMGR_PERMIT[ 0] & ~reg_be))) |
(addr_hit[ 1] & (|(KEYMGR_PERMIT[ 1] & ~reg_be))) |
(addr_hit[ 2] & (|(KEYMGR_PERMIT[ 2] & ~reg_be))) |
(addr_hit[ 3] & (|(KEYMGR_PERMIT[ 3] & ~reg_be))) |
(addr_hit[ 4] & (|(KEYMGR_PERMIT[ 4] & ~reg_be))) |
(addr_hit[ 5] & (|(KEYMGR_PERMIT[ 5] & ~reg_be))) |
(addr_hit[ 6] & (|(KEYMGR_PERMIT[ 6] & ~reg_be))) |
(addr_hit[ 7] & (|(KEYMGR_PERMIT[ 7] & ~reg_be))) |
(addr_hit[ 8] & (|(KEYMGR_PERMIT[ 8] & ~reg_be))) |
(addr_hit[ 9] & (|(KEYMGR_PERMIT[ 9] & ~reg_be))) |
(addr_hit[10] & (|(KEYMGR_PERMIT[10] & ~reg_be))) |
(addr_hit[11] & (|(KEYMGR_PERMIT[11] & ~reg_be))) |
(addr_hit[12] & (|(KEYMGR_PERMIT[12] & ~reg_be))) |
(addr_hit[13] & (|(KEYMGR_PERMIT[13] & ~reg_be))) |
(addr_hit[14] & (|(KEYMGR_PERMIT[14] & ~reg_be))) |
(addr_hit[15] & (|(KEYMGR_PERMIT[15] & ~reg_be))) |
(addr_hit[16] & (|(KEYMGR_PERMIT[16] & ~reg_be))) |
(addr_hit[17] & (|(KEYMGR_PERMIT[17] & ~reg_be))) |
(addr_hit[18] & (|(KEYMGR_PERMIT[18] & ~reg_be))) |
(addr_hit[19] & (|(KEYMGR_PERMIT[19] & ~reg_be))) |
(addr_hit[20] & (|(KEYMGR_PERMIT[20] & ~reg_be))) |
(addr_hit[21] & (|(KEYMGR_PERMIT[21] & ~reg_be))) |
(addr_hit[22] & (|(KEYMGR_PERMIT[22] & ~reg_be))) |
(addr_hit[23] & (|(KEYMGR_PERMIT[23] & ~reg_be))) |
(addr_hit[24] & (|(KEYMGR_PERMIT[24] & ~reg_be))) |
(addr_hit[25] & (|(KEYMGR_PERMIT[25] & ~reg_be))) |
(addr_hit[26] & (|(KEYMGR_PERMIT[26] & ~reg_be))) |
(addr_hit[27] & (|(KEYMGR_PERMIT[27] & ~reg_be))) |
(addr_hit[28] & (|(KEYMGR_PERMIT[28] & ~reg_be))) |
(addr_hit[29] & (|(KEYMGR_PERMIT[29] & ~reg_be))) |
(addr_hit[30] & (|(KEYMGR_PERMIT[30] & ~reg_be))) |
(addr_hit[31] & (|(KEYMGR_PERMIT[31] & ~reg_be))) |
(addr_hit[32] & (|(KEYMGR_PERMIT[32] & ~reg_be))) |
(addr_hit[33] & (|(KEYMGR_PERMIT[33] & ~reg_be))) |
(addr_hit[34] & (|(KEYMGR_PERMIT[34] & ~reg_be))) |
(addr_hit[35] & (|(KEYMGR_PERMIT[35] & ~reg_be))) |
(addr_hit[36] & (|(KEYMGR_PERMIT[36] & ~reg_be))) |
(addr_hit[37] & (|(KEYMGR_PERMIT[37] & ~reg_be))) |
(addr_hit[38] & (|(KEYMGR_PERMIT[38] & ~reg_be))) |
(addr_hit[39] & (|(KEYMGR_PERMIT[39] & ~reg_be))) |
(addr_hit[40] & (|(KEYMGR_PERMIT[40] & ~reg_be))) |
(addr_hit[41] & (|(KEYMGR_PERMIT[41] & ~reg_be))) |
(addr_hit[42] & (|(KEYMGR_PERMIT[42] & ~reg_be))) |
(addr_hit[43] & (|(KEYMGR_PERMIT[43] & ~reg_be))) |
(addr_hit[44] & (|(KEYMGR_PERMIT[44] & ~reg_be))) |
(addr_hit[45] & (|(KEYMGR_PERMIT[45] & ~reg_be))) |
(addr_hit[46] & (|(KEYMGR_PERMIT[46] & ~reg_be))) |
(addr_hit[47] & (|(KEYMGR_PERMIT[47] & ~reg_be))) |
(addr_hit[48] & (|(KEYMGR_PERMIT[48] & ~reg_be))) |
(addr_hit[49] & (|(KEYMGR_PERMIT[49] & ~reg_be))) |
(addr_hit[50] & (|(KEYMGR_PERMIT[50] & ~reg_be))) |
(addr_hit[51] & (|(KEYMGR_PERMIT[51] & ~reg_be))) |
(addr_hit[52] & (|(KEYMGR_PERMIT[52] & ~reg_be))) |
(addr_hit[53] & (|(KEYMGR_PERMIT[53] & ~reg_be))) |
(addr_hit[54] & (|(KEYMGR_PERMIT[54] & ~reg_be))) |
(addr_hit[55] & (|(KEYMGR_PERMIT[55] & ~reg_be))) |
(addr_hit[56] & (|(KEYMGR_PERMIT[56] & ~reg_be))) |
(addr_hit[57] & (|(KEYMGR_PERMIT[57] & ~reg_be))) |
(addr_hit[58] & (|(KEYMGR_PERMIT[58] & ~reg_be))) |
(addr_hit[59] & (|(KEYMGR_PERMIT[59] & ~reg_be))) |
(addr_hit[60] & (|(KEYMGR_PERMIT[60] & ~reg_be))) |
(addr_hit[61] & (|(KEYMGR_PERMIT[61] & ~reg_be))) |
(addr_hit[62] & (|(KEYMGR_PERMIT[62] & ~reg_be)))));
end
// Generate write-enables
assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
assign intr_state_wd = reg_wdata[0];
assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
assign intr_enable_wd = reg_wdata[0];
assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
assign intr_test_wd = reg_wdata[0];
assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
assign alert_test_recov_operation_err_wd = reg_wdata[0];
assign alert_test_fatal_fault_err_wd = reg_wdata[1];
assign cfg_regwen_re = addr_hit[4] & reg_re & !reg_error;
assign start_we = addr_hit[5] & reg_we & !reg_error;
assign start_wd = reg_wdata[0];
assign control_shadowed_re = addr_hit[6] & reg_re & !reg_error;
assign control_shadowed_we = addr_hit[6] & reg_we & !reg_error;
assign control_shadowed_operation_wd = reg_wdata[6:4];
assign control_shadowed_cdi_sel_wd = reg_wdata[7];
assign control_shadowed_dest_sel_wd = reg_wdata[13:12];
assign sideload_clear_we = addr_hit[7] & reg_we & !reg_error;
assign sideload_clear_wd = reg_wdata[2:0];
assign reseed_interval_regwen_we = addr_hit[8] & reg_we & !reg_error;
assign reseed_interval_regwen_wd = reg_wdata[0];
assign reseed_interval_shadowed_re = addr_hit[9] & reg_re & !reg_error;
assign reseed_interval_shadowed_we = addr_hit[9] & reg_we & !reg_error;
assign reseed_interval_shadowed_wd = reg_wdata[15:0];
assign sw_binding_regwen_re = addr_hit[10] & reg_re & !reg_error;
assign sw_binding_regwen_we = addr_hit[10] & reg_we & !reg_error;
assign sw_binding_regwen_wd = reg_wdata[0];
assign sealing_sw_binding_0_we = addr_hit[11] & reg_we & !reg_error;
assign sealing_sw_binding_0_wd = reg_wdata[31:0];
assign sealing_sw_binding_1_we = addr_hit[12] & reg_we & !reg_error;
assign sealing_sw_binding_1_wd = reg_wdata[31:0];
assign sealing_sw_binding_2_we = addr_hit[13] & reg_we & !reg_error;
assign sealing_sw_binding_2_wd = reg_wdata[31:0];
assign sealing_sw_binding_3_we = addr_hit[14] & reg_we & !reg_error;
assign sealing_sw_binding_3_wd = reg_wdata[31:0];
assign sealing_sw_binding_4_we = addr_hit[15] & reg_we & !reg_error;
assign sealing_sw_binding_4_wd = reg_wdata[31:0];
assign sealing_sw_binding_5_we = addr_hit[16] & reg_we & !reg_error;
assign sealing_sw_binding_5_wd = reg_wdata[31:0];
assign sealing_sw_binding_6_we = addr_hit[17] & reg_we & !reg_error;
assign sealing_sw_binding_6_wd = reg_wdata[31:0];
assign sealing_sw_binding_7_we = addr_hit[18] & reg_we & !reg_error;
assign sealing_sw_binding_7_wd = reg_wdata[31:0];
assign attest_sw_binding_0_we = addr_hit[19] & reg_we & !reg_error;
assign attest_sw_binding_0_wd = reg_wdata[31:0];
assign attest_sw_binding_1_we = addr_hit[20] & reg_we & !reg_error;
assign attest_sw_binding_1_wd = reg_wdata[31:0];
assign attest_sw_binding_2_we = addr_hit[21] & reg_we & !reg_error;
assign attest_sw_binding_2_wd = reg_wdata[31:0];
assign attest_sw_binding_3_we = addr_hit[22] & reg_we & !reg_error;
assign attest_sw_binding_3_wd = reg_wdata[31:0];
assign attest_sw_binding_4_we = addr_hit[23] & reg_we & !reg_error;
assign attest_sw_binding_4_wd = reg_wdata[31:0];
assign attest_sw_binding_5_we = addr_hit[24] & reg_we & !reg_error;
assign attest_sw_binding_5_wd = reg_wdata[31:0];
assign attest_sw_binding_6_we = addr_hit[25] & reg_we & !reg_error;
assign attest_sw_binding_6_wd = reg_wdata[31:0];
assign attest_sw_binding_7_we = addr_hit[26] & reg_we & !reg_error;
assign attest_sw_binding_7_wd = reg_wdata[31:0];
assign salt_0_we = addr_hit[27] & reg_we & !reg_error;
assign salt_0_wd = reg_wdata[31:0];
assign salt_1_we = addr_hit[28] & reg_we & !reg_error;
assign salt_1_wd = reg_wdata[31:0];
assign salt_2_we = addr_hit[29] & reg_we & !reg_error;
assign salt_2_wd = reg_wdata[31:0];
assign salt_3_we = addr_hit[30] & reg_we & !reg_error;
assign salt_3_wd = reg_wdata[31:0];
assign salt_4_we = addr_hit[31] & reg_we & !reg_error;
assign salt_4_wd = reg_wdata[31:0];
assign salt_5_we = addr_hit[32] & reg_we & !reg_error;
assign salt_5_wd = reg_wdata[31:0];
assign salt_6_we = addr_hit[33] & reg_we & !reg_error;
assign salt_6_wd = reg_wdata[31:0];
assign salt_7_we = addr_hit[34] & reg_we & !reg_error;
assign salt_7_wd = reg_wdata[31:0];
assign key_version_we = addr_hit[35] & reg_we & !reg_error;
assign key_version_wd = reg_wdata[31:0];
assign max_creator_key_ver_regwen_we = addr_hit[36] & reg_we & !reg_error;
assign max_creator_key_ver_regwen_wd = reg_wdata[0];
assign max_creator_key_ver_shadowed_re = addr_hit[37] & reg_re & !reg_error;
assign max_creator_key_ver_shadowed_we = addr_hit[37] & reg_we & !reg_error;
assign max_creator_key_ver_shadowed_wd = reg_wdata[31:0];
assign max_owner_int_key_ver_regwen_we = addr_hit[38] & reg_we & !reg_error;
assign max_owner_int_key_ver_regwen_wd = reg_wdata[0];
assign max_owner_int_key_ver_shadowed_re = addr_hit[39] & reg_re & !reg_error;
assign max_owner_int_key_ver_shadowed_we = addr_hit[39] & reg_we & !reg_error;
assign max_owner_int_key_ver_shadowed_wd = reg_wdata[31:0];
assign max_owner_key_ver_regwen_we = addr_hit[40] & reg_we & !reg_error;
assign max_owner_key_ver_regwen_wd = reg_wdata[0];
assign max_owner_key_ver_shadowed_re = addr_hit[41] & reg_re & !reg_error;
assign max_owner_key_ver_shadowed_we = addr_hit[41] & reg_we & !reg_error;
assign max_owner_key_ver_shadowed_wd = reg_wdata[31:0];
assign sw_share0_output_0_re = addr_hit[42] & reg_re & !reg_error;
assign sw_share0_output_0_wd = '1;
assign sw_share0_output_1_re = addr_hit[43] & reg_re & !reg_error;
assign sw_share0_output_1_wd = '1;
assign sw_share0_output_2_re = addr_hit[44] & reg_re & !reg_error;
assign sw_share0_output_2_wd = '1;
assign sw_share0_output_3_re = addr_hit[45] & reg_re & !reg_error;
assign sw_share0_output_3_wd = '1;
assign sw_share0_output_4_re = addr_hit[46] & reg_re & !reg_error;
assign sw_share0_output_4_wd = '1;
assign sw_share0_output_5_re = addr_hit[47] & reg_re & !reg_error;
assign sw_share0_output_5_wd = '1;
assign sw_share0_output_6_re = addr_hit[48] & reg_re & !reg_error;
assign sw_share0_output_6_wd = '1;
assign sw_share0_output_7_re = addr_hit[49] & reg_re & !reg_error;
assign sw_share0_output_7_wd = '1;
assign sw_share1_output_0_re = addr_hit[50] & reg_re & !reg_error;
assign sw_share1_output_0_wd = '1;
assign sw_share1_output_1_re = addr_hit[51] & reg_re & !reg_error;
assign sw_share1_output_1_wd = '1;
assign sw_share1_output_2_re = addr_hit[52] & reg_re & !reg_error;
assign sw_share1_output_2_wd = '1;
assign sw_share1_output_3_re = addr_hit[53] & reg_re & !reg_error;
assign sw_share1_output_3_wd = '1;
assign sw_share1_output_4_re = addr_hit[54] & reg_re & !reg_error;
assign sw_share1_output_4_wd = '1;
assign sw_share1_output_5_re = addr_hit[55] & reg_re & !reg_error;
assign sw_share1_output_5_wd = '1;
assign sw_share1_output_6_re = addr_hit[56] & reg_re & !reg_error;
assign sw_share1_output_6_wd = '1;
assign sw_share1_output_7_re = addr_hit[57] & reg_re & !reg_error;
assign sw_share1_output_7_wd = '1;
assign op_status_we = addr_hit[59] & reg_we & !reg_error;
assign op_status_wd = reg_wdata[1:0];
assign err_code_we = addr_hit[60] & reg_we & !reg_error;
assign err_code_invalid_op_wd = reg_wdata[0];
assign err_code_invalid_kmac_input_wd = reg_wdata[1];
assign err_code_invalid_shadow_update_wd = reg_wdata[2];
assign debug_we = addr_hit[62] & reg_we & !reg_error;
assign debug_invalid_creator_seed_wd = reg_wdata[0];
assign debug_invalid_owner_seed_wd = reg_wdata[1];
assign debug_invalid_dev_id_wd = reg_wdata[2];
assign debug_invalid_health_state_wd = reg_wdata[3];
assign debug_invalid_key_version_wd = reg_wdata[4];
assign debug_invalid_key_wd = reg_wdata[5];
assign debug_invalid_digest_wd = reg_wdata[6];
// Assign write-enables to checker logic vector.
always_comb begin
reg_we_check = '0;
reg_we_check[0] = intr_state_we;
reg_we_check[1] = intr_enable_we;
reg_we_check[2] = intr_test_we;
reg_we_check[3] = alert_test_we;
reg_we_check[4] = 1'b0;
reg_we_check[5] = start_gated_we;
reg_we_check[6] = control_shadowed_gated_we;
reg_we_check[7] = sideload_clear_gated_we;
reg_we_check[8] = reseed_interval_regwen_we;
reg_we_check[9] = reseed_interval_shadowed_gated_we;
reg_we_check[10] = sw_binding_regwen_we;
reg_we_check[11] = sealing_sw_binding_0_gated_we;
reg_we_check[12] = sealing_sw_binding_1_gated_we;
reg_we_check[13] = sealing_sw_binding_2_gated_we;
reg_we_check[14] = sealing_sw_binding_3_gated_we;
reg_we_check[15] = sealing_sw_binding_4_gated_we;
reg_we_check[16] = sealing_sw_binding_5_gated_we;
reg_we_check[17] = sealing_sw_binding_6_gated_we;
reg_we_check[18] = sealing_sw_binding_7_gated_we;
reg_we_check[19] = attest_sw_binding_0_gated_we;
reg_we_check[20] = attest_sw_binding_1_gated_we;
reg_we_check[21] = attest_sw_binding_2_gated_we;
reg_we_check[22] = attest_sw_binding_3_gated_we;
reg_we_check[23] = attest_sw_binding_4_gated_we;
reg_we_check[24] = attest_sw_binding_5_gated_we;
reg_we_check[25] = attest_sw_binding_6_gated_we;
reg_we_check[26] = attest_sw_binding_7_gated_we;
reg_we_check[27] = salt_0_gated_we;
reg_we_check[28] = salt_1_gated_we;
reg_we_check[29] = salt_2_gated_we;
reg_we_check[30] = salt_3_gated_we;
reg_we_check[31] = salt_4_gated_we;
reg_we_check[32] = salt_5_gated_we;
reg_we_check[33] = salt_6_gated_we;
reg_we_check[34] = salt_7_gated_we;
reg_we_check[35] = key_version_gated_we;
reg_we_check[36] = max_creator_key_ver_regwen_we;
reg_we_check[37] = max_creator_key_ver_shadowed_gated_we;
reg_we_check[38] = max_owner_int_key_ver_regwen_we;
reg_we_check[39] = max_owner_int_key_ver_shadowed_gated_we;
reg_we_check[40] = max_owner_key_ver_regwen_we;
reg_we_check[41] = max_owner_key_ver_shadowed_gated_we;
reg_we_check[42] = 1'b0;
reg_we_check[43] = 1'b0;
reg_we_check[44] = 1'b0;
reg_we_check[45] = 1'b0;
reg_we_check[46] = 1'b0;
reg_we_check[47] = 1'b0;
reg_we_check[48] = 1'b0;
reg_we_check[49] = 1'b0;
reg_we_check[50] = 1'b0;
reg_we_check[51] = 1'b0;
reg_we_check[52] = 1'b0;
reg_we_check[53] = 1'b0;
reg_we_check[54] = 1'b0;
reg_we_check[55] = 1'b0;
reg_we_check[56] = 1'b0;
reg_we_check[57] = 1'b0;
reg_we_check[58] = 1'b0;
reg_we_check[59] = op_status_we;
reg_we_check[60] = err_code_we;
reg_we_check[61] = 1'b0;
reg_we_check[62] = debug_we;
end
// Read data return
always_comb begin
reg_rdata_next = '0;
unique case (1'b1)
addr_hit[0]: begin
reg_rdata_next[0] = intr_state_qs;
end
addr_hit[1]: begin
reg_rdata_next[0] = intr_enable_qs;
end
addr_hit[2]: begin
reg_rdata_next[0] = '0;
end
addr_hit[3]: begin
reg_rdata_next[0] = '0;
reg_rdata_next[1] = '0;
end
addr_hit[4]: begin
reg_rdata_next[0] = cfg_regwen_qs;
end
addr_hit[5]: begin
reg_rdata_next[0] = start_qs;
end
addr_hit[6]: begin
reg_rdata_next[6:4] = control_shadowed_operation_qs;
reg_rdata_next[7] = control_shadowed_cdi_sel_qs;
reg_rdata_next[13:12] = control_shadowed_dest_sel_qs;
end
addr_hit[7]: begin
reg_rdata_next[2:0] = sideload_clear_qs;
end
addr_hit[8]: begin
reg_rdata_next[0] = reseed_interval_regwen_qs;
end
addr_hit[9]: begin
reg_rdata_next[15:0] = reseed_interval_shadowed_qs;
end
addr_hit[10]: begin
reg_rdata_next[0] = sw_binding_regwen_qs;
end
addr_hit[11]: begin
reg_rdata_next[31:0] = sealing_sw_binding_0_qs;
end
addr_hit[12]: begin
reg_rdata_next[31:0] = sealing_sw_binding_1_qs;
end
addr_hit[13]: begin
reg_rdata_next[31:0] = sealing_sw_binding_2_qs;
end
addr_hit[14]: begin
reg_rdata_next[31:0] = sealing_sw_binding_3_qs;
end
addr_hit[15]: begin
reg_rdata_next[31:0] = sealing_sw_binding_4_qs;
end
addr_hit[16]: begin
reg_rdata_next[31:0] = sealing_sw_binding_5_qs;
end
addr_hit[17]: begin
reg_rdata_next[31:0] = sealing_sw_binding_6_qs;
end
addr_hit[18]: begin
reg_rdata_next[31:0] = sealing_sw_binding_7_qs;
end
addr_hit[19]: begin
reg_rdata_next[31:0] = attest_sw_binding_0_qs;
end
addr_hit[20]: begin
reg_rdata_next[31:0] = attest_sw_binding_1_qs;
end
addr_hit[21]: begin
reg_rdata_next[31:0] = attest_sw_binding_2_qs;
end
addr_hit[22]: begin
reg_rdata_next[31:0] = attest_sw_binding_3_qs;
end
addr_hit[23]: begin
reg_rdata_next[31:0] = attest_sw_binding_4_qs;
end
addr_hit[24]: begin
reg_rdata_next[31:0] = attest_sw_binding_5_qs;
end
addr_hit[25]: begin
reg_rdata_next[31:0] = attest_sw_binding_6_qs;
end
addr_hit[26]: begin
reg_rdata_next[31:0] = attest_sw_binding_7_qs;
end
addr_hit[27]: begin
reg_rdata_next[31:0] = salt_0_qs;
end
addr_hit[28]: begin
reg_rdata_next[31:0] = salt_1_qs;
end
addr_hit[29]: begin
reg_rdata_next[31:0] = salt_2_qs;
end
addr_hit[30]: begin
reg_rdata_next[31:0] = salt_3_qs;
end
addr_hit[31]: begin
reg_rdata_next[31:0] = salt_4_qs;
end
addr_hit[32]: begin
reg_rdata_next[31:0] = salt_5_qs;
end
addr_hit[33]: begin
reg_rdata_next[31:0] = salt_6_qs;
end
addr_hit[34]: begin
reg_rdata_next[31:0] = salt_7_qs;
end
addr_hit[35]: begin
reg_rdata_next[31:0] = key_version_qs;
end
addr_hit[36]: begin
reg_rdata_next[0] = max_creator_key_ver_regwen_qs;
end
addr_hit[37]: begin
reg_rdata_next[31:0] = max_creator_key_ver_shadowed_qs;
end
addr_hit[38]: begin
reg_rdata_next[0] = max_owner_int_key_ver_regwen_qs;
end
addr_hit[39]: begin
reg_rdata_next[31:0] = max_owner_int_key_ver_shadowed_qs;
end
addr_hit[40]: begin
reg_rdata_next[0] = max_owner_key_ver_regwen_qs;
end
addr_hit[41]: begin
reg_rdata_next[31:0] = max_owner_key_ver_shadowed_qs;
end
addr_hit[42]: begin
reg_rdata_next[31:0] = sw_share0_output_0_qs;
end
addr_hit[43]: begin
reg_rdata_next[31:0] = sw_share0_output_1_qs;
end
addr_hit[44]: begin
reg_rdata_next[31:0] = sw_share0_output_2_qs;
end
addr_hit[45]: begin
reg_rdata_next[31:0] = sw_share0_output_3_qs;
end
addr_hit[46]: begin
reg_rdata_next[31:0] = sw_share0_output_4_qs;
end
addr_hit[47]: begin
reg_rdata_next[31:0] = sw_share0_output_5_qs;
end
addr_hit[48]: begin
reg_rdata_next[31:0] = sw_share0_output_6_qs;
end
addr_hit[49]: begin
reg_rdata_next[31:0] = sw_share0_output_7_qs;
end
addr_hit[50]: begin
reg_rdata_next[31:0] = sw_share1_output_0_qs;
end
addr_hit[51]: begin
reg_rdata_next[31:0] = sw_share1_output_1_qs;
end
addr_hit[52]: begin
reg_rdata_next[31:0] = sw_share1_output_2_qs;
end
addr_hit[53]: begin
reg_rdata_next[31:0] = sw_share1_output_3_qs;
end
addr_hit[54]: begin
reg_rdata_next[31:0] = sw_share1_output_4_qs;
end
addr_hit[55]: begin
reg_rdata_next[31:0] = sw_share1_output_5_qs;
end
addr_hit[56]: begin
reg_rdata_next[31:0] = sw_share1_output_6_qs;
end
addr_hit[57]: begin
reg_rdata_next[31:0] = sw_share1_output_7_qs;
end
addr_hit[58]: begin
reg_rdata_next[2:0] = working_state_qs;
end
addr_hit[59]: begin
reg_rdata_next[1:0] = op_status_qs;
end
addr_hit[60]: begin
reg_rdata_next[0] = err_code_invalid_op_qs;
reg_rdata_next[1] = err_code_invalid_kmac_input_qs;
reg_rdata_next[2] = err_code_invalid_shadow_update_qs;
end
addr_hit[61]: begin
reg_rdata_next[0] = fault_status_cmd_qs;
reg_rdata_next[1] = fault_status_kmac_fsm_qs;
reg_rdata_next[2] = fault_status_kmac_done_qs;
reg_rdata_next[3] = fault_status_kmac_op_qs;
reg_rdata_next[4] = fault_status_kmac_out_qs;
reg_rdata_next[5] = fault_status_regfile_intg_qs;
reg_rdata_next[6] = fault_status_shadow_qs;
reg_rdata_next[7] = fault_status_ctrl_fsm_intg_qs;
reg_rdata_next[8] = fault_status_ctrl_fsm_chk_qs;
reg_rdata_next[9] = fault_status_ctrl_fsm_cnt_qs;
reg_rdata_next[10] = fault_status_reseed_cnt_qs;
reg_rdata_next[11] = fault_status_side_ctrl_fsm_qs;
reg_rdata_next[12] = fault_status_side_ctrl_sel_qs;
reg_rdata_next[13] = fault_status_key_ecc_qs;
end
addr_hit[62]: begin
reg_rdata_next[0] = debug_invalid_creator_seed_qs;
reg_rdata_next[1] = debug_invalid_owner_seed_qs;
reg_rdata_next[2] = debug_invalid_dev_id_qs;
reg_rdata_next[3] = debug_invalid_health_state_qs;
reg_rdata_next[4] = debug_invalid_key_version_qs;
reg_rdata_next[5] = debug_invalid_key_qs;
reg_rdata_next[6] = debug_invalid_digest_qs;
end
default: begin
reg_rdata_next = '1;
end
endcase
end
// shadow busy
logic shadow_busy;
logic rst_done;
logic shadow_rst_done;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rst_done <= '0;
end else begin
rst_done <= 1'b1;
end
end
always_ff @(posedge clk_i or negedge rst_shadowed_ni) begin
if (!rst_shadowed_ni) begin
shadow_rst_done <= '0;
end else begin
shadow_rst_done <= 1'b1;
end
end
// both shadow and normal resets have been released
assign shadow_busy = ~(rst_done & shadow_rst_done);
// Collect up storage and update errors
assign shadowed_storage_err_o = |{
control_shadowed_operation_storage_err,
control_shadowed_cdi_sel_storage_err,
control_shadowed_dest_sel_storage_err,
reseed_interval_shadowed_storage_err,
max_creator_key_ver_shadowed_storage_err,
max_owner_int_key_ver_shadowed_storage_err,
max_owner_key_ver_shadowed_storage_err
};
assign shadowed_update_err_o = |{
control_shadowed_operation_update_err,
control_shadowed_cdi_sel_update_err,
control_shadowed_dest_sel_update_err,
reseed_interval_shadowed_update_err,
max_creator_key_ver_shadowed_update_err,
max_owner_int_key_ver_shadowed_update_err,
max_owner_key_ver_shadowed_update_err
};
// register busy
assign reg_busy = shadow_busy;
// Unused signal tieoff
// wdata / byte enable are not always fully used
// add a blanket unused statement to handle lint waivers
logic unused_wdata;
logic unused_be;
assign unused_wdata = ^reg_wdata;
assign unused_be = ^reg_be;
// Assertions for Register Interface
`ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
`ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
`ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)
`ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
// this is formulated as an assumption such that the FPV testbenches do disprove this
// property by mistake
//`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
endmodule