[dif] Refactor dif_gpio.h to use new-style names
Signed-off-by: Miguel Young de la Sota <mcyoung@google.com>
diff --git a/sw/device/boot_rom/bootstrap.c b/sw/device/boot_rom/bootstrap.c
index baa5588..41e507c 100644
--- a/sw/device/boot_rom/bootstrap.c
+++ b/sw/device/boot_rom/bootstrap.c
@@ -38,12 +38,12 @@
// Initialize GPIO device.
dif_gpio_t gpio;
- dif_gpio_config_t gpio_config = {
+ dif_gpio_params_t gpio_params = {
.base_addr = mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR)};
- CHECK(dif_gpio_init(&gpio_config, &gpio) == kDifGpioOk);
+ CHECK(dif_gpio_init(gpio_params, &gpio) == kDifGpioOk);
- uint32_t gpio_in;
- CHECK(dif_gpio_all_read(&gpio, &gpio_in) == kDifGpioOk);
+ dif_gpio_state_t gpio_in;
+ CHECK(dif_gpio_read_all(&gpio, &gpio_in) == kDifGpioOk);
return (gpio_in & GPIO_BOOTSTRAP_BIT_MASK) != 0;
}
diff --git a/sw/device/examples/demos.c b/sw/device/examples/demos.c
index 31ae794..61679dc 100644
--- a/sw/device/examples/demos.c
+++ b/sw/device/examples/demos.c
@@ -18,12 +18,12 @@
LOG_INFO("Watch the LEDs!");
// Give a LED pattern as startup indicator for 5 seconds.
- CHECK(dif_gpio_all_write(gpio, 0xff00) == kDifGpioOk);
+ CHECK(dif_gpio_write_all(gpio, 0xff00) == kDifGpioOk);
for (int i = 0; i < 32; ++i) {
usleep(5 * 1000); // 5 ms
- CHECK(dif_gpio_pin_write(gpio, 8 + (i % 8), (i / 8) % 2) == kDifGpioOk);
+ CHECK(dif_gpio_write(gpio, 8 + (i % 8), (i / 8) % 2) == kDifGpioOk);
}
- CHECK(dif_gpio_all_write(gpio, 0x0000) == kDifGpioOk); // All LEDs off.
+ CHECK(dif_gpio_write_all(gpio, 0x0000) == kDifGpioOk); // All LEDs off.
}
/**
@@ -39,7 +39,7 @@
uint32_t demo_gpio_to_log_echo(dif_gpio_t *gpio, uint32_t prev_gpio_state) {
uint32_t gpio_state;
- CHECK(dif_gpio_all_read(gpio, &gpio_state) == kDifGpioOk);
+ CHECK(dif_gpio_read_all(gpio, &gpio_state) == kDifGpioOk);
gpio_state &= kGpioMask;
uint32_t state_delta = prev_gpio_state ^ gpio_state;
@@ -79,6 +79,6 @@
char rcv_char;
while (uart_rcv_char(&rcv_char) != -1) {
uart_send_char(rcv_char);
- CHECK(dif_gpio_all_write(gpio, rcv_char << 8) == kDifGpioOk);
+ CHECK(dif_gpio_write_all(gpio, rcv_char << 8) == kDifGpioOk);
}
}
diff --git a/sw/device/examples/hello_usbdev/hello_usbdev.c b/sw/device/examples/hello_usbdev/hello_usbdev.c
index 04e19ad..ab9fbe2 100644
--- a/sw/device/examples/hello_usbdev/hello_usbdev.c
+++ b/sw/device/examples/hello_usbdev/hello_usbdev.c
@@ -98,12 +98,12 @@
CHECK(dif_spi_device_init(spi_reg, &spi_config, &spi) ==
kDifSpiDeviceResultOk);
- dif_gpio_config_t gpio_config = {
+ dif_gpio_params_t gpio_params = {
.base_addr = mmio_region_from_addr(0x40010000),
};
- CHECK(dif_gpio_init(&gpio_config, &gpio) == kDifGpioOk);
+ CHECK(dif_gpio_init(gpio_params, &gpio) == kDifGpioOk);
// Enable GPIO: 0-7 and 16 is input; 8-15 is output.
- CHECK(dif_gpio_output_mode_all_set(&gpio, 0x0ff00) == kDifGpioOk);
+ CHECK(dif_gpio_output_set_enabled_all(&gpio, 0x0ff00) == kDifGpioOk);
LOG_INFO("Hello, USB!");
LOG_INFO("Built at: " __DATE__ ", " __TIME__);
@@ -133,7 +133,7 @@
char rcv_char;
while (uart_rcv_char(&rcv_char) != -1) {
uart_send_char(rcv_char);
- CHECK(dif_gpio_all_write(&gpio, rcv_char << 8) == kDifGpioOk);
+ CHECK(dif_gpio_write_all(&gpio, rcv_char << 8) == kDifGpioOk);
if (rcv_char == '/') {
uint32_t usb_irq_state = REG32(USBDEV_INTR_STATE());
diff --git a/sw/device/examples/hello_world/hello_world.c b/sw/device/examples/hello_world/hello_world.c
index 68cd8a7..9a37ae0 100644
--- a/sw/device/examples/hello_world/hello_world.c
+++ b/sw/device/examples/hello_world/hello_world.c
@@ -35,12 +35,13 @@
CHECK(dif_spi_device_init(spi_reg, &spi_config, &spi) ==
kDifSpiDeviceResultOk);
- dif_gpio_config_t gpio_config = {
+ dif_gpio_params_t gpio_params = {
.base_addr = mmio_region_from_addr(0x40010000),
};
- CHECK(dif_gpio_init(&gpio_config, &gpio) == kDifGpioOk);
+ CHECK(dif_gpio_init(gpio_params, &gpio) == kDifGpioOk);
// Enable GPIO: 0-7 and 16 is input; 8-15 is output.
- CHECK(dif_gpio_output_mode_all_set(&gpio, 0x0ff00) == kDifGpioOk);
+ CHECK(dif_gpio_output_set_enabled_all(&gpio, 0x0ff00) == kDifGpioOk);
+
// Add DATE and TIME because I keep fooling myself with old versions
LOG_INFO("Hello World!");
LOG_INFO("Built at: " __DATE__ ", " __TIME__);
@@ -49,7 +50,7 @@
// Now have UART <-> Buttons/LEDs demo
// all LEDs off
- CHECK(dif_gpio_all_write(&gpio, 0x0000) == kDifGpioOk);
+ CHECK(dif_gpio_write_all(&gpio, 0x0000) == kDifGpioOk);
LOG_INFO("Try out the switches on the board");
LOG_INFO("or type anything into the console window.");
LOG_INFO("The LEDs show the ASCII code of the last character.");
diff --git a/sw/device/lib/dif/dif_gpio.c b/sw/device/lib/dif/dif_gpio.c
index 832c735..188d8da 100644
--- a/sw/device/lib/dif/dif_gpio.c
+++ b/sw/device/lib/dif/dif_gpio.c
@@ -4,7 +4,6 @@
#include "sw/device/lib/dif/dif_gpio.h"
-#include "sw/device/lib/common.h"
#include "gpio_regs.h" // Generated.
/**
@@ -37,19 +36,27 @@
* @param mask Mask that identifies the bits to write to.
* @param val Value to write.
*/
-static void gpio_masked_write(const dif_gpio_t *gpio, uint32_t reg_lower_offset,
- uint32_t reg_upper_offset, uint32_t mask,
- uint32_t val) {
+DIF_WARN_UNUSED_RESULT
+static dif_gpio_result_t gpio_masked_write(const dif_gpio_t *gpio,
+ ptrdiff_t reg_lower_offset,
+ ptrdiff_t reg_upper_offset,
+ uint32_t mask, uint32_t val) {
+ if (gpio == NULL) {
+ return kDifGpioBadArg;
+ }
+
const uint32_t mask_lower_half = mask & 0x0000FFFFu;
const uint32_t mask_upper_half = mask & 0xFFFF0000u;
if (mask_lower_half != 0) {
- mmio_region_write32(gpio->base_addr, reg_lower_offset,
+ mmio_region_write32(gpio->params.base_addr, reg_lower_offset,
(mask_lower_half << 16) | (val & 0x0000FFFFu));
}
if (mask_upper_half != 0) {
- mmio_region_write32(gpio->base_addr, reg_upper_offset,
+ mmio_region_write32(gpio->params.base_addr, reg_upper_offset,
mask_upper_half | ((val & 0xFFFF0000u) >> 16));
}
+
+ return kDifGpioOk;
}
/**
@@ -71,33 +78,33 @@
* @param index Zero-based index of the bit to write to.
* @param val Value to write.
*/
-static void gpio_masked_bit_write(const dif_gpio_t *gpio,
- uint32_t reg_lower_offset,
- uint32_t reg_upper_offset, uint32_t index,
- bool val) {
+DIF_WARN_UNUSED_RESULT
+static dif_gpio_result_t gpio_masked_bit_write(const dif_gpio_t *gpio,
+ ptrdiff_t reg_lower_offset,
+ ptrdiff_t reg_upper_offset,
+ uint32_t index, bool val) {
+ if (gpio == NULL) {
+ return kDifGpioBadArg;
+ }
+
// Write to reg_lower_offset if the bit is in the lower half, write to
// reg_upper_offset otherwise.
const ptrdiff_t offset = (index < 16) ? reg_lower_offset : reg_upper_offset;
// Since masked access writes to half of a register, index mod 16 gives the
// index of the bit in the half-word mask.
const uint32_t mask = index_to_mask(index % 16);
- mmio_region_write32(gpio->base_addr, offset,
+ mmio_region_write32(gpio->params.base_addr, offset,
(mask << 16) | (val ? mask : 0u));
+
+ return kDifGpioOk;
}
-dif_gpio_result_t dif_gpio_init(const dif_gpio_config_t *config,
- dif_gpio_t *gpio) {
- if (config == NULL || gpio == NULL) {
+dif_gpio_result_t dif_gpio_init(dif_gpio_params_t params, dif_gpio_t *gpio) {
+ if (gpio == NULL) {
return kDifGpioBadArg;
}
- // Save internal state in the given `dif_gpio_t` instance.
- gpio->base_addr = config->base_addr;
- // Reset the GPIO device at the given `base_addr`.
- dif_gpio_result_t err = dif_gpio_reset(gpio);
- if (err != kDifGpioOk) {
- return err;
- }
+ gpio->params = params;
return kDifGpioOk;
}
@@ -109,274 +116,218 @@
// We don't need to write to `GPIO_MASKED_OE_*` and `GPIO_MASKED_OUT_*`
// since we directly reset `GPIO_DIRECT_OE` and `GPIO_DIRECT_OUT` below.
- mmio_region_write32(gpio->base_addr, GPIO_INTR_ENABLE_REG_OFFSET, 0);
- mmio_region_write32(gpio->base_addr, GPIO_DIRECT_OE_REG_OFFSET, 0);
- mmio_region_write32(gpio->base_addr, GPIO_DIRECT_OUT_REG_OFFSET, 0);
- mmio_region_write32(gpio->base_addr, GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, 0);
- mmio_region_write32(gpio->base_addr, GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, 0);
- mmio_region_write32(gpio->base_addr, GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, 0);
- mmio_region_write32(gpio->base_addr, GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, 0);
- mmio_region_write32(gpio->base_addr, GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, 0);
+ mmio_region_write32(gpio->params.base_addr, GPIO_INTR_ENABLE_REG_OFFSET, 0);
+ mmio_region_write32(gpio->params.base_addr, GPIO_DIRECT_OE_REG_OFFSET, 0);
+ mmio_region_write32(gpio->params.base_addr, GPIO_DIRECT_OUT_REG_OFFSET, 0);
+ mmio_region_write32(gpio->params.base_addr,
+ GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, 0);
+ mmio_region_write32(gpio->params.base_addr,
+ GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, 0);
+ mmio_region_write32(gpio->params.base_addr,
+ GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, 0);
+ mmio_region_write32(gpio->params.base_addr,
+ GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, 0);
+ mmio_region_write32(gpio->params.base_addr,
+ GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, 0);
// Also clear all pending interrupts
- mmio_region_write32(gpio->base_addr, GPIO_INTR_STATE_REG_OFFSET, 0xFFFFFFFFu);
+ mmio_region_write32(gpio->params.base_addr, GPIO_INTR_STATE_REG_OFFSET,
+ 0xFFFFFFFFu);
return kDifGpioOk;
}
-dif_gpio_result_t dif_gpio_all_read(const dif_gpio_t *gpio,
- uint32_t *pin_values) {
- if (gpio == NULL || pin_values == NULL) {
+dif_gpio_result_t dif_gpio_irq_is_pending(const dif_gpio_t *gpio,
+ dif_gpio_pin_t pin,
+ bool *is_pending) {
+ if (gpio == NULL || is_pending == NULL) {
return kDifGpioBadArg;
}
- *pin_values = mmio_region_read32(gpio->base_addr, GPIO_DATA_IN_REG_OFFSET);
+ *is_pending = mmio_region_get_bit32(gpio->params.base_addr,
+ GPIO_INTR_STATE_REG_OFFSET, pin);
return kDifGpioOk;
}
-dif_gpio_result_t dif_gpio_pin_read(const dif_gpio_t *gpio, uint32_t index,
- bool *pin_value) {
- if (gpio == NULL || pin_value == NULL) {
+dif_gpio_result_t dif_gpio_irq_is_pending_all(const dif_gpio_t *gpio,
+ dif_gpio_state_t *is_pending) {
+ if (gpio == NULL || is_pending == NULL) {
return kDifGpioBadArg;
}
- *pin_value =
- mmio_region_get_bit32(gpio->base_addr, GPIO_DATA_IN_REG_OFFSET, index);
+ *is_pending =
+ mmio_region_read32(gpio->params.base_addr, GPIO_INTR_STATE_REG_OFFSET);
return kDifGpioOk;
}
-dif_gpio_result_t dif_gpio_all_write(const dif_gpio_t *gpio, uint32_t val) {
+dif_gpio_result_t dif_gpio_irq_acknowledge(const dif_gpio_t *gpio,
+ dif_gpio_pin_t pin) {
if (gpio == NULL) {
return kDifGpioBadArg;
}
- mmio_region_write32(gpio->base_addr, GPIO_DIRECT_OUT_REG_OFFSET, val);
+ mmio_region_write32(gpio->params.base_addr, GPIO_INTR_STATE_REG_OFFSET,
+ index_to_mask(pin));
return kDifGpioOk;
}
-dif_gpio_result_t dif_gpio_pin_write(const dif_gpio_t *gpio, uint32_t index,
- bool val) {
+dif_gpio_result_t dif_gpio_irq_get_enabled(const dif_gpio_t *gpio,
+ dif_gpio_pin_t pin,
+ dif_gpio_toggle_t *state) {
+ if (gpio == NULL || state == NULL) {
+ return kDifGpioBadArg;
+ }
+
+ bool is_enabled = mmio_region_get_bit32(gpio->params.base_addr,
+ GPIO_INTR_ENABLE_REG_OFFSET, pin);
+ *state = is_enabled ? kDifGpioToggleEnabled : kDifGpioToggleDisabled;
+
+ return kDifGpioOk;
+}
+
+dif_gpio_result_t dif_gpio_irq_set_enabled(const dif_gpio_t *gpio,
+ dif_gpio_pin_t pin,
+ dif_gpio_toggle_t state) {
if (gpio == NULL) {
return kDifGpioBadArg;
}
- gpio_masked_bit_write(gpio, GPIO_MASKED_OUT_LOWER_REG_OFFSET,
- GPIO_MASKED_OUT_UPPER_REG_OFFSET, index, val);
+ switch (state) {
+ case kDifGpioToggleEnabled:
+ mmio_region_nonatomic_set_bit32(gpio->params.base_addr,
+ GPIO_INTR_ENABLE_REG_OFFSET, pin);
+ break;
+ case kDifGpioToggleDisabled:
+ mmio_region_nonatomic_clear_bit32(gpio->params.base_addr,
+ GPIO_INTR_ENABLE_REG_OFFSET, pin);
+ break;
+ default:
+ return kDifGpioBadArg;
+ }
return kDifGpioOk;
}
-dif_gpio_result_t dif_gpio_masked_write(const dif_gpio_t *gpio, uint32_t mask,
- uint32_t val) {
+dif_gpio_result_t dif_gpio_irq_set_enabled_masked(const dif_gpio_t *gpio,
+ dif_gpio_mask_t mask,
+ dif_gpio_toggle_t state) {
if (gpio == NULL) {
return kDifGpioBadArg;
}
- gpio_masked_write(gpio, GPIO_MASKED_OUT_LOWER_REG_OFFSET,
- GPIO_MASKED_OUT_UPPER_REG_OFFSET, mask, val);
+ switch (state) {
+ case kDifGpioToggleEnabled:
+ mmio_region_nonatomic_set_mask32(gpio->params.base_addr,
+ GPIO_INTR_ENABLE_REG_OFFSET, mask, 0);
+ break;
+ case kDifGpioToggleDisabled:
+ mmio_region_nonatomic_clear_mask32(gpio->params.base_addr,
+ GPIO_INTR_ENABLE_REG_OFFSET, mask, 0);
+ break;
+ default:
+ return kDifGpioBadArg;
+ }
return kDifGpioOk;
}
-dif_gpio_result_t dif_gpio_output_mode_all_set(const dif_gpio_t *gpio,
- uint32_t val) {
+dif_gpio_result_t dif_gpio_irq_force(const dif_gpio_t *gpio,
+ dif_gpio_pin_t pin) {
if (gpio == NULL) {
return kDifGpioBadArg;
}
- mmio_region_write32(gpio->base_addr, GPIO_DIRECT_OE_REG_OFFSET, val);
+ mmio_region_write32(gpio->params.base_addr, GPIO_INTR_TEST_REG_OFFSET,
+ index_to_mask(pin));
return kDifGpioOk;
}
-dif_gpio_result_t dif_gpio_output_mode_pin_set(const dif_gpio_t *gpio,
- uint32_t index, bool val) {
+dif_gpio_result_t dif_gpio_irq_disable_all(const dif_gpio_t *gpio,
+ dif_gpio_state_t *snapshot) {
if (gpio == NULL) {
return kDifGpioBadArg;
}
- gpio_masked_bit_write(gpio, GPIO_MASKED_OE_LOWER_REG_OFFSET,
- GPIO_MASKED_OE_UPPER_REG_OFFSET, index, val);
+ if (snapshot != NULL) {
+ *snapshot =
+ mmio_region_read32(gpio->params.base_addr, GPIO_INTR_ENABLE_REG_OFFSET);
+ }
+ mmio_region_write32(gpio->params.base_addr, GPIO_INTR_ENABLE_REG_OFFSET, 0);
return kDifGpioOk;
}
-dif_gpio_result_t dif_gpio_output_mode_masked_set(const dif_gpio_t *gpio,
- uint32_t mask, uint32_t val) {
+dif_gpio_result_t dif_gpio_irq_restore_all(const dif_gpio_t *gpio,
+ const dif_gpio_state_t *snapshot) {
+ if (gpio == NULL || snapshot == NULL) {
+ return kDifGpioBadArg;
+ }
+
+ mmio_region_write32(gpio->params.base_addr, GPIO_INTR_ENABLE_REG_OFFSET,
+ *snapshot);
+
+ return kDifGpioOk;
+}
+
+dif_gpio_result_t dif_gpio_irq_set_trigger(const dif_gpio_t *gpio,
+ dif_gpio_mask_t mask,
+ dif_gpio_irq_trigger_t trigger) {
if (gpio == NULL) {
return kDifGpioBadArg;
}
- gpio_masked_write(gpio, GPIO_MASKED_OE_LOWER_REG_OFFSET,
- GPIO_MASKED_OE_UPPER_REG_OFFSET, mask, val);
-
- return kDifGpioOk;
-}
-
-dif_gpio_result_t dif_gpio_irq_pin_test(const dif_gpio_t *gpio,
- uint32_t index) {
- if (gpio == NULL) {
- return kDifGpioBadArg;
- }
-
- mmio_region_write32(gpio->base_addr, GPIO_INTR_TEST_REG_OFFSET,
- index_to_mask(index));
-
- return kDifGpioOk;
-}
-
-dif_gpio_result_t dif_gpio_irq_all_read(const dif_gpio_t *gpio,
- uint32_t *interrupt_states) {
- if (gpio == NULL || interrupt_states == NULL) {
- return kDifGpioBadArg;
- }
-
- *interrupt_states =
- mmio_region_read32(gpio->base_addr, GPIO_INTR_STATE_REG_OFFSET);
-
- return kDifGpioOk;
-}
-
-dif_gpio_result_t dif_gpio_irq_pin_read(const dif_gpio_t *gpio, uint32_t index,
- bool *interrupt_state) {
- if (gpio == NULL || interrupt_state == NULL) {
- return kDifGpioBadArg;
- }
-
- *interrupt_state =
- mmio_region_get_bit32(gpio->base_addr, GPIO_INTR_STATE_REG_OFFSET, index);
-
- return kDifGpioOk;
-}
-
-dif_gpio_result_t dif_gpio_irq_pin_clear(const dif_gpio_t *gpio,
- uint32_t index) {
- if (gpio == NULL) {
- return kDifGpioBadArg;
- }
-
- mmio_region_write32(gpio->base_addr, GPIO_INTR_STATE_REG_OFFSET,
- index_to_mask(index));
-
- return kDifGpioOk;
-}
-
-dif_gpio_result_t dif_gpio_input_noise_filter_masked_enable(
- const dif_gpio_t *gpio, uint32_t mask) {
- if (gpio == NULL) {
- return kDifGpioBadArg;
- }
-
- mmio_region_nonatomic_set_mask32(
- gpio->base_addr, GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, mask, 0);
-
- return kDifGpioOk;
-}
-
-dif_gpio_result_t dif_gpio_input_noise_filter_masked_disable(
- const dif_gpio_t *gpio, uint32_t mask) {
- if (gpio == NULL) {
- return kDifGpioBadArg;
- }
-
+ // Disable all interrupt triggers for the given mask.
mmio_region_nonatomic_clear_mask32(
- gpio->base_addr, GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, mask, 0);
-
- return kDifGpioOk;
-}
-
-dif_gpio_result_t dif_gpio_irq_masked_enable(const dif_gpio_t *gpio,
- uint32_t mask) {
- if (gpio == NULL) {
- return kDifGpioBadArg;
- }
-
- mmio_region_nonatomic_set_mask32(gpio->base_addr, GPIO_INTR_ENABLE_REG_OFFSET,
- mask, 0);
-
- return kDifGpioOk;
-}
-
-dif_gpio_result_t dif_gpio_irq_masked_disable(const dif_gpio_t *gpio,
- uint32_t mask) {
- if (gpio == NULL) {
- return kDifGpioBadArg;
- }
-
- mmio_region_nonatomic_clear_mask32(gpio->base_addr,
- GPIO_INTR_ENABLE_REG_OFFSET, mask, 0);
-
- return kDifGpioOk;
-}
-
-dif_gpio_result_t dif_gpio_irq_trigger_masked_disable(const dif_gpio_t *gpio,
- uint32_t mask) {
- if (gpio == NULL) {
- return kDifGpioBadArg;
- }
-
- // Disable all interrupt triggers for the given mask
+ gpio->params.base_addr, GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, mask, 0);
mmio_region_nonatomic_clear_mask32(
- gpio->base_addr, GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, mask, 0);
+ gpio->params.base_addr, GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, mask, 0);
mmio_region_nonatomic_clear_mask32(
- gpio->base_addr, GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, mask, 0);
+ gpio->params.base_addr, GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, mask, 0);
mmio_region_nonatomic_clear_mask32(
- gpio->base_addr, GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, mask, 0);
- mmio_region_nonatomic_clear_mask32(
- gpio->base_addr, GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, mask, 0);
+ gpio->params.base_addr, GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, mask, 0);
- return kDifGpioOk;
-}
-
-dif_gpio_result_t dif_gpio_irq_trigger_masked_config(const dif_gpio_t *gpio,
- uint32_t mask,
- dif_gpio_irq_t config) {
- if (gpio == NULL) {
- return kDifGpioBadArg;
- }
-
- // Disable all interrupt triggers for the given mask
- dif_gpio_result_t error = dif_gpio_irq_trigger_masked_disable(gpio, mask);
- if (error != kDifGpioOk) {
- return error;
- }
-
- switch (config) {
- case kDifGpioIrqEdgeRising:
+ switch (trigger) {
+ case kDifGpioIrqTriggerEdgeRising:
mmio_region_nonatomic_set_mask32(
- gpio->base_addr, GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, mask, 0);
+ gpio->params.base_addr, GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, mask, 0);
break;
- case kDifGpioIrqEdgeFalling:
- mmio_region_nonatomic_set_mask32(
- gpio->base_addr, GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, mask, 0);
+ case kDifGpioIrqTriggerEdgeFalling:
+ mmio_region_nonatomic_set_mask32(gpio->params.base_addr,
+ GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET,
+ mask, 0);
break;
- case kDifGpioIrqLevelLow:
+ case kDifGpioIrqTriggerLevelLow:
mmio_region_nonatomic_set_mask32(
- gpio->base_addr, GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, mask, 0);
+ gpio->params.base_addr, GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, mask, 0);
break;
- case kDifGpioIrqLevelHigh:
- mmio_region_nonatomic_set_mask32(
- gpio->base_addr, GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, mask, 0);
+ case kDifGpioIrqTriggerLevelHigh:
+ mmio_region_nonatomic_set_mask32(gpio->params.base_addr,
+ GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET,
+ mask, 0);
break;
- case kDifGpioIrqEdgeRisingFalling:
+ case kDifGpioIrqTriggerEdgeRisingFalling:
mmio_region_nonatomic_set_mask32(
- gpio->base_addr, GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, mask, 0);
- mmio_region_nonatomic_set_mask32(
- gpio->base_addr, GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, mask, 0);
+ gpio->params.base_addr, GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, mask, 0);
+ mmio_region_nonatomic_set_mask32(gpio->params.base_addr,
+ GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET,
+ mask, 0);
break;
- case kDifGpioIrqEdgeRisingLevelLow:
+ case kDifGpioIrqTriggerEdgeRisingLevelLow:
mmio_region_nonatomic_set_mask32(
- gpio->base_addr, GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, mask, 0);
+ gpio->params.base_addr, GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, mask, 0);
mmio_region_nonatomic_set_mask32(
- gpio->base_addr, GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, mask, 0);
+ gpio->params.base_addr, GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, mask, 0);
break;
- case kDifGpioIrqEdgeFallingLevelHigh:
- mmio_region_nonatomic_set_mask32(
- gpio->base_addr, GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, mask, 0);
- mmio_region_nonatomic_set_mask32(
- gpio->base_addr, GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, mask, 0);
+ case kDifGpioIrqTriggerEdgeFallingLevelHigh:
+ mmio_region_nonatomic_set_mask32(gpio->params.base_addr,
+ GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET,
+ mask, 0);
+ mmio_region_nonatomic_set_mask32(gpio->params.base_addr,
+ GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET,
+ mask, 0);
break;
default:
return kDifGpioError;
@@ -384,3 +335,106 @@
return kDifGpioOk;
}
+
+dif_gpio_result_t dif_gpio_read_all(const dif_gpio_t *gpio,
+ dif_gpio_state_t *state) {
+ if (gpio == NULL || state == NULL) {
+ return kDifGpioBadArg;
+ }
+
+ *state = mmio_region_read32(gpio->params.base_addr, GPIO_DATA_IN_REG_OFFSET);
+
+ return kDifGpioOk;
+}
+
+dif_gpio_result_t dif_gpio_read(const dif_gpio_t *gpio, dif_gpio_pin_t pin,
+ bool *state) {
+ if (gpio == NULL || state == NULL) {
+ return kDifGpioBadArg;
+ }
+
+ *state = mmio_region_get_bit32(gpio->params.base_addr,
+ GPIO_DATA_IN_REG_OFFSET, pin);
+
+ return kDifGpioOk;
+}
+
+dif_gpio_result_t dif_gpio_write_all(const dif_gpio_t *gpio,
+ dif_gpio_state_t state) {
+ if (gpio == NULL) {
+ return kDifGpioBadArg;
+ }
+
+ mmio_region_write32(gpio->params.base_addr, GPIO_DIRECT_OUT_REG_OFFSET,
+ state);
+
+ return kDifGpioOk;
+}
+
+dif_gpio_result_t dif_gpio_write(const dif_gpio_t *gpio, dif_gpio_pin_t pin,
+ bool state) {
+ return gpio_masked_bit_write(gpio, GPIO_MASKED_OUT_LOWER_REG_OFFSET,
+ GPIO_MASKED_OUT_UPPER_REG_OFFSET, pin, state);
+}
+
+dif_gpio_result_t dif_gpio_write_masked(const dif_gpio_t *gpio,
+ dif_gpio_mask_t mask,
+ dif_gpio_state_t state) {
+ return gpio_masked_write(gpio, GPIO_MASKED_OUT_LOWER_REG_OFFSET,
+ GPIO_MASKED_OUT_UPPER_REG_OFFSET, mask, state);
+}
+
+dif_gpio_result_t dif_gpio_output_set_enabled_all(const dif_gpio_t *gpio,
+ dif_gpio_state_t state) {
+ if (gpio == NULL) {
+ return kDifGpioBadArg;
+ }
+
+ mmio_region_write32(gpio->params.base_addr, GPIO_DIRECT_OE_REG_OFFSET, state);
+
+ return kDifGpioOk;
+}
+
+dif_gpio_result_t dif_gpio_output_set_enabled(const dif_gpio_t *gpio,
+ dif_gpio_pin_t pin,
+ dif_gpio_toggle_t state) {
+ if (gpio == NULL) {
+ return kDifGpioBadArg;
+ }
+
+ return gpio_masked_bit_write(gpio, GPIO_MASKED_OE_LOWER_REG_OFFSET,
+ GPIO_MASKED_OE_UPPER_REG_OFFSET, pin, state);
+
+ return kDifGpioOk;
+}
+
+dif_gpio_result_t dif_gpio_output_set_enabled_masked(const dif_gpio_t *gpio,
+ dif_gpio_mask_t mask,
+ dif_gpio_state_t state) {
+ return gpio_masked_write(gpio, GPIO_MASKED_OE_LOWER_REG_OFFSET,
+ GPIO_MASKED_OE_UPPER_REG_OFFSET, mask, state);
+}
+
+dif_gpio_result_t dif_gpio_input_noise_filter_set_enabled(
+ const dif_gpio_t *gpio, dif_gpio_mask_t mask, dif_gpio_toggle_t state) {
+ if (gpio == NULL) {
+ return kDifGpioBadArg;
+ }
+
+ switch (state) {
+ case kDifGpioToggleEnabled:
+ mmio_region_nonatomic_set_mask32(gpio->params.base_addr,
+ GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET,
+ mask, 0);
+ break;
+ case kDifGpioToggleDisabled:
+ mmio_region_nonatomic_clear_mask32(gpio->params.base_addr,
+ GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET,
+ mask, 0);
+ break;
+ default:
+ return kDifGpioBadArg;
+ }
+
+ return kDifGpioOk;
+}
diff --git a/sw/device/lib/dif/dif_gpio.h b/sw/device/lib/dif/dif_gpio.h
index 6ffca25..da429d1 100644
--- a/sw/device/lib/dif/dif_gpio.h
+++ b/sw/device/lib/dif/dif_gpio.h
@@ -22,357 +22,415 @@
#endif // __cplusplus
/**
- * Configuration for initializing a GPIO device.
- */
-typedef struct dif_gpio_config { mmio_region_t base_addr; } dif_gpio_config_t;
-
-/**
- * Internal state of a GPIO device.
+ * A toggle state: enabled, or disabled.
*
- * Instances of this struct must be initialized by `dif_gpio_init()` before
- * being passed to other functions.
+ * This enum may be used instead of a `bool` when describing an enabled/disabled
+ * state.
+ *
+ * This enum may be used with `dif_gpio_toggle_vec_t` to set individual bits
+ * within it; `dif_gpio_toggle_t`'s variants are guaranteed to be compatible
+ * with `dif_gpio_toggle_vec_t`.
*/
-typedef struct dif_gpio { mmio_region_t base_addr; } dif_gpio_t;
+typedef enum dif_gpio_toggle {
+ /*
+ * The "enabled" state.
+ */
+ kDifGpioToggleEnabled = true,
+ /**
+ * The "disabled" state.
+ */
+ kDifGpioToggleDisabled = false,
+} dif_gpio_toggle_t;
/**
- * Generic return codes for the functions in this library.
+ * Hardware instantiation parameters for GPIO.
+ *
+ * This struct describes information about the underlying hardware that is
+ * not determined until the hardware design is used as part of a top-level
+ * design.
+ */
+typedef struct dif_gpio_params {
+ /**
+ * The base address for the GPIO hardware registers.
+ */
+ mmio_region_t base_addr;
+} dif_gpio_params_t;
+
+/**
+ * A handle to GPIO.
+ *
+ * This type should be treated as opaque by users.
+ */
+typedef struct dif_gpio { dif_gpio_params_t params; } dif_gpio_t;
+
+/**
+ * The result of a GPIO operation.
*/
typedef enum dif_gpio_result {
/**
- * The function succeeded.
+ * Indicates that the operation succeeded.
*/
- kDifGpioOk,
+ kDifGpioOk = 0,
/**
- * The function failed a non-specific assertion.
- *
- * This error is not recoverable.
+ * Indicates some unspecified failure.
*/
- kDifGpioError,
+ kDifGpioError = 1,
/**
- * There is a problem with the argument(s) to the function.
+ * Indicates that some parameter passed into a function failed a
+ * precondition.
*
- * This return code is only returned before the function has any side effects.
- *
- * This error is recoverable and the operation can be retried after correcting
- * the problem with the argument(s).
+ * When this value is returned, no hardware operations occured.
*/
- kDifGpioBadArg,
-
+ kDifGpioBadArg = 2,
} dif_gpio_result_t;
/**
- * Set of allowed interrupt trigger configurations.
+ * A GPIO interrupt request trigger.
+ *
+ * Each GPIO pin has an associated interrupt that can be independently
+ * configured
+ * to be edge and/or level sensitive. This enum defines supported configurations
+ * for
+ * these interrupts.
*/
-typedef enum dif_gpio_irq {
- kDifGpioIrqEdgeRising,
- kDifGpioIrqEdgeFalling,
- kDifGpioIrqLevelLow,
- kDifGpioIrqLevelHigh,
- kDifGpioIrqEdgeRisingFalling,
- kDifGpioIrqEdgeRisingLevelLow,
- kDifGpioIrqEdgeFallingLevelHigh,
-} dif_gpio_irq_t;
+typedef enum dif_gpio_irq_trigger {
+ /**
+ * Trigger on rising edge.
+ */
+ kDifGpioIrqTriggerEdgeRising,
+ /**
+ * Trigger on falling edge.
+ */
+ kDifGpioIrqTriggerEdgeFalling,
+ /**
+ * Trigger when input is low.
+ */
+ kDifGpioIrqTriggerLevelLow,
+ /**
+ * Trigger when input is high.
+ */
+ kDifGpioIrqTriggerLevelHigh,
+ /**
+ * Trigger on rising and falling edges.
+ */
+ kDifGpioIrqTriggerEdgeRisingFalling,
+ /**
+ * Trigger on rising edge or when the input is low.
+ */
+ kDifGpioIrqTriggerEdgeRisingLevelLow,
+ /**
+ * Trigger on falling edge or when the input is high.
+ */
+ kDifGpioIrqTriggerEdgeFallingLevelHigh,
+} dif_gpio_irq_trigger_t;
/**
- * Initialize a GPIO device using `config` and return its internal state.
+ * A GPIO pin index, ranging from 0 to 31.
*
- * A particular GPIO device must first be initialized by this function
- * before calling other functions of this library.
+ * This type serves as the GPIO interrupt request type.
+ */
+typedef uint32_t dif_gpio_pin_t;
+
+/**
+ * State for all 32 GPIO pins, given as bit fields.
*
- * @param config Configuration for initializing a GPIO device.
- * @param[out] gpio GPIO instance that will store the internal state of the
- * initialized GPIO device.
- * @return `kDifGpioBadArg` if `config` or `gpio` is `NULL`,
- * `kDifGpioOk` otherwise.
+ * The Nth bit represents the state of the Nth pin.
+ *
+ * This type is also used as a vector of `dif_gpio_toggle_t`s, to indicate
+ * toggle state across all 32 pins. A set bit corresponds to
+ * `kDifGpioToggleEnabled`.
+ *
+ * It is also used with `dif_gpio_irq_disable_all()` and
+ * `dif_gpio_irq_restore_all()`.
+ */
+typedef uint32_t dif_gpio_state_t;
+
+/**
+ * A mask for selecting GPIO pins.
+ *
+ * If the Nth bit is enabled, then the Nth pin is selected by the mask.
+ */
+typedef uint32_t dif_gpio_mask_t;
+
+/**
+ * Creates a new handle for GPIO.
+ *
+ * This function does not actuate the hardware.
+ *
+ * @param params Hardware instantiation parameters.
+ * @param[out] gpio Out param for the initialized handle.
+ * @return The result of the operation.
*/
DIF_WARN_UNUSED_RESULT
-dif_gpio_result_t dif_gpio_init(const dif_gpio_config_t *config,
- dif_gpio_t *gpio);
+dif_gpio_result_t dif_gpio_init(dif_gpio_params_t params, dif_gpio_t *gpio);
/**
- * Reset GPIO device.
+ * Resets a GPIO device.
*
* Resets the given GPIO device by setting its configuration registers to
* reset values. Disables interrupts, output, and input filter.
*
- * @param gpio GPIO instance
- * @return `kDifGpioBadArg` if `gpio` is `NULL`,
- * `kDifGpioOk` otherwise.
+ * @param gpio A GPIO handle.
+ * @return The result of the operation.
*/
DIF_WARN_UNUSED_RESULT
dif_gpio_result_t dif_gpio_reset(const dif_gpio_t *gpio);
/**
- * Read from all pins.
+ * Returns whether a particular pin's interrupt is currently pending.
*
- * The value returned by this function is independent of the output enable
- * setting and includes the effects of the input noise filter and the load on
- * the pins.
- *
- * @param gpio GPIO instance.
- * @param[out] pin_values Pin values.
- * @return `kDifGpioBadArg` if `gpio` or `pin_values` is `NULL`,
- * `kDifGpioOk` otherwise.
+ * @param gpio A GPIO handle.
+ * @param pin A GPIO pin.
+ * @param[out] is_pending Out-param for whether the interrupt is pending.
+ * @return The result of the operation.
*/
DIF_WARN_UNUSED_RESULT
-dif_gpio_result_t dif_gpio_all_read(const dif_gpio_t *gpio,
- uint32_t *pin_values);
+dif_gpio_result_t dif_gpio_irq_is_pending(const dif_gpio_t *gpio,
+ dif_gpio_pin_t pin, bool *is_pending);
/**
- * Read from a pin.
+ * Returns a GPIO state representing which pins have interrupts enabled.
*
- * The value returned by this function is independent of the output enable
- * setting and includes the effects of the input noise filter and the load on
- * the pin.
- *
- * @param gpio GPIO instance.
- * @param index Zero-based index of the pin to read from.
- * @param[out] pin_value Pin value.
- * @return `kDifGpioBadArg` if `gpio` or `pin_values` is `NULL`,
- * `kDifGpioOk` otherwise.
+ * @param gpio A GPIO handle.
+ * @param[out] is_pending Out-param for which interrupts are pending.
+ * @return The result of the operation.
*/
DIF_WARN_UNUSED_RESULT
-dif_gpio_result_t dif_gpio_pin_read(const dif_gpio_t *gpio, uint32_t index,
- bool *pin_value);
+dif_gpio_result_t dif_gpio_irq_is_pending_all(const dif_gpio_t *gpio,
+ dif_gpio_state_t *is_pending);
/**
- * Write to all pins.
+ * Acknowledges a particular pin's interrupt, indicating to the hardware that it
+ * has
+ * been successfully serviced.
*
- * The actual values on the pins depend on the output enable setting.
- *
- * @param gpio GPIO instance.
- * @param val Value to write.
- * @return `kDifGpioBadArg` if `gpio` is `NULL`,
- * `kDifGpioOk` otherwise.
+ * @param gpio A GPIO handle.
+ * @param pin A GPIO pin.
+ * @return The result of the operation.
*/
DIF_WARN_UNUSED_RESULT
-dif_gpio_result_t dif_gpio_all_write(const dif_gpio_t *gpio, uint32_t val);
+dif_gpio_result_t dif_gpio_irq_acknowledge(const dif_gpio_t *gpio,
+ dif_gpio_pin_t pin);
/**
- * Write to a pin.
+ * Checks whether a particular pin's interrupt is currently enabled or disabled.
*
- * The actual value on the pin depends on the output enable setting.
- *
- * @param gpio GPIO instance.
- * @param index Zero-based index of the pin to write to.
- * @param val Value to write.
- * @return `kDifGpioBadArg` if `gpio` is `NULL`,
- * `kDifGpioOk` otherwise.
+ * @param gpio A GPIO handle.
+ * @param pin A GPIO pin.
+ * @param[out] state Out-param toggle state of the interrupt.
+ * @return The result of the operation.
*/
DIF_WARN_UNUSED_RESULT
-dif_gpio_result_t dif_gpio_pin_write(const dif_gpio_t *gpio, uint32_t index,
- bool val);
+dif_gpio_result_t dif_gpio_irq_get_enabled(const dif_gpio_t *gpio,
+ dif_gpio_pin_t pin,
+ dif_gpio_toggle_t *state);
/**
- * Write to the pins identified by a mask.
+ * Sets whether a particular pin's interrupt is currently enabled or disabled.
*
- * The actual values on the pins depend on the output enable setting.
- *
- * @param gpio GPIO instance
- * @param mask Mask that identifies the pins to write to.
- * @param val Value to write.
- * @return `kDifGpioBadArg` if `gpio` is `NULL`,
- * `kDifGpioOk` otherwise.
+ * @param gpio A GPIO handle.
+ * @param pin A GPIO pin.
+ * @param state The new toggle state for the interrupt.
+ * @return The result of the operation.
*/
DIF_WARN_UNUSED_RESULT
-dif_gpio_result_t dif_gpio_masked_write(const dif_gpio_t *gpio, uint32_t mask,
- uint32_t val);
+dif_gpio_result_t dif_gpio_irq_set_enabled(const dif_gpio_t *gpio,
+ dif_gpio_pin_t pin,
+ dif_gpio_toggle_t state);
/**
- * Set output modes of all pins.
+ * Sets whether a particular pin's interrupt is currently enabled or disabled.
*
- * Setting `val[i]` to 1 enables output mode for pin `i`.
- *
- * @param gpio GPIO instance.
- * @param val Output modes of the pins.
- * @return `kDifGpioBadArg` if `gpio` is `NULL`,
- * `kDifGpioOk` otherwise.
+ * @param gpio A GPIO handle.
+ * @param pin A GPIO pin.
+ * @param state The new toggle state for the interrupt.
+ * @return The result of the operation.
*/
DIF_WARN_UNUSED_RESULT
-dif_gpio_result_t dif_gpio_output_mode_all_set(const dif_gpio_t *gpio,
- uint32_t val);
+dif_gpio_result_t dif_gpio_irq_set_enabled_masked(const dif_gpio_t *gpio,
+ dif_gpio_mask_t mask,
+ dif_gpio_toggle_t state);
/**
- * Set output mode of a pin.
+ * Forces a particular pin's interrupt, causing it to be serviced as if hardware
+ * had asserted it.
*
- * Setting `val` to `true` enables output mode for the pin.
- *
- * @param gpio GPIO instance
- * @param index Zero-based index of the pin.
- * @param val Output mode of the pin.
- * @return `kDifGpioBadArg` if `gpio` is `NULL`,
- * `kDifGpioOk` otherwise.
+ * @param gpio A GPIO handle.
+ * @param pin A GPIO pin.
+ * @return The result of the operation.
*/
DIF_WARN_UNUSED_RESULT
-dif_gpio_result_t dif_gpio_output_mode_pin_set(const dif_gpio_t *gpio,
- uint32_t index, bool val);
+dif_gpio_result_t dif_gpio_irq_force(const dif_gpio_t *gpio,
+ dif_gpio_pin_t pin);
/**
- * Set the output modes of the pins identified by a mask.
+ * Disables all interrupts, optionally snapshotting all toggle state for later
+ * restoration.
*
- * Setting `val[i]` to 1 enables output mode for pin `i`.
- *
- * @param gpio GPIO instance
- * @param mask Mask that identifies the pins whose output modes will be set.
- * @param val Output modes of the pins.
- * @return `kDifGpioBadArg` if `gpio` is `NULL`,
- * `kDifGpioOk` otherwise.
+ * @param gpio A GPIO handle.
+ * @param[out] snapshot Out-param for the snapshot; may be `NULL`.
+ * @return The result of the operation.
*/
DIF_WARN_UNUSED_RESULT
-dif_gpio_result_t dif_gpio_output_mode_masked_set(const dif_gpio_t *gpio,
- uint32_t mask, uint32_t val);
+dif_gpio_result_t dif_gpio_irq_disable_all(const dif_gpio_t *gpio,
+ dif_gpio_state_t *snapshot);
/**
- * Test the reporting of the interrupt of a pin.
+ * Restores interrupts from the given snapshot.
*
- * Sets the corresponding bit in the interrupt state register. The level of
- * the interrupt output to the processor depends on the interrupt enable
- * register.
+ * This function can be used with `dif_gpio_irq_disable_all()` to temporary
+ * interrupt save-and-restore.
*
- * @param gpio GPIO instance.
- * @param index Zero-based index of the pin.
- * @return `kDifGpioBadArg` if `gpio` is `NULL`,
- * `kDifGpioOk` otherwise.
+ * @param gpio A GPIO handle.
+ * @param snapshot A snapshot to restore from.
+ * @return The result of the operation.
*/
DIF_WARN_UNUSED_RESULT
-dif_gpio_result_t dif_gpio_irq_pin_test(const dif_gpio_t *gpio, uint32_t index);
+dif_gpio_result_t dif_gpio_irq_restore_all(const dif_gpio_t *gpio,
+ const dif_gpio_state_t *snapshot);
/**
- * Read the interrupt states of all pins.
- *
- * @param gpio GPIO instance.
- * @param[out] interrupt_states Interrupt states of all pins.
- * @return `kDifGpioBadArg` if `gpio` or `interrupt_states` is
- * `NULL`, `kDifGpioOk` otherwise.
- */
-DIF_WARN_UNUSED_RESULT
-dif_gpio_result_t dif_gpio_irq_all_read(const dif_gpio_t *gpio,
- uint32_t *interrupt_states);
-
-/**
- * Read the interrupt state of a pin.
- *
- * @param gpio GPIO instance.
- * @param index Zero-based index of the pin.
- * @param[out] interrupt_state Interrupt state of the pin. True if there is a
- * pending interrupt, false otherwise.
- * @return `kDifGpioBadArg` if `gpio` or `interrupt_state` is
- * `NULL`, `kDifGpioOk` otherwise.
- */
-DIF_WARN_UNUSED_RESULT
-dif_gpio_result_t dif_gpio_irq_pin_read(const dif_gpio_t *gpio, uint32_t index,
- bool *interrupt_state);
-
-/**
- * Clear the interrupt of a pin.
- *
- * @param gpio GPIO instance.
- * @param index Zero-based index of the pin.
- * @return `kDifGpioBadArg` if `gpio` is `NULL`,
- * `kDifGpioOk` otherwise.
- */
-DIF_WARN_UNUSED_RESULT
-dif_gpio_result_t dif_gpio_irq_pin_clear(const dif_gpio_t *gpio,
- uint32_t index);
-
-/**
- * Enable noise filter for GPIO inputs.
- *
- * Setting `mask[i]` to 1 enables input noise filter for pin `i`. If enabled,
- * changes in the pin value will be ignored unless stable for 16 cycles.
- *
- * @param gpio GPIO instance.
- * @param mask Mask that identifies the pins for which input noise filter will
- * be enabled.
- * @return `kDifGpioBadArg` if `gpio` is `NULL`,
- * `kDifGpioOk` otherwise.
- */
-DIF_WARN_UNUSED_RESULT
-dif_gpio_result_t dif_gpio_input_noise_filter_masked_enable(
- const dif_gpio_t *gpio, uint32_t mask);
-
-/**
- * Disable noise filter for GPIO inputs.
- *
- * Setting `mask[i]` to 1 disables input noise filter for pin `i`.
- *
- * @param gpio GPIO instance.
- * @param mask Mask that identifies the pins for which input noise filter will
- * be disabled.
- * @return `kDifGpioBadArg` if `gpio` is `NULL`,
- * `kDifGpioOk` otherwise.
- */
-DIF_WARN_UNUSED_RESULT
-dif_gpio_result_t dif_gpio_input_noise_filter_masked_disable(
- const dif_gpio_t *gpio, uint32_t mask);
-
-/**
- * Enable interrupts for GPIO inputs.
- *
- * Setting `mask[i]` to 1 enables detection of interrupt events for pin `i`.
- * There are four types of interrupts per pin: rising-edge, falling-edge,
- * high-level, and low-level. At least one of them must be enabled to generate
- * interrupts.
- *
- * @param gpio GPIO instance.
- * @param mask Mask that identifies the pins for which interrupts will be
- * enabled.
- * @return `kDifGpioBadArg` if `gpio` is `NULL`,
- * `kDifGpioOk` otherwise.
- */
-DIF_WARN_UNUSED_RESULT
-dif_gpio_result_t dif_gpio_irq_masked_enable(const dif_gpio_t *gpio,
- uint32_t mask);
-
-/**
- * Disable interrupts for GPIO inputs.
- *
- * Setting `mask[i]` to 1 disables detection of interrupt events for pin `i`.
- *
- * @param gpio GPIO instance.
- * @param mask Mask that identifies the pins for which interrupts will be
- * disabled.
- * @return `kDifGpioBadArg` if `gpio` is `NULL`,
- * `kDifGpioOk` otherwise.
- */
-DIF_WARN_UNUSED_RESULT
-dif_gpio_result_t dif_gpio_irq_masked_disable(const dif_gpio_t *gpio,
- uint32_t mask);
-
-/**
- * Disable all interrupt triggers for GPIO inputs.
- *
- * This function disables all interrupt triggers, i.e. rising-edge,
- * falling-edge, level-high, and level-low, for the pins given by the mask.
- *
- * @param gpio GPIO instance.
- * @param mask Mask that identifies the pins whose interrupt triggers will be
- * disabled.
- * @return `kDifGpioBadArg` if `gpio` is `NULL`,
- * `kDifGpioOk` otherwise.
- */
-DIF_WARN_UNUSED_RESULT
-dif_gpio_result_t dif_gpio_irq_trigger_masked_disable(const dif_gpio_t *gpio,
- uint32_t mask);
-
-/**
- * Configure interrupt triggers for GPIO inputs.
+ * Configures interrupt triggers for a set of pins.
*
* This function configures interrupt triggers, i.e. rising-edge, falling-edge,
* level-high, and level-low, for the pins given by the mask. Note that
* interrupt of the pin must also be enabled to generate interrupts.
*
- * @param gpio GPIO instance.
+ * @param gpio A GPIO handle.
* @param mask Mask that identifies the pins whose interrupt triggers will be
* configured.
- * @param config New configuration of interrupt triggers.
- * @return `kDifGpioOk` if the function is successful,
- * `kDifGpioBadArg` otherwise.
+ * @param trigger New configuration of interrupt triggers.
+ * @return The result of the operation.
*/
DIF_WARN_UNUSED_RESULT
-dif_gpio_result_t dif_gpio_irq_trigger_masked_config(const dif_gpio_t *gpio,
- uint32_t mask,
- dif_gpio_irq_t config);
+dif_gpio_result_t dif_gpio_irq_set_trigger(const dif_gpio_t *gpio,
+ dif_gpio_mask_t mask,
+ dif_gpio_irq_trigger_t trigger);
+
+/**
+ * Reads from a pin.
+ *
+ * The value returned by this function is independent of the output enable
+ * setting and includes the effects of the input noise filter and the load on
+ * the pin.
+ *
+ * @param gpio A GPIO handle.
+ * @param pin A GPIO pin.
+ * @param[out] state Pin value.
+ * @return The result of the operation.
+ */
+DIF_WARN_UNUSED_RESULT
+dif_gpio_result_t dif_gpio_read(const dif_gpio_t *gpio, dif_gpio_pin_t pin,
+ bool *state);
+
+/**
+ * Reads from all pins.
+ *
+ * The value returned by this function is independent of the output enable
+ * setting and includes the effects of the input noise filter and the load on
+ * the pins.
+ *
+ * @param gpio A GPIO handle.
+ * @param[out] state Pin values.
+ * @return The result of the operation.
+ */
+DIF_WARN_UNUSED_RESULT
+dif_gpio_result_t dif_gpio_read_all(const dif_gpio_t *gpio,
+ dif_gpio_state_t *state);
+
+/**
+ * Writes to a pin.
+ *
+ * The actual value on the pin depends on the output enable setting.
+ *
+ * @param gpio A GPIO handle.
+ * @param pin A GPIO pin.
+ * @param state Value to write.
+ * @return The result of the operation.
+ */
+DIF_WARN_UNUSED_RESULT
+dif_gpio_result_t dif_gpio_write(const dif_gpio_t *gpio, dif_gpio_pin_t pin,
+ bool state);
+
+/**
+ * Writes to all pins.
+ *
+ * The actual values on the pins depend on the output enable setting.
+ *
+ * @param gpio A GPIO handle.
+ * @param val Value to write.
+ * @return The result of the operation.
+ */
+DIF_WARN_UNUSED_RESULT
+dif_gpio_result_t dif_gpio_write_all(const dif_gpio_t *gpio,
+ dif_gpio_state_t state);
+
+/**
+ * Writes to the pins identified by a mask.
+ *
+ * The actual values on the pins depend on the output enable setting.
+ *
+ * @param gpio A GPIO handle.
+ * @param mask Mask that identifies the pins to write to.
+ * @param state Value to write.
+ * @return The result of the operation.
+ */
+DIF_WARN_UNUSED_RESULT
+dif_gpio_result_t dif_gpio_write_masked(const dif_gpio_t *gpio,
+ dif_gpio_mask_t mask,
+ dif_gpio_state_t state);
+
+/**
+ * Sets output enable mode of a pin.
+ *
+ * @param gpio A GPIO handle.
+ * @param pin A GPIO pin.
+ * @param state Output mode of the pin.
+ * @return The result of the operation.
+ */
+DIF_WARN_UNUSED_RESULT
+dif_gpio_result_t dif_gpio_output_set_enabled(const dif_gpio_t *gpio,
+ dif_gpio_pin_t pin,
+ dif_gpio_toggle_t state);
+
+/**
+ * Sets output modes of all pins.
+ *
+ * @param gpio A GPIO handle.
+ * @param state Output modes of the pins.
+ * @return The result of the operation.
+ */
+DIF_WARN_UNUSED_RESULT
+dif_gpio_result_t dif_gpio_output_set_enabled_all(const dif_gpio_t *gpio,
+ dif_gpio_state_t state);
+
+/**
+ * Sets the output modes of the pins identified by a mask.
+ *
+ * @param gpio A GPIO handle.
+ * @param mask Mask that identifies the pins whose output modes will be set.
+ * @param state Output modes of the pins.
+ * @return The result of the operation.
+ */
+DIF_WARN_UNUSED_RESULT
+dif_gpio_result_t dif_gpio_output_set_enabled_masked(const dif_gpio_t *gpio,
+ dif_gpio_mask_t mask,
+ dif_gpio_state_t state);
+
+/**
+ * Enable noise filter for GPIO inputs.
+ *
+ * When enabled, changes in the pin value will be ignored unless stable
+ * for 16 cycles.
+ *
+ * @param gpio A GPIO handle.
+ * @param mask Mask that identifies pins to set the filter state of.
+ * @param state The new toggle state for the filter.
+ * @return The result of the operation.
+ */
+DIF_WARN_UNUSED_RESULT
+dif_gpio_result_t dif_gpio_input_noise_filter_set_enabled(
+ const dif_gpio_t *gpio, dif_gpio_mask_t mask, dif_gpio_toggle_t state);
#ifdef __cplusplus
} // extern "C"
diff --git a/sw/device/sca/aes_serial/aes_serial.c b/sw/device/sca/aes_serial/aes_serial.c
index 348091c..2a45baa 100644
--- a/sw/device/sca/aes_serial/aes_serial.c
+++ b/sw/device/sca/aes_serial/aes_serial.c
@@ -210,12 +210,12 @@
&timer, kHart, kDifRvTimerEnabled) == kDifRvTimerOk);
aes_data_put_wait(plain_text);
- SS_CHECK(dif_gpio_all_write(&gpio, kGpioCaptureTriggerHigh) == kDifGpioOk);
+ SS_CHECK(dif_gpio_write_all(&gpio, kGpioCaptureTriggerHigh) == kDifGpioOk);
aes_manual_trigger();
wait_for_interrupt();
- SS_CHECK(dif_gpio_all_write(&gpio, kGpioCaptureTriggerLow) == kDifGpioOk);
+ SS_CHECK(dif_gpio_write_all(&gpio, kGpioCaptureTriggerLow) == kDifGpioOk);
aes_data_get_wait(cipher_text);
print_cmd_response('r', cipher_text, plain_text_len);
@@ -288,11 +288,11 @@
CHECK(dif_rv_timer_irq_enable(&timer, kHart, kComparator,
kDifRvTimerEnabled) == kDifRvTimerOk);
- dif_gpio_config_t gpio_config = {.base_addr =
+ dif_gpio_params_t gpio_params = {.base_addr =
mmio_region_from_addr(0x40010000)};
- CHECK(dif_gpio_init(&gpio_config, &gpio) == kDifGpioOk);
- CHECK(dif_gpio_output_mode_all_set(&gpio, 0x08200) == kDifGpioOk);
- CHECK(dif_gpio_all_write(&gpio, kGpioCaptureTriggerLow) == kDifGpioOk);
+ CHECK(dif_gpio_init(gpio_params, &gpio) == kDifGpioOk);
+ CHECK(dif_gpio_output_set_enabled_all(&gpio, 0x08200) == kDifGpioOk);
+ CHECK(dif_gpio_write_all(&gpio, kGpioCaptureTriggerLow) == kDifGpioOk);
aes_cfg_t aes_cfg;
aes_cfg.key_len = kAes128;
diff --git a/sw/device/tests/dif/dif_gpio_unittest.cc b/sw/device/tests/dif/dif_gpio_unittest.cc
index 8a4d74f..395a754 100644
--- a/sw/device/tests/dif/dif_gpio_unittest.cc
+++ b/sw/device/tests/dif/dif_gpio_unittest.cc
@@ -29,38 +29,22 @@
class InitTest : public DifGpioTest {};
TEST_F(InitTest, NullArgs) {
- dif_gpio_config_t config{.base_addr = dev().region()};
- dif_gpio_t out_arg_gpio;
+ dif_gpio_params_t params{.base_addr = dev().region()};
- EXPECT_EQ(dif_gpio_init(nullptr, &out_arg_gpio), kDifGpioBadArg);
- EXPECT_EQ(dif_gpio_init(&config, nullptr), kDifGpioBadArg);
- EXPECT_EQ(dif_gpio_init(nullptr, nullptr), kDifGpioBadArg);
+ EXPECT_EQ(dif_gpio_init(params, nullptr), kDifGpioBadArg);
}
TEST_F(InitTest, Init) {
- // Note: `dif_gpio_init` does not write to `GPIO_MASKED_OE_*` and
- // `GPIO_MASKED_OUT_*` since it directly resets `GPIO_DIRECT_OE` and
- // `GPIO_DIRECT_OUT`.
- EXPECT_WRITE32(GPIO_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_WRITE32(GPIO_DIRECT_OE_REG_OFFSET, 0);
- EXPECT_WRITE32(GPIO_DIRECT_OUT_REG_OFFSET, 0);
- EXPECT_WRITE32(GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, 0);
- EXPECT_WRITE32(GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, 0);
- EXPECT_WRITE32(GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, 0);
- EXPECT_WRITE32(GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, 0);
- EXPECT_WRITE32(GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, 0);
- EXPECT_WRITE32(GPIO_INTR_STATE_REG_OFFSET, kAllOnes);
-
- dif_gpio_config_t config{.base_addr = dev().region()};
+ dif_gpio_params_t params{.base_addr = dev().region()};
dif_gpio_t gpio;
- EXPECT_EQ(dif_gpio_init(&config, &gpio), kDifGpioOk);
+ EXPECT_EQ(dif_gpio_init(params, &gpio), kDifGpioOk);
}
// Base class for the rest of the tests in this file, provides a
// `dif_gpio_t` instance.
class DifGpioTestInitialized : public DifGpioTest {
protected:
- const dif_gpio_t gpio_ = {.base_addr = dev().region()};
+ const dif_gpio_t gpio_ = {.params = {.base_addr = dev().region()}};
};
// Reset tests
@@ -88,24 +72,24 @@
class ReadTest : public DifGpioTestInitialized {};
TEST_F(ReadTest, NullArgs) {
- uint32_t out_arg_uint32_t;
+ dif_gpio_state_t out_arg_uint32_t;
bool out_arg_bool;
- EXPECT_EQ(dif_gpio_all_read(nullptr, &out_arg_uint32_t), kDifGpioBadArg);
- EXPECT_EQ(dif_gpio_all_read(&gpio_, nullptr), kDifGpioBadArg);
- EXPECT_EQ(dif_gpio_all_read(nullptr, nullptr), kDifGpioBadArg);
+ EXPECT_EQ(dif_gpio_read_all(nullptr, &out_arg_uint32_t), kDifGpioBadArg);
+ EXPECT_EQ(dif_gpio_read_all(&gpio_, nullptr), kDifGpioBadArg);
+ EXPECT_EQ(dif_gpio_read_all(nullptr, nullptr), kDifGpioBadArg);
- EXPECT_EQ(dif_gpio_pin_read(nullptr, 0, &out_arg_bool), kDifGpioBadArg);
- EXPECT_EQ(dif_gpio_pin_read(&gpio_, 0, nullptr), kDifGpioBadArg);
- EXPECT_EQ(dif_gpio_pin_read(nullptr, 0, nullptr), kDifGpioBadArg);
+ EXPECT_EQ(dif_gpio_read(nullptr, 0, &out_arg_bool), kDifGpioBadArg);
+ EXPECT_EQ(dif_gpio_read(&gpio_, 0, nullptr), kDifGpioBadArg);
+ EXPECT_EQ(dif_gpio_read(nullptr, 0, nullptr), kDifGpioBadArg);
}
TEST_F(ReadTest, AllPins) {
constexpr uint32_t kVal = 0xA5A5A5A5;
EXPECT_READ32(GPIO_DATA_IN_REG_OFFSET, kVal);
- uint32_t pin_values = 0;
- EXPECT_EQ(dif_gpio_all_read(&gpio_, &pin_values), kDifGpioOk);
+ dif_gpio_state_t pin_values = 0;
+ EXPECT_EQ(dif_gpio_read_all(&gpio_, &pin_values), kDifGpioOk);
EXPECT_EQ(pin_values, kVal);
}
@@ -115,8 +99,9 @@
const uint32_t reg_val =
exp_pin_val ? AllZerosExcept(pin) : AllOnesExcept(pin);
EXPECT_READ32(GPIO_DATA_IN_REG_OFFSET, reg_val);
+
bool pin_val = !exp_pin_val;
- EXPECT_EQ(dif_gpio_pin_read(&gpio_, pin, &pin_val), kDifGpioOk);
+ EXPECT_EQ(dif_gpio_read(&gpio_, pin, &pin_val), kDifGpioOk);
EXPECT_EQ(pin_val, exp_pin_val);
}
}
@@ -126,16 +111,16 @@
class WriteTest : public DifGpioTestInitialized {};
TEST_F(WriteTest, NullArgs) {
- EXPECT_EQ(dif_gpio_all_write(nullptr, kAllOnes), kDifGpioBadArg);
- EXPECT_EQ(dif_gpio_pin_write(nullptr, 0, true), kDifGpioBadArg);
- EXPECT_EQ(dif_gpio_masked_write(nullptr, kAllOnes, kAllOnes), kDifGpioBadArg);
+ EXPECT_EQ(dif_gpio_write_all(nullptr, kAllOnes), kDifGpioBadArg);
+ EXPECT_EQ(dif_gpio_write(nullptr, 0, true), kDifGpioBadArg);
+ EXPECT_EQ(dif_gpio_write_masked(nullptr, kAllOnes, kAllOnes), kDifGpioBadArg);
}
TEST_F(WriteTest, AllPins) {
constexpr uint32_t kVal = 0xA5A5A5A5;
EXPECT_WRITE32(GPIO_DIRECT_OUT_REG_OFFSET, kVal);
- EXPECT_EQ(dif_gpio_all_write(&gpio_, kVal), kDifGpioOk);
+ EXPECT_EQ(dif_gpio_write_all(&gpio_, kVal), kDifGpioOk);
}
// The GPIO device provides masked bit-level atomic writes to its DIRECT_OUT
@@ -160,37 +145,38 @@
TEST_F(WriteTest, SinglePin) {
EXPECT_WRITE32(GPIO_MASKED_OUT_LOWER_REG_OFFSET, {{16, 1}, {0, 1}});
- EXPECT_EQ(dif_gpio_pin_write(&gpio_, 0, true), kDifGpioOk);
+ EXPECT_EQ(dif_gpio_write(&gpio_, 0, true), kDifGpioOk);
EXPECT_WRITE32(GPIO_MASKED_OUT_LOWER_REG_OFFSET, {{31, 1}, {15, 0}});
- EXPECT_EQ(dif_gpio_pin_write(&gpio_, 15, false), kDifGpioOk);
+ EXPECT_EQ(dif_gpio_write(&gpio_, 15, false), kDifGpioOk);
EXPECT_WRITE32(GPIO_MASKED_OUT_UPPER_REG_OFFSET, {{16, 1}, {0, 1}});
- EXPECT_EQ(dif_gpio_pin_write(&gpio_, 16, true), kDifGpioOk);
+ EXPECT_EQ(dif_gpio_write(&gpio_, 16, true), kDifGpioOk);
EXPECT_WRITE32(GPIO_MASKED_OUT_UPPER_REG_OFFSET, {{31, 1}, {15, 0}});
- EXPECT_EQ(dif_gpio_pin_write(&gpio_, 31, false), kDifGpioOk);
+ EXPECT_EQ(dif_gpio_write(&gpio_, 31, false), kDifGpioOk);
}
TEST_F(WriteTest, Masked) {
EXPECT_WRITE32(GPIO_MASKED_OUT_LOWER_REG_OFFSET, 0xCDCD3322);
EXPECT_WRITE32(GPIO_MASKED_OUT_UPPER_REG_OFFSET, 0xABAB5544);
- EXPECT_EQ(dif_gpio_masked_write(&gpio_, 0xABABCDCD, 0x55443322), kDifGpioOk);
+ EXPECT_EQ(dif_gpio_write_masked(&gpio_, 0xABABCDCD, 0x55443322), kDifGpioOk);
EXPECT_WRITE32(GPIO_MASKED_OUT_UPPER_REG_OFFSET, 0xABAB5544);
- EXPECT_EQ(dif_gpio_masked_write(&gpio_, 0xABAB0000, 0x55443322), kDifGpioOk);
+ EXPECT_EQ(dif_gpio_write_masked(&gpio_, 0xABAB0000, 0x55443322), kDifGpioOk);
EXPECT_WRITE32(GPIO_MASKED_OUT_LOWER_REG_OFFSET, 0xCDCD3322);
- EXPECT_EQ(dif_gpio_masked_write(&gpio_, 0x0000CDCD, 0x55443322), kDifGpioOk);
+ EXPECT_EQ(dif_gpio_write_masked(&gpio_, 0x0000CDCD, 0x55443322), kDifGpioOk);
}
// Output mode tests
class OutputModeTest : public DifGpioTestInitialized {};
TEST_F(OutputModeTest, NullArgs) {
- EXPECT_EQ(dif_gpio_output_mode_all_set(nullptr, kAllOnes), kDifGpioBadArg);
- EXPECT_EQ(dif_gpio_output_mode_pin_set(nullptr, 0, true), kDifGpioBadArg);
- EXPECT_EQ(dif_gpio_output_mode_masked_set(nullptr, kAllOnes, kAllOnes),
+ EXPECT_EQ(dif_gpio_output_set_enabled_all(nullptr, kAllOnes), kDifGpioBadArg);
+ EXPECT_EQ(dif_gpio_output_set_enabled(nullptr, 0, kDifGpioToggleEnabled),
+ kDifGpioBadArg);
+ EXPECT_EQ(dif_gpio_output_set_enabled_masked(nullptr, kAllOnes, kAllOnes),
kDifGpioBadArg);
}
@@ -198,35 +184,39 @@
constexpr uint32_t kVal = 0xA5A5A5A5;
EXPECT_WRITE32(GPIO_DIRECT_OE_REG_OFFSET, kVal);
- EXPECT_EQ(dif_gpio_output_mode_all_set(&gpio_, kVal), kDifGpioOk);
+ EXPECT_EQ(dif_gpio_output_set_enabled_all(&gpio_, kVal), kDifGpioOk);
}
TEST_F(OutputModeTest, SinglePin) {
EXPECT_WRITE32(GPIO_MASKED_OE_LOWER_REG_OFFSET, {{16, 1}, {0, 1}});
- EXPECT_EQ(dif_gpio_output_mode_pin_set(&gpio_, 0, true), kDifGpioOk);
+ EXPECT_EQ(dif_gpio_output_set_enabled(&gpio_, 0, kDifGpioToggleEnabled),
+ kDifGpioOk);
EXPECT_WRITE32(GPIO_MASKED_OE_LOWER_REG_OFFSET, {{31, 1}, {15, 0}});
- EXPECT_EQ(dif_gpio_output_mode_pin_set(&gpio_, 15, false), kDifGpioOk);
+ EXPECT_EQ(dif_gpio_output_set_enabled(&gpio_, 15, kDifGpioToggleDisabled),
+ kDifGpioOk);
EXPECT_WRITE32(GPIO_MASKED_OE_UPPER_REG_OFFSET, {{16, 1}, {0, 1}});
- EXPECT_EQ(dif_gpio_output_mode_pin_set(&gpio_, 16, true), kDifGpioOk);
+ EXPECT_EQ(dif_gpio_output_set_enabled(&gpio_, 16, kDifGpioToggleEnabled),
+ kDifGpioOk);
EXPECT_WRITE32(GPIO_MASKED_OE_UPPER_REG_OFFSET, {{31, 1}, {15, 0}});
- EXPECT_EQ(dif_gpio_output_mode_pin_set(&gpio_, 31, false), kDifGpioOk);
+ EXPECT_EQ(dif_gpio_output_set_enabled(&gpio_, 31, kDifGpioToggleDisabled),
+ kDifGpioOk);
}
TEST_F(OutputModeTest, Masked) {
EXPECT_WRITE32(GPIO_MASKED_OE_LOWER_REG_OFFSET, 0xCDCD3322);
EXPECT_WRITE32(GPIO_MASKED_OE_UPPER_REG_OFFSET, 0xABAB5544);
- EXPECT_EQ(dif_gpio_output_mode_masked_set(&gpio_, 0xABABCDCD, 0x55443322),
+ EXPECT_EQ(dif_gpio_output_set_enabled_masked(&gpio_, 0xABABCDCD, 0x55443322),
kDifGpioOk);
EXPECT_WRITE32(GPIO_MASKED_OE_LOWER_REG_OFFSET, 0xCDCD3322);
- EXPECT_EQ(dif_gpio_output_mode_masked_set(&gpio_, 0x0000CDCD, 0x55443322),
+ EXPECT_EQ(dif_gpio_output_set_enabled_masked(&gpio_, 0x0000CDCD, 0x55443322),
kDifGpioOk);
EXPECT_WRITE32(GPIO_MASKED_OE_UPPER_REG_OFFSET, 0xABAB5544);
- EXPECT_EQ(dif_gpio_output_mode_masked_set(&gpio_, 0xABAB0000, 0x55443322),
+ EXPECT_EQ(dif_gpio_output_set_enabled_masked(&gpio_, 0xABAB0000, 0x55443322),
kDifGpioOk);
}
@@ -234,9 +224,11 @@
class InputFilterTest : public DifGpioTestInitialized {};
TEST_F(InputFilterTest, NullArgs) {
- EXPECT_EQ(dif_gpio_input_noise_filter_masked_enable(nullptr, kAllOnes),
+ EXPECT_EQ(dif_gpio_input_noise_filter_set_enabled(nullptr, kAllOnes,
+ kDifGpioToggleEnabled),
kDifGpioBadArg);
- EXPECT_EQ(dif_gpio_input_noise_filter_masked_disable(nullptr, kAllOnes),
+ EXPECT_EQ(dif_gpio_input_noise_filter_set_enabled(nullptr, kAllOnes,
+ kDifGpioToggleDisabled),
kDifGpioBadArg);
}
@@ -245,7 +237,8 @@
EXPECT_READ32(GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, 0x0);
EXPECT_WRITE32(GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, kVal);
- EXPECT_EQ(dif_gpio_input_noise_filter_masked_enable(&gpio_, kVal),
+ EXPECT_EQ(dif_gpio_input_noise_filter_set_enabled(&gpio_, kVal,
+ kDifGpioToggleEnabled),
kDifGpioOk);
}
@@ -254,7 +247,8 @@
EXPECT_READ32(GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, kAllOnes);
EXPECT_WRITE32(GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, ~kVal);
- EXPECT_EQ(dif_gpio_input_noise_filter_masked_disable(&gpio_, kVal),
+ EXPECT_EQ(dif_gpio_input_noise_filter_set_enabled(&gpio_, kVal,
+ kDifGpioToggleDisabled),
kDifGpioOk);
}
@@ -275,44 +269,42 @@
};
TEST_F(IrqTest, NullArgs) {
- EXPECT_EQ(dif_gpio_irq_pin_test(nullptr, 0), kDifGpioBadArg);
+ EXPECT_EQ(dif_gpio_irq_force(nullptr, 0), kDifGpioBadArg);
- uint32_t out_arg_uint32_t;
- EXPECT_EQ(dif_gpio_irq_all_read(nullptr, &out_arg_uint32_t), kDifGpioBadArg);
- EXPECT_EQ(dif_gpio_irq_all_read(&gpio_, nullptr), kDifGpioBadArg);
- EXPECT_EQ(dif_gpio_irq_all_read(nullptr, nullptr), kDifGpioBadArg);
+ dif_gpio_state_t out_arg_uint32_t;
+ EXPECT_EQ(dif_gpio_irq_is_pending_all(nullptr, &out_arg_uint32_t),
+ kDifGpioBadArg);
+ EXPECT_EQ(dif_gpio_irq_is_pending_all(&gpio_, nullptr), kDifGpioBadArg);
+ EXPECT_EQ(dif_gpio_irq_is_pending_all(nullptr, nullptr), kDifGpioBadArg);
bool out_arg_bool;
- EXPECT_EQ(dif_gpio_irq_pin_read(nullptr, 0, &out_arg_bool), kDifGpioBadArg);
- EXPECT_EQ(dif_gpio_irq_pin_read(&gpio_, 0, nullptr), kDifGpioBadArg);
- EXPECT_EQ(dif_gpio_irq_pin_read(nullptr, 0, nullptr), kDifGpioBadArg);
+ EXPECT_EQ(dif_gpio_irq_is_pending(nullptr, 0, &out_arg_bool), kDifGpioBadArg);
+ EXPECT_EQ(dif_gpio_irq_is_pending(&gpio_, 0, nullptr), kDifGpioBadArg);
+ EXPECT_EQ(dif_gpio_irq_is_pending(nullptr, 0, nullptr), kDifGpioBadArg);
- EXPECT_EQ(dif_gpio_irq_pin_clear(nullptr, 0), kDifGpioBadArg);
+ EXPECT_EQ(dif_gpio_irq_acknowledge(nullptr, 0), kDifGpioBadArg);
- EXPECT_EQ(dif_gpio_irq_masked_enable(nullptr, kAllOnes), kDifGpioBadArg);
+ EXPECT_EQ(
+ dif_gpio_irq_set_enabled_masked(nullptr, kAllOnes, kDifGpioToggleEnabled),
+ kDifGpioBadArg);
- EXPECT_EQ(dif_gpio_irq_masked_disable(nullptr, kAllOnes), kDifGpioBadArg);
-
- EXPECT_EQ(dif_gpio_irq_trigger_masked_disable(nullptr, kAllOnes),
- kDifGpioBadArg);
-
- EXPECT_EQ(dif_gpio_irq_trigger_masked_config(nullptr, kAllOnes,
- kDifGpioIrqEdgeRising),
- kDifGpioBadArg);
+ EXPECT_EQ(
+ dif_gpio_irq_set_trigger(nullptr, kAllOnes, kDifGpioIrqTriggerEdgeRising),
+ kDifGpioBadArg);
}
TEST_F(IrqTest, ForceSinglePin) {
for (uint32_t pin = 0; pin < 32; ++pin) {
EXPECT_WRITE32(GPIO_INTR_TEST_REG_OFFSET, {{pin, 1}});
- EXPECT_EQ(dif_gpio_irq_pin_test(&gpio_, pin), kDifGpioOk);
+ EXPECT_EQ(dif_gpio_irq_force(&gpio_, pin), kDifGpioOk);
}
}
TEST_F(IrqTest, ReadAllPins) {
constexpr uint32_t kVal = 0xABABABAB;
EXPECT_READ32(GPIO_INTR_STATE_REG_OFFSET, kVal);
- uint32_t irq_state = 0;
- EXPECT_EQ(dif_gpio_irq_all_read(&gpio_, &irq_state), kDifGpioOk);
+ dif_gpio_state_t irq_state = 0;
+ EXPECT_EQ(dif_gpio_irq_is_pending_all(&gpio_, &irq_state), kDifGpioOk);
EXPECT_EQ(irq_state, kVal);
}
@@ -323,7 +315,7 @@
exp_irq_state ? AllZerosExcept(pin) : AllOnesExcept(pin);
EXPECT_READ32(GPIO_INTR_STATE_REG_OFFSET, reg_val);
bool irq_state = !exp_irq_state;
- EXPECT_EQ(dif_gpio_irq_pin_read(&gpio_, pin, &irq_state), kDifGpioOk);
+ EXPECT_EQ(dif_gpio_irq_is_pending(&gpio_, pin, &irq_state), kDifGpioOk);
EXPECT_EQ(irq_state, exp_irq_state);
}
}
@@ -332,7 +324,7 @@
TEST_F(IrqTest, ClearSinglePin) {
for (uint32_t pin = 0; pin < 32; ++pin) {
EXPECT_WRITE32(GPIO_INTR_STATE_REG_OFFSET, {{pin, 1}});
- EXPECT_EQ(dif_gpio_irq_pin_clear(&gpio_, pin), kDifGpioOk);
+ EXPECT_EQ(dif_gpio_irq_acknowledge(&gpio_, pin), kDifGpioOk);
}
}
@@ -341,7 +333,9 @@
EXPECT_READ32(GPIO_INTR_ENABLE_REG_OFFSET, 0x0);
EXPECT_WRITE32(GPIO_INTR_ENABLE_REG_OFFSET, kVal);
- EXPECT_EQ(dif_gpio_irq_masked_enable(&gpio_, kVal), kDifGpioOk);
+ EXPECT_EQ(
+ dif_gpio_irq_set_enabled_masked(&gpio_, kVal, kDifGpioToggleEnabled),
+ kDifGpioOk);
}
TEST_F(IrqTest, MaskedDisable) {
@@ -349,7 +343,9 @@
EXPECT_READ32(GPIO_INTR_ENABLE_REG_OFFSET, kAllOnes);
EXPECT_WRITE32(GPIO_INTR_ENABLE_REG_OFFSET, ~kVal);
- EXPECT_EQ(dif_gpio_irq_masked_disable(&gpio_, kVal), kDifGpioOk);
+ EXPECT_EQ(
+ dif_gpio_irq_set_enabled_masked(&gpio_, kVal, kDifGpioToggleDisabled),
+ kDifGpioOk);
}
TEST_F(IrqTest, MaskedConfigTriggerEdgeRising) {
@@ -360,7 +356,7 @@
EXPECT_WRITE32(GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, kVal);
EXPECT_EQ(
- dif_gpio_irq_trigger_masked_config(&gpio_, kVal, kDifGpioIrqEdgeRising),
+ dif_gpio_irq_set_trigger(&gpio_, kVal, kDifGpioIrqTriggerEdgeRising),
kDifGpioOk);
}
@@ -372,7 +368,7 @@
EXPECT_WRITE32(GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, kVal);
EXPECT_EQ(
- dif_gpio_irq_trigger_masked_config(&gpio_, kVal, kDifGpioIrqEdgeFalling),
+ dif_gpio_irq_set_trigger(&gpio_, kVal, kDifGpioIrqTriggerEdgeFalling),
kDifGpioOk);
}
@@ -383,9 +379,8 @@
EXPECT_READ32(GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, 0);
EXPECT_WRITE32(GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, kVal);
- EXPECT_EQ(
- dif_gpio_irq_trigger_masked_config(&gpio_, kVal, kDifGpioIrqLevelLow),
- kDifGpioOk);
+ EXPECT_EQ(dif_gpio_irq_set_trigger(&gpio_, kVal, kDifGpioIrqTriggerLevelLow),
+ kDifGpioOk);
}
TEST_F(IrqTest, MaskedConfigTriggerLevelHigh) {
@@ -395,9 +390,8 @@
EXPECT_READ32(GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, 0);
EXPECT_WRITE32(GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, kVal);
- EXPECT_EQ(
- dif_gpio_irq_trigger_masked_config(&gpio_, kVal, kDifGpioIrqLevelHigh),
- kDifGpioOk);
+ EXPECT_EQ(dif_gpio_irq_set_trigger(&gpio_, kVal, kDifGpioIrqTriggerLevelHigh),
+ kDifGpioOk);
}
TEST_F(IrqTest, MaskedConfigTriggerEdgeRisingFalling) {
@@ -409,8 +403,8 @@
EXPECT_READ32(GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, 0);
EXPECT_WRITE32(GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, kVal);
- EXPECT_EQ(dif_gpio_irq_trigger_masked_config(&gpio_, kVal,
- kDifGpioIrqEdgeRisingFalling),
+ EXPECT_EQ(dif_gpio_irq_set_trigger(&gpio_, kVal,
+ kDifGpioIrqTriggerEdgeRisingFalling),
kDifGpioOk);
}
@@ -423,8 +417,8 @@
EXPECT_READ32(GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, 0);
EXPECT_WRITE32(GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, kVal);
- EXPECT_EQ(dif_gpio_irq_trigger_masked_config(&gpio_, kVal,
- kDifGpioIrqEdgeRisingLevelLow),
+ EXPECT_EQ(dif_gpio_irq_set_trigger(&gpio_, kVal,
+ kDifGpioIrqTriggerEdgeRisingLevelLow),
kDifGpioOk);
}
@@ -437,8 +431,8 @@
EXPECT_READ32(GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, 0);
EXPECT_WRITE32(GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, kVal);
- EXPECT_EQ(dif_gpio_irq_trigger_masked_config(&gpio_, kVal,
- kDifGpioIrqEdgeFallingLevelHigh),
+ EXPECT_EQ(dif_gpio_irq_set_trigger(&gpio_, kVal,
+ kDifGpioIrqTriggerEdgeFallingLevelHigh),
kDifGpioOk);
}
@@ -447,18 +441,10 @@
constexpr uint32_t kVal = 0xABABABAB;
ExpectIrqTriggerMaskedDisable(kVal);
- EXPECT_EQ(dif_gpio_irq_trigger_masked_config(
- &gpio_, kVal, static_cast<dif_gpio_irq_t>(kAllOnes)),
+ EXPECT_EQ(dif_gpio_irq_set_trigger(
+ &gpio_, kVal, static_cast<dif_gpio_irq_trigger_t>(kAllOnes)),
kDifGpioError);
}
-TEST_F(IrqTest, MaskedDisableTrigger) {
- SCOPED_TRACE("IrqTest.MaskedDisableTrigger");
- constexpr uint32_t kVal = 0xABABABAB;
- ExpectIrqTriggerMaskedDisable(kVal);
-
- EXPECT_EQ(dif_gpio_irq_trigger_masked_disable(&gpio_, kVal), kDifGpioOk);
-}
-
} // namespace
} // namespace dif_gpio_unittest
diff --git a/sw/device/tests/sim_dv/gpio_test.c b/sw/device/tests/sim_dv/gpio_test.c
index 2f3a2b4..87a0194 100644
--- a/sw/device/tests/sim_dv/gpio_test.c
+++ b/sw/device/tests/sim_dv/gpio_test.c
@@ -105,19 +105,19 @@
LOG_INFO("Starting GPIO output test");
// Set the GPIOs to be in output mode.
- CHECK(dif_gpio_output_mode_all_set(gpio, kGpiosAllowedMask) == kDifGpioOk,
- "dif_gpio_output_mode_all_set failed");
+ CHECK(dif_gpio_output_set_enabled_all(gpio, kGpiosAllowedMask) == kDifGpioOk,
+ "dif_gpio_output_set_enabled_all failed");
// Walk 1s - 0001, 0010, 0100, 1000, etc.
for (uint32_t i = 0; i < kNumGpios; ++i) {
uint32_t gpio_val = 1 << i;
- CHECK(dif_gpio_all_write(gpio, gpio_val) == kDifGpioOk,
- "dif_gpio_all_write failed");
+ CHECK(dif_gpio_write_all(gpio, gpio_val) == kDifGpioOk,
+ "dif_gpio_write_all failed");
// Read GPIO_IN to confirm what we wrote.
uint32_t read_val;
- CHECK(dif_gpio_all_read(gpio, &read_val) == kDifGpioOk,
- "dif_gpio_all_read failed");
+ CHECK(dif_gpio_read_all(gpio, &read_val) == kDifGpioOk,
+ "dif_gpio_read_all failed");
// Check written and read val for correctness.
// Though we try to set all available GPIOs, only the ones that are exposed
@@ -130,23 +130,23 @@
}
// Write all 0s to the GPIOs.
- CHECK(dif_gpio_all_write(gpio, ~kGpiosMask) == kDifGpioOk,
- "dif_gpio_all_write failed");
+ CHECK(dif_gpio_write_all(gpio, ~kGpiosMask) == kDifGpioOk,
+ "dif_gpio_write_all failed");
// Write all 1s to the GPIOs.
- CHECK(dif_gpio_all_write(gpio, kGpiosMask) == kDifGpioOk,
- "dif_gpio_all_write failed");
+ CHECK(dif_gpio_write_all(gpio, kGpiosMask) == kDifGpioOk,
+ "dif_gpio_write_all failed");
// Now walk 0s - 1110, 1101, 1011, 0111, etc.
for (uint32_t i = 0; i < kNumGpios; ++i) {
uint32_t gpio_val = ~(1 << i);
- CHECK(dif_gpio_all_write(gpio, gpio_val) == kDifGpioOk,
- "dif_gpio_all_write failed");
+ CHECK(dif_gpio_write_all(gpio, gpio_val) == kDifGpioOk,
+ "dif_gpio_write_all failed");
// Read GPIO_IN to confirm what we wrote.
uint32_t read_val;
- CHECK(dif_gpio_all_read(gpio, &read_val) == kDifGpioOk,
- "dif_gpio_all_read failed");
+ CHECK(dif_gpio_read_all(gpio, &read_val) == kDifGpioOk,
+ "dif_gpio_read_all failed");
// Check written and read val for correctness.
// Though we try to set all available GPIOs, only the ones that are exposed
@@ -159,12 +159,12 @@
}
// Write all 1s to the GPIOs.
- CHECK(dif_gpio_all_write(gpio, kGpiosMask) == kDifGpioOk,
- "dif_gpio_all_write failed");
+ CHECK(dif_gpio_write_all(gpio, kGpiosMask) == kDifGpioOk,
+ "dif_gpio_write_all failed");
// Write all 0s to the GPIOs.
- CHECK(dif_gpio_all_write(gpio, ~kGpiosMask) == kDifGpioOk,
- "dif_gpio_all_write failed");
+ CHECK(dif_gpio_write_all(gpio, ~kGpiosMask) == kDifGpioOk,
+ "dif_gpio_write_all failed");
}
/**
@@ -181,23 +181,24 @@
LOG_INFO("Starting GPIO input test");
// Enable the noise filter on all GPIOs.
- CHECK(dif_gpio_input_noise_filter_masked_enable(gpio, kGpiosAllowedMask) ==
- kDifGpioOk,
- "dif_gpio_input_noise_filter_masked_enable failed");
+ CHECK(dif_gpio_input_noise_filter_set_enabled(
+ gpio, kGpiosAllowedMask, kDifGpioToggleEnabled) == kDifGpioOk,
+ "dif_gpio_input_noise_filter_set_enabled failed");
// Configure all GPIOs to be rising and falling edge interrupts.
- CHECK(
- dif_gpio_irq_trigger_masked_config(
- gpio, kGpiosAllowedMask, kDifGpioIrqEdgeRisingFalling) == kDifGpioOk,
- "dif_gpio_irq_trigger_masked_config failed");
+ CHECK(dif_gpio_irq_set_trigger(gpio, kGpiosAllowedMask,
+ kDifGpioIrqTriggerEdgeRisingFalling) ==
+ kDifGpioOk,
+ "dif_gpio_irq_set_trigger failed");
// Enable interrupts on all GPIOs.
- CHECK(dif_gpio_irq_masked_enable(gpio, kGpiosAllowedMask) == kDifGpioOk,
- "dif_gpio_irq_masked_enable failed");
+ CHECK(dif_gpio_irq_set_enabled_masked(gpio, kGpiosAllowedMask,
+ kDifGpioToggleEnabled) == kDifGpioOk,
+ "dif_gpio_irq_set_enabled_masked failed");
// Set the GPIOs to be in input mode.
- CHECK(dif_gpio_output_mode_all_set(gpio, 0u) == kDifGpioOk,
- "dif_gpio_output_mode_all_set failed");
+ CHECK(dif_gpio_output_set_enabled_all(gpio, 0u) == kDifGpioOk,
+ "dif_gpio_output_set_enabled_all failed");
// Wait for rising edge interrupt on each pin.
expected_irq_edge = true;
@@ -244,24 +245,24 @@
// Check if the same interrupt fired at GPIO as well.
uint32_t gpio_irqs_status;
- CHECK(dif_gpio_irq_all_read(&gpio, &gpio_irqs_status) == kDifGpioOk,
- "dif_gpio_irq_all_read failed");
+ CHECK(dif_gpio_irq_is_pending_all(&gpio, &gpio_irqs_status) == kDifGpioOk,
+ "dif_gpio_irq_is_pending_all failed");
CHECK(gpio_irqs_status == (1 << expected_gpio_pin_irq),
"Incorrect GPIO irqs status {exp: %x, obs: %x}",
(1 << expected_gpio_pin_irq), gpio_irqs_status);
// Read the gpio pin value to ensure the right value is being reflected.
bool pin_val;
- CHECK(dif_gpio_pin_read(&gpio, expected_gpio_pin_irq, &pin_val) == kDifGpioOk,
- "dif_gpio_pin_read failed");
+ CHECK(dif_gpio_read(&gpio, expected_gpio_pin_irq, &pin_val) == kDifGpioOk,
+ "dif_gpio_read failed");
// Check if the pin value is set correctly.
CHECK(pin_val == expected_irq_edge, "Incorrect GPIO %d pin value (exp: %b)",
expected_gpio_pin_irq, expected_irq_edge);
// Clear the interrupt at GPIO.
- CHECK(dif_gpio_irq_pin_clear(&gpio, gpio_pin_irq_fired) == kDifGpioOk,
- "dif_gpio_irq_pin_clear failed");
+ CHECK(dif_gpio_irq_acknowledge(&gpio, gpio_pin_irq_fired) == kDifGpioOk,
+ "dif_gpio_irq_acknowledge failed");
// Complete the IRQ at PLIC.
CHECK(dif_plic_irq_complete(&plic, kTopEarlgreyPlicTargetIbex0,
@@ -276,9 +277,9 @@
pinmux_init();
// Initialize the GPIO.
- dif_gpio_config_t gpio_config = {
+ dif_gpio_params_t gpio_params = {
.base_addr = mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR)};
- CHECK(dif_gpio_init(&gpio_config, &gpio) == kDifGpioOk,
+ CHECK(dif_gpio_init(gpio_params, &gpio) == kDifGpioOk,
"dif_gpio_init failed");
// Initialize the PLIC.
