| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| { name: "PWRMGR", |
| clock_primary: "clk_i", |
| other_clock_list: [ "clk_slow_i" ] |
| reset_primary: "rst_ni", |
| other_reset_list: [ "rst_slow_ni" ] |
| bus_device: "tlul", |
| interrupt_list: [ |
| { name: "wakeup", desc: "Wake from low power state. See wake info for more details" }, |
| ], |
| |
| // Define flash_ctrl <-> flash_phy struct package |
| inter_signal_list: [ |
| { struct: "pwr_ast", |
| type: "req_rsp", |
| name: "pwr_ast", |
| act: "requester", |
| package: "pwrmgr_pkg", |
| }, |
| |
| { struct: "pwr_rst", |
| type: "req_rsp", |
| name: "pwr_rst", |
| act: "requester", |
| package: "pwrmgr_pkg", |
| }, |
| |
| { struct: "pwr_clk", |
| type: "req_rsp", |
| name: "pwr_clk", |
| act: "requester", |
| package: "pwrmgr_pkg", |
| }, |
| |
| { struct: "pwr_otp", |
| type: "req_rsp", |
| name: "pwr_otp", |
| act: "requester", |
| package: "pwrmgr_pkg", |
| }, |
| |
| { struct: "pwr_lc", |
| type: "req_rsp", |
| name: "pwr_lc", |
| act: "requester", |
| package: "pwrmgr_pkg", |
| }, |
| |
| { struct: "pwr_pinmux", |
| type: "broadcast", |
| name: "pwr_pinmux", |
| act: "receiver", |
| package: "pwrmgr_pkg", |
| }, |
| |
| { struct: "pwr_peris", |
| type: "broadcast", |
| name: "pwr_peris", |
| act: "receiver", |
| package: "pwrmgr_pkg", |
| }, |
| |
| ], |
| |
| param_list: [ |
| ], |
| |
| regwidth: "32", |
| registers: [ |
| |
| { name: "CTRL_CFG_REGWEN", |
| swaccess: "rw0c", |
| hwaccess: "hwo", |
| hwext: "true", |
| hwqe: "true", |
| desc: ''' |
| Controls the configurability of the CONTROL register. |
| |
| This register ensures the contents do not change once a low power hint and |
| WFI has occurred. |
| |
| It unlocks whenever a low power transition has completed (transition back to the |
| ACTIVE state) for any reason. |
| ''', |
| |
| fields: [ |
| { bits: "0", |
| name: "EN", |
| desc: "Configuration enable. Once set to 0, it can longer be configured to 1", |
| resval: "1", |
| }, |
| ] |
| }, |
| |
| { name: "CONTROL", |
| desc: "Control register", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "CTRL_CFG_REGWEN", |
| fields: [ |
| { bits: "0", |
| hwaccess: "hrw", |
| name: "LOW_POWER_HINT", |
| desc: ''' |
| The low power hint to power manager. |
| The hint is an indication for how the manager should treat the next WFI. |
| ''' |
| resval: "0" |
| enum: [ |
| { value: "0", |
| name: "None", |
| desc: ''' |
| No low power intent |
| ''' |
| }, |
| { value: "1", |
| name: "Low Power", |
| desc: ''' |
| Next WFI should trigger low power entry |
| ''' |
| }, |
| ] |
| }, |
| |
| { bits: "4", |
| name: "CORE_CLK_EN", |
| desc: "core clock enable during low power state", |
| resval: "0" |
| enum: [ |
| { value: "0", |
| name: "Disabled", |
| desc: ''' |
| Core clock disabled during low power state |
| ''' |
| }, |
| { value: "1", |
| name: "Enabled", |
| desc: ''' |
| Core clock enabled during low power state |
| ''' |
| }, |
| ] |
| }, |
| |
| { bits: "5", |
| name: "IO_CLK_EN", |
| desc: "IO clock enable during low power state", |
| resval: "0" |
| enum: [ |
| { value: "0", |
| name: "Disabled", |
| desc: ''' |
| IO clock disabled during low power state |
| ''' |
| }, |
| { value: "1", |
| name: "Enabled", |
| desc: ''' |
| IO clock enabled during low power state |
| ''' |
| }, |
| ] |
| }, |
| |
| { bits: "6", |
| name: "MAIN_PDB", |
| desc: "Main power domain power down", |
| resval: "1" |
| enum: [ |
| { value: "0", |
| name: "Power down", |
| desc: ''' |
| Main power domain is powered down during low power state |
| ''' |
| }, |
| { value: "1", |
| name: "Power up", |
| desc: ''' |
| Main power domain is kept powered during low power state |
| ''' |
| }, |
| ] |
| }, |
| ], |
| }, |
| |
| { name: "WAKEUP_EN_REGWEN", |
| desc: "Configuration enable for wakeup register", |
| swaccess: "rw0c", |
| hwaccess: "none", |
| fields: [ |
| { bits: "0", |
| resval: "1" |
| name: "EN", |
| desc: ''' |
| When 1, WAKEUP register can be configured. |
| When 0, WAKEUP register cannot be configured. |
| ''', |
| }, |
| ] |
| }, |
| |
| { name: "WAKEUP_EN", |
| desc: "Bit mask for enabled wakeups", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "WAKEUP_EN_REGWEN", |
| resval: "0" |
| fields: [ |
| { bits: "15:0", |
| name: "EN", |
| desc: ''' |
| Whenever a particular bit is set to 1, that wakeup is also enabled. |
| Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. |
| ''', |
| }, |
| ] |
| }, |
| |
| { name: "WAKE_STATUS", |
| desc: "A read only register of all current wake requests post enable mask", |
| swaccess: "ro", |
| hwaccess: "none", |
| resval: "0" |
| fields: [ |
| { bits: "15:0", |
| name: "VAL", |
| desc: ''' |
| Current value of wake requests |
| ''', |
| }, |
| ] |
| }, |
| |
| { name: "RESET_EN_REGWEN", |
| desc: "Configuration enable for reset register", |
| swaccess: "rw0c", |
| hwaccess: "none", |
| fields: [ |
| { bits: "0", |
| resval: "1" |
| name: "EN", |
| desc: ''' |
| When 1, RESET register can be configured. |
| When 0, RESET register cannot be configured. |
| ''', |
| }, |
| ] |
| }, |
| |
| { name: "RESET_EN", |
| desc: "Bit mask for enabled resets", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "RESET_EN_REGWEN", |
| resval: "0" |
| fields: [ |
| { bits: "1:0", |
| name: "EN", |
| desc: ''' |
| Whenever a particular bit is set to 1, that reset request is enabled. |
| Whenever a particular bit is set to 0, that reset request cannot reset the device. |
| ''', |
| }, |
| ] |
| }, |
| |
| { name: "RESET_STATUS", |
| desc: "A read only register of all current reset requests post enable mask", |
| swaccess: "ro", |
| hwaccess: "none", |
| resval: "0" |
| fields: [ |
| { bits: "1:0", |
| name: "VAL", |
| desc: ''' |
| Current value of reset request |
| ''', |
| }, |
| ] |
| }, |
| |
| { name: "WAKE_INFO_CAPTURE_DIS", |
| desc: "Indicates which functions caused the chip to wakeup", |
| swaccess: "rw", |
| hwaccess: "hro", |
| resval: "0" |
| fields: [ |
| { bits: "0", |
| name: "VAL", |
| desc: ''' |
| When written to 1, this actively suppresses the wakeup infor capture. |
| When written to 0, wakeup info capture timign is controlled by HW. |
| ''', |
| }, |
| ] |
| }, |
| |
| { name: "WAKE_INFO", |
| desc: "Indicates which functions caused the chip to wakeup", |
| swaccess: "rw1c", |
| hwaccess: "hrw", |
| hwext: "true", |
| hwqe: "true", |
| resval: "0" |
| fields: [ |
| { bits: "15:0", |
| name: "REASONS", |
| desc: ''' |
| The wake info recording begins whenever the device begins a valid low power entry. |
| |
| This capture is continued until it is explicitly disabled through WAKE_INFO_CAPTURE_DIS. |
| This means it is possible to capture multiple wakeup reasons. |
| ''', |
| }, |
| { bits: "16", |
| name: "FALL_THROUGH", |
| desc: ''' |
| The fall through wakeup reason indicates that despite setting a WFI and providing a low power |
| hint, an interrupt arrived at just the right time to break the executing core out of WFI. |
| |
| The power manager detects this condition, halts low power entry and reports as a wakeup reason |
| ''', |
| }, |
| { bits: "17", |
| name: "ABORT", |
| desc: ''' |
| The abort wakeup reason indicates that despite setting a WFI and providing a low power |
| hint, an active flash / lifecycle / otp transaction was ongoing when the power controller |
| attempted to initiate low power entry. |
| |
| The power manager detects this condition, halts low power entry and reports as a wakeup reason |
| ''', |
| }, |
| ] |
| }, |
| |
| |
| |
| |
| ] |
| } |
