| # Copyright lowRISC contributors. |
| # Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| # Target configuration for the lowRISC "Earl Grey" chip |
| |
| if { [info exists CHIPNAME] } { |
| set _CHIPNAME $CHIPNAME |
| } else { |
| set _CHIPNAME riscv |
| } |
| |
| if { [info exists CPUTAPID ] } { |
| set _CPUTAPID $CPUTAPID |
| } else { |
| set _CPUTAPID 0x04f5484d |
| } |
| |
| jtag newtap $_CHIPNAME tap -irlen 5 -expected-id $_CPUTAPID |
| set _TARGETNAME $_CHIPNAME.tap |
| target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread |
| |
| # Configure work area in on-chip SRAM |
| $_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 1000 -work-area-backup 0 |
| |
| # This chip implements system bus access, use it. |
| # Accessing the memory through the system bus is faster than through |
| # instruction feeding. |
| riscv set_prefer_sba on |
| |
| # Be verbose about GDB errors |
| gdb_report_data_abort enable |
| gdb_report_register_access_error enable |
