[top_earlgrey] Generated files based on Multi-tiered This commit is for generating files for top_earlgrey based on the multi-tiered crossbar update. Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index a803c59..5b014e0 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -610,11 +610,8 @@ debug_mem ram_main eflash - uart - gpio - spi_device + peri flash_ctrl - rv_timer aes hmac rv_plic @@ -627,11 +624,8 @@ rom ram_main eflash - uart - gpio - spi_device + peri flash_ctrl - rv_timer aes hmac rv_plic @@ -648,6 +642,7 @@ clock: clk_main_i reset: rst_main_ni pipeline: "false" + xbar: false inst_type: rv_core_ibex pipeline_byp: "true" } @@ -657,6 +652,7 @@ clock: clk_main_i reset: rst_main_ni pipeline: "false" + xbar: false inst_type: rv_core_ibex pipeline_byp: "true" } @@ -666,6 +662,7 @@ clock: clk_main_i reset: rst_main_ni pipeline_byp: "false" + xbar: false inst_type: rv_dm pipeline: "true" } @@ -678,6 +675,7 @@ inst_type: rom base_addr: 0x00008000 size_byte: 0x2000 + xbar: false pipeline_byp: "true" } { @@ -689,6 +687,7 @@ inst_type: rv_dm base_addr: 0x1A110000 size_byte: 0x1000 + xbar: false pipeline: "true" } { @@ -700,6 +699,7 @@ inst_type: ram_1p base_addr: 0x10000000 size_byte: 0x10000 + xbar: false pipeline_byp: "true" } { @@ -711,40 +711,28 @@ inst_type: eflash base_addr: 0x20000000 size_byte: 0x80000 + xbar: false pipeline_byp: "true" } { - name: uart + name: peri type: device clock: clk_fixed_i reset: rst_fixed_ni pipeline_byp: "false" - inst_type: uart - base_addr: 0x40000000 - size_byte: 0x1000 + xbar: true pipeline: "true" - } - { - name: gpio - type: device - clock: clk_fixed_i - reset: rst_fixed_ni - pipeline_byp: "false" - inst_type: gpio - base_addr: 0x40010000 - size_byte: 0x1000 - pipeline: "true" - } - { - name: spi_device - type: device - clock: clk_fixed_i - reset: rst_fixed_ni - pipeline_byp: "false" - inst_type: spi_device - base_addr: 0x40020000 - size_byte: 0x1000 - pipeline: "true" + xbar_addr: + [ + { + base_addr: 0x40000000 + size_byte: 0x21000 + } + { + base_addr: 0x40080000 + size_byte: 0x1000 + } + ] } { name: flash_ctrl @@ -755,17 +743,7 @@ inst_type: flash_ctrl base_addr: 0x40030000 size_byte: 0x1000 - pipeline: "true" - } - { - name: rv_timer - type: device - clock: clk_fixed_i - reset: rst_fixed_ni - pipeline_byp: "false" - inst_type: rv_timer - base_addr: 0x40080000 - size_byte: 0x1000 + xbar: false pipeline: "true" } { @@ -777,6 +755,7 @@ inst_type: hmac base_addr: 0x40120000 size_byte: 0x1000 + xbar: false pipeline: "true" } { @@ -788,6 +767,7 @@ inst_type: aes base_addr: 0x40110000 size_byte: 0x1000 + xbar: false pipeline: "true" } { @@ -799,6 +779,7 @@ base_addr: 0x40090000 size_byte: 0x1000 pipeline_byp: "false" + xbar: false pipeline: "true" } { @@ -810,6 +791,7 @@ base_addr: 0x40070000 size_byte: 0x1000 pipeline_byp: "false" + xbar: false pipeline: "true" } { @@ -820,6 +802,7 @@ pipeline_byp: "false" base_addr: 0x40130000 size_byte: 0x1000 + xbar: false pipeline: "true" } { @@ -830,11 +813,96 @@ pipeline_byp: "false" base_addr: 0x40140000 size_byte: 0x1000 + xbar: false pipeline: "true" } ] clock: clk_main_i } + { + name: peri + clock_connections: + { + clk_peri_i: fixed + } + reset: rst_peri_ni + reset_connections: + { + rst_peri_ni: sys_fixed + } + connections: + { + main: + [ + uart + gpio + spi_device + rv_timer + ] + } + nodes: + [ + { + name: main + type: host + clock: clk_peri_i + reset: rst_peri_ni + xbar: true + pipeline: "false" + inst_type: "" + pipeline_byp: "true" + } + { + name: uart + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: "false" + inst_type: uart + base_addr: 0x40000000 + size_byte: 0x1000 + xbar: false + pipeline_byp: "true" + } + { + name: gpio + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: "false" + inst_type: gpio + base_addr: 0x40010000 + size_byte: 0x1000 + xbar: false + pipeline_byp: "true" + } + { + name: spi_device + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: "false" + inst_type: spi_device + base_addr: 0x40020000 + size_byte: 0x1000 + xbar: false + pipeline_byp: "true" + } + { + name: rv_timer + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: "false" + inst_type: rv_timer + base_addr: 0x40080000 + size_byte: 0x1000 + xbar: false + pipeline_byp: "true" + } + ] + clock: clk_peri_i + } ] interrupt_module: [
diff --git a/hw/top_earlgrey/dv/chip_sim.core b/hw/top_earlgrey/dv/chip_sim.core index 15cb46f..7e25831 100644 --- a/hw/top_earlgrey/dv/chip_sim.core +++ b/hw/top_earlgrey/dv/chip_sim.core
@@ -11,7 +11,8 @@ - lowrisc:ibex:ibex_tracer:0.1 files: - ../rtl/top_earlgrey_asic.sv - - ../ip/xbar/dv/autogen/xbar_main_bind.sv + - ../ip/xbar_main/dv/autogen/xbar_main_bind.sv + - ../ip/xbar_peri/dv/autogen/xbar_peri_bind.sv file_type: systemVerilogSource files_dv:
diff --git a/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv deleted file mode 100644 index bc02862..0000000 --- a/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv +++ /dev/null
@@ -1,847 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// xbar_main module generated by `tlgen.py` tool -// all reset signals should be generated from one reset signal to not make any deadlock -// -// Interconnect -// corei -// -> s1n_18 -// -> sm1_19 -// -> rom -// -> sm1_20 -// -> debug_mem -// -> sm1_21 -// -> ram_main -// -> sm1_22 -// -> eflash -// cored -// -> s1n_23 -// -> sm1_19 -// -> rom -// -> sm1_20 -// -> debug_mem -// -> sm1_21 -// -> ram_main -// -> sm1_22 -// -> eflash -// -> sm1_25 -// -> asf_24 -// -> uart -// -> sm1_27 -// -> asf_26 -// -> gpio -// -> sm1_29 -// -> asf_28 -// -> spi_device -// -> sm1_30 -// -> flash_ctrl -// -> sm1_32 -// -> asf_31 -// -> rv_timer -// -> sm1_33 -// -> aes -// -> sm1_34 -// -> hmac -// -> sm1_35 -// -> rv_plic -// -> sm1_36 -// -> pinmux -// -> sm1_37 -// -> alert_handler -// -> sm1_38 -// -> nmi_gen -// dm_sba -// -> s1n_39 -// -> sm1_19 -// -> rom -// -> sm1_21 -// -> ram_main -// -> sm1_22 -// -> eflash -// -> sm1_25 -// -> asf_24 -// -> uart -// -> sm1_27 -// -> asf_26 -// -> gpio -// -> sm1_29 -// -> asf_28 -// -> spi_device -// -> sm1_30 -// -> flash_ctrl -// -> sm1_32 -// -> asf_31 -// -> rv_timer -// -> sm1_33 -// -> aes -// -> sm1_34 -// -> hmac -// -> sm1_35 -// -> rv_plic -// -> sm1_36 -// -> pinmux -// -> sm1_37 -// -> alert_handler -// -> sm1_38 -// -> nmi_gen - -module xbar_main ( - input clk_main_i, - input clk_fixed_i, - input rst_main_ni, - input rst_fixed_ni, - - // Host interfaces - input tlul_pkg::tl_h2d_t tl_corei_i, - output tlul_pkg::tl_d2h_t tl_corei_o, - input tlul_pkg::tl_h2d_t tl_cored_i, - output tlul_pkg::tl_d2h_t tl_cored_o, - input tlul_pkg::tl_h2d_t tl_dm_sba_i, - output tlul_pkg::tl_d2h_t tl_dm_sba_o, - - // Device interfaces - output tlul_pkg::tl_h2d_t tl_rom_o, - input tlul_pkg::tl_d2h_t tl_rom_i, - output tlul_pkg::tl_h2d_t tl_debug_mem_o, - input tlul_pkg::tl_d2h_t tl_debug_mem_i, - output tlul_pkg::tl_h2d_t tl_ram_main_o, - input tlul_pkg::tl_d2h_t tl_ram_main_i, - output tlul_pkg::tl_h2d_t tl_eflash_o, - input tlul_pkg::tl_d2h_t tl_eflash_i, - output tlul_pkg::tl_h2d_t tl_uart_o, - input tlul_pkg::tl_d2h_t tl_uart_i, - output tlul_pkg::tl_h2d_t tl_gpio_o, - input tlul_pkg::tl_d2h_t tl_gpio_i, - output tlul_pkg::tl_h2d_t tl_spi_device_o, - input tlul_pkg::tl_d2h_t tl_spi_device_i, - output tlul_pkg::tl_h2d_t tl_flash_ctrl_o, - input tlul_pkg::tl_d2h_t tl_flash_ctrl_i, - output tlul_pkg::tl_h2d_t tl_rv_timer_o, - input tlul_pkg::tl_d2h_t tl_rv_timer_i, - output tlul_pkg::tl_h2d_t tl_hmac_o, - input tlul_pkg::tl_d2h_t tl_hmac_i, - output tlul_pkg::tl_h2d_t tl_aes_o, - input tlul_pkg::tl_d2h_t tl_aes_i, - output tlul_pkg::tl_h2d_t tl_rv_plic_o, - input tlul_pkg::tl_d2h_t tl_rv_plic_i, - output tlul_pkg::tl_h2d_t tl_pinmux_o, - input tlul_pkg::tl_d2h_t tl_pinmux_i, - output tlul_pkg::tl_h2d_t tl_alert_handler_o, - input tlul_pkg::tl_d2h_t tl_alert_handler_i, - output tlul_pkg::tl_h2d_t tl_nmi_gen_o, - input tlul_pkg::tl_d2h_t tl_nmi_gen_i, - - input scanmode_i -); - - import tlul_pkg::*; - import tl_main_pkg::*; - - // scanmode_i is currently not used, but provisioned for future use - // this assignment prevents lint warnings - logic unused_scanmode; - assign unused_scanmode = scanmode_i; - - tl_h2d_t tl_s1n_18_us_h2d ; - tl_d2h_t tl_s1n_18_us_d2h ; - - - tl_h2d_t tl_s1n_18_ds_h2d [4]; - tl_d2h_t tl_s1n_18_ds_d2h [4]; - - // Create steering signal - logic [2:0] dev_sel_s1n_18; - - - tl_h2d_t tl_sm1_19_us_h2d [3]; - tl_d2h_t tl_sm1_19_us_d2h [3]; - - tl_h2d_t tl_sm1_19_ds_h2d ; - tl_d2h_t tl_sm1_19_ds_d2h ; - - - tl_h2d_t tl_sm1_20_us_h2d [2]; - tl_d2h_t tl_sm1_20_us_d2h [2]; - - tl_h2d_t tl_sm1_20_ds_h2d ; - tl_d2h_t tl_sm1_20_ds_d2h ; - - - tl_h2d_t tl_sm1_21_us_h2d [3]; - tl_d2h_t tl_sm1_21_us_d2h [3]; - - tl_h2d_t tl_sm1_21_ds_h2d ; - tl_d2h_t tl_sm1_21_ds_d2h ; - - - tl_h2d_t tl_sm1_22_us_h2d [3]; - tl_d2h_t tl_sm1_22_us_d2h [3]; - - tl_h2d_t tl_sm1_22_ds_h2d ; - tl_d2h_t tl_sm1_22_ds_d2h ; - - tl_h2d_t tl_s1n_23_us_h2d ; - tl_d2h_t tl_s1n_23_us_d2h ; - - - tl_h2d_t tl_s1n_23_ds_h2d [15]; - tl_d2h_t tl_s1n_23_ds_d2h [15]; - - // Create steering signal - logic [3:0] dev_sel_s1n_23; - - tl_h2d_t tl_asf_24_us_h2d ; - tl_d2h_t tl_asf_24_us_d2h ; - tl_h2d_t tl_asf_24_ds_h2d ; - tl_d2h_t tl_asf_24_ds_d2h ; - - - tl_h2d_t tl_sm1_25_us_h2d [2]; - tl_d2h_t tl_sm1_25_us_d2h [2]; - - tl_h2d_t tl_sm1_25_ds_h2d ; - tl_d2h_t tl_sm1_25_ds_d2h ; - - tl_h2d_t tl_asf_26_us_h2d ; - tl_d2h_t tl_asf_26_us_d2h ; - tl_h2d_t tl_asf_26_ds_h2d ; - tl_d2h_t tl_asf_26_ds_d2h ; - - - tl_h2d_t tl_sm1_27_us_h2d [2]; - tl_d2h_t tl_sm1_27_us_d2h [2]; - - tl_h2d_t tl_sm1_27_ds_h2d ; - tl_d2h_t tl_sm1_27_ds_d2h ; - - tl_h2d_t tl_asf_28_us_h2d ; - tl_d2h_t tl_asf_28_us_d2h ; - tl_h2d_t tl_asf_28_ds_h2d ; - tl_d2h_t tl_asf_28_ds_d2h ; - - - tl_h2d_t tl_sm1_29_us_h2d [2]; - tl_d2h_t tl_sm1_29_us_d2h [2]; - - tl_h2d_t tl_sm1_29_ds_h2d ; - tl_d2h_t tl_sm1_29_ds_d2h ; - - - tl_h2d_t tl_sm1_30_us_h2d [2]; - tl_d2h_t tl_sm1_30_us_d2h [2]; - - tl_h2d_t tl_sm1_30_ds_h2d ; - tl_d2h_t tl_sm1_30_ds_d2h ; - - tl_h2d_t tl_asf_31_us_h2d ; - tl_d2h_t tl_asf_31_us_d2h ; - tl_h2d_t tl_asf_31_ds_h2d ; - tl_d2h_t tl_asf_31_ds_d2h ; - - - tl_h2d_t tl_sm1_32_us_h2d [2]; - tl_d2h_t tl_sm1_32_us_d2h [2]; - - tl_h2d_t tl_sm1_32_ds_h2d ; - tl_d2h_t tl_sm1_32_ds_d2h ; - - - tl_h2d_t tl_sm1_33_us_h2d [2]; - tl_d2h_t tl_sm1_33_us_d2h [2]; - - tl_h2d_t tl_sm1_33_ds_h2d ; - tl_d2h_t tl_sm1_33_ds_d2h ; - - - tl_h2d_t tl_sm1_34_us_h2d [2]; - tl_d2h_t tl_sm1_34_us_d2h [2]; - - tl_h2d_t tl_sm1_34_ds_h2d ; - tl_d2h_t tl_sm1_34_ds_d2h ; - - - tl_h2d_t tl_sm1_35_us_h2d [2]; - tl_d2h_t tl_sm1_35_us_d2h [2]; - - tl_h2d_t tl_sm1_35_ds_h2d ; - tl_d2h_t tl_sm1_35_ds_d2h ; - - - tl_h2d_t tl_sm1_36_us_h2d [2]; - tl_d2h_t tl_sm1_36_us_d2h [2]; - - tl_h2d_t tl_sm1_36_ds_h2d ; - tl_d2h_t tl_sm1_36_ds_d2h ; - - - tl_h2d_t tl_sm1_37_us_h2d [2]; - tl_d2h_t tl_sm1_37_us_d2h [2]; - - tl_h2d_t tl_sm1_37_ds_h2d ; - tl_d2h_t tl_sm1_37_ds_d2h ; - - - tl_h2d_t tl_sm1_38_us_h2d [2]; - tl_d2h_t tl_sm1_38_us_d2h [2]; - - tl_h2d_t tl_sm1_38_ds_h2d ; - tl_d2h_t tl_sm1_38_ds_d2h ; - - tl_h2d_t tl_s1n_39_us_h2d ; - tl_d2h_t tl_s1n_39_us_d2h ; - - - tl_h2d_t tl_s1n_39_ds_h2d [14]; - tl_d2h_t tl_s1n_39_ds_d2h [14]; - - // Create steering signal - logic [3:0] dev_sel_s1n_39; - - - - assign tl_sm1_19_us_h2d[0] = tl_s1n_18_ds_h2d[0]; - assign tl_s1n_18_ds_d2h[0] = tl_sm1_19_us_d2h[0]; - - assign tl_sm1_20_us_h2d[0] = tl_s1n_18_ds_h2d[1]; - assign tl_s1n_18_ds_d2h[1] = tl_sm1_20_us_d2h[0]; - - assign tl_sm1_21_us_h2d[0] = tl_s1n_18_ds_h2d[2]; - assign tl_s1n_18_ds_d2h[2] = tl_sm1_21_us_d2h[0]; - - assign tl_sm1_22_us_h2d[0] = tl_s1n_18_ds_h2d[3]; - assign tl_s1n_18_ds_d2h[3] = tl_sm1_22_us_d2h[0]; - - assign tl_sm1_19_us_h2d[1] = tl_s1n_23_ds_h2d[0]; - assign tl_s1n_23_ds_d2h[0] = tl_sm1_19_us_d2h[1]; - - assign tl_sm1_20_us_h2d[1] = tl_s1n_23_ds_h2d[1]; - assign tl_s1n_23_ds_d2h[1] = tl_sm1_20_us_d2h[1]; - - assign tl_sm1_21_us_h2d[1] = tl_s1n_23_ds_h2d[2]; - assign tl_s1n_23_ds_d2h[2] = tl_sm1_21_us_d2h[1]; - - assign tl_sm1_22_us_h2d[1] = tl_s1n_23_ds_h2d[3]; - assign tl_s1n_23_ds_d2h[3] = tl_sm1_22_us_d2h[1]; - - assign tl_sm1_25_us_h2d[0] = tl_s1n_23_ds_h2d[4]; - assign tl_s1n_23_ds_d2h[4] = tl_sm1_25_us_d2h[0]; - - assign tl_sm1_27_us_h2d[0] = tl_s1n_23_ds_h2d[5]; - assign tl_s1n_23_ds_d2h[5] = tl_sm1_27_us_d2h[0]; - - assign tl_sm1_29_us_h2d[0] = tl_s1n_23_ds_h2d[6]; - assign tl_s1n_23_ds_d2h[6] = tl_sm1_29_us_d2h[0]; - - assign tl_sm1_30_us_h2d[0] = tl_s1n_23_ds_h2d[7]; - assign tl_s1n_23_ds_d2h[7] = tl_sm1_30_us_d2h[0]; - - assign tl_sm1_32_us_h2d[0] = tl_s1n_23_ds_h2d[8]; - assign tl_s1n_23_ds_d2h[8] = tl_sm1_32_us_d2h[0]; - - assign tl_sm1_33_us_h2d[0] = tl_s1n_23_ds_h2d[9]; - assign tl_s1n_23_ds_d2h[9] = tl_sm1_33_us_d2h[0]; - - assign tl_sm1_34_us_h2d[0] = tl_s1n_23_ds_h2d[10]; - assign tl_s1n_23_ds_d2h[10] = tl_sm1_34_us_d2h[0]; - - assign tl_sm1_35_us_h2d[0] = tl_s1n_23_ds_h2d[11]; - assign tl_s1n_23_ds_d2h[11] = tl_sm1_35_us_d2h[0]; - - assign tl_sm1_36_us_h2d[0] = tl_s1n_23_ds_h2d[12]; - assign tl_s1n_23_ds_d2h[12] = tl_sm1_36_us_d2h[0]; - - assign tl_sm1_37_us_h2d[0] = tl_s1n_23_ds_h2d[13]; - assign tl_s1n_23_ds_d2h[13] = tl_sm1_37_us_d2h[0]; - - assign tl_sm1_38_us_h2d[0] = tl_s1n_23_ds_h2d[14]; - assign tl_s1n_23_ds_d2h[14] = tl_sm1_38_us_d2h[0]; - - assign tl_sm1_19_us_h2d[2] = tl_s1n_39_ds_h2d[0]; - assign tl_s1n_39_ds_d2h[0] = tl_sm1_19_us_d2h[2]; - - assign tl_sm1_21_us_h2d[2] = tl_s1n_39_ds_h2d[1]; - assign tl_s1n_39_ds_d2h[1] = tl_sm1_21_us_d2h[2]; - - assign tl_sm1_22_us_h2d[2] = tl_s1n_39_ds_h2d[2]; - assign tl_s1n_39_ds_d2h[2] = tl_sm1_22_us_d2h[2]; - - assign tl_sm1_25_us_h2d[1] = tl_s1n_39_ds_h2d[3]; - assign tl_s1n_39_ds_d2h[3] = tl_sm1_25_us_d2h[1]; - - assign tl_sm1_27_us_h2d[1] = tl_s1n_39_ds_h2d[4]; - assign tl_s1n_39_ds_d2h[4] = tl_sm1_27_us_d2h[1]; - - assign tl_sm1_29_us_h2d[1] = tl_s1n_39_ds_h2d[5]; - assign tl_s1n_39_ds_d2h[5] = tl_sm1_29_us_d2h[1]; - - assign tl_sm1_30_us_h2d[1] = tl_s1n_39_ds_h2d[6]; - assign tl_s1n_39_ds_d2h[6] = tl_sm1_30_us_d2h[1]; - - assign tl_sm1_32_us_h2d[1] = tl_s1n_39_ds_h2d[7]; - assign tl_s1n_39_ds_d2h[7] = tl_sm1_32_us_d2h[1]; - - assign tl_sm1_33_us_h2d[1] = tl_s1n_39_ds_h2d[8]; - assign tl_s1n_39_ds_d2h[8] = tl_sm1_33_us_d2h[1]; - - assign tl_sm1_34_us_h2d[1] = tl_s1n_39_ds_h2d[9]; - assign tl_s1n_39_ds_d2h[9] = tl_sm1_34_us_d2h[1]; - - assign tl_sm1_35_us_h2d[1] = tl_s1n_39_ds_h2d[10]; - assign tl_s1n_39_ds_d2h[10] = tl_sm1_35_us_d2h[1]; - - assign tl_sm1_36_us_h2d[1] = tl_s1n_39_ds_h2d[11]; - assign tl_s1n_39_ds_d2h[11] = tl_sm1_36_us_d2h[1]; - - assign tl_sm1_37_us_h2d[1] = tl_s1n_39_ds_h2d[12]; - assign tl_s1n_39_ds_d2h[12] = tl_sm1_37_us_d2h[1]; - - assign tl_sm1_38_us_h2d[1] = tl_s1n_39_ds_h2d[13]; - assign tl_s1n_39_ds_d2h[13] = tl_sm1_38_us_d2h[1]; - - assign tl_s1n_18_us_h2d = tl_corei_i; - assign tl_corei_o = tl_s1n_18_us_d2h; - - assign tl_rom_o = tl_sm1_19_ds_h2d; - assign tl_sm1_19_ds_d2h = tl_rom_i; - - assign tl_debug_mem_o = tl_sm1_20_ds_h2d; - assign tl_sm1_20_ds_d2h = tl_debug_mem_i; - - assign tl_ram_main_o = tl_sm1_21_ds_h2d; - assign tl_sm1_21_ds_d2h = tl_ram_main_i; - - assign tl_eflash_o = tl_sm1_22_ds_h2d; - assign tl_sm1_22_ds_d2h = tl_eflash_i; - - assign tl_s1n_23_us_h2d = tl_cored_i; - assign tl_cored_o = tl_s1n_23_us_d2h; - - assign tl_uart_o = tl_asf_24_ds_h2d; - assign tl_asf_24_ds_d2h = tl_uart_i; - - assign tl_asf_24_us_h2d = tl_sm1_25_ds_h2d; - assign tl_sm1_25_ds_d2h = tl_asf_24_us_d2h; - - assign tl_gpio_o = tl_asf_26_ds_h2d; - assign tl_asf_26_ds_d2h = tl_gpio_i; - - assign tl_asf_26_us_h2d = tl_sm1_27_ds_h2d; - assign tl_sm1_27_ds_d2h = tl_asf_26_us_d2h; - - assign tl_spi_device_o = tl_asf_28_ds_h2d; - assign tl_asf_28_ds_d2h = tl_spi_device_i; - - assign tl_asf_28_us_h2d = tl_sm1_29_ds_h2d; - assign tl_sm1_29_ds_d2h = tl_asf_28_us_d2h; - - assign tl_flash_ctrl_o = tl_sm1_30_ds_h2d; - assign tl_sm1_30_ds_d2h = tl_flash_ctrl_i; - - assign tl_rv_timer_o = tl_asf_31_ds_h2d; - assign tl_asf_31_ds_d2h = tl_rv_timer_i; - - assign tl_asf_31_us_h2d = tl_sm1_32_ds_h2d; - assign tl_sm1_32_ds_d2h = tl_asf_31_us_d2h; - - assign tl_aes_o = tl_sm1_33_ds_h2d; - assign tl_sm1_33_ds_d2h = tl_aes_i; - - assign tl_hmac_o = tl_sm1_34_ds_h2d; - assign tl_sm1_34_ds_d2h = tl_hmac_i; - - assign tl_rv_plic_o = tl_sm1_35_ds_h2d; - assign tl_sm1_35_ds_d2h = tl_rv_plic_i; - - assign tl_pinmux_o = tl_sm1_36_ds_h2d; - assign tl_sm1_36_ds_d2h = tl_pinmux_i; - - assign tl_alert_handler_o = tl_sm1_37_ds_h2d; - assign tl_sm1_37_ds_d2h = tl_alert_handler_i; - - assign tl_nmi_gen_o = tl_sm1_38_ds_h2d; - assign tl_sm1_38_ds_d2h = tl_nmi_gen_i; - - assign tl_s1n_39_us_h2d = tl_dm_sba_i; - assign tl_dm_sba_o = tl_s1n_39_us_d2h; - - always_comb begin - // default steering to generate error response if address is not within the range - dev_sel_s1n_18 = 3'd4; - if ((tl_s1n_18_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin - dev_sel_s1n_18 = 3'd0; - end else if ((tl_s1n_18_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin - dev_sel_s1n_18 = 3'd1; - end else if ((tl_s1n_18_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin - dev_sel_s1n_18 = 3'd2; - end else if ((tl_s1n_18_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin - dev_sel_s1n_18 = 3'd3; - end - end - - always_comb begin - // default steering to generate error response if address is not within the range - dev_sel_s1n_23 = 4'd15; - if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin - dev_sel_s1n_23 = 4'd0; - end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin - dev_sel_s1n_23 = 4'd1; - end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin - dev_sel_s1n_23 = 4'd2; - end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin - dev_sel_s1n_23 = 4'd3; - end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin - dev_sel_s1n_23 = 4'd4; - end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin - dev_sel_s1n_23 = 4'd5; - end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin - dev_sel_s1n_23 = 4'd6; - end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin - dev_sel_s1n_23 = 4'd7; - end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin - dev_sel_s1n_23 = 4'd8; - end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin - dev_sel_s1n_23 = 4'd9; - end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin - dev_sel_s1n_23 = 4'd10; - end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin - dev_sel_s1n_23 = 4'd11; - end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin - dev_sel_s1n_23 = 4'd12; - end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin - dev_sel_s1n_23 = 4'd13; - end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin - dev_sel_s1n_23 = 4'd14; - end - end - - always_comb begin - // default steering to generate error response if address is not within the range - dev_sel_s1n_39 = 4'd14; - if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin - dev_sel_s1n_39 = 4'd0; - end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin - dev_sel_s1n_39 = 4'd1; - end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin - dev_sel_s1n_39 = 4'd2; - end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin - dev_sel_s1n_39 = 4'd3; - end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin - dev_sel_s1n_39 = 4'd4; - end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin - dev_sel_s1n_39 = 4'd5; - end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin - dev_sel_s1n_39 = 4'd6; - end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin - dev_sel_s1n_39 = 4'd7; - end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin - dev_sel_s1n_39 = 4'd8; - end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin - dev_sel_s1n_39 = 4'd9; - end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin - dev_sel_s1n_39 = 4'd10; - end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin - dev_sel_s1n_39 = 4'd11; - end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin - dev_sel_s1n_39 = 4'd12; - end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin - dev_sel_s1n_39 = 4'd13; - end - end - - - // Instantiation phase - tlul_socket_1n #( - .HReqDepth (4'h0), - .HRspDepth (4'h0), - .DReqDepth ({4{4'h0}}), - .DRspDepth ({4{4'h0}}), - .N (4) - ) u_s1n_18 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_s1n_18_us_h2d), - .tl_h_o (tl_s1n_18_us_d2h), - .tl_d_o (tl_s1n_18_ds_h2d), - .tl_d_i (tl_s1n_18_ds_d2h), - .dev_select (dev_sel_s1n_18) - ); - tlul_socket_m1 #( - .HReqDepth ({3{4'h0}}), - .HRspDepth ({3{4'h0}}), - .DReqDepth (4'h0), - .DRspDepth (4'h0), - .M (3) - ) u_sm1_19 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_19_us_h2d), - .tl_h_o (tl_sm1_19_us_d2h), - .tl_d_o (tl_sm1_19_ds_h2d), - .tl_d_i (tl_sm1_19_ds_d2h) - ); - tlul_socket_m1 #( - .HReqPass (2'h0), - .HRspPass (2'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_20 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_20_us_h2d), - .tl_h_o (tl_sm1_20_us_d2h), - .tl_d_o (tl_sm1_20_ds_h2d), - .tl_d_i (tl_sm1_20_ds_d2h) - ); - tlul_socket_m1 #( - .HReqDepth ({3{4'h0}}), - .HRspDepth ({3{4'h0}}), - .DReqDepth (4'h0), - .DRspDepth (4'h0), - .M (3) - ) u_sm1_21 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_21_us_h2d), - .tl_h_o (tl_sm1_21_us_d2h), - .tl_d_o (tl_sm1_21_ds_h2d), - .tl_d_i (tl_sm1_21_ds_d2h) - ); - tlul_socket_m1 #( - .HReqDepth ({3{4'h0}}), - .HRspDepth ({3{4'h0}}), - .DReqDepth (4'h0), - .DRspDepth (4'h0), - .M (3) - ) u_sm1_22 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_22_us_h2d), - .tl_h_o (tl_sm1_22_us_d2h), - .tl_d_o (tl_sm1_22_ds_h2d), - .tl_d_i (tl_sm1_22_ds_d2h) - ); - tlul_socket_1n #( - .HReqDepth (4'h0), - .HRspDepth (4'h0), - .DReqDepth ({15{4'h0}}), - .DRspDepth ({15{4'h0}}), - .N (15) - ) u_s1n_23 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_s1n_23_us_h2d), - .tl_h_o (tl_s1n_23_us_d2h), - .tl_d_o (tl_s1n_23_ds_h2d), - .tl_d_i (tl_s1n_23_ds_d2h), - .dev_select (dev_sel_s1n_23) - ); - tlul_fifo_async #( - .ReqDepth (3),// At least 3 to make async work - .RspDepth (3) // At least 3 to make async work - ) u_asf_24 ( - .clk_h_i (clk_main_i), - .rst_h_ni (rst_main_ni), - .clk_d_i (clk_fixed_i), - .rst_d_ni (rst_fixed_ni), - .tl_h_i (tl_asf_24_us_h2d), - .tl_h_o (tl_asf_24_us_d2h), - .tl_d_o (tl_asf_24_ds_h2d), - .tl_d_i (tl_asf_24_ds_d2h) - ); - tlul_socket_m1 #( - .M (2) - ) u_sm1_25 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_25_us_h2d), - .tl_h_o (tl_sm1_25_us_d2h), - .tl_d_o (tl_sm1_25_ds_h2d), - .tl_d_i (tl_sm1_25_ds_d2h) - ); - tlul_fifo_async #( - .ReqDepth (3),// At least 3 to make async work - .RspDepth (3) // At least 3 to make async work - ) u_asf_26 ( - .clk_h_i (clk_main_i), - .rst_h_ni (rst_main_ni), - .clk_d_i (clk_fixed_i), - .rst_d_ni (rst_fixed_ni), - .tl_h_i (tl_asf_26_us_h2d), - .tl_h_o (tl_asf_26_us_d2h), - .tl_d_o (tl_asf_26_ds_h2d), - .tl_d_i (tl_asf_26_ds_d2h) - ); - tlul_socket_m1 #( - .M (2) - ) u_sm1_27 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_27_us_h2d), - .tl_h_o (tl_sm1_27_us_d2h), - .tl_d_o (tl_sm1_27_ds_h2d), - .tl_d_i (tl_sm1_27_ds_d2h) - ); - tlul_fifo_async #( - .ReqDepth (3),// At least 3 to make async work - .RspDepth (3) // At least 3 to make async work - ) u_asf_28 ( - .clk_h_i (clk_main_i), - .rst_h_ni (rst_main_ni), - .clk_d_i (clk_fixed_i), - .rst_d_ni (rst_fixed_ni), - .tl_h_i (tl_asf_28_us_h2d), - .tl_h_o (tl_asf_28_us_d2h), - .tl_d_o (tl_asf_28_ds_h2d), - .tl_d_i (tl_asf_28_ds_d2h) - ); - tlul_socket_m1 #( - .M (2) - ) u_sm1_29 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_29_us_h2d), - .tl_h_o (tl_sm1_29_us_d2h), - .tl_d_o (tl_sm1_29_ds_h2d), - .tl_d_i (tl_sm1_29_ds_d2h) - ); - tlul_socket_m1 #( - .HReqPass (2'h0), - .HRspPass (2'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_30 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_30_us_h2d), - .tl_h_o (tl_sm1_30_us_d2h), - .tl_d_o (tl_sm1_30_ds_h2d), - .tl_d_i (tl_sm1_30_ds_d2h) - ); - tlul_fifo_async #( - .ReqDepth (3),// At least 3 to make async work - .RspDepth (3) // At least 3 to make async work - ) u_asf_31 ( - .clk_h_i (clk_main_i), - .rst_h_ni (rst_main_ni), - .clk_d_i (clk_fixed_i), - .rst_d_ni (rst_fixed_ni), - .tl_h_i (tl_asf_31_us_h2d), - .tl_h_o (tl_asf_31_us_d2h), - .tl_d_o (tl_asf_31_ds_h2d), - .tl_d_i (tl_asf_31_ds_d2h) - ); - tlul_socket_m1 #( - .M (2) - ) u_sm1_32 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_32_us_h2d), - .tl_h_o (tl_sm1_32_us_d2h), - .tl_d_o (tl_sm1_32_ds_h2d), - .tl_d_i (tl_sm1_32_ds_d2h) - ); - tlul_socket_m1 #( - .HReqPass (2'h0), - .HRspPass (2'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_33 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_33_us_h2d), - .tl_h_o (tl_sm1_33_us_d2h), - .tl_d_o (tl_sm1_33_ds_h2d), - .tl_d_i (tl_sm1_33_ds_d2h) - ); - tlul_socket_m1 #( - .HReqPass (2'h0), - .HRspPass (2'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_34 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_34_us_h2d), - .tl_h_o (tl_sm1_34_us_d2h), - .tl_d_o (tl_sm1_34_ds_h2d), - .tl_d_i (tl_sm1_34_ds_d2h) - ); - tlul_socket_m1 #( - .HReqPass (2'h0), - .HRspPass (2'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_35 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_35_us_h2d), - .tl_h_o (tl_sm1_35_us_d2h), - .tl_d_o (tl_sm1_35_ds_h2d), - .tl_d_i (tl_sm1_35_ds_d2h) - ); - tlul_socket_m1 #( - .HReqPass (2'h0), - .HRspPass (2'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_36 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_36_us_h2d), - .tl_h_o (tl_sm1_36_us_d2h), - .tl_d_o (tl_sm1_36_ds_h2d), - .tl_d_i (tl_sm1_36_ds_d2h) - ); - tlul_socket_m1 #( - .HReqPass (2'h0), - .HRspPass (2'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_37 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_37_us_h2d), - .tl_h_o (tl_sm1_37_us_d2h), - .tl_d_o (tl_sm1_37_ds_h2d), - .tl_d_i (tl_sm1_37_ds_d2h) - ); - tlul_socket_m1 #( - .HReqPass (2'h0), - .HRspPass (2'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_38 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_38_us_h2d), - .tl_h_o (tl_sm1_38_us_d2h), - .tl_d_o (tl_sm1_38_ds_h2d), - .tl_d_i (tl_sm1_38_ds_d2h) - ); - tlul_socket_1n #( - .HReqPass (1'b0), - .HRspPass (1'b0), - .DReqPass (14'h0), - .DRspPass (14'h0), - .N (14) - ) u_s1n_39 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_s1n_39_us_h2d), - .tl_h_o (tl_s1n_39_us_d2h), - .tl_d_o (tl_s1n_39_ds_h2d), - .tl_d_i (tl_s1n_39_ds_d2h), - .dev_select (dev_sel_s1n_39) - ); - -endmodule
diff --git a/hw/top_earlgrey/ip/xbar/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson similarity index 82% rename from hw/top_earlgrey/ip/xbar/data/autogen/xbar_main.gen.hjson rename to hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson index bdff50c..3390ce4 100644 --- a/hw/top_earlgrey/ip/xbar/data/autogen/xbar_main.gen.hjson +++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
@@ -34,11 +34,8 @@ debug_mem ram_main eflash - uart - gpio - spi_device + peri flash_ctrl - rv_timer aes hmac rv_plic @@ -51,11 +48,8 @@ rom ram_main eflash - uart - gpio - spi_device + peri flash_ctrl - rv_timer aes hmac rv_plic @@ -72,6 +66,7 @@ clock: clk_main_i reset: rst_main_ni pipeline: "false" + xbar: false inst_type: rv_core_ibex pipeline_byp: "true" } @@ -81,6 +76,7 @@ clock: clk_main_i reset: rst_main_ni pipeline: "false" + xbar: false inst_type: rv_core_ibex pipeline_byp: "true" } @@ -90,6 +86,7 @@ clock: clk_main_i reset: rst_main_ni pipeline_byp: "false" + xbar: false inst_type: rv_dm pipeline: "true" } @@ -102,6 +99,7 @@ inst_type: rom base_addr: 0x00008000 size_byte: 0x2000 + xbar: false pipeline_byp: "true" } { @@ -113,6 +111,7 @@ inst_type: rv_dm base_addr: 0x1A110000 size_byte: 0x1000 + xbar: false pipeline: "true" } { @@ -124,6 +123,7 @@ inst_type: ram_1p base_addr: 0x10000000 size_byte: 0x10000 + xbar: false pipeline_byp: "true" } { @@ -135,40 +135,28 @@ inst_type: eflash base_addr: 0x20000000 size_byte: 0x80000 + xbar: false pipeline_byp: "true" } { - name: uart + name: peri type: device clock: clk_fixed_i reset: rst_fixed_ni pipeline_byp: "false" - inst_type: uart - base_addr: 0x40000000 - size_byte: 0x1000 + xbar: true pipeline: "true" - } - { - name: gpio - type: device - clock: clk_fixed_i - reset: rst_fixed_ni - pipeline_byp: "false" - inst_type: gpio - base_addr: 0x40010000 - size_byte: 0x1000 - pipeline: "true" - } - { - name: spi_device - type: device - clock: clk_fixed_i - reset: rst_fixed_ni - pipeline_byp: "false" - inst_type: spi_device - base_addr: 0x40020000 - size_byte: 0x1000 - pipeline: "true" + xbar_addr: + [ + { + base_addr: 0x40000000 + size_byte: 0x21000 + } + { + base_addr: 0x40080000 + size_byte: 0x1000 + } + ] } { name: flash_ctrl @@ -179,17 +167,7 @@ inst_type: flash_ctrl base_addr: 0x40030000 size_byte: 0x1000 - pipeline: "true" - } - { - name: rv_timer - type: device - clock: clk_fixed_i - reset: rst_fixed_ni - pipeline_byp: "false" - inst_type: rv_timer - base_addr: 0x40080000 - size_byte: 0x1000 + xbar: false pipeline: "true" } { @@ -201,6 +179,7 @@ inst_type: hmac base_addr: 0x40120000 size_byte: 0x1000 + xbar: false pipeline: "true" } { @@ -212,6 +191,7 @@ inst_type: aes base_addr: 0x40110000 size_byte: 0x1000 + xbar: false pipeline: "true" } { @@ -223,6 +203,7 @@ base_addr: 0x40090000 size_byte: 0x1000 pipeline_byp: "false" + xbar: false pipeline: "true" } { @@ -234,6 +215,7 @@ base_addr: 0x40070000 size_byte: 0x1000 pipeline_byp: "false" + xbar: false pipeline: "true" } { @@ -244,6 +226,7 @@ pipeline_byp: "false" base_addr: 0x40130000 size_byte: 0x1000 + xbar: false pipeline: "true" } { @@ -254,6 +237,7 @@ pipeline_byp: "false" base_addr: 0x40140000 size_byte: 0x1000 + xbar: false pipeline: "true" } ]
diff --git a/hw/top_earlgrey/ip/xbar/dv/autogen/xbar_main_bind.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv similarity index 82% rename from hw/top_earlgrey/ip/xbar/dv/autogen/xbar_main_bind.sv rename to hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv index 66f0b00..9b89826 100644 --- a/hw/top_earlgrey/ip/xbar/dv/autogen/xbar_main_bind.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv
@@ -50,23 +50,11 @@ .h2d (tl_eflash_o), .d2h (tl_eflash_i) ); - bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_uart ( + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_peri ( .clk_i (clk_fixed_i), .rst_ni (rst_fixed_ni), - .h2d (tl_uart_o), - .d2h (tl_uart_i) - ); - bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_gpio ( - .clk_i (clk_fixed_i), - .rst_ni (rst_fixed_ni), - .h2d (tl_gpio_o), - .d2h (tl_gpio_i) - ); - bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_spi_device ( - .clk_i (clk_fixed_i), - .rst_ni (rst_fixed_ni), - .h2d (tl_spi_device_o), - .d2h (tl_spi_device_i) + .h2d (tl_peri_o), + .d2h (tl_peri_i) ); bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_flash_ctrl ( .clk_i (clk_main_i), @@ -74,12 +62,6 @@ .h2d (tl_flash_ctrl_o), .d2h (tl_flash_ctrl_i) ); - bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_timer ( - .clk_i (clk_fixed_i), - .rst_ni (rst_fixed_ni), - .h2d (tl_rv_timer_o), - .d2h (tl_rv_timer_i) - ); bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_hmac ( .clk_i (clk_main_i), .rst_ni (rst_main_ni),
diff --git a/hw/top_earlgrey/ip/xbar/rtl/autogen/tl_main_pkg.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv similarity index 71% rename from hw/top_earlgrey/ip/xbar/rtl/autogen/tl_main_pkg.sv rename to hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv index 84a257b..15573dd 100644 --- a/hw/top_earlgrey/ip/xbar/rtl/autogen/tl_main_pkg.sv +++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
@@ -10,11 +10,11 @@ localparam logic [31:0] ADDR_SPACE_DEBUG_MEM = 32'h 1a110000; localparam logic [31:0] ADDR_SPACE_RAM_MAIN = 32'h 10000000; localparam logic [31:0] ADDR_SPACE_EFLASH = 32'h 20000000; - localparam logic [31:0] ADDR_SPACE_UART = 32'h 40000000; - localparam logic [31:0] ADDR_SPACE_GPIO = 32'h 40010000; - localparam logic [31:0] ADDR_SPACE_SPI_DEVICE = 32'h 40020000; + localparam logic [1:0][31:0] ADDR_SPACE_PERI = { + 32'h 40000000, + 32'h 40080000 + }; localparam logic [31:0] ADDR_SPACE_FLASH_CTRL = 32'h 40030000; - localparam logic [31:0] ADDR_SPACE_RV_TIMER = 32'h 40080000; localparam logic [31:0] ADDR_SPACE_HMAC = 32'h 40120000; localparam logic [31:0] ADDR_SPACE_AES = 32'h 40110000; localparam logic [31:0] ADDR_SPACE_RV_PLIC = 32'h 40090000; @@ -26,11 +26,11 @@ localparam logic [31:0] ADDR_MASK_DEBUG_MEM = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_RAM_MAIN = 32'h 0000ffff; localparam logic [31:0] ADDR_MASK_EFLASH = 32'h 0007ffff; - localparam logic [31:0] ADDR_MASK_UART = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_GPIO = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_SPI_DEVICE = 32'h 00000fff; + localparam logic [1:0][31:0] ADDR_MASK_PERI = { + 32'h 00020fff, + 32'h 00000fff + }; localparam logic [31:0] ADDR_MASK_FLASH_CTRL = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_RV_TIMER = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_HMAC = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_AES = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_RV_PLIC = 32'h 00000fff; @@ -39,24 +39,21 @@ localparam logic [31:0] ADDR_MASK_NMI_GEN = 32'h 00000fff; localparam int N_HOST = 3; - localparam int N_DEVICE = 15; + localparam int N_DEVICE = 12; typedef enum int { TlRom = 0, TlDebugMem = 1, TlRamMain = 2, TlEflash = 3, - TlUart = 4, - TlGpio = 5, - TlSpiDevice = 6, - TlFlashCtrl = 7, - TlRvTimer = 8, - TlHmac = 9, - TlAes = 10, - TlRvPlic = 11, - TlPinmux = 12, - TlAlertHandler = 13, - TlNmiGen = 14 + TlPeri = 4, + TlFlashCtrl = 5, + TlHmac = 6, + TlAes = 7, + TlRvPlic = 8, + TlPinmux = 9, + TlAlertHandler = 10, + TlNmiGen = 11 } tl_device_e; typedef enum int {
diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv new file mode 100644 index 0000000..592566e --- /dev/null +++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
@@ -0,0 +1,704 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_main module generated by `tlgen.py` tool +// all reset signals should be generated from one reset signal to not make any deadlock +// +// Interconnect +// corei +// -> s1n_15 +// -> sm1_16 +// -> rom +// -> sm1_17 +// -> debug_mem +// -> sm1_18 +// -> ram_main +// -> sm1_19 +// -> eflash +// cored +// -> s1n_20 +// -> sm1_16 +// -> rom +// -> sm1_17 +// -> debug_mem +// -> sm1_18 +// -> ram_main +// -> sm1_19 +// -> eflash +// -> sm1_22 +// -> asf_21 +// -> peri +// -> sm1_23 +// -> flash_ctrl +// -> sm1_24 +// -> aes +// -> sm1_25 +// -> hmac +// -> sm1_26 +// -> rv_plic +// -> sm1_27 +// -> pinmux +// -> sm1_28 +// -> alert_handler +// -> sm1_29 +// -> nmi_gen +// dm_sba +// -> s1n_30 +// -> sm1_16 +// -> rom +// -> sm1_18 +// -> ram_main +// -> sm1_19 +// -> eflash +// -> sm1_22 +// -> asf_21 +// -> peri +// -> sm1_23 +// -> flash_ctrl +// -> sm1_24 +// -> aes +// -> sm1_25 +// -> hmac +// -> sm1_26 +// -> rv_plic +// -> sm1_27 +// -> pinmux +// -> sm1_28 +// -> alert_handler +// -> sm1_29 +// -> nmi_gen + +module xbar_main ( + input clk_main_i, + input clk_fixed_i, + input rst_main_ni, + input rst_fixed_ni, + + // Host interfaces + input tlul_pkg::tl_h2d_t tl_corei_i, + output tlul_pkg::tl_d2h_t tl_corei_o, + input tlul_pkg::tl_h2d_t tl_cored_i, + output tlul_pkg::tl_d2h_t tl_cored_o, + input tlul_pkg::tl_h2d_t tl_dm_sba_i, + output tlul_pkg::tl_d2h_t tl_dm_sba_o, + + // Device interfaces + output tlul_pkg::tl_h2d_t tl_rom_o, + input tlul_pkg::tl_d2h_t tl_rom_i, + output tlul_pkg::tl_h2d_t tl_debug_mem_o, + input tlul_pkg::tl_d2h_t tl_debug_mem_i, + output tlul_pkg::tl_h2d_t tl_ram_main_o, + input tlul_pkg::tl_d2h_t tl_ram_main_i, + output tlul_pkg::tl_h2d_t tl_eflash_o, + input tlul_pkg::tl_d2h_t tl_eflash_i, + output tlul_pkg::tl_h2d_t tl_peri_o, + input tlul_pkg::tl_d2h_t tl_peri_i, + output tlul_pkg::tl_h2d_t tl_flash_ctrl_o, + input tlul_pkg::tl_d2h_t tl_flash_ctrl_i, + output tlul_pkg::tl_h2d_t tl_hmac_o, + input tlul_pkg::tl_d2h_t tl_hmac_i, + output tlul_pkg::tl_h2d_t tl_aes_o, + input tlul_pkg::tl_d2h_t tl_aes_i, + output tlul_pkg::tl_h2d_t tl_rv_plic_o, + input tlul_pkg::tl_d2h_t tl_rv_plic_i, + output tlul_pkg::tl_h2d_t tl_pinmux_o, + input tlul_pkg::tl_d2h_t tl_pinmux_i, + output tlul_pkg::tl_h2d_t tl_alert_handler_o, + input tlul_pkg::tl_d2h_t tl_alert_handler_i, + output tlul_pkg::tl_h2d_t tl_nmi_gen_o, + input tlul_pkg::tl_d2h_t tl_nmi_gen_i, + + input scanmode_i +); + + import tlul_pkg::*; + import tl_main_pkg::*; + + // scanmode_i is currently not used, but provisioned for future use + // this assignment prevents lint warnings + logic unused_scanmode; + assign unused_scanmode = scanmode_i; + + tl_h2d_t tl_s1n_15_us_h2d ; + tl_d2h_t tl_s1n_15_us_d2h ; + + + tl_h2d_t tl_s1n_15_ds_h2d [4]; + tl_d2h_t tl_s1n_15_ds_d2h [4]; + + // Create steering signal + logic [2:0] dev_sel_s1n_15; + + + tl_h2d_t tl_sm1_16_us_h2d [3]; + tl_d2h_t tl_sm1_16_us_d2h [3]; + + tl_h2d_t tl_sm1_16_ds_h2d ; + tl_d2h_t tl_sm1_16_ds_d2h ; + + + tl_h2d_t tl_sm1_17_us_h2d [2]; + tl_d2h_t tl_sm1_17_us_d2h [2]; + + tl_h2d_t tl_sm1_17_ds_h2d ; + tl_d2h_t tl_sm1_17_ds_d2h ; + + + tl_h2d_t tl_sm1_18_us_h2d [3]; + tl_d2h_t tl_sm1_18_us_d2h [3]; + + tl_h2d_t tl_sm1_18_ds_h2d ; + tl_d2h_t tl_sm1_18_ds_d2h ; + + + tl_h2d_t tl_sm1_19_us_h2d [3]; + tl_d2h_t tl_sm1_19_us_d2h [3]; + + tl_h2d_t tl_sm1_19_ds_h2d ; + tl_d2h_t tl_sm1_19_ds_d2h ; + + tl_h2d_t tl_s1n_20_us_h2d ; + tl_d2h_t tl_s1n_20_us_d2h ; + + + tl_h2d_t tl_s1n_20_ds_h2d [12]; + tl_d2h_t tl_s1n_20_ds_d2h [12]; + + // Create steering signal + logic [3:0] dev_sel_s1n_20; + + tl_h2d_t tl_asf_21_us_h2d ; + tl_d2h_t tl_asf_21_us_d2h ; + tl_h2d_t tl_asf_21_ds_h2d ; + tl_d2h_t tl_asf_21_ds_d2h ; + + + tl_h2d_t tl_sm1_22_us_h2d [2]; + tl_d2h_t tl_sm1_22_us_d2h [2]; + + tl_h2d_t tl_sm1_22_ds_h2d ; + tl_d2h_t tl_sm1_22_ds_d2h ; + + + tl_h2d_t tl_sm1_23_us_h2d [2]; + tl_d2h_t tl_sm1_23_us_d2h [2]; + + tl_h2d_t tl_sm1_23_ds_h2d ; + tl_d2h_t tl_sm1_23_ds_d2h ; + + + tl_h2d_t tl_sm1_24_us_h2d [2]; + tl_d2h_t tl_sm1_24_us_d2h [2]; + + tl_h2d_t tl_sm1_24_ds_h2d ; + tl_d2h_t tl_sm1_24_ds_d2h ; + + + tl_h2d_t tl_sm1_25_us_h2d [2]; + tl_d2h_t tl_sm1_25_us_d2h [2]; + + tl_h2d_t tl_sm1_25_ds_h2d ; + tl_d2h_t tl_sm1_25_ds_d2h ; + + + tl_h2d_t tl_sm1_26_us_h2d [2]; + tl_d2h_t tl_sm1_26_us_d2h [2]; + + tl_h2d_t tl_sm1_26_ds_h2d ; + tl_d2h_t tl_sm1_26_ds_d2h ; + + + tl_h2d_t tl_sm1_27_us_h2d [2]; + tl_d2h_t tl_sm1_27_us_d2h [2]; + + tl_h2d_t tl_sm1_27_ds_h2d ; + tl_d2h_t tl_sm1_27_ds_d2h ; + + + tl_h2d_t tl_sm1_28_us_h2d [2]; + tl_d2h_t tl_sm1_28_us_d2h [2]; + + tl_h2d_t tl_sm1_28_ds_h2d ; + tl_d2h_t tl_sm1_28_ds_d2h ; + + + tl_h2d_t tl_sm1_29_us_h2d [2]; + tl_d2h_t tl_sm1_29_us_d2h [2]; + + tl_h2d_t tl_sm1_29_ds_h2d ; + tl_d2h_t tl_sm1_29_ds_d2h ; + + tl_h2d_t tl_s1n_30_us_h2d ; + tl_d2h_t tl_s1n_30_us_d2h ; + + + tl_h2d_t tl_s1n_30_ds_h2d [11]; + tl_d2h_t tl_s1n_30_ds_d2h [11]; + + // Create steering signal + logic [3:0] dev_sel_s1n_30; + + + + assign tl_sm1_16_us_h2d[0] = tl_s1n_15_ds_h2d[0]; + assign tl_s1n_15_ds_d2h[0] = tl_sm1_16_us_d2h[0]; + + assign tl_sm1_17_us_h2d[0] = tl_s1n_15_ds_h2d[1]; + assign tl_s1n_15_ds_d2h[1] = tl_sm1_17_us_d2h[0]; + + assign tl_sm1_18_us_h2d[0] = tl_s1n_15_ds_h2d[2]; + assign tl_s1n_15_ds_d2h[2] = tl_sm1_18_us_d2h[0]; + + assign tl_sm1_19_us_h2d[0] = tl_s1n_15_ds_h2d[3]; + assign tl_s1n_15_ds_d2h[3] = tl_sm1_19_us_d2h[0]; + + assign tl_sm1_16_us_h2d[1] = tl_s1n_20_ds_h2d[0]; + assign tl_s1n_20_ds_d2h[0] = tl_sm1_16_us_d2h[1]; + + assign tl_sm1_17_us_h2d[1] = tl_s1n_20_ds_h2d[1]; + assign tl_s1n_20_ds_d2h[1] = tl_sm1_17_us_d2h[1]; + + assign tl_sm1_18_us_h2d[1] = tl_s1n_20_ds_h2d[2]; + assign tl_s1n_20_ds_d2h[2] = tl_sm1_18_us_d2h[1]; + + assign tl_sm1_19_us_h2d[1] = tl_s1n_20_ds_h2d[3]; + assign tl_s1n_20_ds_d2h[3] = tl_sm1_19_us_d2h[1]; + + assign tl_sm1_22_us_h2d[0] = tl_s1n_20_ds_h2d[4]; + assign tl_s1n_20_ds_d2h[4] = tl_sm1_22_us_d2h[0]; + + assign tl_sm1_23_us_h2d[0] = tl_s1n_20_ds_h2d[5]; + assign tl_s1n_20_ds_d2h[5] = tl_sm1_23_us_d2h[0]; + + assign tl_sm1_24_us_h2d[0] = tl_s1n_20_ds_h2d[6]; + assign tl_s1n_20_ds_d2h[6] = tl_sm1_24_us_d2h[0]; + + assign tl_sm1_25_us_h2d[0] = tl_s1n_20_ds_h2d[7]; + assign tl_s1n_20_ds_d2h[7] = tl_sm1_25_us_d2h[0]; + + assign tl_sm1_26_us_h2d[0] = tl_s1n_20_ds_h2d[8]; + assign tl_s1n_20_ds_d2h[8] = tl_sm1_26_us_d2h[0]; + + assign tl_sm1_27_us_h2d[0] = tl_s1n_20_ds_h2d[9]; + assign tl_s1n_20_ds_d2h[9] = tl_sm1_27_us_d2h[0]; + + assign tl_sm1_28_us_h2d[0] = tl_s1n_20_ds_h2d[10]; + assign tl_s1n_20_ds_d2h[10] = tl_sm1_28_us_d2h[0]; + + assign tl_sm1_29_us_h2d[0] = tl_s1n_20_ds_h2d[11]; + assign tl_s1n_20_ds_d2h[11] = tl_sm1_29_us_d2h[0]; + + assign tl_sm1_16_us_h2d[2] = tl_s1n_30_ds_h2d[0]; + assign tl_s1n_30_ds_d2h[0] = tl_sm1_16_us_d2h[2]; + + assign tl_sm1_18_us_h2d[2] = tl_s1n_30_ds_h2d[1]; + assign tl_s1n_30_ds_d2h[1] = tl_sm1_18_us_d2h[2]; + + assign tl_sm1_19_us_h2d[2] = tl_s1n_30_ds_h2d[2]; + assign tl_s1n_30_ds_d2h[2] = tl_sm1_19_us_d2h[2]; + + assign tl_sm1_22_us_h2d[1] = tl_s1n_30_ds_h2d[3]; + assign tl_s1n_30_ds_d2h[3] = tl_sm1_22_us_d2h[1]; + + assign tl_sm1_23_us_h2d[1] = tl_s1n_30_ds_h2d[4]; + assign tl_s1n_30_ds_d2h[4] = tl_sm1_23_us_d2h[1]; + + assign tl_sm1_24_us_h2d[1] = tl_s1n_30_ds_h2d[5]; + assign tl_s1n_30_ds_d2h[5] = tl_sm1_24_us_d2h[1]; + + assign tl_sm1_25_us_h2d[1] = tl_s1n_30_ds_h2d[6]; + assign tl_s1n_30_ds_d2h[6] = tl_sm1_25_us_d2h[1]; + + assign tl_sm1_26_us_h2d[1] = tl_s1n_30_ds_h2d[7]; + assign tl_s1n_30_ds_d2h[7] = tl_sm1_26_us_d2h[1]; + + assign tl_sm1_27_us_h2d[1] = tl_s1n_30_ds_h2d[8]; + assign tl_s1n_30_ds_d2h[8] = tl_sm1_27_us_d2h[1]; + + assign tl_sm1_28_us_h2d[1] = tl_s1n_30_ds_h2d[9]; + assign tl_s1n_30_ds_d2h[9] = tl_sm1_28_us_d2h[1]; + + assign tl_sm1_29_us_h2d[1] = tl_s1n_30_ds_h2d[10]; + assign tl_s1n_30_ds_d2h[10] = tl_sm1_29_us_d2h[1]; + + assign tl_s1n_15_us_h2d = tl_corei_i; + assign tl_corei_o = tl_s1n_15_us_d2h; + + assign tl_rom_o = tl_sm1_16_ds_h2d; + assign tl_sm1_16_ds_d2h = tl_rom_i; + + assign tl_debug_mem_o = tl_sm1_17_ds_h2d; + assign tl_sm1_17_ds_d2h = tl_debug_mem_i; + + assign tl_ram_main_o = tl_sm1_18_ds_h2d; + assign tl_sm1_18_ds_d2h = tl_ram_main_i; + + assign tl_eflash_o = tl_sm1_19_ds_h2d; + assign tl_sm1_19_ds_d2h = tl_eflash_i; + + assign tl_s1n_20_us_h2d = tl_cored_i; + assign tl_cored_o = tl_s1n_20_us_d2h; + + assign tl_peri_o = tl_asf_21_ds_h2d; + assign tl_asf_21_ds_d2h = tl_peri_i; + + assign tl_asf_21_us_h2d = tl_sm1_22_ds_h2d; + assign tl_sm1_22_ds_d2h = tl_asf_21_us_d2h; + + assign tl_flash_ctrl_o = tl_sm1_23_ds_h2d; + assign tl_sm1_23_ds_d2h = tl_flash_ctrl_i; + + assign tl_aes_o = tl_sm1_24_ds_h2d; + assign tl_sm1_24_ds_d2h = tl_aes_i; + + assign tl_hmac_o = tl_sm1_25_ds_h2d; + assign tl_sm1_25_ds_d2h = tl_hmac_i; + + assign tl_rv_plic_o = tl_sm1_26_ds_h2d; + assign tl_sm1_26_ds_d2h = tl_rv_plic_i; + + assign tl_pinmux_o = tl_sm1_27_ds_h2d; + assign tl_sm1_27_ds_d2h = tl_pinmux_i; + + assign tl_alert_handler_o = tl_sm1_28_ds_h2d; + assign tl_sm1_28_ds_d2h = tl_alert_handler_i; + + assign tl_nmi_gen_o = tl_sm1_29_ds_h2d; + assign tl_sm1_29_ds_d2h = tl_nmi_gen_i; + + assign tl_s1n_30_us_h2d = tl_dm_sba_i; + assign tl_dm_sba_o = tl_s1n_30_us_d2h; + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_15 = 3'd4; + if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin + dev_sel_s1n_15 = 3'd0; + + end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin + dev_sel_s1n_15 = 3'd1; + + end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin + dev_sel_s1n_15 = 3'd2; + + end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin + dev_sel_s1n_15 = 3'd3; + end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_20 = 4'd12; + if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin + dev_sel_s1n_20 = 4'd0; + + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin + dev_sel_s1n_20 = 4'd1; + + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin + dev_sel_s1n_20 = 4'd2; + + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin + dev_sel_s1n_20 = 4'd3; + + end else if ( + ((tl_s1n_20_us_h2d.a_address <= (ADDR_MASK_PERI[0] + ADDR_SPACE_PERI[0])) && + (tl_s1n_20_us_h2d.a_address >= ADDR_SPACE_PERI[0])) || + ((tl_s1n_20_us_h2d.a_address <= (ADDR_MASK_PERI[1] + ADDR_SPACE_PERI[1])) && + (tl_s1n_20_us_h2d.a_address >= ADDR_SPACE_PERI[1])) + ) begin + dev_sel_s1n_20 = 4'd4; + + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin + dev_sel_s1n_20 = 4'd5; + + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin + dev_sel_s1n_20 = 4'd6; + + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin + dev_sel_s1n_20 = 4'd7; + + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin + dev_sel_s1n_20 = 4'd8; + + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin + dev_sel_s1n_20 = 4'd9; + + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin + dev_sel_s1n_20 = 4'd10; + + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin + dev_sel_s1n_20 = 4'd11; + end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_30 = 4'd11; + if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin + dev_sel_s1n_30 = 4'd0; + + end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin + dev_sel_s1n_30 = 4'd1; + + end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin + dev_sel_s1n_30 = 4'd2; + + end else if ( + ((tl_s1n_30_us_h2d.a_address <= (ADDR_MASK_PERI[0] + ADDR_SPACE_PERI[0])) && + (tl_s1n_30_us_h2d.a_address >= ADDR_SPACE_PERI[0])) || + ((tl_s1n_30_us_h2d.a_address <= (ADDR_MASK_PERI[1] + ADDR_SPACE_PERI[1])) && + (tl_s1n_30_us_h2d.a_address >= ADDR_SPACE_PERI[1])) + ) begin + dev_sel_s1n_30 = 4'd3; + + end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin + dev_sel_s1n_30 = 4'd4; + + end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin + dev_sel_s1n_30 = 4'd5; + + end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin + dev_sel_s1n_30 = 4'd6; + + end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin + dev_sel_s1n_30 = 4'd7; + + end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin + dev_sel_s1n_30 = 4'd8; + + end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin + dev_sel_s1n_30 = 4'd9; + + end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin + dev_sel_s1n_30 = 4'd10; + end + end + + + // Instantiation phase + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth ({4{4'h0}}), + .DRspDepth ({4{4'h0}}), + .N (4) + ) u_s1n_15 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_15_us_h2d), + .tl_h_o (tl_s1n_15_us_d2h), + .tl_d_o (tl_s1n_15_ds_h2d), + .tl_d_i (tl_s1n_15_ds_d2h), + .dev_select (dev_sel_s1n_15) + ); + tlul_socket_m1 #( + .HReqDepth ({3{4'h0}}), + .HRspDepth ({3{4'h0}}), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (3) + ) u_sm1_16 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_16_us_h2d), + .tl_h_o (tl_sm1_16_us_d2h), + .tl_d_o (tl_sm1_16_ds_h2d), + .tl_d_i (tl_sm1_16_ds_d2h) + ); + tlul_socket_m1 #( + .HReqPass (2'h0), + .HRspPass (2'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_17 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_17_us_h2d), + .tl_h_o (tl_sm1_17_us_d2h), + .tl_d_o (tl_sm1_17_ds_h2d), + .tl_d_i (tl_sm1_17_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth ({3{4'h0}}), + .HRspDepth ({3{4'h0}}), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (3) + ) u_sm1_18 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_18_us_h2d), + .tl_h_o (tl_sm1_18_us_d2h), + .tl_d_o (tl_sm1_18_ds_h2d), + .tl_d_i (tl_sm1_18_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth ({3{4'h0}}), + .HRspDepth ({3{4'h0}}), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (3) + ) u_sm1_19 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_19_us_h2d), + .tl_h_o (tl_sm1_19_us_d2h), + .tl_d_o (tl_sm1_19_ds_h2d), + .tl_d_i (tl_sm1_19_ds_d2h) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth ({12{4'h0}}), + .DRspDepth ({12{4'h0}}), + .N (12) + ) u_s1n_20 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_20_us_h2d), + .tl_h_o (tl_s1n_20_us_d2h), + .tl_d_o (tl_s1n_20_ds_h2d), + .tl_d_i (tl_s1n_20_ds_d2h), + .dev_select (dev_sel_s1n_20) + ); + tlul_fifo_async #( + .ReqDepth (3),// At least 3 to make async work + .RspDepth (3) // At least 3 to make async work + ) u_asf_21 ( + .clk_h_i (clk_main_i), + .rst_h_ni (rst_main_ni), + .clk_d_i (clk_fixed_i), + .rst_d_ni (rst_fixed_ni), + .tl_h_i (tl_asf_21_us_h2d), + .tl_h_o (tl_asf_21_us_d2h), + .tl_d_o (tl_asf_21_ds_h2d), + .tl_d_i (tl_asf_21_ds_d2h) + ); + tlul_socket_m1 #( + .M (2) + ) u_sm1_22 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_22_us_h2d), + .tl_h_o (tl_sm1_22_us_d2h), + .tl_d_o (tl_sm1_22_ds_h2d), + .tl_d_i (tl_sm1_22_ds_d2h) + ); + tlul_socket_m1 #( + .HReqPass (2'h0), + .HRspPass (2'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_23 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_23_us_h2d), + .tl_h_o (tl_sm1_23_us_d2h), + .tl_d_o (tl_sm1_23_ds_h2d), + .tl_d_i (tl_sm1_23_ds_d2h) + ); + tlul_socket_m1 #( + .HReqPass (2'h0), + .HRspPass (2'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_24 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_24_us_h2d), + .tl_h_o (tl_sm1_24_us_d2h), + .tl_d_o (tl_sm1_24_ds_h2d), + .tl_d_i (tl_sm1_24_ds_d2h) + ); + tlul_socket_m1 #( + .HReqPass (2'h0), + .HRspPass (2'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_25 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_25_us_h2d), + .tl_h_o (tl_sm1_25_us_d2h), + .tl_d_o (tl_sm1_25_ds_h2d), + .tl_d_i (tl_sm1_25_ds_d2h) + ); + tlul_socket_m1 #( + .HReqPass (2'h0), + .HRspPass (2'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_26 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_26_us_h2d), + .tl_h_o (tl_sm1_26_us_d2h), + .tl_d_o (tl_sm1_26_ds_h2d), + .tl_d_i (tl_sm1_26_ds_d2h) + ); + tlul_socket_m1 #( + .HReqPass (2'h0), + .HRspPass (2'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_27 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_27_us_h2d), + .tl_h_o (tl_sm1_27_us_d2h), + .tl_d_o (tl_sm1_27_ds_h2d), + .tl_d_i (tl_sm1_27_ds_d2h) + ); + tlul_socket_m1 #( + .HReqPass (2'h0), + .HRspPass (2'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_28 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_28_us_h2d), + .tl_h_o (tl_sm1_28_us_d2h), + .tl_d_o (tl_sm1_28_ds_h2d), + .tl_d_i (tl_sm1_28_ds_d2h) + ); + tlul_socket_m1 #( + .HReqPass (2'h0), + .HRspPass (2'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_29 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_29_us_h2d), + .tl_h_o (tl_sm1_29_us_d2h), + .tl_d_o (tl_sm1_29_ds_h2d), + .tl_d_i (tl_sm1_29_ds_d2h) + ); + tlul_socket_1n #( + .HReqPass (1'b0), + .HRspPass (1'b0), + .DReqPass (11'h0), + .DRspPass (11'h0), + .N (11) + ) u_s1n_30 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_30_us_h2d), + .tl_h_o (tl_s1n_30_us_d2h), + .tl_d_o (tl_s1n_30_ds_h2d), + .tl_d_i (tl_s1n_30_ds_d2h), + .dev_select (dev_sel_s1n_30) + ); + +endmodule
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson new file mode 100644 index 0000000..b929379 --- /dev/null +++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
@@ -0,0 +1,93 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ + +{ + name: peri + clock_connections: + { + clk_peri_i: fixed + } + reset: rst_peri_ni + reset_connections: + { + rst_peri_ni: sys_fixed + } + connections: + { + main: + [ + uart + gpio + spi_device + rv_timer + ] + } + nodes: + [ + { + name: main + type: host + clock: clk_peri_i + reset: rst_peri_ni + xbar: true + pipeline: "false" + inst_type: "" + pipeline_byp: "true" + } + { + name: uart + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: "false" + inst_type: uart + base_addr: 0x40000000 + size_byte: 0x1000 + xbar: false + pipeline_byp: "true" + } + { + name: gpio + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: "false" + inst_type: gpio + base_addr: 0x40010000 + size_byte: 0x1000 + xbar: false + pipeline_byp: "true" + } + { + name: spi_device + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: "false" + inst_type: spi_device + base_addr: 0x40020000 + size_byte: 0x1000 + xbar: false + pipeline_byp: "true" + } + { + name: rv_timer + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: "false" + inst_type: rv_timer + base_addr: 0x40080000 + size_byte: 0x1000 + xbar: false + pipeline_byp: "true" + } + ] + clock: clk_peri_i + type: xbar +} \ No newline at end of file
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv new file mode 100644 index 0000000..380c458 --- /dev/null +++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
@@ -0,0 +1,42 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_peri_bind module generated by `tlgen.py` tool for assertions +module xbar_peri_bind; + + // Host interfaces + bind xbar_peri tlul_assert #(.EndpointType("Device")) tlul_assert_host_main ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_main_i), + .d2h (tl_main_o) + ); + + // Device interfaces + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_uart ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_uart_o), + .d2h (tl_uart_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_gpio ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_gpio_o), + .d2h (tl_gpio_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_spi_device ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_spi_device_o), + .d2h (tl_spi_device_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_timer ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_rv_timer_o), + .d2h (tl_rv_timer_i) + ); + +endmodule
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv new file mode 100644 index 0000000..3f303fa --- /dev/null +++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
@@ -0,0 +1,33 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tl_peri package generated by `tlgen.py` tool + +package tl_peri_pkg; + + localparam logic [31:0] ADDR_SPACE_UART = 32'h 40000000; + localparam logic [31:0] ADDR_SPACE_GPIO = 32'h 40010000; + localparam logic [31:0] ADDR_SPACE_SPI_DEVICE = 32'h 40020000; + localparam logic [31:0] ADDR_SPACE_RV_TIMER = 32'h 40080000; + + localparam logic [31:0] ADDR_MASK_UART = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_GPIO = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_SPI_DEVICE = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_RV_TIMER = 32'h 00000fff; + + localparam int N_HOST = 1; + localparam int N_DEVICE = 4; + + typedef enum int { + TlUart = 0, + TlGpio = 1, + TlSpiDevice = 2, + TlRvTimer = 3 + } tl_device_e; + + typedef enum int { + TlMain = 0 + } tl_host_e; + +endpackage
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv new file mode 100644 index 0000000..4ee2010 --- /dev/null +++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
@@ -0,0 +1,107 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_peri module generated by `tlgen.py` tool +// all reset signals should be generated from one reset signal to not make any deadlock +// +// Interconnect +// main +// -> s1n_5 +// -> uart +// -> gpio +// -> spi_device +// -> rv_timer + +module xbar_peri ( + input clk_peri_i, + input rst_peri_ni, + + // Host interfaces + input tlul_pkg::tl_h2d_t tl_main_i, + output tlul_pkg::tl_d2h_t tl_main_o, + + // Device interfaces + output tlul_pkg::tl_h2d_t tl_uart_o, + input tlul_pkg::tl_d2h_t tl_uart_i, + output tlul_pkg::tl_h2d_t tl_gpio_o, + input tlul_pkg::tl_d2h_t tl_gpio_i, + output tlul_pkg::tl_h2d_t tl_spi_device_o, + input tlul_pkg::tl_d2h_t tl_spi_device_i, + output tlul_pkg::tl_h2d_t tl_rv_timer_o, + input tlul_pkg::tl_d2h_t tl_rv_timer_i, + + input scanmode_i +); + + import tlul_pkg::*; + import tl_peri_pkg::*; + + // scanmode_i is currently not used, but provisioned for future use + // this assignment prevents lint warnings + logic unused_scanmode; + assign unused_scanmode = scanmode_i; + + tl_h2d_t tl_s1n_5_us_h2d ; + tl_d2h_t tl_s1n_5_us_d2h ; + + + tl_h2d_t tl_s1n_5_ds_h2d [4]; + tl_d2h_t tl_s1n_5_ds_d2h [4]; + + // Create steering signal + logic [2:0] dev_sel_s1n_5; + + + + assign tl_uart_o = tl_s1n_5_ds_h2d[0]; + assign tl_s1n_5_ds_d2h[0] = tl_uart_i; + + assign tl_gpio_o = tl_s1n_5_ds_h2d[1]; + assign tl_s1n_5_ds_d2h[1] = tl_gpio_i; + + assign tl_spi_device_o = tl_s1n_5_ds_h2d[2]; + assign tl_s1n_5_ds_d2h[2] = tl_spi_device_i; + + assign tl_rv_timer_o = tl_s1n_5_ds_h2d[3]; + assign tl_s1n_5_ds_d2h[3] = tl_rv_timer_i; + + assign tl_s1n_5_us_h2d = tl_main_i; + assign tl_main_o = tl_s1n_5_us_d2h; + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_5 = 3'd4; + if ((tl_s1n_5_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin + dev_sel_s1n_5 = 3'd0; + + end else if ((tl_s1n_5_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin + dev_sel_s1n_5 = 3'd1; + + end else if ((tl_s1n_5_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin + dev_sel_s1n_5 = 3'd2; + + end else if ((tl_s1n_5_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin + dev_sel_s1n_5 = 3'd3; + end + end + + + // Instantiation phase + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth ({4{4'h0}}), + .DRspDepth ({4{4'h0}}), + .N (4) + ) u_s1n_5 ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .tl_h_i (tl_s1n_5_us_h2d), + .tl_h_o (tl_s1n_5_us_d2h), + .tl_d_o (tl_s1n_5_ds_h2d), + .tl_d_i (tl_s1n_5_ds_d2h), + .dev_select (dev_sel_s1n_5) + ); + +endmodule
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index b79ceb0..640968c 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -93,6 +93,14 @@ tl_h2d_t tl_eflash_d_h2d; tl_d2h_t tl_eflash_d_d2h; + tl_h2d_t tl_main_h_h2d; + tl_d2h_t tl_main_h_d2h; + tl_h2d_t tl_peri_d_h2d; + tl_d2h_t tl_peri_d_d2h; + + assign tl_main_h_h2d = tl_peri_d_h2d; + assign tl_peri_d_d2h = tl_main_h_d2h; + //reset wires declaration logic lc_rst_n; logic sys_rst_n; @@ -667,16 +675,10 @@ .tl_ram_main_i (tl_ram_main_d_d2h), .tl_eflash_o (tl_eflash_d_h2d), .tl_eflash_i (tl_eflash_d_d2h), - .tl_uart_o (tl_uart_d_h2d), - .tl_uart_i (tl_uart_d_d2h), - .tl_gpio_o (tl_gpio_d_h2d), - .tl_gpio_i (tl_gpio_d_d2h), - .tl_spi_device_o (tl_spi_device_d_h2d), - .tl_spi_device_i (tl_spi_device_d_d2h), + .tl_peri_o (tl_peri_d_h2d), + .tl_peri_i (tl_peri_d_d2h), .tl_flash_ctrl_o (tl_flash_ctrl_d_h2d), .tl_flash_ctrl_i (tl_flash_ctrl_d_d2h), - .tl_rv_timer_o (tl_rv_timer_d_h2d), - .tl_rv_timer_i (tl_rv_timer_d_d2h), .tl_hmac_o (tl_hmac_d_h2d), .tl_hmac_i (tl_hmac_d_d2h), .tl_aes_o (tl_aes_d_h2d), @@ -692,6 +694,22 @@ .scanmode_i ); + xbar_peri u_xbar_peri ( + .clk_peri_i (fixed_clk), + .rst_peri_ni (sys_fixed_rst_n), + .tl_main_i (tl_main_h_h2d), + .tl_main_o (tl_main_h_d2h), + .tl_uart_o (tl_uart_d_h2d), + .tl_uart_i (tl_uart_d_d2h), + .tl_gpio_o (tl_gpio_d_h2d), + .tl_gpio_i (tl_gpio_d_d2h), + .tl_spi_device_o (tl_spi_device_d_h2d), + .tl_spi_device_i (tl_spi_device_d_d2h), + .tl_rv_timer_o (tl_rv_timer_d_h2d), + .tl_rv_timer_i (tl_rv_timer_d_d2h), + + .scanmode_i + ); // Pinmux connections assign p2m = {
diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core index ff5b396..e78f0f1 100644 --- a/hw/top_earlgrey/top_earlgrey.core +++ b/hw/top_earlgrey/top_earlgrey.core
@@ -24,8 +24,10 @@ - lowrisc:constants:top_pkg - lowrisc:ip:nmi_gen files: - - ip/xbar/rtl/autogen/tl_main_pkg.sv - - ip/xbar/rtl/autogen/xbar_main.sv + - ip/xbar_main/rtl/autogen/tl_main_pkg.sv + - ip/xbar_main/rtl/autogen/xbar_main.sv + - ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv + - ip/xbar_peri/rtl/autogen/xbar_peri.sv - ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv - ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv - ip/rv_plic/rtl/autogen/rv_plic.sv