Update lowrisc_ibex to lowRISC/ibex@42827fc9
Update code from upstream repository
https://github.com/lowRISC/ibex.git to revision
42827fc9cd0b2043d5d179cae46b0238a55d3652
* [rtl/icache] Switch ECC granularity to 32bits (Tom Roberts)
* Update lowrisc_ip to lowRISC/opentitan@1ae03937f (Tom Roberts)
* [rtl] Fix lint issues (Greg Chadwick)
* [dv/ibex] filter out tests on a per-config basis (Udi Jonnalagadda)
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
diff --git a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
index 72b8d93..23d13be 100644
--- a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
+++ b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
@@ -37,6 +37,7 @@
input logic rst_esc_ni,
input logic test_en_i, // enable all clock gates for testing
+ input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
input logic [31:0] hart_id_i,
input logic [31:0] boot_addr_i,
@@ -196,6 +197,7 @@
.rst_ni,
.test_en_i,
+ .ram_cfg_i,
.hart_id_i,
.boot_addr_i,
diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index f0b4bcb..6477ee4 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -268,6 +268,7 @@
.clk_esc_i (${esc_clk}),
.rst_esc_ni (${esc_rst}[rstmgr_pkg::Domain0Sel]),
.test_en_i (1'b0),
+ .ram_cfg_i (ast_ram_1p_cfg),
// static pinning
.hart_id_i (32'b0),
.boot_addr_i (ADDR_SPACE_ROM),
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index a8a7349..e3d1dea 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -682,6 +682,7 @@
.clk_esc_i (clkmgr_aon_clocks.clk_io_div4_timers),
.rst_esc_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]),
.test_en_i (1'b0),
+ .ram_cfg_i (ast_ram_1p_cfg),
// static pinning
.hart_id_i (32'b0),
.boot_addr_i (ADDR_SPACE_ROM),
diff --git a/hw/vendor/lowrisc_ibex.lock.hjson b/hw/vendor/lowrisc_ibex.lock.hjson
index 63cc879..da03b10 100644
--- a/hw/vendor/lowrisc_ibex.lock.hjson
+++ b/hw/vendor/lowrisc_ibex.lock.hjson
@@ -9,6 +9,6 @@
upstream:
{
url: https://github.com/lowRISC/ibex.git
- rev: 6d9e1aca8ad7cf09d4effcde97e471d6c213ead1
+ rev: 42827fc9cd0b2043d5d179cae46b0238a55d3652
}
}
diff --git a/hw/vendor/lowrisc_ibex/doc/02_user/integration.rst b/hw/vendor/lowrisc_ibex/doc/02_user/integration.rst
index 94de101..d165fdb 100644
--- a/hw/vendor/lowrisc_ibex/doc/02_user/integration.rst
+++ b/hw/vendor/lowrisc_ibex/doc/02_user/integration.rst
@@ -33,6 +33,7 @@
.clk_i (),
.rst_ni (),
.test_en_i (),
+ .ram_cfg_i (),
// Configuration
.hart_id_i (),
@@ -158,6 +159,9 @@
+-------------------------+-------------------------+-----+----------------------------------------+
| ``test_en_i`` | 1 | in | Test input, enables clock |
+-------------------------+-------------------------+-----+----------------------------------------+
+| ``ram_cfg_i`` | 10 | in | RAM configuration inputs, routed to |
+| | | | the icache RAMs |
++-------------------------+-------------------------+-----+----------------------------------------+
| ``hart_id_i`` | 32 | in | Hart ID, usually static, can be read |
| | | | from :ref:`csr-mhartid` CSR |
+-------------------------+-------------------------+-----+----------------------------------------+
diff --git a/hw/vendor/lowrisc_ibex/examples/fpga/artya7/rtl/top_artya7.sv b/hw/vendor/lowrisc_ibex/examples/fpga/artya7/rtl/top_artya7.sv
index ef50ceb..db4e461 100644
--- a/hw/vendor/lowrisc_ibex/examples/fpga/artya7/rtl/top_artya7.sv
+++ b/hw/vendor/lowrisc_ibex/examples/fpga/artya7/rtl/top_artya7.sv
@@ -51,6 +51,7 @@
.rst_ni (rst_sys_n),
.test_en_i ('b0),
+ .ram_cfg_i ('b0),
.hart_id_i (32'b0),
// First instruction executed is at 0x0 + 0x80
diff --git a/hw/vendor/lowrisc_ibex/examples/simple_system/rtl/ibex_simple_system.sv b/hw/vendor/lowrisc_ibex/examples/simple_system/rtl/ibex_simple_system.sv
index debf4c2..3de2c17 100644
--- a/hw/vendor/lowrisc_ibex/examples/simple_system/rtl/ibex_simple_system.sv
+++ b/hw/vendor/lowrisc_ibex/examples/simple_system/rtl/ibex_simple_system.sv
@@ -183,6 +183,7 @@
.rst_ni (rst_sys_n),
.test_en_i ('b0),
+ .ram_cfg_i ('b0),
.hart_id_i (32'b0),
// First instruction executed is at 0x0 + 0x80
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_core.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_core.sv
index 63b5712..a74448b 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_core.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_core.sv
@@ -34,78 +34,79 @@
parameter int unsigned DmExceptionAddr = 32'h1A110808
) (
// Clock and Reset
- input logic clk_i,
- input logic rst_ni,
+ input logic clk_i,
+ input logic rst_ni,
- input logic test_en_i, // enable all clock gates for testing
+ input logic test_en_i, // enable all clock gates for testing
+ input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
- input logic [31:0] hart_id_i,
- input logic [31:0] boot_addr_i,
+ input logic [31:0] hart_id_i,
+ input logic [31:0] boot_addr_i,
// Instruction memory interface
- output logic instr_req_o,
- input logic instr_gnt_i,
- input logic instr_rvalid_i,
- output logic [31:0] instr_addr_o,
- input logic [31:0] instr_rdata_i,
- input logic instr_err_i,
+ output logic instr_req_o,
+ input logic instr_gnt_i,
+ input logic instr_rvalid_i,
+ output logic [31:0] instr_addr_o,
+ input logic [31:0] instr_rdata_i,
+ input logic instr_err_i,
// Data memory interface
- output logic data_req_o,
- input logic data_gnt_i,
- input logic data_rvalid_i,
- output logic data_we_o,
- output logic [3:0] data_be_o,
- output logic [31:0] data_addr_o,
- output logic [31:0] data_wdata_o,
- input logic [31:0] data_rdata_i,
- input logic data_err_i,
+ output logic data_req_o,
+ input logic data_gnt_i,
+ input logic data_rvalid_i,
+ output logic data_we_o,
+ output logic [3:0] data_be_o,
+ output logic [31:0] data_addr_o,
+ output logic [31:0] data_wdata_o,
+ input logic [31:0] data_rdata_i,
+ input logic data_err_i,
// Interrupt inputs
- input logic irq_software_i,
- input logic irq_timer_i,
- input logic irq_external_i,
- input logic [14:0] irq_fast_i,
- input logic irq_nm_i, // non-maskeable interrupt
+ input logic irq_software_i,
+ input logic irq_timer_i,
+ input logic irq_external_i,
+ input logic [14:0] irq_fast_i,
+ input logic irq_nm_i, // non-maskeable interrupt
// Debug Interface
- input logic debug_req_i,
- output ibex_pkg::crash_dump_t crash_dump_o,
+ input logic debug_req_i,
+ output ibex_pkg::crash_dump_t crash_dump_o,
// RISC-V Formal Interface
// Does not comply with the coding standards of _i/_o suffixes, but follows
// the convention of RISC-V Formal Interface Specification.
`ifdef RVFI
- output logic rvfi_valid,
- output logic [63:0] rvfi_order,
- output logic [31:0] rvfi_insn,
- output logic rvfi_trap,
- output logic rvfi_halt,
- output logic rvfi_intr,
- output logic [ 1:0] rvfi_mode,
- output logic [ 1:0] rvfi_ixl,
- output logic [ 4:0] rvfi_rs1_addr,
- output logic [ 4:0] rvfi_rs2_addr,
- output logic [ 4:0] rvfi_rs3_addr,
- output logic [31:0] rvfi_rs1_rdata,
- output logic [31:0] rvfi_rs2_rdata,
- output logic [31:0] rvfi_rs3_rdata,
- output logic [ 4:0] rvfi_rd_addr,
- output logic [31:0] rvfi_rd_wdata,
- output logic [31:0] rvfi_pc_rdata,
- output logic [31:0] rvfi_pc_wdata,
- output logic [31:0] rvfi_mem_addr,
- output logic [ 3:0] rvfi_mem_rmask,
- output logic [ 3:0] rvfi_mem_wmask,
- output logic [31:0] rvfi_mem_rdata,
- output logic [31:0] rvfi_mem_wdata,
+ output logic rvfi_valid,
+ output logic [63:0] rvfi_order,
+ output logic [31:0] rvfi_insn,
+ output logic rvfi_trap,
+ output logic rvfi_halt,
+ output logic rvfi_intr,
+ output logic [ 1:0] rvfi_mode,
+ output logic [ 1:0] rvfi_ixl,
+ output logic [ 4:0] rvfi_rs1_addr,
+ output logic [ 4:0] rvfi_rs2_addr,
+ output logic [ 4:0] rvfi_rs3_addr,
+ output logic [31:0] rvfi_rs1_rdata,
+ output logic [31:0] rvfi_rs2_rdata,
+ output logic [31:0] rvfi_rs3_rdata,
+ output logic [ 4:0] rvfi_rd_addr,
+ output logic [31:0] rvfi_rd_wdata,
+ output logic [31:0] rvfi_pc_rdata,
+ output logic [31:0] rvfi_pc_wdata,
+ output logic [31:0] rvfi_mem_addr,
+ output logic [ 3:0] rvfi_mem_rmask,
+ output logic [ 3:0] rvfi_mem_wmask,
+ output logic [31:0] rvfi_mem_rdata,
+ output logic [31:0] rvfi_mem_wdata,
`endif
// CPU Control Signals
- input logic fetch_enable_i,
- output logic alert_minor_o,
- output logic alert_major_o,
- output logic core_sleep_o
+ input logic fetch_enable_i,
+ output logic alert_minor_o,
+ output logic alert_major_o,
+ output logic core_sleep_o
);
import ibex_pkg::*;
@@ -411,6 +412,7 @@
.clk_i ( clk ),
.rst_ni ( rst_ni ),
+ .ram_cfg_i ( ram_cfg_i ),
.boot_addr_i ( boot_addr_i ),
.req_i ( instr_req_int ), // instruction request control
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_core_tracing.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_core_tracing.sv
index 96bdc22..d921ef7 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_core_tracing.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_core_tracing.sv
@@ -28,49 +28,51 @@
parameter int unsigned DmExceptionAddr = 32'h1A110808
) (
// Clock and Reset
- input logic clk_i,
- input logic rst_ni,
+ input logic clk_i,
+ input logic rst_ni,
- input logic test_en_i, // enable all clock gates for testing
+ input logic test_en_i, // enable all clock gates for testing
+ input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
- input logic [31:0] hart_id_i,
- input logic [31:0] boot_addr_i,
+
+ input logic [31:0] hart_id_i,
+ input logic [31:0] boot_addr_i,
// Instruction memory interface
- output logic instr_req_o,
- input logic instr_gnt_i,
- input logic instr_rvalid_i,
- output logic [31:0] instr_addr_o,
- input logic [31:0] instr_rdata_i,
- input logic instr_err_i,
+ output logic instr_req_o,
+ input logic instr_gnt_i,
+ input logic instr_rvalid_i,
+ output logic [31:0] instr_addr_o,
+ input logic [31:0] instr_rdata_i,
+ input logic instr_err_i,
// Data memory interface
- output logic data_req_o,
- input logic data_gnt_i,
- input logic data_rvalid_i,
- output logic data_we_o,
- output logic [3:0] data_be_o,
- output logic [31:0] data_addr_o,
- output logic [31:0] data_wdata_o,
- input logic [31:0] data_rdata_i,
- input logic data_err_i,
+ output logic data_req_o,
+ input logic data_gnt_i,
+ input logic data_rvalid_i,
+ output logic data_we_o,
+ output logic [3:0] data_be_o,
+ output logic [31:0] data_addr_o,
+ output logic [31:0] data_wdata_o,
+ input logic [31:0] data_rdata_i,
+ input logic data_err_i,
// Interrupt inputs
- input logic irq_software_i,
- input logic irq_timer_i,
- input logic irq_external_i,
- input logic [14:0] irq_fast_i,
- input logic irq_nm_i, // non-maskeable interrupt
+ input logic irq_software_i,
+ input logic irq_timer_i,
+ input logic irq_external_i,
+ input logic [14:0] irq_fast_i,
+ input logic irq_nm_i, // non-maskeable interrupt
// Debug Interface
- input logic debug_req_i,
- output ibex_pkg::crash_dump_t crash_dump_o,
+ input logic debug_req_i,
+ output ibex_pkg::crash_dump_t crash_dump_o,
// CPU Control Signals
- input logic fetch_enable_i,
- output logic alert_minor_o,
- output logic alert_major_o,
- output logic core_sleep_o
+ input logic fetch_enable_i,
+ output logic alert_minor_o,
+ output logic alert_major_o,
+ output logic core_sleep_o
);
@@ -130,6 +132,7 @@
.rst_ni,
.test_en_i,
+ .ram_cfg_i,
.hart_id_i,
.boot_addr_i,
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv
index 9091e92..39ce15d 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv
@@ -1282,7 +1282,7 @@
if (DbgTriggerEn) begin : gen_trigger_regs
localparam int unsigned DbgHwNumLen = DbgHwBreakNum > 1 ? $clog2(DbgHwBreakNum) : 1;
- localparam int MaxTselect = DbgHwBreakNum - 1;
+ localparam int unsigned MaxTselect = DbgHwBreakNum - 1;
// Register values
logic [DbgHwNumLen-1:0] tselect_d, tselect_q;
@@ -1313,6 +1313,7 @@
// select register. Only allow changes to the register if it is within the supported region.
assign tselect_d = (csr_wdata_int < DbgHwBreakNum) ? csr_wdata_int[DbgHwNumLen-1:0] :
MaxTselect[DbgHwNumLen-1:0];
+
// tmatch_control is enabled when the execute bit is set
assign tmatch_control_d = csr_wdata_int[2];
assign tmatch_value_d = csr_wdata_int[31:0];
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_icache.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_icache.sv
index 346e6a2..591e3b0 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_icache.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_icache.sv
@@ -22,40 +22,41 @@
parameter bit BranchCache = 1'b0
) (
// Clock and reset
- input logic clk_i,
- input logic rst_ni,
+ input logic clk_i,
+ input logic rst_ni,
// Signal that the core would like instructions
- input logic req_i,
+ input logic req_i,
// Set the cache's address counter
- input logic branch_i,
- input logic branch_spec_i,
- input logic predicted_branch_i,
- input logic branch_mispredict_i,
- input logic [31:0] addr_i,
+ input logic branch_i,
+ input logic branch_spec_i,
+ input logic predicted_branch_i,
+ input logic branch_mispredict_i,
+ input logic [31:0] addr_i,
// IF stage interface: Pass fetched instructions to the core
- input logic ready_i,
- output logic valid_o,
- output logic [31:0] rdata_o,
- output logic [31:0] addr_o,
- output logic err_o,
- output logic err_plus2_o,
+ input logic ready_i,
+ output logic valid_o,
+ output logic [31:0] rdata_o,
+ output logic [31:0] addr_o,
+ output logic err_o,
+ output logic err_plus2_o,
// Instruction memory / interconnect interface: Fetch instruction data from memory
- output logic instr_req_o,
- input logic instr_gnt_i,
- output logic [31:0] instr_addr_o,
- input logic [BusWidth-1:0] instr_rdata_i,
- input logic instr_err_i,
- input logic instr_pmp_err_i,
- input logic instr_rvalid_i,
+ output logic instr_req_o,
+ input logic instr_gnt_i,
+ output logic [31:0] instr_addr_o,
+ input logic [BusWidth-1:0] instr_rdata_i,
+ input logic instr_err_i,
+ input logic instr_pmp_err_i,
+ input logic instr_rvalid_i,
// Cache status
- input logic icache_enable_i,
- input logic icache_inval_i,
- output logic busy_o
+ input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
+ input logic icache_enable_i,
+ input logic icache_inval_i,
+ output logic busy_o
);
// Local constants
localparam int unsigned ADDR_W = 32;
@@ -64,14 +65,15 @@
// Request throttling threshold
localparam int unsigned FB_THRESHOLD = NUM_FB - 2;
// Derived parameters
- localparam int unsigned LINE_SIZE_ECC = ICacheECC ? (LineSize + 8) : LineSize;
localparam int unsigned LINE_SIZE_BYTES = LineSize/8;
localparam int unsigned LINE_W = $clog2(LINE_SIZE_BYTES);
+ localparam int unsigned BUS_SIZE_ECC = ICacheECC ? (BusWidth + 7) : BusWidth;
localparam int unsigned BUS_BYTES = BusWidth/8;
localparam int unsigned BUS_W = $clog2(BUS_BYTES);
localparam int unsigned LINE_BEATS = LINE_SIZE_BYTES / BUS_BYTES;
localparam int unsigned LINE_BEATS_W = $clog2(LINE_BEATS);
localparam int unsigned NUM_LINES = CacheSizeBytes / NumWays / LINE_SIZE_BYTES;
+ localparam int unsigned LINE_SIZE_ECC = BUS_SIZE_ECC * LINE_BEATS;
localparam int unsigned INDEX_W = $clog2(NUM_LINES);
localparam int unsigned INDEX_HI = INDEX_W + LINE_W - 1;
localparam int unsigned TAG_SIZE = ADDR_W - INDEX_W - LINE_W + 1; // 1 valid bit
@@ -110,7 +112,8 @@
// Cache pipelipe IC1 signals
logic [TAG_SIZE_ECC-1:0] tag_rdata_ic1 [NumWays];
logic [LINE_SIZE_ECC-1:0] data_rdata_ic1 [NumWays];
- logic [LINE_SIZE_ECC-1:0] hit_data_ic1;
+ logic [LINE_SIZE_ECC-1:0] hit_data_ecc_ic1;
+ logic [LineSize-1:0] hit_data_ic1;
logic lookup_valid_ic1;
logic [ADDR_W-1:INDEX_HI+1] lookup_addr_ic1;
logic [NumWays-1:0] tag_match_ic1;
@@ -315,10 +318,12 @@
assign tag_wdata_ic0 = {tag_ecc_output_padded[27:22],tag_ecc_output_padded[TAG_SIZE-1:0]};
// Dataram ECC
- prim_secded_72_64_enc data_ecc_enc (
- .in (fill_wdata_ic0),
- .out (data_wdata_ic0)
- );
+ for (genvar bank = 0; bank < LINE_BEATS; bank ++) begin : gen_ecc_banks
+ prim_secded_39_32_enc data_ecc_enc (
+ .in (fill_wdata_ic0[bank*BusWidth+:BusWidth]),
+ .out (data_wdata_ic0[bank*BUS_SIZE_ECC+:BUS_SIZE_ECC])
+ );
+ end
end else begin : gen_noecc_wdata
assign tag_wdata_ic0 = fill_tag_ic0;
@@ -338,6 +343,7 @@
) tag_bank (
.clk_i (clk_i),
.req_i (tag_req_ic0 & tag_banks_ic0[way]),
+ .cfg_i (ram_cfg_i),
.write_i (tag_write_ic0),
.wmask_i ({TAG_SIZE_ECC{1'b1}}),
.addr_i (tag_index_ic0),
@@ -352,6 +358,7 @@
) data_bank (
.clk_i (clk_i),
.req_i (data_req_ic0 & data_banks_ic0[way]),
+ .cfg_i (ram_cfg_i),
.write_i (data_write_ic0),
.wmask_i ({LINE_SIZE_ECC{1'b1}}),
.addr_i (data_index_ic0),
@@ -390,10 +397,10 @@
// Hit data mux
always_comb begin
- hit_data_ic1 = 'b0;
+ hit_data_ecc_ic1 = 'b0;
for (int way = 0; way < NumWays; way++) begin
if (tag_match_ic1[way]) begin
- hit_data_ic1 |= data_rdata_ic1[way];
+ hit_data_ecc_ic1 |= data_rdata_ic1[way];
end
end
end
@@ -421,11 +428,11 @@
// ECC checking logic
if (ICacheECC) begin : gen_data_ecc_checking
- logic [NumWays-1:0] tag_err_ic1;
- logic [1:0] data_err_ic1;
- logic ecc_correction_write_d, ecc_correction_write_q;
- logic [NumWays-1:0] ecc_correction_ways_d, ecc_correction_ways_q;
- logic [INDEX_W-1:0] lookup_index_ic1, ecc_correction_index_q;
+ logic [NumWays-1:0] tag_err_ic1;
+ logic [LINE_BEATS*2-1:0] data_err_ic1;
+ logic ecc_correction_write_d, ecc_correction_write_q;
+ logic [NumWays-1:0] ecc_correction_ways_d, ecc_correction_ways_q;
+ logic [INDEX_W-1:0] lookup_index_ic1, ecc_correction_index_q;
// Tag ECC checking
for (genvar way = 0; way < NumWays; way++) begin : gen_tag_ecc
@@ -448,12 +455,17 @@
// Data ECC checking
// Note - could generate for all ways and mux after
- prim_secded_72_64_dec data_ecc_dec (
- .in (hit_data_ic1),
- .d_o (),
- .syndrome_o (),
- .err_o (data_err_ic1)
- );
+ for (genvar bank = 0; bank < LINE_BEATS; bank++) begin : gen_ecc_banks
+ prim_secded_39_32_dec data_ecc_dec (
+ .in (hit_data_ecc_ic1[bank*BUS_SIZE_ECC+:BUS_SIZE_ECC]),
+ .d_o (),
+ .syndrome_o (),
+ .err_o (data_err_ic1[bank*2+:2])
+ );
+
+ assign hit_data_ic1[bank*BusWidth+:BusWidth] = hit_data_ecc_ic1[bank*BUS_SIZE_ECC+:BusWidth];
+
+ end
assign ecc_err_ic1 = lookup_valid_ic1 & ((|data_err_ic1) | (|tag_err_ic1));
@@ -497,6 +509,7 @@
assign ecc_write_req = 1'b0;
assign ecc_write_ways = '0;
assign ecc_write_index = '0;
+ assign hit_data_ic1 = hit_data_ecc_ic1;
end
///////////////////////////////
@@ -782,7 +795,7 @@
// Data either comes from the cache or the bus. If there was an ECC error, we must take
// the incoming bus data since the cache hit data is corrupted.
- assign fill_data_d[fb] = fill_hit_ic1[fb] ? hit_data_ic1[LineSize-1:0] :
+ assign fill_data_d[fb] = fill_hit_ic1[fb] ? hit_data_ic1 :
{LINE_BEATS{instr_rdata_i}};
for (genvar b = 0; b < LINE_BEATS; b++) begin : gen_data_buf
@@ -881,7 +894,7 @@
////////////////////////
// Mux between line-width data sources
- assign line_data = |fill_data_hit ? hit_data_ic1[LineSize-1:0] : fill_out_data;
+ assign line_data = |fill_data_hit ? hit_data_ic1 : fill_out_data;
assign line_err = |fill_data_hit ? {LINE_BEATS{1'b0}} : fill_out_err;
// Mux the relevant beat of line data, based on the output address
@@ -1059,7 +1072,7 @@
// ECC primitives will need to be changed for different sizes
`ASSERT_INIT(ecc_tag_param_legal, (TAG_SIZE <= 27))
- `ASSERT_INIT(ecc_data_param_legal, (LineSize <= 121))
+ `ASSERT_INIT(ecc_data_param_legal, !ICacheECC || (BusWidth == 32))
// Lookups in the tag ram should always give a known result
`ASSERT_KNOWN(TagHitKnown, lookup_valid_ic1 & tag_hit_ic1)
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_id_stage.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_id_stage.sv
index 53db94a..5c158f7 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_id_stage.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_id_stage.sv
@@ -671,9 +671,12 @@
// Branches always take two cycles in fixed time execution mode, with or without the branch
// target ALU (to avoid a path from the branch decision into the branch target ALU operand
// muxing).
- assign branch_set_raw = (BranchTargetALU && !data_ind_timing_i) ? branch_set_raw_d : branch_set_raw_q;
+ assign branch_set_raw = (BranchTargetALU && !data_ind_timing_i) ? branch_set_raw_d :
+ branch_set_raw_q;
+
// Use the speculative branch signal when BTALU is enabled
- assign branch_set_raw_spec = (BranchTargetALU && !data_ind_timing_i) ? branch_spec : branch_set_raw_q;
+ assign branch_set_raw_spec = (BranchTargetALU && !data_ind_timing_i) ? branch_spec :
+ branch_set_raw_q;
end
// Track whether the current instruction in ID/EX has done a branch or jump set.
@@ -691,10 +694,10 @@
// the _raw signals from the state machine may be asserted for multiple cycles when
// instr_executing_spec is asserted and instr_executing is not asserted. This may occur where
// a memory error is seen or a there are outstanding memory accesses (indicate a load or store is
- // in the WB stage). The branch or jump speculatively begins the fetch but is held back from completing
- // until it is certain the outstanding access hasn't seen a memory error. This logic ensures only
- // the first cycle of a branch or jump set is sent to the controller to prevent needless extra IF
- // flushes and fetches.
+ // in the WB stage). The branch or jump speculatively begins the fetch but is held back from
+ // completing until it is certain the outstanding access hasn't seen a memory error. This logic
+ // ensures only the first cycle of a branch or jump set is sent to the controller to prevent
+ // needless extra IF flushes and fetches.
assign jump_set = jump_set_raw & ~branch_jump_set_done_q;
assign branch_set = branch_set_raw & ~branch_jump_set_done_q;
assign branch_set_spec = branch_set_raw_spec & ~branch_jump_set_done_q;
@@ -716,7 +719,8 @@
end else begin : g_nosec_branch_taken
- // Signal unused without fixed time execution mode - only taken branches will trigger branch_set_raw
+ // Signal unused without fixed time execution mode - only taken branches will trigger
+ // branch_set_raw
assign branch_taken = 1'b1;
end
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_if_stage.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_if_stage.sv
index 33911e4..2c49175 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_if_stage.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_if_stage.sv
@@ -21,76 +21,77 @@
parameter bit PCIncrCheck = 1'b0,
parameter bit BranchPredictor = 1'b0
) (
- input logic clk_i,
- input logic rst_ni,
+ input logic clk_i,
+ input logic rst_ni,
- input logic [31:0] boot_addr_i, // also used for mtvec
- input logic req_i, // instruction request control
+ input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
+ input logic [31:0] boot_addr_i, // also used for mtvec
+ input logic req_i, // instruction request control
// instruction cache interface
- output logic instr_req_o,
- output logic [31:0] instr_addr_o,
- input logic instr_gnt_i,
- input logic instr_rvalid_i,
- input logic [31:0] instr_rdata_i,
- input logic instr_err_i,
- input logic instr_pmp_err_i,
+ output logic instr_req_o,
+ output logic [31:0] instr_addr_o,
+ input logic instr_gnt_i,
+ input logic instr_rvalid_i,
+ input logic [31:0] instr_rdata_i,
+ input logic instr_err_i,
+ input logic instr_pmp_err_i,
// output of ID stage
- output logic instr_valid_id_o, // instr in IF-ID is valid
- output logic instr_new_id_o, // instr in IF-ID is new
- output logic [31:0] instr_rdata_id_o, // instr for ID stage
- output logic [31:0] instr_rdata_alu_id_o, // replicated instr for ID stage
- // to reduce fan-out
- output logic [15:0] instr_rdata_c_id_o, // compressed instr for ID stage
- // (mtval), meaningful only if
- // instr_is_compressed_id_o = 1'b1
- output logic instr_is_compressed_id_o, // compressed decoder thinks this
- // is a compressed instr
- output logic instr_bp_taken_o, // instruction was predicted to be
- // a taken branch
- output logic instr_fetch_err_o, // bus error on fetch
- output logic instr_fetch_err_plus2_o, // bus error misaligned
- output logic illegal_c_insn_id_o, // compressed decoder thinks this
- // is an invalid instr
- output logic dummy_instr_id_o, // Instruction is a dummy
- output logic [31:0] pc_if_o,
- output logic [31:0] pc_id_o,
+ output logic instr_valid_id_o, // instr in IF-ID is valid
+ output logic instr_new_id_o, // instr in IF-ID is new
+ output logic [31:0] instr_rdata_id_o, // instr for ID stage
+ output logic [31:0] instr_rdata_alu_id_o, // replicated instr for ID stage
+ // to reduce fan-out
+ output logic [15:0] instr_rdata_c_id_o, // compressed instr for ID stage
+ // (mtval), meaningful only if
+ // instr_is_compressed_id_o = 1'b1
+ output logic instr_is_compressed_id_o, // compressed decoder thinks this
+ // is a compressed instr
+ output logic instr_bp_taken_o, // instruction was predicted to be
+ // a taken branch
+ output logic instr_fetch_err_o, // bus error on fetch
+ output logic instr_fetch_err_plus2_o, // bus error misaligned
+ output logic illegal_c_insn_id_o, // compressed decoder thinks this
+ // is an invalid instr
+ output logic dummy_instr_id_o, // Instruction is a dummy
+ output logic [31:0] pc_if_o,
+ output logic [31:0] pc_id_o,
// control signals
- input logic instr_valid_clear_i, // clear instr valid bit in IF-ID
- input logic pc_set_i, // set the PC to a new value
- input logic pc_set_spec_i,
- input ibex_pkg::pc_sel_e pc_mux_i, // selector for PC multiplexer
- input logic nt_branch_mispredict_i, // Not-taken branch in ID/EX was
- // mispredicted (predicted taken)
- input ibex_pkg::exc_pc_sel_e exc_pc_mux_i, // selects ISR address
- input ibex_pkg::exc_cause_e exc_cause, // selects ISR address for
- // vectorized interrupt lines
- input logic dummy_instr_en_i,
- input logic [2:0] dummy_instr_mask_i,
- input logic dummy_instr_seed_en_i,
- input logic [31:0] dummy_instr_seed_i,
- input logic icache_enable_i,
- input logic icache_inval_i,
+ input logic instr_valid_clear_i, // clear instr valid bit in IF-ID
+ input logic pc_set_i, // set the PC to a new value
+ input logic pc_set_spec_i,
+ input ibex_pkg::pc_sel_e pc_mux_i, // selector for PC multiplexer
+ input logic nt_branch_mispredict_i, // Not-taken branch in ID/EX was
+ // mispredicted (predicted taken)
+ input ibex_pkg::exc_pc_sel_e exc_pc_mux_i, // selects ISR address
+ input ibex_pkg::exc_cause_e exc_cause, // selects ISR address for
+ // vectorized interrupt lines
+ input logic dummy_instr_en_i,
+ input logic [2:0] dummy_instr_mask_i,
+ input logic dummy_instr_seed_en_i,
+ input logic [31:0] dummy_instr_seed_i,
+ input logic icache_enable_i,
+ input logic icache_inval_i,
// jump and branch target
- input logic [31:0] branch_target_ex_i, // branch/jump target address
+ input logic [31:0] branch_target_ex_i, // branch/jump target address
// CSRs
- input logic [31:0] csr_mepc_i, // PC to restore after handling
- // the interrupt/exception
- input logic [31:0] csr_depc_i, // PC to restore after handling
- // the debug request
- input logic [31:0] csr_mtvec_i, // base PC to jump to on exception
- output logic csr_mtvec_init_o, // tell CS regfile to init mtvec
+ input logic [31:0] csr_mepc_i, // PC to restore after handling
+ // the interrupt/exception
+ input logic [31:0] csr_depc_i, // PC to restore after handling
+ // the debug request
+ input logic [31:0] csr_mtvec_i, // base PC to jump to on exception
+ output logic csr_mtvec_init_o, // tell CS regfile to init mtvec
// pipeline stall
- input logic id_in_ready_i, // ID stage is ready for new instr
+ input logic id_in_ready_i, // ID stage is ready for new instr
// misc signals
- output logic pc_mismatch_alert_o,
- output logic if_busy_o // IF stage is busy fetching instr
+ output logic pc_mismatch_alert_o,
+ output logic if_busy_o // IF stage is busy fetching instr
);
import ibex_pkg::*;
@@ -213,6 +214,7 @@
.instr_err_i ( instr_err_i ),
.instr_pmp_err_i ( instr_pmp_err_i ),
+ .ram_cfg_i ( ram_cfg_i ),
.icache_enable_i ( icache_enable_i ),
.icache_inval_i ( icache_inval_i ),
.busy_o ( prefetch_busy )
@@ -252,8 +254,10 @@
);
// ICache tieoffs
logic unused_icen, unused_icinv;
- assign unused_icen = icache_enable_i;
- assign unused_icinv = icache_inval_i;
+ prim_ram_1p_pkg::ram_1p_cfg_t unused_ram_cfg;
+ assign unused_icen = icache_enable_i;
+ assign unused_icinv = icache_inval_i;
+ assign unused_ram_cfg = ram_cfg_i;
end
assign unused_fetch_addr_n0 = fetch_addr_n[0];
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_multdiv_fast.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_multdiv_fast.sv
index cf69f00..4da8f0d 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_multdiv_fast.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_multdiv_fast.sv
@@ -224,7 +224,7 @@
summand1 = '0;
summand2 = accum;
- summand3 = mult3_res;
+ summand3 = $unsigned(mult3_res);
mult_state_d = MULL;
mult_valid = 1'b1;
diff --git a/hw/vendor/lowrisc_ibex/util/ibex_config.py b/hw/vendor/lowrisc_ibex/util/ibex_config.py
index abe2d65..484aae2 100755
--- a/hw/vendor/lowrisc_ibex/util/ibex_config.py
+++ b/hw/vendor/lowrisc_ibex/util/ibex_config.py
@@ -214,6 +214,40 @@
return os.environ.get('IBEX_CONFIG_FILE', _DEFAULT_CONFIG_FILE)
+def parse_config(config_name, config_filename):
+ """Parses the selected config file and returns selected config information.
+
+ Arguments:
+
+ config_name: Name of the chosen Ibex core config
+
+ config_filename: Name of the configuration filename to be parsed
+
+ Returns: the chosen Ibex config as a YAML object.
+
+ Raises a ConfigException if there are any error while parsing the YAML.
+
+ Raises a FileNotFoundError if there are errors opening the chosen config file.
+ """
+ try:
+ config_file = open(config_filename)
+ config_dicts = get_config_dicts(config_file)
+
+ if config_name not in config_dicts:
+ print('ERROR: configuration {!r} not found in {!r}.'.format(
+ config_name, config_filename), file=sys.stderr)
+ sys.exit(1)
+ return config_dicts[config_name]
+ except ConfigException as ce:
+ print('ERROR: failure to process configuration from {!r} {!r}.'.format(
+ config_filename, ce), file=sys.stderr)
+ sys.exit(1)
+ except FileNotFoundError:
+ print('ERROR: could not find configuration file {!r}.'.format(
+ config_filename), file=sys.stderr)
+ sys.exit(1)
+
+
def main():
outputters = [
FusesocOpts(),
@@ -270,32 +304,8 @@
print('ERROR: No output format specified.')
sys.exit(1)
- try:
- config_file = open(args.config_filename)
- config_dicts = get_config_dicts(config_file)
-
- if args.config_name not in config_dicts:
- print('ERROR: configuration',
- args.config_name,
- 'not found in',
- args.config_filename,
- file=sys.stderr)
-
- sys.exit(1)
-
- print(args.output_fn(config_dicts[args.config_name], args))
- except ConfigException as ce:
- print('ERROR: failure to process configuration from',
- args.config_filename,
- ce,
- file=sys.stderr)
- sys.exit(1)
- except FileNotFoundError:
- print('ERROR: could not find configuration file',
- args.config_filename,
- file=sys.stderr)
- sys.exit(1)
-
+ parsed_ibex_config = parse_config(args.config_name, args.config_filename)
+ print(args.output_fn(parsed_ibex_config, args))
if __name__ == "__main__":
main()
