[usbdev] Wire up integrity alert Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/hw/ip/usbdev/data/usbdev.hjson b/hw/ip/usbdev/data/usbdev.hjson index 5b5a5fd..db9c22b 100644 --- a/hw/ip/usbdev/data/usbdev.hjson +++ b/hw/ip/usbdev/data/usbdev.hjson
@@ -180,6 +180,13 @@ ''' } ] + alert_list: [ + { name: "fatal_fault", + desc: ''' + This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. + ''' + } + ], regwidth: "32", registers: [ { name: "usbctrl",
diff --git a/hw/ip/usbdev/dv/env/usbdev_env_cfg.sv b/hw/ip/usbdev/dv/env/usbdev_env_cfg.sv index 1c07fd9..0083ab8 100644 --- a/hw/ip/usbdev/dv/env/usbdev_env_cfg.sv +++ b/hw/ip/usbdev/dv/env/usbdev_env_cfg.sv
@@ -26,6 +26,7 @@ `uvm_object_new virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1); + list_of_alerts = usbdev_env_pkg::LIST_OF_ALERTS; super.initialize(csr_base_addr); // create usb20 agent config obj m_usb20_agent_cfg = usb20_agent_cfg::type_id::create("m_usb20_agent_cfg");
diff --git a/hw/ip/usbdev/dv/env/usbdev_env_pkg.sv b/hw/ip/usbdev/dv/env/usbdev_env_pkg.sv index 86ebe83..fa3099c 100644 --- a/hw/ip/usbdev/dv/env/usbdev_env_pkg.sv +++ b/hw/ip/usbdev/dv/env/usbdev_env_pkg.sv
@@ -20,6 +20,10 @@ // parameters + // alerts + parameter uint NUM_ALERTS = 1; + parameter string LIST_OF_ALERTS[] = {"fatal_fault"}; + // types typedef enum { IntrPktReceived = 0,
diff --git a/hw/ip/usbdev/dv/tb/tb.sv b/hw/ip/usbdev/dv/tb/tb.sv index 681cd1f..6794280 100644 --- a/hw/ip/usbdev/dv/tb/tb.sv +++ b/hw/ip/usbdev/dv/tb/tb.sv
@@ -43,6 +43,8 @@ tl_if tl_if(.clk(clk), .rst_n(rst_n)); usb20_if usb20_if(); + `DV_ALERT_IF_CONNECT + // dut usbdev dut ( .clk_i (clk ), @@ -55,6 +57,9 @@ .tl_i (tl_if.h2d ), .tl_o (tl_if.d2h ), + .alert_rx_i (alert_rx ), + .alert_tx_o (alert_tx ), + // pinmux wakeup interface .usb_state_debug_i ('0),
diff --git a/hw/ip/usbdev/rtl/usbdev.sv b/hw/ip/usbdev/rtl/usbdev.sv index 2096fe3..b5edc1d 100644 --- a/hw/ip/usbdev/rtl/usbdev.sv +++ b/hw/ip/usbdev/rtl/usbdev.sv
@@ -7,7 +7,12 @@ // -module usbdev import usbdev_pkg::*; ( +module usbdev + import usbdev_pkg::*; + import usbdev_reg_pkg::*; +#( + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}} +) ( input logic clk_i, input logic rst_ni, input logic clk_aon_i, @@ -19,6 +24,10 @@ input tlul_pkg::tl_h2d_t tl_i, output tlul_pkg::tl_d2h_t tl_o, + // Alerts + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + // Data inputs input logic cio_d_i, // differential input logic cio_dp_i, // single-ended, can be used in differential mode to detect SE0 @@ -724,6 +733,8 @@ .cfg_i (ram_cfg_i) ); + logic [NumAlerts-1:0] alert_test, alerts; + // Register module usbdev_reg_top u_reg ( .clk_i, @@ -737,10 +748,33 @@ .reg2hw, .hw2reg, - .intg_err_o(), + .intg_err_o (alerts[0]), .devmode_i (1'b1) ); + // Alerts + assign alert_test = { + reg2hw.alert_test.q & + reg2hw.alert_test.qe + }; + + for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[i]), + .IsFatal(i) + ) u_prim_alert_sender ( + .clk_i, + .rst_ni, + .alert_test_i ( alert_test[i] ), + .alert_req_i ( alerts[0] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[i] ), + .alert_tx_o ( alert_tx_o[i] ) + ); + end + + // Interrupts prim_intr_hw #(.Width(1)) intr_hw_pkt_received ( .clk_i, .rst_ni, @@ -1150,6 +1184,8 @@ `ASSERT_KNOWN(USBSuspendKnown_A, usb_suspend_o) `ASSERT_KNOWN(USBRefValKnown_A, usb_ref_val_o, clk_usb_48mhz_i, !rst_usb_48mhz_ni) `ASSERT_KNOWN(USBRefPulseKnown_A, usb_ref_pulse_o, clk_usb_48mhz_i, !rst_usb_48mhz_ni) + // Assert Known for alerts + `ASSERT_KNOWN(AlertsKnown_A, alert_tx_o) //Interrupt signals `ASSERT_KNOWN(USBIntrPktRcvdKnown_A, intr_pkt_received_o) `ASSERT_KNOWN(USBIntrPktSentKnown_A, intr_pkt_sent_o)
diff --git a/hw/ip/usbdev/rtl/usbdev_reg_pkg.sv b/hw/ip/usbdev/rtl/usbdev_reg_pkg.sv index 069e435..6445b8c 100644 --- a/hw/ip/usbdev/rtl/usbdev_reg_pkg.sv +++ b/hw/ip/usbdev/rtl/usbdev_reg_pkg.sv
@@ -8,6 +8,7 @@ // Param list parameter int NEndpoints = 12; + parameter int NumAlerts = 1; // Address widths within the block parameter int BlockAw = 12; @@ -196,6 +197,11 @@ } usbdev_reg2hw_intr_test_reg_t; typedef struct packed { + logic q; + logic qe; + } usbdev_reg2hw_alert_test_reg_t; + + typedef struct packed { struct packed { logic q; } enable; @@ -514,9 +520,10 @@ // Register -> HW type typedef struct packed { - usbdev_reg2hw_intr_state_reg_t intr_state; // [362:346] - usbdev_reg2hw_intr_enable_reg_t intr_enable; // [345:329] - usbdev_reg2hw_intr_test_reg_t intr_test; // [328:295] + usbdev_reg2hw_intr_state_reg_t intr_state; // [364:348] + usbdev_reg2hw_intr_enable_reg_t intr_enable; // [347:331] + usbdev_reg2hw_intr_test_reg_t intr_test; // [330:297] + usbdev_reg2hw_alert_test_reg_t alert_test; // [296:295] usbdev_reg2hw_usbctrl_reg_t usbctrl; // [294:287] usbdev_reg2hw_avbuffer_reg_t avbuffer; // [286:281] usbdev_reg2hw_rxfifo_reg_t rxfifo; // [280:260] @@ -548,33 +555,34 @@ parameter logic [BlockAw-1:0] USBDEV_INTR_STATE_OFFSET = 12'h 0; parameter logic [BlockAw-1:0] USBDEV_INTR_ENABLE_OFFSET = 12'h 4; parameter logic [BlockAw-1:0] USBDEV_INTR_TEST_OFFSET = 12'h 8; - parameter logic [BlockAw-1:0] USBDEV_USBCTRL_OFFSET = 12'h c; - parameter logic [BlockAw-1:0] USBDEV_USBSTAT_OFFSET = 12'h 10; - parameter logic [BlockAw-1:0] USBDEV_AVBUFFER_OFFSET = 12'h 14; - parameter logic [BlockAw-1:0] USBDEV_RXFIFO_OFFSET = 12'h 18; - parameter logic [BlockAw-1:0] USBDEV_RXENABLE_SETUP_OFFSET = 12'h 1c; - parameter logic [BlockAw-1:0] USBDEV_RXENABLE_OUT_OFFSET = 12'h 20; - parameter logic [BlockAw-1:0] USBDEV_IN_SENT_OFFSET = 12'h 24; - parameter logic [BlockAw-1:0] USBDEV_STALL_OFFSET = 12'h 28; - parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_0_OFFSET = 12'h 2c; - parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_1_OFFSET = 12'h 30; - parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_2_OFFSET = 12'h 34; - parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_3_OFFSET = 12'h 38; - parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_4_OFFSET = 12'h 3c; - parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_5_OFFSET = 12'h 40; - parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_6_OFFSET = 12'h 44; - parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_7_OFFSET = 12'h 48; - parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_8_OFFSET = 12'h 4c; - parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_9_OFFSET = 12'h 50; - parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_10_OFFSET = 12'h 54; - parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_11_OFFSET = 12'h 58; - parameter logic [BlockAw-1:0] USBDEV_ISO_OFFSET = 12'h 5c; - parameter logic [BlockAw-1:0] USBDEV_DATA_TOGGLE_CLEAR_OFFSET = 12'h 60; - parameter logic [BlockAw-1:0] USBDEV_PHY_PINS_SENSE_OFFSET = 12'h 64; - parameter logic [BlockAw-1:0] USBDEV_PHY_PINS_DRIVE_OFFSET = 12'h 68; - parameter logic [BlockAw-1:0] USBDEV_PHY_CONFIG_OFFSET = 12'h 6c; - parameter logic [BlockAw-1:0] USBDEV_WAKE_CONFIG_OFFSET = 12'h 70; - parameter logic [BlockAw-1:0] USBDEV_WAKE_DEBUG_OFFSET = 12'h 74; + parameter logic [BlockAw-1:0] USBDEV_ALERT_TEST_OFFSET = 12'h c; + parameter logic [BlockAw-1:0] USBDEV_USBCTRL_OFFSET = 12'h 10; + parameter logic [BlockAw-1:0] USBDEV_USBSTAT_OFFSET = 12'h 14; + parameter logic [BlockAw-1:0] USBDEV_AVBUFFER_OFFSET = 12'h 18; + parameter logic [BlockAw-1:0] USBDEV_RXFIFO_OFFSET = 12'h 1c; + parameter logic [BlockAw-1:0] USBDEV_RXENABLE_SETUP_OFFSET = 12'h 20; + parameter logic [BlockAw-1:0] USBDEV_RXENABLE_OUT_OFFSET = 12'h 24; + parameter logic [BlockAw-1:0] USBDEV_IN_SENT_OFFSET = 12'h 28; + parameter logic [BlockAw-1:0] USBDEV_STALL_OFFSET = 12'h 2c; + parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_0_OFFSET = 12'h 30; + parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_1_OFFSET = 12'h 34; + parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_2_OFFSET = 12'h 38; + parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_3_OFFSET = 12'h 3c; + parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_4_OFFSET = 12'h 40; + parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_5_OFFSET = 12'h 44; + parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_6_OFFSET = 12'h 48; + parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_7_OFFSET = 12'h 4c; + parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_8_OFFSET = 12'h 50; + parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_9_OFFSET = 12'h 54; + parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_10_OFFSET = 12'h 58; + parameter logic [BlockAw-1:0] USBDEV_CONFIGIN_11_OFFSET = 12'h 5c; + parameter logic [BlockAw-1:0] USBDEV_ISO_OFFSET = 12'h 60; + parameter logic [BlockAw-1:0] USBDEV_DATA_TOGGLE_CLEAR_OFFSET = 12'h 64; + parameter logic [BlockAw-1:0] USBDEV_PHY_PINS_SENSE_OFFSET = 12'h 68; + parameter logic [BlockAw-1:0] USBDEV_PHY_PINS_DRIVE_OFFSET = 12'h 6c; + parameter logic [BlockAw-1:0] USBDEV_PHY_CONFIG_OFFSET = 12'h 70; + parameter logic [BlockAw-1:0] USBDEV_WAKE_CONFIG_OFFSET = 12'h 74; + parameter logic [BlockAw-1:0] USBDEV_WAKE_DEBUG_OFFSET = 12'h 78; // Reset values for hwext registers and their fields parameter logic [16:0] USBDEV_INTR_TEST_RESVAL = 17'h 0; @@ -595,6 +603,8 @@ parameter logic [0:0] USBDEV_INTR_TEST_FRAME_RESVAL = 1'h 0; parameter logic [0:0] USBDEV_INTR_TEST_CONNECTED_RESVAL = 1'h 0; parameter logic [0:0] USBDEV_INTR_TEST_LINK_OUT_ERR_RESVAL = 1'h 0; + parameter logic [0:0] USBDEV_ALERT_TEST_RESVAL = 1'h 0; + parameter logic [0:0] USBDEV_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0; parameter logic [31:0] USBDEV_USBSTAT_RESVAL = 32'h 80000000; parameter logic [0:0] USBDEV_USBSTAT_RX_EMPTY_RESVAL = 1'h 1; parameter logic [23:0] USBDEV_RXFIFO_RESVAL = 24'h 0; @@ -609,6 +619,7 @@ USBDEV_INTR_STATE, USBDEV_INTR_ENABLE, USBDEV_INTR_TEST, + USBDEV_ALERT_TEST, USBDEV_USBCTRL, USBDEV_USBSTAT, USBDEV_AVBUFFER, @@ -639,37 +650,38 @@ } usbdev_id_e; // Register width information to check illegal writes - parameter logic [3:0] USBDEV_PERMIT [30] = '{ + parameter logic [3:0] USBDEV_PERMIT [31] = '{ 4'b 0111, // index[ 0] USBDEV_INTR_STATE 4'b 0111, // index[ 1] USBDEV_INTR_ENABLE 4'b 0111, // index[ 2] USBDEV_INTR_TEST - 4'b 0111, // index[ 3] USBDEV_USBCTRL - 4'b 1111, // index[ 4] USBDEV_USBSTAT - 4'b 0001, // index[ 5] USBDEV_AVBUFFER - 4'b 0111, // index[ 6] USBDEV_RXFIFO - 4'b 0011, // index[ 7] USBDEV_RXENABLE_SETUP - 4'b 0011, // index[ 8] USBDEV_RXENABLE_OUT - 4'b 0011, // index[ 9] USBDEV_IN_SENT - 4'b 0011, // index[10] USBDEV_STALL - 4'b 1111, // index[11] USBDEV_CONFIGIN_0 - 4'b 1111, // index[12] USBDEV_CONFIGIN_1 - 4'b 1111, // index[13] USBDEV_CONFIGIN_2 - 4'b 1111, // index[14] USBDEV_CONFIGIN_3 - 4'b 1111, // index[15] USBDEV_CONFIGIN_4 - 4'b 1111, // index[16] USBDEV_CONFIGIN_5 - 4'b 1111, // index[17] USBDEV_CONFIGIN_6 - 4'b 1111, // index[18] USBDEV_CONFIGIN_7 - 4'b 1111, // index[19] USBDEV_CONFIGIN_8 - 4'b 1111, // index[20] USBDEV_CONFIGIN_9 - 4'b 1111, // index[21] USBDEV_CONFIGIN_10 - 4'b 1111, // index[22] USBDEV_CONFIGIN_11 - 4'b 0011, // index[23] USBDEV_ISO - 4'b 0011, // index[24] USBDEV_DATA_TOGGLE_CLEAR - 4'b 0111, // index[25] USBDEV_PHY_PINS_SENSE - 4'b 0111, // index[26] USBDEV_PHY_PINS_DRIVE - 4'b 0001, // index[27] USBDEV_PHY_CONFIG - 4'b 0001, // index[28] USBDEV_WAKE_CONFIG - 4'b 0001 // index[29] USBDEV_WAKE_DEBUG + 4'b 0001, // index[ 3] USBDEV_ALERT_TEST + 4'b 0111, // index[ 4] USBDEV_USBCTRL + 4'b 1111, // index[ 5] USBDEV_USBSTAT + 4'b 0001, // index[ 6] USBDEV_AVBUFFER + 4'b 0111, // index[ 7] USBDEV_RXFIFO + 4'b 0011, // index[ 8] USBDEV_RXENABLE_SETUP + 4'b 0011, // index[ 9] USBDEV_RXENABLE_OUT + 4'b 0011, // index[10] USBDEV_IN_SENT + 4'b 0011, // index[11] USBDEV_STALL + 4'b 1111, // index[12] USBDEV_CONFIGIN_0 + 4'b 1111, // index[13] USBDEV_CONFIGIN_1 + 4'b 1111, // index[14] USBDEV_CONFIGIN_2 + 4'b 1111, // index[15] USBDEV_CONFIGIN_3 + 4'b 1111, // index[16] USBDEV_CONFIGIN_4 + 4'b 1111, // index[17] USBDEV_CONFIGIN_5 + 4'b 1111, // index[18] USBDEV_CONFIGIN_6 + 4'b 1111, // index[19] USBDEV_CONFIGIN_7 + 4'b 1111, // index[20] USBDEV_CONFIGIN_8 + 4'b 1111, // index[21] USBDEV_CONFIGIN_9 + 4'b 1111, // index[22] USBDEV_CONFIGIN_10 + 4'b 1111, // index[23] USBDEV_CONFIGIN_11 + 4'b 0011, // index[24] USBDEV_ISO + 4'b 0011, // index[25] USBDEV_DATA_TOGGLE_CLEAR + 4'b 0111, // index[26] USBDEV_PHY_PINS_SENSE + 4'b 0111, // index[27] USBDEV_PHY_PINS_DRIVE + 4'b 0001, // index[28] USBDEV_PHY_CONFIG + 4'b 0001, // index[29] USBDEV_WAKE_CONFIG + 4'b 0001 // index[30] USBDEV_WAKE_DEBUG }; endpackage
diff --git a/hw/ip/usbdev/rtl/usbdev_reg_top.sv b/hw/ip/usbdev/rtl/usbdev_reg_top.sv index 4a9e469..c4e5b07 100644 --- a/hw/ip/usbdev/rtl/usbdev_reg_top.sv +++ b/hw/ip/usbdev/rtl/usbdev_reg_top.sv
@@ -240,6 +240,8 @@ logic intr_test_frame_wd; logic intr_test_connected_wd; logic intr_test_link_out_err_wd; + logic alert_test_we; + logic alert_test_wd; logic usbctrl_we; logic usbctrl_enable_qs; logic usbctrl_enable_wd; @@ -1709,6 +1711,22 @@ ); + // R[alert_test]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_alert_test ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_wd), + .d ('0), + .qre (), + .qe (reg2hw.alert_test.qe), + .q (reg2hw.alert_test.q), + .qs () + ); + + // R[usbctrl]: V(False) // F[enable]: 0:0 @@ -5869,39 +5887,40 @@ - logic [29:0] addr_hit; + logic [30:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == USBDEV_INTR_STATE_OFFSET); addr_hit[ 1] = (reg_addr == USBDEV_INTR_ENABLE_OFFSET); addr_hit[ 2] = (reg_addr == USBDEV_INTR_TEST_OFFSET); - addr_hit[ 3] = (reg_addr == USBDEV_USBCTRL_OFFSET); - addr_hit[ 4] = (reg_addr == USBDEV_USBSTAT_OFFSET); - addr_hit[ 5] = (reg_addr == USBDEV_AVBUFFER_OFFSET); - addr_hit[ 6] = (reg_addr == USBDEV_RXFIFO_OFFSET); - addr_hit[ 7] = (reg_addr == USBDEV_RXENABLE_SETUP_OFFSET); - addr_hit[ 8] = (reg_addr == USBDEV_RXENABLE_OUT_OFFSET); - addr_hit[ 9] = (reg_addr == USBDEV_IN_SENT_OFFSET); - addr_hit[10] = (reg_addr == USBDEV_STALL_OFFSET); - addr_hit[11] = (reg_addr == USBDEV_CONFIGIN_0_OFFSET); - addr_hit[12] = (reg_addr == USBDEV_CONFIGIN_1_OFFSET); - addr_hit[13] = (reg_addr == USBDEV_CONFIGIN_2_OFFSET); - addr_hit[14] = (reg_addr == USBDEV_CONFIGIN_3_OFFSET); - addr_hit[15] = (reg_addr == USBDEV_CONFIGIN_4_OFFSET); - addr_hit[16] = (reg_addr == USBDEV_CONFIGIN_5_OFFSET); - addr_hit[17] = (reg_addr == USBDEV_CONFIGIN_6_OFFSET); - addr_hit[18] = (reg_addr == USBDEV_CONFIGIN_7_OFFSET); - addr_hit[19] = (reg_addr == USBDEV_CONFIGIN_8_OFFSET); - addr_hit[20] = (reg_addr == USBDEV_CONFIGIN_9_OFFSET); - addr_hit[21] = (reg_addr == USBDEV_CONFIGIN_10_OFFSET); - addr_hit[22] = (reg_addr == USBDEV_CONFIGIN_11_OFFSET); - addr_hit[23] = (reg_addr == USBDEV_ISO_OFFSET); - addr_hit[24] = (reg_addr == USBDEV_DATA_TOGGLE_CLEAR_OFFSET); - addr_hit[25] = (reg_addr == USBDEV_PHY_PINS_SENSE_OFFSET); - addr_hit[26] = (reg_addr == USBDEV_PHY_PINS_DRIVE_OFFSET); - addr_hit[27] = (reg_addr == USBDEV_PHY_CONFIG_OFFSET); - addr_hit[28] = (reg_addr == USBDEV_WAKE_CONFIG_OFFSET); - addr_hit[29] = (reg_addr == USBDEV_WAKE_DEBUG_OFFSET); + addr_hit[ 3] = (reg_addr == USBDEV_ALERT_TEST_OFFSET); + addr_hit[ 4] = (reg_addr == USBDEV_USBCTRL_OFFSET); + addr_hit[ 5] = (reg_addr == USBDEV_USBSTAT_OFFSET); + addr_hit[ 6] = (reg_addr == USBDEV_AVBUFFER_OFFSET); + addr_hit[ 7] = (reg_addr == USBDEV_RXFIFO_OFFSET); + addr_hit[ 8] = (reg_addr == USBDEV_RXENABLE_SETUP_OFFSET); + addr_hit[ 9] = (reg_addr == USBDEV_RXENABLE_OUT_OFFSET); + addr_hit[10] = (reg_addr == USBDEV_IN_SENT_OFFSET); + addr_hit[11] = (reg_addr == USBDEV_STALL_OFFSET); + addr_hit[12] = (reg_addr == USBDEV_CONFIGIN_0_OFFSET); + addr_hit[13] = (reg_addr == USBDEV_CONFIGIN_1_OFFSET); + addr_hit[14] = (reg_addr == USBDEV_CONFIGIN_2_OFFSET); + addr_hit[15] = (reg_addr == USBDEV_CONFIGIN_3_OFFSET); + addr_hit[16] = (reg_addr == USBDEV_CONFIGIN_4_OFFSET); + addr_hit[17] = (reg_addr == USBDEV_CONFIGIN_5_OFFSET); + addr_hit[18] = (reg_addr == USBDEV_CONFIGIN_6_OFFSET); + addr_hit[19] = (reg_addr == USBDEV_CONFIGIN_7_OFFSET); + addr_hit[20] = (reg_addr == USBDEV_CONFIGIN_8_OFFSET); + addr_hit[21] = (reg_addr == USBDEV_CONFIGIN_9_OFFSET); + addr_hit[22] = (reg_addr == USBDEV_CONFIGIN_10_OFFSET); + addr_hit[23] = (reg_addr == USBDEV_CONFIGIN_11_OFFSET); + addr_hit[24] = (reg_addr == USBDEV_ISO_OFFSET); + addr_hit[25] = (reg_addr == USBDEV_DATA_TOGGLE_CLEAR_OFFSET); + addr_hit[26] = (reg_addr == USBDEV_PHY_PINS_SENSE_OFFSET); + addr_hit[27] = (reg_addr == USBDEV_PHY_PINS_DRIVE_OFFSET); + addr_hit[28] = (reg_addr == USBDEV_PHY_CONFIG_OFFSET); + addr_hit[29] = (reg_addr == USBDEV_WAKE_CONFIG_OFFSET); + addr_hit[30] = (reg_addr == USBDEV_WAKE_DEBUG_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -5938,7 +5957,8 @@ (addr_hit[26] & (|(USBDEV_PERMIT[26] & ~reg_be))) | (addr_hit[27] & (|(USBDEV_PERMIT[27] & ~reg_be))) | (addr_hit[28] & (|(USBDEV_PERMIT[28] & ~reg_be))) | - (addr_hit[29] & (|(USBDEV_PERMIT[29] & ~reg_be))))); + (addr_hit[29] & (|(USBDEV_PERMIT[29] & ~reg_be))) | + (addr_hit[30] & (|(USBDEV_PERMIT[30] & ~reg_be))))); end assign intr_state_we = addr_hit[0] & reg_we & !reg_error; @@ -6045,17 +6065,20 @@ assign intr_test_connected_wd = reg_wdata[15]; assign intr_test_link_out_err_wd = reg_wdata[16]; - assign usbctrl_we = addr_hit[3] & reg_we & !reg_error; + assign alert_test_we = addr_hit[3] & reg_we & !reg_error; + + assign alert_test_wd = reg_wdata[0]; + assign usbctrl_we = addr_hit[4] & reg_we & !reg_error; assign usbctrl_enable_wd = reg_wdata[0]; assign usbctrl_device_address_wd = reg_wdata[22:16]; - assign usbstat_re = addr_hit[4] & reg_re & !reg_error; - assign avbuffer_we = addr_hit[5] & reg_we & !reg_error; + assign usbstat_re = addr_hit[5] & reg_re & !reg_error; + assign avbuffer_we = addr_hit[6] & reg_we & !reg_error; assign avbuffer_wd = reg_wdata[4:0]; - assign rxfifo_re = addr_hit[6] & reg_re & !reg_error; - assign rxenable_setup_we = addr_hit[7] & reg_we & !reg_error; + assign rxfifo_re = addr_hit[7] & reg_re & !reg_error; + assign rxenable_setup_we = addr_hit[8] & reg_we & !reg_error; assign rxenable_setup_setup_0_wd = reg_wdata[0]; @@ -6080,7 +6103,7 @@ assign rxenable_setup_setup_10_wd = reg_wdata[10]; assign rxenable_setup_setup_11_wd = reg_wdata[11]; - assign rxenable_out_we = addr_hit[8] & reg_we & !reg_error; + assign rxenable_out_we = addr_hit[9] & reg_we & !reg_error; assign rxenable_out_out_0_wd = reg_wdata[0]; @@ -6105,7 +6128,7 @@ assign rxenable_out_out_10_wd = reg_wdata[10]; assign rxenable_out_out_11_wd = reg_wdata[11]; - assign in_sent_we = addr_hit[9] & reg_we & !reg_error; + assign in_sent_we = addr_hit[10] & reg_we & !reg_error; assign in_sent_sent_0_wd = reg_wdata[0]; @@ -6130,7 +6153,7 @@ assign in_sent_sent_10_wd = reg_wdata[10]; assign in_sent_sent_11_wd = reg_wdata[11]; - assign stall_we = addr_hit[10] & reg_we & !reg_error; + assign stall_we = addr_hit[11] & reg_we & !reg_error; assign stall_stall_0_wd = reg_wdata[0]; @@ -6155,7 +6178,7 @@ assign stall_stall_10_wd = reg_wdata[10]; assign stall_stall_11_wd = reg_wdata[11]; - assign configin_0_we = addr_hit[11] & reg_we & !reg_error; + assign configin_0_we = addr_hit[12] & reg_we & !reg_error; assign configin_0_buffer_0_wd = reg_wdata[4:0]; @@ -6164,7 +6187,7 @@ assign configin_0_pend_0_wd = reg_wdata[30]; assign configin_0_rdy_0_wd = reg_wdata[31]; - assign configin_1_we = addr_hit[12] & reg_we & !reg_error; + assign configin_1_we = addr_hit[13] & reg_we & !reg_error; assign configin_1_buffer_1_wd = reg_wdata[4:0]; @@ -6173,7 +6196,7 @@ assign configin_1_pend_1_wd = reg_wdata[30]; assign configin_1_rdy_1_wd = reg_wdata[31]; - assign configin_2_we = addr_hit[13] & reg_we & !reg_error; + assign configin_2_we = addr_hit[14] & reg_we & !reg_error; assign configin_2_buffer_2_wd = reg_wdata[4:0]; @@ -6182,7 +6205,7 @@ assign configin_2_pend_2_wd = reg_wdata[30]; assign configin_2_rdy_2_wd = reg_wdata[31]; - assign configin_3_we = addr_hit[14] & reg_we & !reg_error; + assign configin_3_we = addr_hit[15] & reg_we & !reg_error; assign configin_3_buffer_3_wd = reg_wdata[4:0]; @@ -6191,7 +6214,7 @@ assign configin_3_pend_3_wd = reg_wdata[30]; assign configin_3_rdy_3_wd = reg_wdata[31]; - assign configin_4_we = addr_hit[15] & reg_we & !reg_error; + assign configin_4_we = addr_hit[16] & reg_we & !reg_error; assign configin_4_buffer_4_wd = reg_wdata[4:0]; @@ -6200,7 +6223,7 @@ assign configin_4_pend_4_wd = reg_wdata[30]; assign configin_4_rdy_4_wd = reg_wdata[31]; - assign configin_5_we = addr_hit[16] & reg_we & !reg_error; + assign configin_5_we = addr_hit[17] & reg_we & !reg_error; assign configin_5_buffer_5_wd = reg_wdata[4:0]; @@ -6209,7 +6232,7 @@ assign configin_5_pend_5_wd = reg_wdata[30]; assign configin_5_rdy_5_wd = reg_wdata[31]; - assign configin_6_we = addr_hit[17] & reg_we & !reg_error; + assign configin_6_we = addr_hit[18] & reg_we & !reg_error; assign configin_6_buffer_6_wd = reg_wdata[4:0]; @@ -6218,7 +6241,7 @@ assign configin_6_pend_6_wd = reg_wdata[30]; assign configin_6_rdy_6_wd = reg_wdata[31]; - assign configin_7_we = addr_hit[18] & reg_we & !reg_error; + assign configin_7_we = addr_hit[19] & reg_we & !reg_error; assign configin_7_buffer_7_wd = reg_wdata[4:0]; @@ -6227,7 +6250,7 @@ assign configin_7_pend_7_wd = reg_wdata[30]; assign configin_7_rdy_7_wd = reg_wdata[31]; - assign configin_8_we = addr_hit[19] & reg_we & !reg_error; + assign configin_8_we = addr_hit[20] & reg_we & !reg_error; assign configin_8_buffer_8_wd = reg_wdata[4:0]; @@ -6236,7 +6259,7 @@ assign configin_8_pend_8_wd = reg_wdata[30]; assign configin_8_rdy_8_wd = reg_wdata[31]; - assign configin_9_we = addr_hit[20] & reg_we & !reg_error; + assign configin_9_we = addr_hit[21] & reg_we & !reg_error; assign configin_9_buffer_9_wd = reg_wdata[4:0]; @@ -6245,7 +6268,7 @@ assign configin_9_pend_9_wd = reg_wdata[30]; assign configin_9_rdy_9_wd = reg_wdata[31]; - assign configin_10_we = addr_hit[21] & reg_we & !reg_error; + assign configin_10_we = addr_hit[22] & reg_we & !reg_error; assign configin_10_buffer_10_wd = reg_wdata[4:0]; @@ -6254,7 +6277,7 @@ assign configin_10_pend_10_wd = reg_wdata[30]; assign configin_10_rdy_10_wd = reg_wdata[31]; - assign configin_11_we = addr_hit[22] & reg_we & !reg_error; + assign configin_11_we = addr_hit[23] & reg_we & !reg_error; assign configin_11_buffer_11_wd = reg_wdata[4:0]; @@ -6263,7 +6286,7 @@ assign configin_11_pend_11_wd = reg_wdata[30]; assign configin_11_rdy_11_wd = reg_wdata[31]; - assign iso_we = addr_hit[23] & reg_we & !reg_error; + assign iso_we = addr_hit[24] & reg_we & !reg_error; assign iso_iso_0_wd = reg_wdata[0]; @@ -6288,7 +6311,7 @@ assign iso_iso_10_wd = reg_wdata[10]; assign iso_iso_11_wd = reg_wdata[11]; - assign data_toggle_clear_we = addr_hit[24] & reg_we & !reg_error; + assign data_toggle_clear_we = addr_hit[25] & reg_we & !reg_error; assign data_toggle_clear_clear_0_wd = reg_wdata[0]; @@ -6313,8 +6336,8 @@ assign data_toggle_clear_clear_10_wd = reg_wdata[10]; assign data_toggle_clear_clear_11_wd = reg_wdata[11]; - assign phy_pins_sense_re = addr_hit[25] & reg_re & !reg_error; - assign phy_pins_drive_we = addr_hit[26] & reg_we & !reg_error; + assign phy_pins_sense_re = addr_hit[26] & reg_re & !reg_error; + assign phy_pins_drive_we = addr_hit[27] & reg_we & !reg_error; assign phy_pins_drive_dp_o_wd = reg_wdata[0]; @@ -6335,7 +6358,7 @@ assign phy_pins_drive_suspend_o_wd = reg_wdata[8]; assign phy_pins_drive_en_wd = reg_wdata[16]; - assign phy_config_we = addr_hit[27] & reg_we & !reg_error; + assign phy_config_we = addr_hit[28] & reg_we & !reg_error; assign phy_config_rx_differential_mode_wd = reg_wdata[0]; @@ -6352,7 +6375,7 @@ assign phy_config_usb_ref_disable_wd = reg_wdata[6]; assign phy_config_tx_osc_test_mode_wd = reg_wdata[7]; - assign wake_config_we = addr_hit[28] & reg_we & !reg_error; + assign wake_config_we = addr_hit[29] & reg_we & !reg_error; assign wake_config_wake_en_wd = reg_wdata[0]; @@ -6423,11 +6446,15 @@ end addr_hit[3]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[4]: begin reg_rdata_next[0] = usbctrl_enable_qs; reg_rdata_next[22:16] = usbctrl_device_address_qs; end - addr_hit[4]: begin + addr_hit[5]: begin reg_rdata_next[10:0] = usbstat_frame_qs; reg_rdata_next[11] = usbstat_host_lost_qs; reg_rdata_next[14:12] = usbstat_link_state_qs; @@ -6438,18 +6465,18 @@ reg_rdata_next[31] = usbstat_rx_empty_qs; end - addr_hit[5]: begin + addr_hit[6]: begin reg_rdata_next[4:0] = '0; end - addr_hit[6]: begin + addr_hit[7]: begin reg_rdata_next[4:0] = rxfifo_buffer_qs; reg_rdata_next[14:8] = rxfifo_size_qs; reg_rdata_next[19] = rxfifo_setup_qs; reg_rdata_next[23:20] = rxfifo_ep_qs; end - addr_hit[7]: begin + addr_hit[8]: begin reg_rdata_next[0] = rxenable_setup_setup_0_qs; reg_rdata_next[1] = rxenable_setup_setup_1_qs; reg_rdata_next[2] = rxenable_setup_setup_2_qs; @@ -6464,7 +6491,7 @@ reg_rdata_next[11] = rxenable_setup_setup_11_qs; end - addr_hit[8]: begin + addr_hit[9]: begin reg_rdata_next[0] = rxenable_out_out_0_qs; reg_rdata_next[1] = rxenable_out_out_1_qs; reg_rdata_next[2] = rxenable_out_out_2_qs; @@ -6479,7 +6506,7 @@ reg_rdata_next[11] = rxenable_out_out_11_qs; end - addr_hit[9]: begin + addr_hit[10]: begin reg_rdata_next[0] = in_sent_sent_0_qs; reg_rdata_next[1] = in_sent_sent_1_qs; reg_rdata_next[2] = in_sent_sent_2_qs; @@ -6494,7 +6521,7 @@ reg_rdata_next[11] = in_sent_sent_11_qs; end - addr_hit[10]: begin + addr_hit[11]: begin reg_rdata_next[0] = stall_stall_0_qs; reg_rdata_next[1] = stall_stall_1_qs; reg_rdata_next[2] = stall_stall_2_qs; @@ -6509,91 +6536,91 @@ reg_rdata_next[11] = stall_stall_11_qs; end - addr_hit[11]: begin + addr_hit[12]: begin reg_rdata_next[4:0] = configin_0_buffer_0_qs; reg_rdata_next[14:8] = configin_0_size_0_qs; reg_rdata_next[30] = configin_0_pend_0_qs; reg_rdata_next[31] = configin_0_rdy_0_qs; end - addr_hit[12]: begin + addr_hit[13]: begin reg_rdata_next[4:0] = configin_1_buffer_1_qs; reg_rdata_next[14:8] = configin_1_size_1_qs; reg_rdata_next[30] = configin_1_pend_1_qs; reg_rdata_next[31] = configin_1_rdy_1_qs; end - addr_hit[13]: begin + addr_hit[14]: begin reg_rdata_next[4:0] = configin_2_buffer_2_qs; reg_rdata_next[14:8] = configin_2_size_2_qs; reg_rdata_next[30] = configin_2_pend_2_qs; reg_rdata_next[31] = configin_2_rdy_2_qs; end - addr_hit[14]: begin + addr_hit[15]: begin reg_rdata_next[4:0] = configin_3_buffer_3_qs; reg_rdata_next[14:8] = configin_3_size_3_qs; reg_rdata_next[30] = configin_3_pend_3_qs; reg_rdata_next[31] = configin_3_rdy_3_qs; end - addr_hit[15]: begin + addr_hit[16]: begin reg_rdata_next[4:0] = configin_4_buffer_4_qs; reg_rdata_next[14:8] = configin_4_size_4_qs; reg_rdata_next[30] = configin_4_pend_4_qs; reg_rdata_next[31] = configin_4_rdy_4_qs; end - addr_hit[16]: begin + addr_hit[17]: begin reg_rdata_next[4:0] = configin_5_buffer_5_qs; reg_rdata_next[14:8] = configin_5_size_5_qs; reg_rdata_next[30] = configin_5_pend_5_qs; reg_rdata_next[31] = configin_5_rdy_5_qs; end - addr_hit[17]: begin + addr_hit[18]: begin reg_rdata_next[4:0] = configin_6_buffer_6_qs; reg_rdata_next[14:8] = configin_6_size_6_qs; reg_rdata_next[30] = configin_6_pend_6_qs; reg_rdata_next[31] = configin_6_rdy_6_qs; end - addr_hit[18]: begin + addr_hit[19]: begin reg_rdata_next[4:0] = configin_7_buffer_7_qs; reg_rdata_next[14:8] = configin_7_size_7_qs; reg_rdata_next[30] = configin_7_pend_7_qs; reg_rdata_next[31] = configin_7_rdy_7_qs; end - addr_hit[19]: begin + addr_hit[20]: begin reg_rdata_next[4:0] = configin_8_buffer_8_qs; reg_rdata_next[14:8] = configin_8_size_8_qs; reg_rdata_next[30] = configin_8_pend_8_qs; reg_rdata_next[31] = configin_8_rdy_8_qs; end - addr_hit[20]: begin + addr_hit[21]: begin reg_rdata_next[4:0] = configin_9_buffer_9_qs; reg_rdata_next[14:8] = configin_9_size_9_qs; reg_rdata_next[30] = configin_9_pend_9_qs; reg_rdata_next[31] = configin_9_rdy_9_qs; end - addr_hit[21]: begin + addr_hit[22]: begin reg_rdata_next[4:0] = configin_10_buffer_10_qs; reg_rdata_next[14:8] = configin_10_size_10_qs; reg_rdata_next[30] = configin_10_pend_10_qs; reg_rdata_next[31] = configin_10_rdy_10_qs; end - addr_hit[22]: begin + addr_hit[23]: begin reg_rdata_next[4:0] = configin_11_buffer_11_qs; reg_rdata_next[14:8] = configin_11_size_11_qs; reg_rdata_next[30] = configin_11_pend_11_qs; reg_rdata_next[31] = configin_11_rdy_11_qs; end - addr_hit[23]: begin + addr_hit[24]: begin reg_rdata_next[0] = iso_iso_0_qs; reg_rdata_next[1] = iso_iso_1_qs; reg_rdata_next[2] = iso_iso_2_qs; @@ -6608,7 +6635,7 @@ reg_rdata_next[11] = iso_iso_11_qs; end - addr_hit[24]: begin + addr_hit[25]: begin reg_rdata_next[0] = '0; reg_rdata_next[1] = '0; reg_rdata_next[2] = '0; @@ -6623,7 +6650,7 @@ reg_rdata_next[11] = '0; end - addr_hit[25]: begin + addr_hit[26]: begin reg_rdata_next[0] = phy_pins_sense_rx_dp_i_qs; reg_rdata_next[1] = phy_pins_sense_rx_dn_i_qs; reg_rdata_next[2] = phy_pins_sense_rx_d_i_qs; @@ -6636,7 +6663,7 @@ reg_rdata_next[16] = phy_pins_sense_pwr_sense_qs; end - addr_hit[26]: begin + addr_hit[27]: begin reg_rdata_next[0] = phy_pins_drive_dp_o_qs; reg_rdata_next[1] = phy_pins_drive_dn_o_qs; reg_rdata_next[2] = phy_pins_drive_d_o_qs; @@ -6649,7 +6676,7 @@ reg_rdata_next[16] = phy_pins_drive_en_qs; end - addr_hit[27]: begin + addr_hit[28]: begin reg_rdata_next[0] = phy_config_rx_differential_mode_qs; reg_rdata_next[1] = phy_config_tx_differential_mode_qs; reg_rdata_next[2] = phy_config_eop_single_bit_qs; @@ -6660,12 +6687,12 @@ reg_rdata_next[7] = phy_config_tx_osc_test_mode_qs; end - addr_hit[28]: begin + addr_hit[29]: begin reg_rdata_next[0] = wake_config_wake_en_qs; reg_rdata_next[1] = wake_config_wake_ack_qs; end - addr_hit[29]: begin + addr_hit[30]: begin reg_rdata_next[2:0] = wake_debug_qs; end
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 716aba5..7973296 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -11870,6 +11870,7 @@ i2c1 i2c2 pattgen + usbdev otp_ctrl lc_ctrl pwrmgr_aon @@ -11984,6 +11985,13 @@ module_name: pattgen } { + name: usbdev_fatal_fault + width: 1 + type: alert + async: "1" + module_name: usbdev + } + { name: otp_ctrl_fatal_macro_error width: 1 type: alert
diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv index 3b308b3..48adc0f 100644 --- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv +++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
@@ -16,57 +16,58 @@ assign alert_if[9].alert_tx = `CHIP_HIER.u_i2c1.alert_tx_o[0]; assign alert_if[10].alert_tx = `CHIP_HIER.u_i2c2.alert_tx_o[0]; assign alert_if[11].alert_tx = `CHIP_HIER.u_pattgen.alert_tx_o[0]; -assign alert_if[12].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0]; -assign alert_if[13].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1]; -assign alert_if[14].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[2]; -assign alert_if[15].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0]; -assign alert_if[16].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1]; -assign alert_if[17].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[2]; -assign alert_if[18].alert_tx = `CHIP_HIER.u_pwrmgr_aon.alert_tx_o[0]; -assign alert_if[19].alert_tx = `CHIP_HIER.u_rstmgr_aon.alert_tx_o[0]; -assign alert_if[20].alert_tx = `CHIP_HIER.u_clkmgr_aon.alert_tx_o[0]; -assign alert_if[21].alert_tx = `CHIP_HIER.u_sysrst_ctrl_aon.alert_tx_o[0]; -assign alert_if[22].alert_tx = `CHIP_HIER.u_adc_ctrl_aon.alert_tx_o[0]; -assign alert_if[23].alert_tx = `CHIP_HIER.u_pwm_aon.alert_tx_o[0]; -assign alert_if[24].alert_tx = `CHIP_HIER.u_pinmux_aon.alert_tx_o[0]; -assign alert_if[25].alert_tx = `CHIP_HIER.u_aon_timer_aon.alert_tx_o[0]; -assign alert_if[26].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[0]; -assign alert_if[27].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[1]; -assign alert_if[28].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[2]; -assign alert_if[29].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[3]; -assign alert_if[30].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[4]; -assign alert_if[31].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[5]; -assign alert_if[32].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[6]; -assign alert_if[33].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[7]; -assign alert_if[34].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[8]; -assign alert_if[35].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[9]; -assign alert_if[36].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[10]; -assign alert_if[37].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[11]; -assign alert_if[38].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[12]; -assign alert_if[39].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0]; -assign alert_if[40].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[1]; -assign alert_if[41].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0]; -assign alert_if[42].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1]; -assign alert_if[43].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2]; -assign alert_if[44].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3]; -assign alert_if[45].alert_tx = `CHIP_HIER.u_rv_plic.alert_tx_o[0]; -assign alert_if[46].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0]; -assign alert_if[47].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1]; -assign alert_if[48].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0]; -assign alert_if[49].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0]; -assign alert_if[50].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0]; -assign alert_if[51].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1]; -assign alert_if[52].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0]; -assign alert_if[53].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0]; -assign alert_if[54].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1]; -assign alert_if[55].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0]; -assign alert_if[56].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0]; -assign alert_if[57].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0]; -assign alert_if[58].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1]; -assign alert_if[59].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0]; -assign alert_if[60].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1]; -assign alert_if[61].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0]; -assign alert_if[62].alert_tx = `CHIP_HIER.u_rv_core_ibex_peri.alert_tx_o[0]; -assign alert_if[63].alert_tx = `CHIP_HIER.u_rv_core_ibex_peri.alert_tx_o[1]; -assign alert_if[64].alert_tx = `CHIP_HIER.u_rv_core_ibex_peri.alert_tx_o[2]; -assign alert_if[65].alert_tx = `CHIP_HIER.u_rv_core_ibex_peri.alert_tx_o[3]; +assign alert_if[12].alert_tx = `CHIP_HIER.u_usbdev.alert_tx_o[0]; +assign alert_if[13].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0]; +assign alert_if[14].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1]; +assign alert_if[15].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[2]; +assign alert_if[16].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0]; +assign alert_if[17].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1]; +assign alert_if[18].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[2]; +assign alert_if[19].alert_tx = `CHIP_HIER.u_pwrmgr_aon.alert_tx_o[0]; +assign alert_if[20].alert_tx = `CHIP_HIER.u_rstmgr_aon.alert_tx_o[0]; +assign alert_if[21].alert_tx = `CHIP_HIER.u_clkmgr_aon.alert_tx_o[0]; +assign alert_if[22].alert_tx = `CHIP_HIER.u_sysrst_ctrl_aon.alert_tx_o[0]; +assign alert_if[23].alert_tx = `CHIP_HIER.u_adc_ctrl_aon.alert_tx_o[0]; +assign alert_if[24].alert_tx = `CHIP_HIER.u_pwm_aon.alert_tx_o[0]; +assign alert_if[25].alert_tx = `CHIP_HIER.u_pinmux_aon.alert_tx_o[0]; +assign alert_if[26].alert_tx = `CHIP_HIER.u_aon_timer_aon.alert_tx_o[0]; +assign alert_if[27].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[0]; +assign alert_if[28].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[1]; +assign alert_if[29].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[2]; +assign alert_if[30].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[3]; +assign alert_if[31].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[4]; +assign alert_if[32].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[5]; +assign alert_if[33].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[6]; +assign alert_if[34].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[7]; +assign alert_if[35].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[8]; +assign alert_if[36].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[9]; +assign alert_if[37].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[10]; +assign alert_if[38].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[11]; +assign alert_if[39].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[12]; +assign alert_if[40].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0]; +assign alert_if[41].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[1]; +assign alert_if[42].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0]; +assign alert_if[43].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1]; +assign alert_if[44].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2]; +assign alert_if[45].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3]; +assign alert_if[46].alert_tx = `CHIP_HIER.u_rv_plic.alert_tx_o[0]; +assign alert_if[47].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0]; +assign alert_if[48].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1]; +assign alert_if[49].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0]; +assign alert_if[50].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0]; +assign alert_if[51].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0]; +assign alert_if[52].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1]; +assign alert_if[53].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0]; +assign alert_if[54].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0]; +assign alert_if[55].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1]; +assign alert_if[56].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0]; +assign alert_if[57].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0]; +assign alert_if[58].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0]; +assign alert_if[59].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1]; +assign alert_if[60].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0]; +assign alert_if[61].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1]; +assign alert_if[62].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0]; +assign alert_if[63].alert_tx = `CHIP_HIER.u_rv_core_ibex_peri.alert_tx_o[0]; +assign alert_if[64].alert_tx = `CHIP_HIER.u_rv_core_ibex_peri.alert_tx_o[1]; +assign alert_if[65].alert_tx = `CHIP_HIER.u_rv_core_ibex_peri.alert_tx_o[2]; +assign alert_if[66].alert_tx = `CHIP_HIER.u_rv_core_ibex_peri.alert_tx_o[3];
diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv index 44c34f1..be4ec50 100644 --- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
@@ -17,6 +17,7 @@ "i2c1_fatal_fault", "i2c2_fatal_fault", "pattgen_fatal_fault", + "usbdev_fatal_fault", "otp_ctrl_fatal_macro_error", "otp_ctrl_fatal_check_error", "otp_ctrl_fatal_bus_integ_error", @@ -73,4 +74,4 @@ "rv_core_ibex_peri_recov_hw_err" }; -parameter uint NUM_ALERTS = 66; +parameter uint NUM_ALERTS = 67;
diff --git a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson index 3c9f12d..aed413c 100644 --- a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson +++ b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
@@ -48,7 +48,7 @@ { name: "NAlerts", desc: "Number of alert channels.", type: "int", - default: "66", + default: "67", local: "true" }, { name: "EscCntDw", @@ -69,7 +69,7 @@ defines whether the protocol is synchronous (0) or asynchronous (1). ''' type: "logic [NAlerts-1:0]", - default: "66'h3ffffffffffffffff", + default: "67'h7ffffffffffffffff", local: "true" }, { name: "N_CLASSES",
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv index 8fc092f..40231dc 100644 --- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv +++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
@@ -7,10 +7,10 @@ package alert_handler_reg_pkg; // Param list - parameter int NAlerts = 66; + parameter int NAlerts = 67; parameter int EscCntDw = 32; parameter int AccuCntDw = 16; - parameter logic [NAlerts-1:0] AsyncOn = 66'h3ffffffffffffffff; + parameter logic [NAlerts-1:0] AsyncOn = 67'h7ffffffffffffffff; parameter int N_CLASSES = 4; parameter int N_ESC_SEV = 4; parameter int N_PHASES = 4; @@ -464,15 +464,15 @@ // Register -> HW type typedef struct packed { - alert_handler_reg2hw_intr_state_reg_t intr_state; // [1150:1147] - alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1146:1143] - alert_handler_reg2hw_intr_test_reg_t intr_test; // [1142:1135] - alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [1134:1119] - alert_handler_reg2hw_ping_timer_en_reg_t ping_timer_en; // [1118:1118] - alert_handler_reg2hw_alert_regwen_mreg_t [65:0] alert_regwen; // [1117:1052] - alert_handler_reg2hw_alert_en_mreg_t [65:0] alert_en; // [1051:986] - alert_handler_reg2hw_alert_class_mreg_t [65:0] alert_class; // [985:854] - alert_handler_reg2hw_alert_cause_mreg_t [65:0] alert_cause; // [853:788] + alert_handler_reg2hw_intr_state_reg_t intr_state; // [1155:1152] + alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1151:1148] + alert_handler_reg2hw_intr_test_reg_t intr_test; // [1147:1140] + alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [1139:1124] + alert_handler_reg2hw_ping_timer_en_reg_t ping_timer_en; // [1123:1123] + alert_handler_reg2hw_alert_regwen_mreg_t [66:0] alert_regwen; // [1122:1056] + alert_handler_reg2hw_alert_en_mreg_t [66:0] alert_en; // [1055:989] + alert_handler_reg2hw_alert_class_mreg_t [66:0] alert_class; // [988:855] + alert_handler_reg2hw_alert_cause_mreg_t [66:0] alert_cause; // [854:788] alert_handler_reg2hw_loc_alert_en_mreg_t [4:0] loc_alert_en; // [787:783] alert_handler_reg2hw_loc_alert_class_mreg_t [4:0] loc_alert_class; // [782:773] alert_handler_reg2hw_loc_alert_cause_mreg_t [4:0] loc_alert_cause; // [772:768] @@ -512,8 +512,8 @@ // HW -> register type typedef struct packed { - alert_handler_hw2reg_intr_state_reg_t intr_state; // [361:354] - alert_handler_hw2reg_alert_cause_mreg_t [65:0] alert_cause; // [353:222] + alert_handler_hw2reg_intr_state_reg_t intr_state; // [363:356] + alert_handler_hw2reg_alert_cause_mreg_t [66:0] alert_cause; // [355:222] alert_handler_hw2reg_loc_alert_cause_mreg_t [4:0] loc_alert_cause; // [221:212] alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210] alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194] @@ -606,276 +606,280 @@ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_63_OFFSET = 11'h 114; parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_64_OFFSET = 11'h 118; parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_65_OFFSET = 11'h 11c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_0_OFFSET = 11'h 120; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_1_OFFSET = 11'h 124; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_2_OFFSET = 11'h 128; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_3_OFFSET = 11'h 12c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_4_OFFSET = 11'h 130; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_5_OFFSET = 11'h 134; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_6_OFFSET = 11'h 138; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_7_OFFSET = 11'h 13c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_8_OFFSET = 11'h 140; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_9_OFFSET = 11'h 144; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_10_OFFSET = 11'h 148; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_11_OFFSET = 11'h 14c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_12_OFFSET = 11'h 150; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_13_OFFSET = 11'h 154; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_14_OFFSET = 11'h 158; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_15_OFFSET = 11'h 15c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_16_OFFSET = 11'h 160; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_17_OFFSET = 11'h 164; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_18_OFFSET = 11'h 168; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_19_OFFSET = 11'h 16c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_20_OFFSET = 11'h 170; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_21_OFFSET = 11'h 174; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_22_OFFSET = 11'h 178; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_23_OFFSET = 11'h 17c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_24_OFFSET = 11'h 180; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_25_OFFSET = 11'h 184; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_26_OFFSET = 11'h 188; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_27_OFFSET = 11'h 18c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_28_OFFSET = 11'h 190; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_29_OFFSET = 11'h 194; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_30_OFFSET = 11'h 198; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_31_OFFSET = 11'h 19c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_32_OFFSET = 11'h 1a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_33_OFFSET = 11'h 1a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_34_OFFSET = 11'h 1a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_35_OFFSET = 11'h 1ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_36_OFFSET = 11'h 1b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_37_OFFSET = 11'h 1b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_38_OFFSET = 11'h 1b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_39_OFFSET = 11'h 1bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_40_OFFSET = 11'h 1c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_41_OFFSET = 11'h 1c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_42_OFFSET = 11'h 1c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_43_OFFSET = 11'h 1cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_44_OFFSET = 11'h 1d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_45_OFFSET = 11'h 1d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_46_OFFSET = 11'h 1d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_47_OFFSET = 11'h 1dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_48_OFFSET = 11'h 1e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_49_OFFSET = 11'h 1e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_50_OFFSET = 11'h 1e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_51_OFFSET = 11'h 1ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_52_OFFSET = 11'h 1f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_53_OFFSET = 11'h 1f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_54_OFFSET = 11'h 1f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_55_OFFSET = 11'h 1fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_56_OFFSET = 11'h 200; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_57_OFFSET = 11'h 204; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_58_OFFSET = 11'h 208; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_59_OFFSET = 11'h 20c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_60_OFFSET = 11'h 210; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_61_OFFSET = 11'h 214; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_62_OFFSET = 11'h 218; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_63_OFFSET = 11'h 21c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_64_OFFSET = 11'h 220; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_65_OFFSET = 11'h 224; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_0_OFFSET = 11'h 228; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_1_OFFSET = 11'h 22c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_2_OFFSET = 11'h 230; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_3_OFFSET = 11'h 234; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_4_OFFSET = 11'h 238; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_5_OFFSET = 11'h 23c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_6_OFFSET = 11'h 240; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_7_OFFSET = 11'h 244; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_8_OFFSET = 11'h 248; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_9_OFFSET = 11'h 24c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_10_OFFSET = 11'h 250; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_11_OFFSET = 11'h 254; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_12_OFFSET = 11'h 258; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_13_OFFSET = 11'h 25c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_14_OFFSET = 11'h 260; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_15_OFFSET = 11'h 264; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_16_OFFSET = 11'h 268; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_17_OFFSET = 11'h 26c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_18_OFFSET = 11'h 270; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_19_OFFSET = 11'h 274; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_20_OFFSET = 11'h 278; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_21_OFFSET = 11'h 27c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_22_OFFSET = 11'h 280; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_23_OFFSET = 11'h 284; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_24_OFFSET = 11'h 288; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_25_OFFSET = 11'h 28c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_26_OFFSET = 11'h 290; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_27_OFFSET = 11'h 294; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_28_OFFSET = 11'h 298; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_29_OFFSET = 11'h 29c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_30_OFFSET = 11'h 2a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_31_OFFSET = 11'h 2a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_32_OFFSET = 11'h 2a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_33_OFFSET = 11'h 2ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_34_OFFSET = 11'h 2b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_35_OFFSET = 11'h 2b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_36_OFFSET = 11'h 2b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_37_OFFSET = 11'h 2bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_38_OFFSET = 11'h 2c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_39_OFFSET = 11'h 2c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_40_OFFSET = 11'h 2c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_41_OFFSET = 11'h 2cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_42_OFFSET = 11'h 2d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_43_OFFSET = 11'h 2d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_44_OFFSET = 11'h 2d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_45_OFFSET = 11'h 2dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_46_OFFSET = 11'h 2e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_47_OFFSET = 11'h 2e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_48_OFFSET = 11'h 2e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_49_OFFSET = 11'h 2ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_50_OFFSET = 11'h 2f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_51_OFFSET = 11'h 2f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_52_OFFSET = 11'h 2f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_53_OFFSET = 11'h 2fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_54_OFFSET = 11'h 300; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_55_OFFSET = 11'h 304; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_56_OFFSET = 11'h 308; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_57_OFFSET = 11'h 30c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_58_OFFSET = 11'h 310; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_59_OFFSET = 11'h 314; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_60_OFFSET = 11'h 318; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_61_OFFSET = 11'h 31c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_62_OFFSET = 11'h 320; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_63_OFFSET = 11'h 324; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_64_OFFSET = 11'h 328; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_65_OFFSET = 11'h 32c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 330; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 334; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 338; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 33c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 340; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 344; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 348; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 34c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 350; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 354; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 358; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 35c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 360; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 364; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 368; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 36c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 370; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 374; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 378; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 37c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 380; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 384; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 388; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 38c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 390; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 394; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 398; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 39c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 3a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 3a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 3a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 3ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 3b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 3b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 3b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 3bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 3c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 3c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 3c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 3cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 3d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 3d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 3d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 3dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 3e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 3e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 3e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 3ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 3f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 3f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 3f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 3fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 400; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 404; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 408; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 40c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 410; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 414; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 418; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 41c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_60_OFFSET = 11'h 420; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_61_OFFSET = 11'h 424; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_62_OFFSET = 11'h 428; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_63_OFFSET = 11'h 42c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_64_OFFSET = 11'h 430; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_65_OFFSET = 11'h 434; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 438; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 43c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 440; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 444; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 448; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET = 11'h 44c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET = 11'h 450; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET = 11'h 454; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET = 11'h 458; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET = 11'h 45c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET = 11'h 460; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET = 11'h 464; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET = 11'h 468; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET = 11'h 46c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET = 11'h 470; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 474; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 478; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 47c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 480; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 484; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 488; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_OFFSET = 11'h 48c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 490; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_OFFSET = 11'h 494; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 498; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 11'h 49c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 11'h 4a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 11'h 4a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 11'h 4a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 11'h 4ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 11'h 4b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 4b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 4b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 4bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_OFFSET = 11'h 4c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 4c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_OFFSET = 11'h 4c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 4cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 11'h 4d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 11'h 4d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 11'h 4d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 11'h 4dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 11'h 4e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 11'h 4e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 4e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 4ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 4f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_OFFSET = 11'h 4f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 4f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_OFFSET = 11'h 4fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 500; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 11'h 504; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 11'h 508; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 11'h 50c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 11'h 510; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 11'h 514; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 11'h 518; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 51c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 520; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 524; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_OFFSET = 11'h 528; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 52c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_OFFSET = 11'h 530; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 534; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 11'h 538; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 11'h 53c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 11'h 540; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 11'h 544; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 11'h 548; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 11'h 54c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 550; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 554; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_66_OFFSET = 11'h 120; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_0_OFFSET = 11'h 124; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_1_OFFSET = 11'h 128; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_2_OFFSET = 11'h 12c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_3_OFFSET = 11'h 130; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_4_OFFSET = 11'h 134; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_5_OFFSET = 11'h 138; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_6_OFFSET = 11'h 13c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_7_OFFSET = 11'h 140; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_8_OFFSET = 11'h 144; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_9_OFFSET = 11'h 148; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_10_OFFSET = 11'h 14c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_11_OFFSET = 11'h 150; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_12_OFFSET = 11'h 154; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_13_OFFSET = 11'h 158; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_14_OFFSET = 11'h 15c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_15_OFFSET = 11'h 160; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_16_OFFSET = 11'h 164; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_17_OFFSET = 11'h 168; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_18_OFFSET = 11'h 16c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_19_OFFSET = 11'h 170; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_20_OFFSET = 11'h 174; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_21_OFFSET = 11'h 178; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_22_OFFSET = 11'h 17c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_23_OFFSET = 11'h 180; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_24_OFFSET = 11'h 184; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_25_OFFSET = 11'h 188; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_26_OFFSET = 11'h 18c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_27_OFFSET = 11'h 190; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_28_OFFSET = 11'h 194; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_29_OFFSET = 11'h 198; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_30_OFFSET = 11'h 19c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_31_OFFSET = 11'h 1a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_32_OFFSET = 11'h 1a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_33_OFFSET = 11'h 1a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_34_OFFSET = 11'h 1ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_35_OFFSET = 11'h 1b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_36_OFFSET = 11'h 1b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_37_OFFSET = 11'h 1b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_38_OFFSET = 11'h 1bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_39_OFFSET = 11'h 1c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_40_OFFSET = 11'h 1c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_41_OFFSET = 11'h 1c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_42_OFFSET = 11'h 1cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_43_OFFSET = 11'h 1d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_44_OFFSET = 11'h 1d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_45_OFFSET = 11'h 1d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_46_OFFSET = 11'h 1dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_47_OFFSET = 11'h 1e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_48_OFFSET = 11'h 1e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_49_OFFSET = 11'h 1e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_50_OFFSET = 11'h 1ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_51_OFFSET = 11'h 1f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_52_OFFSET = 11'h 1f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_53_OFFSET = 11'h 1f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_54_OFFSET = 11'h 1fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_55_OFFSET = 11'h 200; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_56_OFFSET = 11'h 204; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_57_OFFSET = 11'h 208; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_58_OFFSET = 11'h 20c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_59_OFFSET = 11'h 210; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_60_OFFSET = 11'h 214; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_61_OFFSET = 11'h 218; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_62_OFFSET = 11'h 21c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_63_OFFSET = 11'h 220; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_64_OFFSET = 11'h 224; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_65_OFFSET = 11'h 228; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_66_OFFSET = 11'h 22c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_0_OFFSET = 11'h 230; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_1_OFFSET = 11'h 234; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_2_OFFSET = 11'h 238; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_3_OFFSET = 11'h 23c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_4_OFFSET = 11'h 240; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_5_OFFSET = 11'h 244; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_6_OFFSET = 11'h 248; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_7_OFFSET = 11'h 24c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_8_OFFSET = 11'h 250; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_9_OFFSET = 11'h 254; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_10_OFFSET = 11'h 258; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_11_OFFSET = 11'h 25c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_12_OFFSET = 11'h 260; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_13_OFFSET = 11'h 264; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_14_OFFSET = 11'h 268; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_15_OFFSET = 11'h 26c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_16_OFFSET = 11'h 270; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_17_OFFSET = 11'h 274; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_18_OFFSET = 11'h 278; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_19_OFFSET = 11'h 27c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_20_OFFSET = 11'h 280; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_21_OFFSET = 11'h 284; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_22_OFFSET = 11'h 288; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_23_OFFSET = 11'h 28c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_24_OFFSET = 11'h 290; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_25_OFFSET = 11'h 294; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_26_OFFSET = 11'h 298; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_27_OFFSET = 11'h 29c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_28_OFFSET = 11'h 2a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_29_OFFSET = 11'h 2a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_30_OFFSET = 11'h 2a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_31_OFFSET = 11'h 2ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_32_OFFSET = 11'h 2b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_33_OFFSET = 11'h 2b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_34_OFFSET = 11'h 2b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_35_OFFSET = 11'h 2bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_36_OFFSET = 11'h 2c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_37_OFFSET = 11'h 2c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_38_OFFSET = 11'h 2c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_39_OFFSET = 11'h 2cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_40_OFFSET = 11'h 2d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_41_OFFSET = 11'h 2d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_42_OFFSET = 11'h 2d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_43_OFFSET = 11'h 2dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_44_OFFSET = 11'h 2e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_45_OFFSET = 11'h 2e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_46_OFFSET = 11'h 2e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_47_OFFSET = 11'h 2ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_48_OFFSET = 11'h 2f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_49_OFFSET = 11'h 2f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_50_OFFSET = 11'h 2f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_51_OFFSET = 11'h 2fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_52_OFFSET = 11'h 300; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_53_OFFSET = 11'h 304; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_54_OFFSET = 11'h 308; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_55_OFFSET = 11'h 30c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_56_OFFSET = 11'h 310; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_57_OFFSET = 11'h 314; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_58_OFFSET = 11'h 318; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_59_OFFSET = 11'h 31c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_60_OFFSET = 11'h 320; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_61_OFFSET = 11'h 324; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_62_OFFSET = 11'h 328; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_63_OFFSET = 11'h 32c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_64_OFFSET = 11'h 330; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_65_OFFSET = 11'h 334; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_66_OFFSET = 11'h 338; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 33c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 340; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 344; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 348; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 34c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 350; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 354; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 358; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 35c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 360; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 364; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 368; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 36c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 370; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 374; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 378; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 37c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 380; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 384; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 388; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 38c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 390; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 394; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 398; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 39c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 3a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 3a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 3a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 3ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 3b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 3b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 3b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 3bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 3c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 3c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 3c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 3cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 3d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 3d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 3d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 3dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 3e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 3e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 3e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 3ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 3f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 3f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 3f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 3fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 400; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 404; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 408; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 40c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 410; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 414; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 418; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 41c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 420; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 424; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 428; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_60_OFFSET = 11'h 42c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_61_OFFSET = 11'h 430; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_62_OFFSET = 11'h 434; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_63_OFFSET = 11'h 438; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_64_OFFSET = 11'h 43c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_65_OFFSET = 11'h 440; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_66_OFFSET = 11'h 444; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 448; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 44c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 450; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 454; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 458; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET = 11'h 45c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET = 11'h 460; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET = 11'h 464; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET = 11'h 468; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET = 11'h 46c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET = 11'h 470; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET = 11'h 474; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET = 11'h 478; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET = 11'h 47c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET = 11'h 480; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 484; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 488; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 48c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 490; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 494; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 498; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_OFFSET = 11'h 49c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 4a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_OFFSET = 11'h 4a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 4a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 11'h 4ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 11'h 4b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 11'h 4b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 11'h 4b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 11'h 4bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 11'h 4c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 4c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 4c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 4cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_OFFSET = 11'h 4d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 4d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_OFFSET = 11'h 4d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 4dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 11'h 4e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 11'h 4e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 11'h 4e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 11'h 4ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 11'h 4f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 11'h 4f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 4f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 4fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 500; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_OFFSET = 11'h 504; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 508; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_OFFSET = 11'h 50c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 510; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 11'h 514; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 11'h 518; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 11'h 51c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 11'h 520; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 11'h 524; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 11'h 528; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 52c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 530; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 534; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_OFFSET = 11'h 538; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 53c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_OFFSET = 11'h 540; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 544; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 11'h 548; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 11'h 54c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 11'h 550; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 11'h 554; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 11'h 558; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 11'h 55c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 560; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 564; // Reset values for hwext registers and their fields parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0; @@ -970,6 +974,7 @@ ALERT_HANDLER_ALERT_REGWEN_63, ALERT_HANDLER_ALERT_REGWEN_64, ALERT_HANDLER_ALERT_REGWEN_65, + ALERT_HANDLER_ALERT_REGWEN_66, ALERT_HANDLER_ALERT_EN_0, ALERT_HANDLER_ALERT_EN_1, ALERT_HANDLER_ALERT_EN_2, @@ -1036,6 +1041,7 @@ ALERT_HANDLER_ALERT_EN_63, ALERT_HANDLER_ALERT_EN_64, ALERT_HANDLER_ALERT_EN_65, + ALERT_HANDLER_ALERT_EN_66, ALERT_HANDLER_ALERT_CLASS_0, ALERT_HANDLER_ALERT_CLASS_1, ALERT_HANDLER_ALERT_CLASS_2, @@ -1102,6 +1108,7 @@ ALERT_HANDLER_ALERT_CLASS_63, ALERT_HANDLER_ALERT_CLASS_64, ALERT_HANDLER_ALERT_CLASS_65, + ALERT_HANDLER_ALERT_CLASS_66, ALERT_HANDLER_ALERT_CAUSE_0, ALERT_HANDLER_ALERT_CAUSE_1, ALERT_HANDLER_ALERT_CAUSE_2, @@ -1168,6 +1175,7 @@ ALERT_HANDLER_ALERT_CAUSE_63, ALERT_HANDLER_ALERT_CAUSE_64, ALERT_HANDLER_ALERT_CAUSE_65, + ALERT_HANDLER_ALERT_CAUSE_66, ALERT_HANDLER_LOC_ALERT_REGWEN_0, ALERT_HANDLER_LOC_ALERT_REGWEN_1, ALERT_HANDLER_LOC_ALERT_REGWEN_2, @@ -1243,7 +1251,7 @@ } alert_handler_id_e; // Register width information to check illegal writes - parameter logic [3:0] ALERT_HANDLER_PERMIT [342] = '{ + parameter logic [3:0] ALERT_HANDLER_PERMIT [346] = '{ 4'b 0001, // index[ 0] ALERT_HANDLER_INTR_STATE 4'b 0001, // index[ 1] ALERT_HANDLER_INTR_ENABLE 4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST @@ -1316,276 +1324,280 @@ 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_REGWEN_63 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_REGWEN_64 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_REGWEN_65 - 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_0 - 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_1 - 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_2 - 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_3 - 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_4 - 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_5 - 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_6 - 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_7 - 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_8 - 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_9 - 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_10 - 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_11 - 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_12 - 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_13 - 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_14 - 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_15 - 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_16 - 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_17 - 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_18 - 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_19 - 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_20 - 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_21 - 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_22 - 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_23 - 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_24 - 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_25 - 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_26 - 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_27 - 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_28 - 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_29 - 4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_30 - 4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_31 - 4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_32 - 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_33 - 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_34 - 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_35 - 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_36 - 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_37 - 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_38 - 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_39 - 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_40 - 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_41 - 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_42 - 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_43 - 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_44 - 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_45 - 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_46 - 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_47 - 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_48 - 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_49 - 4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_50 - 4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_51 - 4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_52 - 4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_53 - 4'b 0001, // index[126] ALERT_HANDLER_ALERT_EN_54 - 4'b 0001, // index[127] ALERT_HANDLER_ALERT_EN_55 - 4'b 0001, // index[128] ALERT_HANDLER_ALERT_EN_56 - 4'b 0001, // index[129] ALERT_HANDLER_ALERT_EN_57 - 4'b 0001, // index[130] ALERT_HANDLER_ALERT_EN_58 - 4'b 0001, // index[131] ALERT_HANDLER_ALERT_EN_59 - 4'b 0001, // index[132] ALERT_HANDLER_ALERT_EN_60 - 4'b 0001, // index[133] ALERT_HANDLER_ALERT_EN_61 - 4'b 0001, // index[134] ALERT_HANDLER_ALERT_EN_62 - 4'b 0001, // index[135] ALERT_HANDLER_ALERT_EN_63 - 4'b 0001, // index[136] ALERT_HANDLER_ALERT_EN_64 - 4'b 0001, // index[137] ALERT_HANDLER_ALERT_EN_65 - 4'b 0001, // index[138] ALERT_HANDLER_ALERT_CLASS_0 - 4'b 0001, // index[139] ALERT_HANDLER_ALERT_CLASS_1 - 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_2 - 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_3 - 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_4 - 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_5 - 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_6 - 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_7 - 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_8 - 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_9 - 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_10 - 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_11 - 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_12 - 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_13 - 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_14 - 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_15 - 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_16 - 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_17 - 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_18 - 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_19 - 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_20 - 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_21 - 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_22 - 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_23 - 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_24 - 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_25 - 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_26 - 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_27 - 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_28 - 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_29 - 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_30 - 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_31 - 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_32 - 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_33 - 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_34 - 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_35 - 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_36 - 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_37 - 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_38 - 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_39 - 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_40 - 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_41 - 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_42 - 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_43 - 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_44 - 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CLASS_45 - 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CLASS_46 - 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CLASS_47 - 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CLASS_48 - 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CLASS_49 - 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CLASS_50 - 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CLASS_51 - 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CLASS_52 - 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CLASS_53 - 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CLASS_54 - 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CLASS_55 - 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CLASS_56 - 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CLASS_57 - 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CLASS_58 - 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CLASS_59 - 4'b 0001, // index[198] ALERT_HANDLER_ALERT_CLASS_60 - 4'b 0001, // index[199] ALERT_HANDLER_ALERT_CLASS_61 - 4'b 0001, // index[200] ALERT_HANDLER_ALERT_CLASS_62 - 4'b 0001, // index[201] ALERT_HANDLER_ALERT_CLASS_63 - 4'b 0001, // index[202] ALERT_HANDLER_ALERT_CLASS_64 - 4'b 0001, // index[203] ALERT_HANDLER_ALERT_CLASS_65 - 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CAUSE_0 - 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CAUSE_1 - 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CAUSE_2 - 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CAUSE_3 - 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CAUSE_4 - 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CAUSE_5 - 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CAUSE_6 - 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CAUSE_7 - 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CAUSE_8 - 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_9 - 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_10 - 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_11 - 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_12 - 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_13 - 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_14 - 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_15 - 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_16 - 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_17 - 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_18 - 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_19 - 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_20 - 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_21 - 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_22 - 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_23 - 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_24 - 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_25 - 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_26 - 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_27 - 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_28 - 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_29 - 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_30 - 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_31 - 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_32 - 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_33 - 4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_34 - 4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_35 - 4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_36 - 4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_37 - 4'b 0001, // index[242] ALERT_HANDLER_ALERT_CAUSE_38 - 4'b 0001, // index[243] ALERT_HANDLER_ALERT_CAUSE_39 - 4'b 0001, // index[244] ALERT_HANDLER_ALERT_CAUSE_40 - 4'b 0001, // index[245] ALERT_HANDLER_ALERT_CAUSE_41 - 4'b 0001, // index[246] ALERT_HANDLER_ALERT_CAUSE_42 - 4'b 0001, // index[247] ALERT_HANDLER_ALERT_CAUSE_43 - 4'b 0001, // index[248] ALERT_HANDLER_ALERT_CAUSE_44 - 4'b 0001, // index[249] ALERT_HANDLER_ALERT_CAUSE_45 - 4'b 0001, // index[250] ALERT_HANDLER_ALERT_CAUSE_46 - 4'b 0001, // index[251] ALERT_HANDLER_ALERT_CAUSE_47 - 4'b 0001, // index[252] ALERT_HANDLER_ALERT_CAUSE_48 - 4'b 0001, // index[253] ALERT_HANDLER_ALERT_CAUSE_49 - 4'b 0001, // index[254] ALERT_HANDLER_ALERT_CAUSE_50 - 4'b 0001, // index[255] ALERT_HANDLER_ALERT_CAUSE_51 - 4'b 0001, // index[256] ALERT_HANDLER_ALERT_CAUSE_52 - 4'b 0001, // index[257] ALERT_HANDLER_ALERT_CAUSE_53 - 4'b 0001, // index[258] ALERT_HANDLER_ALERT_CAUSE_54 - 4'b 0001, // index[259] ALERT_HANDLER_ALERT_CAUSE_55 - 4'b 0001, // index[260] ALERT_HANDLER_ALERT_CAUSE_56 - 4'b 0001, // index[261] ALERT_HANDLER_ALERT_CAUSE_57 - 4'b 0001, // index[262] ALERT_HANDLER_ALERT_CAUSE_58 - 4'b 0001, // index[263] ALERT_HANDLER_ALERT_CAUSE_59 - 4'b 0001, // index[264] ALERT_HANDLER_ALERT_CAUSE_60 - 4'b 0001, // index[265] ALERT_HANDLER_ALERT_CAUSE_61 - 4'b 0001, // index[266] ALERT_HANDLER_ALERT_CAUSE_62 - 4'b 0001, // index[267] ALERT_HANDLER_ALERT_CAUSE_63 - 4'b 0001, // index[268] ALERT_HANDLER_ALERT_CAUSE_64 - 4'b 0001, // index[269] ALERT_HANDLER_ALERT_CAUSE_65 - 4'b 0001, // index[270] ALERT_HANDLER_LOC_ALERT_REGWEN_0 - 4'b 0001, // index[271] ALERT_HANDLER_LOC_ALERT_REGWEN_1 - 4'b 0001, // index[272] ALERT_HANDLER_LOC_ALERT_REGWEN_2 - 4'b 0001, // index[273] ALERT_HANDLER_LOC_ALERT_REGWEN_3 - 4'b 0001, // index[274] ALERT_HANDLER_LOC_ALERT_REGWEN_4 - 4'b 0001, // index[275] ALERT_HANDLER_LOC_ALERT_EN_0 - 4'b 0001, // index[276] ALERT_HANDLER_LOC_ALERT_EN_1 - 4'b 0001, // index[277] ALERT_HANDLER_LOC_ALERT_EN_2 - 4'b 0001, // index[278] ALERT_HANDLER_LOC_ALERT_EN_3 - 4'b 0001, // index[279] ALERT_HANDLER_LOC_ALERT_EN_4 - 4'b 0001, // index[280] ALERT_HANDLER_LOC_ALERT_CLASS_0 - 4'b 0001, // index[281] ALERT_HANDLER_LOC_ALERT_CLASS_1 - 4'b 0001, // index[282] ALERT_HANDLER_LOC_ALERT_CLASS_2 - 4'b 0001, // index[283] ALERT_HANDLER_LOC_ALERT_CLASS_3 - 4'b 0001, // index[284] ALERT_HANDLER_LOC_ALERT_CLASS_4 - 4'b 0001, // index[285] ALERT_HANDLER_LOC_ALERT_CAUSE_0 - 4'b 0001, // index[286] ALERT_HANDLER_LOC_ALERT_CAUSE_1 - 4'b 0001, // index[287] ALERT_HANDLER_LOC_ALERT_CAUSE_2 - 4'b 0001, // index[288] ALERT_HANDLER_LOC_ALERT_CAUSE_3 - 4'b 0001, // index[289] ALERT_HANDLER_LOC_ALERT_CAUSE_4 - 4'b 0001, // index[290] ALERT_HANDLER_CLASSA_REGWEN - 4'b 0011, // index[291] ALERT_HANDLER_CLASSA_CTRL - 4'b 0001, // index[292] ALERT_HANDLER_CLASSA_CLR_REGWEN - 4'b 0001, // index[293] ALERT_HANDLER_CLASSA_CLR - 4'b 0011, // index[294] ALERT_HANDLER_CLASSA_ACCUM_CNT - 4'b 0011, // index[295] ALERT_HANDLER_CLASSA_ACCUM_THRESH - 4'b 1111, // index[296] ALERT_HANDLER_CLASSA_TIMEOUT_CYC - 4'b 1111, // index[297] ALERT_HANDLER_CLASSA_PHASE0_CYC - 4'b 1111, // index[298] ALERT_HANDLER_CLASSA_PHASE1_CYC - 4'b 1111, // index[299] ALERT_HANDLER_CLASSA_PHASE2_CYC - 4'b 1111, // index[300] ALERT_HANDLER_CLASSA_PHASE3_CYC - 4'b 1111, // index[301] ALERT_HANDLER_CLASSA_ESC_CNT - 4'b 0001, // index[302] ALERT_HANDLER_CLASSA_STATE - 4'b 0001, // index[303] ALERT_HANDLER_CLASSB_REGWEN - 4'b 0011, // index[304] ALERT_HANDLER_CLASSB_CTRL - 4'b 0001, // index[305] ALERT_HANDLER_CLASSB_CLR_REGWEN - 4'b 0001, // index[306] ALERT_HANDLER_CLASSB_CLR - 4'b 0011, // index[307] ALERT_HANDLER_CLASSB_ACCUM_CNT - 4'b 0011, // index[308] ALERT_HANDLER_CLASSB_ACCUM_THRESH - 4'b 1111, // index[309] ALERT_HANDLER_CLASSB_TIMEOUT_CYC - 4'b 1111, // index[310] ALERT_HANDLER_CLASSB_PHASE0_CYC - 4'b 1111, // index[311] ALERT_HANDLER_CLASSB_PHASE1_CYC - 4'b 1111, // index[312] ALERT_HANDLER_CLASSB_PHASE2_CYC - 4'b 1111, // index[313] ALERT_HANDLER_CLASSB_PHASE3_CYC - 4'b 1111, // index[314] ALERT_HANDLER_CLASSB_ESC_CNT - 4'b 0001, // index[315] ALERT_HANDLER_CLASSB_STATE - 4'b 0001, // index[316] ALERT_HANDLER_CLASSC_REGWEN - 4'b 0011, // index[317] ALERT_HANDLER_CLASSC_CTRL - 4'b 0001, // index[318] ALERT_HANDLER_CLASSC_CLR_REGWEN - 4'b 0001, // index[319] ALERT_HANDLER_CLASSC_CLR - 4'b 0011, // index[320] ALERT_HANDLER_CLASSC_ACCUM_CNT - 4'b 0011, // index[321] ALERT_HANDLER_CLASSC_ACCUM_THRESH - 4'b 1111, // index[322] ALERT_HANDLER_CLASSC_TIMEOUT_CYC - 4'b 1111, // index[323] ALERT_HANDLER_CLASSC_PHASE0_CYC - 4'b 1111, // index[324] ALERT_HANDLER_CLASSC_PHASE1_CYC - 4'b 1111, // index[325] ALERT_HANDLER_CLASSC_PHASE2_CYC - 4'b 1111, // index[326] ALERT_HANDLER_CLASSC_PHASE3_CYC - 4'b 1111, // index[327] ALERT_HANDLER_CLASSC_ESC_CNT - 4'b 0001, // index[328] ALERT_HANDLER_CLASSC_STATE - 4'b 0001, // index[329] ALERT_HANDLER_CLASSD_REGWEN - 4'b 0011, // index[330] ALERT_HANDLER_CLASSD_CTRL - 4'b 0001, // index[331] ALERT_HANDLER_CLASSD_CLR_REGWEN - 4'b 0001, // index[332] ALERT_HANDLER_CLASSD_CLR - 4'b 0011, // index[333] ALERT_HANDLER_CLASSD_ACCUM_CNT - 4'b 0011, // index[334] ALERT_HANDLER_CLASSD_ACCUM_THRESH - 4'b 1111, // index[335] ALERT_HANDLER_CLASSD_TIMEOUT_CYC - 4'b 1111, // index[336] ALERT_HANDLER_CLASSD_PHASE0_CYC - 4'b 1111, // index[337] ALERT_HANDLER_CLASSD_PHASE1_CYC - 4'b 1111, // index[338] ALERT_HANDLER_CLASSD_PHASE2_CYC - 4'b 1111, // index[339] ALERT_HANDLER_CLASSD_PHASE3_CYC - 4'b 1111, // index[340] ALERT_HANDLER_CLASSD_ESC_CNT - 4'b 0001 // index[341] ALERT_HANDLER_CLASSD_STATE + 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_REGWEN_66 + 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_0 + 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_1 + 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_2 + 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_3 + 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_4 + 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_5 + 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_6 + 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_7 + 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_8 + 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_9 + 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_10 + 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_11 + 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_12 + 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_13 + 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_14 + 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_15 + 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_16 + 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_17 + 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_18 + 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_19 + 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_20 + 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_21 + 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_22 + 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_23 + 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_24 + 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_25 + 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_26 + 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_27 + 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_28 + 4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_29 + 4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_30 + 4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_31 + 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_32 + 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_33 + 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_34 + 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_35 + 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_36 + 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_37 + 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_38 + 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_39 + 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_40 + 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_41 + 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_42 + 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_43 + 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_44 + 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_45 + 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_46 + 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_47 + 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_48 + 4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_49 + 4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_50 + 4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_51 + 4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_52 + 4'b 0001, // index[126] ALERT_HANDLER_ALERT_EN_53 + 4'b 0001, // index[127] ALERT_HANDLER_ALERT_EN_54 + 4'b 0001, // index[128] ALERT_HANDLER_ALERT_EN_55 + 4'b 0001, // index[129] ALERT_HANDLER_ALERT_EN_56 + 4'b 0001, // index[130] ALERT_HANDLER_ALERT_EN_57 + 4'b 0001, // index[131] ALERT_HANDLER_ALERT_EN_58 + 4'b 0001, // index[132] ALERT_HANDLER_ALERT_EN_59 + 4'b 0001, // index[133] ALERT_HANDLER_ALERT_EN_60 + 4'b 0001, // index[134] ALERT_HANDLER_ALERT_EN_61 + 4'b 0001, // index[135] ALERT_HANDLER_ALERT_EN_62 + 4'b 0001, // index[136] ALERT_HANDLER_ALERT_EN_63 + 4'b 0001, // index[137] ALERT_HANDLER_ALERT_EN_64 + 4'b 0001, // index[138] ALERT_HANDLER_ALERT_EN_65 + 4'b 0001, // index[139] ALERT_HANDLER_ALERT_EN_66 + 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_0 + 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_1 + 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_2 + 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_3 + 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_4 + 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_5 + 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_6 + 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_7 + 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_8 + 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_9 + 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_10 + 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_11 + 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_12 + 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_13 + 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_14 + 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_15 + 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_16 + 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_17 + 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_18 + 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_19 + 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_20 + 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_21 + 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_22 + 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_23 + 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_24 + 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_25 + 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_26 + 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_27 + 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_28 + 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_29 + 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_30 + 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_31 + 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_32 + 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_33 + 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_34 + 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_35 + 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_36 + 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_37 + 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_38 + 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_39 + 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_40 + 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_41 + 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_42 + 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CLASS_43 + 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CLASS_44 + 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CLASS_45 + 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CLASS_46 + 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CLASS_47 + 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CLASS_48 + 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CLASS_49 + 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CLASS_50 + 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CLASS_51 + 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CLASS_52 + 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CLASS_53 + 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CLASS_54 + 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CLASS_55 + 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CLASS_56 + 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CLASS_57 + 4'b 0001, // index[198] ALERT_HANDLER_ALERT_CLASS_58 + 4'b 0001, // index[199] ALERT_HANDLER_ALERT_CLASS_59 + 4'b 0001, // index[200] ALERT_HANDLER_ALERT_CLASS_60 + 4'b 0001, // index[201] ALERT_HANDLER_ALERT_CLASS_61 + 4'b 0001, // index[202] ALERT_HANDLER_ALERT_CLASS_62 + 4'b 0001, // index[203] ALERT_HANDLER_ALERT_CLASS_63 + 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CLASS_64 + 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CLASS_65 + 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CLASS_66 + 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CAUSE_0 + 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CAUSE_1 + 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CAUSE_2 + 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CAUSE_3 + 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CAUSE_4 + 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CAUSE_5 + 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_6 + 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_7 + 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_8 + 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_9 + 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_10 + 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_11 + 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_12 + 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_13 + 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_14 + 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_15 + 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_16 + 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_17 + 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_18 + 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_19 + 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_20 + 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_21 + 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_22 + 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_23 + 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_24 + 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_25 + 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_26 + 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_27 + 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_28 + 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_29 + 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_30 + 4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_31 + 4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_32 + 4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_33 + 4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_34 + 4'b 0001, // index[242] ALERT_HANDLER_ALERT_CAUSE_35 + 4'b 0001, // index[243] ALERT_HANDLER_ALERT_CAUSE_36 + 4'b 0001, // index[244] ALERT_HANDLER_ALERT_CAUSE_37 + 4'b 0001, // index[245] ALERT_HANDLER_ALERT_CAUSE_38 + 4'b 0001, // index[246] ALERT_HANDLER_ALERT_CAUSE_39 + 4'b 0001, // index[247] ALERT_HANDLER_ALERT_CAUSE_40 + 4'b 0001, // index[248] ALERT_HANDLER_ALERT_CAUSE_41 + 4'b 0001, // index[249] ALERT_HANDLER_ALERT_CAUSE_42 + 4'b 0001, // index[250] ALERT_HANDLER_ALERT_CAUSE_43 + 4'b 0001, // index[251] ALERT_HANDLER_ALERT_CAUSE_44 + 4'b 0001, // index[252] ALERT_HANDLER_ALERT_CAUSE_45 + 4'b 0001, // index[253] ALERT_HANDLER_ALERT_CAUSE_46 + 4'b 0001, // index[254] ALERT_HANDLER_ALERT_CAUSE_47 + 4'b 0001, // index[255] ALERT_HANDLER_ALERT_CAUSE_48 + 4'b 0001, // index[256] ALERT_HANDLER_ALERT_CAUSE_49 + 4'b 0001, // index[257] ALERT_HANDLER_ALERT_CAUSE_50 + 4'b 0001, // index[258] ALERT_HANDLER_ALERT_CAUSE_51 + 4'b 0001, // index[259] ALERT_HANDLER_ALERT_CAUSE_52 + 4'b 0001, // index[260] ALERT_HANDLER_ALERT_CAUSE_53 + 4'b 0001, // index[261] ALERT_HANDLER_ALERT_CAUSE_54 + 4'b 0001, // index[262] ALERT_HANDLER_ALERT_CAUSE_55 + 4'b 0001, // index[263] ALERT_HANDLER_ALERT_CAUSE_56 + 4'b 0001, // index[264] ALERT_HANDLER_ALERT_CAUSE_57 + 4'b 0001, // index[265] ALERT_HANDLER_ALERT_CAUSE_58 + 4'b 0001, // index[266] ALERT_HANDLER_ALERT_CAUSE_59 + 4'b 0001, // index[267] ALERT_HANDLER_ALERT_CAUSE_60 + 4'b 0001, // index[268] ALERT_HANDLER_ALERT_CAUSE_61 + 4'b 0001, // index[269] ALERT_HANDLER_ALERT_CAUSE_62 + 4'b 0001, // index[270] ALERT_HANDLER_ALERT_CAUSE_63 + 4'b 0001, // index[271] ALERT_HANDLER_ALERT_CAUSE_64 + 4'b 0001, // index[272] ALERT_HANDLER_ALERT_CAUSE_65 + 4'b 0001, // index[273] ALERT_HANDLER_ALERT_CAUSE_66 + 4'b 0001, // index[274] ALERT_HANDLER_LOC_ALERT_REGWEN_0 + 4'b 0001, // index[275] ALERT_HANDLER_LOC_ALERT_REGWEN_1 + 4'b 0001, // index[276] ALERT_HANDLER_LOC_ALERT_REGWEN_2 + 4'b 0001, // index[277] ALERT_HANDLER_LOC_ALERT_REGWEN_3 + 4'b 0001, // index[278] ALERT_HANDLER_LOC_ALERT_REGWEN_4 + 4'b 0001, // index[279] ALERT_HANDLER_LOC_ALERT_EN_0 + 4'b 0001, // index[280] ALERT_HANDLER_LOC_ALERT_EN_1 + 4'b 0001, // index[281] ALERT_HANDLER_LOC_ALERT_EN_2 + 4'b 0001, // index[282] ALERT_HANDLER_LOC_ALERT_EN_3 + 4'b 0001, // index[283] ALERT_HANDLER_LOC_ALERT_EN_4 + 4'b 0001, // index[284] ALERT_HANDLER_LOC_ALERT_CLASS_0 + 4'b 0001, // index[285] ALERT_HANDLER_LOC_ALERT_CLASS_1 + 4'b 0001, // index[286] ALERT_HANDLER_LOC_ALERT_CLASS_2 + 4'b 0001, // index[287] ALERT_HANDLER_LOC_ALERT_CLASS_3 + 4'b 0001, // index[288] ALERT_HANDLER_LOC_ALERT_CLASS_4 + 4'b 0001, // index[289] ALERT_HANDLER_LOC_ALERT_CAUSE_0 + 4'b 0001, // index[290] ALERT_HANDLER_LOC_ALERT_CAUSE_1 + 4'b 0001, // index[291] ALERT_HANDLER_LOC_ALERT_CAUSE_2 + 4'b 0001, // index[292] ALERT_HANDLER_LOC_ALERT_CAUSE_3 + 4'b 0001, // index[293] ALERT_HANDLER_LOC_ALERT_CAUSE_4 + 4'b 0001, // index[294] ALERT_HANDLER_CLASSA_REGWEN + 4'b 0011, // index[295] ALERT_HANDLER_CLASSA_CTRL + 4'b 0001, // index[296] ALERT_HANDLER_CLASSA_CLR_REGWEN + 4'b 0001, // index[297] ALERT_HANDLER_CLASSA_CLR + 4'b 0011, // index[298] ALERT_HANDLER_CLASSA_ACCUM_CNT + 4'b 0011, // index[299] ALERT_HANDLER_CLASSA_ACCUM_THRESH + 4'b 1111, // index[300] ALERT_HANDLER_CLASSA_TIMEOUT_CYC + 4'b 1111, // index[301] ALERT_HANDLER_CLASSA_PHASE0_CYC + 4'b 1111, // index[302] ALERT_HANDLER_CLASSA_PHASE1_CYC + 4'b 1111, // index[303] ALERT_HANDLER_CLASSA_PHASE2_CYC + 4'b 1111, // index[304] ALERT_HANDLER_CLASSA_PHASE3_CYC + 4'b 1111, // index[305] ALERT_HANDLER_CLASSA_ESC_CNT + 4'b 0001, // index[306] ALERT_HANDLER_CLASSA_STATE + 4'b 0001, // index[307] ALERT_HANDLER_CLASSB_REGWEN + 4'b 0011, // index[308] ALERT_HANDLER_CLASSB_CTRL + 4'b 0001, // index[309] ALERT_HANDLER_CLASSB_CLR_REGWEN + 4'b 0001, // index[310] ALERT_HANDLER_CLASSB_CLR + 4'b 0011, // index[311] ALERT_HANDLER_CLASSB_ACCUM_CNT + 4'b 0011, // index[312] ALERT_HANDLER_CLASSB_ACCUM_THRESH + 4'b 1111, // index[313] ALERT_HANDLER_CLASSB_TIMEOUT_CYC + 4'b 1111, // index[314] ALERT_HANDLER_CLASSB_PHASE0_CYC + 4'b 1111, // index[315] ALERT_HANDLER_CLASSB_PHASE1_CYC + 4'b 1111, // index[316] ALERT_HANDLER_CLASSB_PHASE2_CYC + 4'b 1111, // index[317] ALERT_HANDLER_CLASSB_PHASE3_CYC + 4'b 1111, // index[318] ALERT_HANDLER_CLASSB_ESC_CNT + 4'b 0001, // index[319] ALERT_HANDLER_CLASSB_STATE + 4'b 0001, // index[320] ALERT_HANDLER_CLASSC_REGWEN + 4'b 0011, // index[321] ALERT_HANDLER_CLASSC_CTRL + 4'b 0001, // index[322] ALERT_HANDLER_CLASSC_CLR_REGWEN + 4'b 0001, // index[323] ALERT_HANDLER_CLASSC_CLR + 4'b 0011, // index[324] ALERT_HANDLER_CLASSC_ACCUM_CNT + 4'b 0011, // index[325] ALERT_HANDLER_CLASSC_ACCUM_THRESH + 4'b 1111, // index[326] ALERT_HANDLER_CLASSC_TIMEOUT_CYC + 4'b 1111, // index[327] ALERT_HANDLER_CLASSC_PHASE0_CYC + 4'b 1111, // index[328] ALERT_HANDLER_CLASSC_PHASE1_CYC + 4'b 1111, // index[329] ALERT_HANDLER_CLASSC_PHASE2_CYC + 4'b 1111, // index[330] ALERT_HANDLER_CLASSC_PHASE3_CYC + 4'b 1111, // index[331] ALERT_HANDLER_CLASSC_ESC_CNT + 4'b 0001, // index[332] ALERT_HANDLER_CLASSC_STATE + 4'b 0001, // index[333] ALERT_HANDLER_CLASSD_REGWEN + 4'b 0011, // index[334] ALERT_HANDLER_CLASSD_CTRL + 4'b 0001, // index[335] ALERT_HANDLER_CLASSD_CLR_REGWEN + 4'b 0001, // index[336] ALERT_HANDLER_CLASSD_CLR + 4'b 0011, // index[337] ALERT_HANDLER_CLASSD_ACCUM_CNT + 4'b 0011, // index[338] ALERT_HANDLER_CLASSD_ACCUM_THRESH + 4'b 1111, // index[339] ALERT_HANDLER_CLASSD_TIMEOUT_CYC + 4'b 1111, // index[340] ALERT_HANDLER_CLASSD_PHASE0_CYC + 4'b 1111, // index[341] ALERT_HANDLER_CLASSD_PHASE1_CYC + 4'b 1111, // index[342] ALERT_HANDLER_CLASSD_PHASE2_CYC + 4'b 1111, // index[343] ALERT_HANDLER_CLASSD_PHASE3_CYC + 4'b 1111, // index[344] ALERT_HANDLER_CLASSD_ESC_CNT + 4'b 0001 // index[345] ALERT_HANDLER_CLASSD_STATE }; endpackage
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv index 8476756..084c881 100644 --- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv +++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
@@ -334,6 +334,9 @@ logic alert_regwen_65_we; logic alert_regwen_65_qs; logic alert_regwen_65_wd; + logic alert_regwen_66_we; + logic alert_regwen_66_qs; + logic alert_regwen_66_wd; logic alert_en_0_we; logic alert_en_0_qs; logic alert_en_0_wd; @@ -532,6 +535,9 @@ logic alert_en_65_we; logic alert_en_65_qs; logic alert_en_65_wd; + logic alert_en_66_we; + logic alert_en_66_qs; + logic alert_en_66_wd; logic alert_class_0_we; logic [1:0] alert_class_0_qs; logic [1:0] alert_class_0_wd; @@ -730,6 +736,9 @@ logic alert_class_65_we; logic [1:0] alert_class_65_qs; logic [1:0] alert_class_65_wd; + logic alert_class_66_we; + logic [1:0] alert_class_66_qs; + logic [1:0] alert_class_66_wd; logic alert_cause_0_we; logic alert_cause_0_qs; logic alert_cause_0_wd; @@ -928,6 +937,9 @@ logic alert_cause_65_we; logic alert_cause_65_qs; logic alert_cause_65_wd; + logic alert_cause_66_we; + logic alert_cause_66_qs; + logic alert_cause_66_wd; logic loc_alert_regwen_0_we; logic loc_alert_regwen_0_qs; logic loc_alert_regwen_0_wd; @@ -3340,6 +3352,33 @@ .qs (alert_regwen_65_qs) ); + // Subregister 66 of Multireg alert_regwen + // R[alert_regwen_66]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_alert_regwen_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_66_we), + .wd (alert_regwen_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[66].q), + + // to register interface (read) + .qs (alert_regwen_66_qs) + ); + // Subregister 0 of Multireg alert_en @@ -5124,6 +5163,33 @@ .qs (alert_en_65_qs) ); + // Subregister 66 of Multireg alert_en + // R[alert_en_66]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_alert_en_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_en_66_we & alert_regwen_66_qs), + .wd (alert_en_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en[66].q), + + // to register interface (read) + .qs (alert_en_66_qs) + ); + // Subregister 0 of Multireg alert_class @@ -6908,6 +6974,33 @@ .qs (alert_class_65_qs) ); + // Subregister 66 of Multireg alert_class + // R[alert_class_66]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_alert_class_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_class_66_we & alert_regwen_66_qs), + .wd (alert_class_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class[66].q), + + // to register interface (read) + .qs (alert_class_66_qs) + ); + // Subregister 0 of Multireg alert_cause @@ -8692,6 +8785,33 @@ .qs (alert_cause_65_qs) ); + // Subregister 66 of Multireg alert_cause + // R[alert_cause_66]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_alert_cause_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_66_we), + .wd (alert_cause_66_wd), + + // from internal hardware + .de (hw2reg.alert_cause[66].de), + .d (hw2reg.alert_cause[66].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[66].q), + + // to register interface (read) + .qs (alert_cause_66_qs) + ); + // Subregister 0 of Multireg loc_alert_regwen @@ -11455,7 +11575,7 @@ - logic [341:0] addr_hit; + logic [345:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET); @@ -11530,276 +11650,280 @@ addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_63_OFFSET); addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_64_OFFSET); addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_65_OFFSET); - addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_0_OFFSET); - addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_1_OFFSET); - addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_2_OFFSET); - addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_3_OFFSET); - addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_4_OFFSET); - addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_5_OFFSET); - addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_6_OFFSET); - addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_7_OFFSET); - addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_8_OFFSET); - addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_9_OFFSET); - addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_10_OFFSET); - addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_11_OFFSET); - addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_12_OFFSET); - addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_13_OFFSET); - addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_14_OFFSET); - addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_15_OFFSET); - addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_16_OFFSET); - addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_17_OFFSET); - addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_18_OFFSET); - addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_19_OFFSET); - addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_20_OFFSET); - addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_21_OFFSET); - addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_22_OFFSET); - addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_23_OFFSET); - addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_24_OFFSET); - addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_25_OFFSET); - addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_26_OFFSET); - addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_27_OFFSET); - addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_28_OFFSET); - addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_29_OFFSET); - addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_30_OFFSET); - addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_31_OFFSET); - addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_32_OFFSET); - addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_33_OFFSET); - addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_34_OFFSET); - addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_35_OFFSET); - addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_36_OFFSET); - addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_37_OFFSET); - addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_38_OFFSET); - addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_39_OFFSET); - addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_40_OFFSET); - addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_41_OFFSET); - addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_42_OFFSET); - addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_43_OFFSET); - addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_44_OFFSET); - addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_45_OFFSET); - addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_46_OFFSET); - addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_47_OFFSET); - addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_48_OFFSET); - addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_49_OFFSET); - addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_50_OFFSET); - addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_51_OFFSET); - addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_52_OFFSET); - addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_53_OFFSET); - addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_EN_54_OFFSET); - addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_EN_55_OFFSET); - addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_EN_56_OFFSET); - addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_EN_57_OFFSET); - addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_EN_58_OFFSET); - addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_EN_59_OFFSET); - addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_EN_60_OFFSET); - addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_EN_61_OFFSET); - addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_EN_62_OFFSET); - addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_EN_63_OFFSET); - addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_EN_64_OFFSET); - addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_EN_65_OFFSET); - addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_0_OFFSET); - addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_1_OFFSET); - addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_2_OFFSET); - addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_3_OFFSET); - addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_4_OFFSET); - addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_5_OFFSET); - addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_6_OFFSET); - addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_7_OFFSET); - addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_8_OFFSET); - addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_9_OFFSET); - addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_10_OFFSET); - addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_11_OFFSET); - addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_12_OFFSET); - addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_13_OFFSET); - addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_14_OFFSET); - addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_15_OFFSET); - addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_16_OFFSET); - addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_17_OFFSET); - addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_18_OFFSET); - addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_19_OFFSET); - addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_20_OFFSET); - addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_21_OFFSET); - addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_22_OFFSET); - addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_23_OFFSET); - addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_24_OFFSET); - addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_25_OFFSET); - addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_26_OFFSET); - addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_27_OFFSET); - addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_28_OFFSET); - addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_29_OFFSET); - addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_30_OFFSET); - addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_31_OFFSET); - addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_32_OFFSET); - addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_33_OFFSET); - addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_34_OFFSET); - addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_35_OFFSET); - addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_36_OFFSET); - addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_37_OFFSET); - addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_38_OFFSET); - addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_39_OFFSET); - addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_40_OFFSET); - addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_41_OFFSET); - addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_42_OFFSET); - addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_43_OFFSET); - addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_44_OFFSET); - addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_45_OFFSET); - addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_46_OFFSET); - addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_47_OFFSET); - addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_48_OFFSET); - addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_49_OFFSET); - addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_50_OFFSET); - addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_51_OFFSET); - addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_52_OFFSET); - addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_53_OFFSET); - addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_54_OFFSET); - addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_55_OFFSET); - addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_56_OFFSET); - addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_57_OFFSET); - addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_58_OFFSET); - addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_59_OFFSET); - addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_60_OFFSET); - addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_61_OFFSET); - addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_62_OFFSET); - addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_63_OFFSET); - addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_64_OFFSET); - addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_65_OFFSET); - addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET); - addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET); - addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET); - addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET); - addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET); - addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET); - addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET); - addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET); - addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET); - addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET); - addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET); - addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET); - addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET); - addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET); - addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET); - addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET); - addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET); - addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET); - addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET); - addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET); - addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET); - addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET); - addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET); - addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET); - addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET); - addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET); - addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET); - addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET); - addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET); - addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET); - addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET); - addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET); - addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET); - addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET); - addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET); - addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET); - addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET); - addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET); - addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET); - addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET); - addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET); - addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET); - addr_hit[246] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET); - addr_hit[247] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET); - addr_hit[248] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET); - addr_hit[249] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET); - addr_hit[250] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET); - addr_hit[251] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET); - addr_hit[252] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET); - addr_hit[253] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET); - addr_hit[254] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET); - addr_hit[255] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET); - addr_hit[256] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET); - addr_hit[257] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET); - addr_hit[258] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET); - addr_hit[259] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET); - addr_hit[260] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET); - addr_hit[261] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET); - addr_hit[262] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET); - addr_hit[263] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET); - addr_hit[264] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_60_OFFSET); - addr_hit[265] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_61_OFFSET); - addr_hit[266] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_62_OFFSET); - addr_hit[267] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_63_OFFSET); - addr_hit[268] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_64_OFFSET); - addr_hit[269] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_65_OFFSET); - addr_hit[270] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET); - addr_hit[271] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET); - addr_hit[272] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET); - addr_hit[273] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET); - addr_hit[274] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET); - addr_hit[275] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET); - addr_hit[276] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET); - addr_hit[277] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET); - addr_hit[278] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET); - addr_hit[279] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET); - addr_hit[280] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET); - addr_hit[281] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET); - addr_hit[282] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET); - addr_hit[283] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET); - addr_hit[284] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET); - addr_hit[285] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET); - addr_hit[286] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET); - addr_hit[287] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET); - addr_hit[288] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET); - addr_hit[289] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET); - addr_hit[290] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET); - addr_hit[291] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET); - addr_hit[292] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET); - addr_hit[293] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET); - addr_hit[294] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET); - addr_hit[295] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET); - addr_hit[296] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET); - addr_hit[297] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET); - addr_hit[298] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET); - addr_hit[299] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET); - addr_hit[300] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET); - addr_hit[301] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET); - addr_hit[302] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET); - addr_hit[303] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET); - addr_hit[304] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET); - addr_hit[305] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET); - addr_hit[306] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET); - addr_hit[307] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET); - addr_hit[308] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET); - addr_hit[309] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET); - addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET); - addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET); - addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET); - addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET); - addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET); - addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET); - addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET); - addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET); - addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET); - addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET); - addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET); - addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET); - addr_hit[322] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET); - addr_hit[323] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET); - addr_hit[324] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET); - addr_hit[325] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET); - addr_hit[326] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET); - addr_hit[327] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET); - addr_hit[328] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET); - addr_hit[329] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET); - addr_hit[330] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET); - addr_hit[331] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET); - addr_hit[332] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET); - addr_hit[333] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET); - addr_hit[334] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET); - addr_hit[335] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET); - addr_hit[336] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET); - addr_hit[337] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET); - addr_hit[338] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET); - addr_hit[339] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET); - addr_hit[340] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET); - addr_hit[341] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET); + addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_66_OFFSET); + addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_0_OFFSET); + addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_1_OFFSET); + addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_2_OFFSET); + addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_3_OFFSET); + addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_4_OFFSET); + addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_5_OFFSET); + addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_6_OFFSET); + addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_7_OFFSET); + addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_8_OFFSET); + addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_9_OFFSET); + addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_10_OFFSET); + addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_11_OFFSET); + addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_12_OFFSET); + addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_13_OFFSET); + addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_14_OFFSET); + addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_15_OFFSET); + addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_16_OFFSET); + addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_17_OFFSET); + addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_18_OFFSET); + addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_19_OFFSET); + addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_20_OFFSET); + addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_21_OFFSET); + addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_22_OFFSET); + addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_23_OFFSET); + addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_24_OFFSET); + addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_25_OFFSET); + addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_26_OFFSET); + addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_27_OFFSET); + addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_28_OFFSET); + addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_29_OFFSET); + addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_30_OFFSET); + addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_31_OFFSET); + addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_32_OFFSET); + addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_33_OFFSET); + addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_34_OFFSET); + addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_35_OFFSET); + addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_36_OFFSET); + addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_37_OFFSET); + addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_38_OFFSET); + addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_39_OFFSET); + addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_40_OFFSET); + addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_41_OFFSET); + addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_42_OFFSET); + addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_43_OFFSET); + addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_44_OFFSET); + addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_45_OFFSET); + addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_46_OFFSET); + addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_47_OFFSET); + addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_48_OFFSET); + addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_49_OFFSET); + addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_50_OFFSET); + addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_51_OFFSET); + addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_52_OFFSET); + addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_EN_53_OFFSET); + addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_EN_54_OFFSET); + addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_EN_55_OFFSET); + addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_EN_56_OFFSET); + addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_EN_57_OFFSET); + addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_EN_58_OFFSET); + addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_EN_59_OFFSET); + addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_EN_60_OFFSET); + addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_EN_61_OFFSET); + addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_EN_62_OFFSET); + addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_EN_63_OFFSET); + addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_EN_64_OFFSET); + addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_EN_65_OFFSET); + addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_EN_66_OFFSET); + addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_0_OFFSET); + addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_1_OFFSET); + addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_2_OFFSET); + addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_3_OFFSET); + addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_4_OFFSET); + addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_5_OFFSET); + addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_6_OFFSET); + addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_7_OFFSET); + addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_8_OFFSET); + addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_9_OFFSET); + addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_10_OFFSET); + addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_11_OFFSET); + addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_12_OFFSET); + addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_13_OFFSET); + addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_14_OFFSET); + addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_15_OFFSET); + addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_16_OFFSET); + addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_17_OFFSET); + addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_18_OFFSET); + addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_19_OFFSET); + addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_20_OFFSET); + addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_21_OFFSET); + addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_22_OFFSET); + addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_23_OFFSET); + addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_24_OFFSET); + addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_25_OFFSET); + addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_26_OFFSET); + addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_27_OFFSET); + addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_28_OFFSET); + addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_29_OFFSET); + addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_30_OFFSET); + addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_31_OFFSET); + addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_32_OFFSET); + addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_33_OFFSET); + addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_34_OFFSET); + addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_35_OFFSET); + addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_36_OFFSET); + addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_37_OFFSET); + addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_38_OFFSET); + addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_39_OFFSET); + addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_40_OFFSET); + addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_41_OFFSET); + addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_42_OFFSET); + addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_43_OFFSET); + addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_44_OFFSET); + addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_45_OFFSET); + addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_46_OFFSET); + addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_47_OFFSET); + addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_48_OFFSET); + addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_49_OFFSET); + addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_50_OFFSET); + addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_51_OFFSET); + addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_52_OFFSET); + addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_53_OFFSET); + addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_54_OFFSET); + addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_55_OFFSET); + addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_56_OFFSET); + addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_57_OFFSET); + addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_58_OFFSET); + addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_59_OFFSET); + addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_60_OFFSET); + addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_61_OFFSET); + addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_62_OFFSET); + addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_63_OFFSET); + addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_64_OFFSET); + addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_65_OFFSET); + addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_66_OFFSET); + addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET); + addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET); + addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET); + addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET); + addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET); + addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET); + addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET); + addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET); + addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET); + addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET); + addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET); + addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET); + addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET); + addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET); + addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET); + addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET); + addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET); + addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET); + addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET); + addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET); + addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET); + addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET); + addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET); + addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET); + addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET); + addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET); + addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET); + addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET); + addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET); + addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET); + addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET); + addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET); + addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET); + addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET); + addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET); + addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET); + addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET); + addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET); + addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET); + addr_hit[246] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET); + addr_hit[247] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET); + addr_hit[248] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET); + addr_hit[249] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET); + addr_hit[250] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET); + addr_hit[251] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET); + addr_hit[252] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET); + addr_hit[253] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET); + addr_hit[254] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET); + addr_hit[255] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET); + addr_hit[256] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET); + addr_hit[257] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET); + addr_hit[258] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET); + addr_hit[259] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET); + addr_hit[260] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET); + addr_hit[261] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET); + addr_hit[262] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET); + addr_hit[263] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET); + addr_hit[264] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET); + addr_hit[265] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET); + addr_hit[266] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET); + addr_hit[267] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_60_OFFSET); + addr_hit[268] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_61_OFFSET); + addr_hit[269] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_62_OFFSET); + addr_hit[270] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_63_OFFSET); + addr_hit[271] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_64_OFFSET); + addr_hit[272] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_65_OFFSET); + addr_hit[273] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_66_OFFSET); + addr_hit[274] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET); + addr_hit[275] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET); + addr_hit[276] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET); + addr_hit[277] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET); + addr_hit[278] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET); + addr_hit[279] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET); + addr_hit[280] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET); + addr_hit[281] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET); + addr_hit[282] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET); + addr_hit[283] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET); + addr_hit[284] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET); + addr_hit[285] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET); + addr_hit[286] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET); + addr_hit[287] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET); + addr_hit[288] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET); + addr_hit[289] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET); + addr_hit[290] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET); + addr_hit[291] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET); + addr_hit[292] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET); + addr_hit[293] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET); + addr_hit[294] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET); + addr_hit[295] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET); + addr_hit[296] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET); + addr_hit[297] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET); + addr_hit[298] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET); + addr_hit[299] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET); + addr_hit[300] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET); + addr_hit[301] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET); + addr_hit[302] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET); + addr_hit[303] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET); + addr_hit[304] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET); + addr_hit[305] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET); + addr_hit[306] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET); + addr_hit[307] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET); + addr_hit[308] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET); + addr_hit[309] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET); + addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET); + addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET); + addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET); + addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET); + addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET); + addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET); + addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET); + addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET); + addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET); + addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET); + addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET); + addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET); + addr_hit[322] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET); + addr_hit[323] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET); + addr_hit[324] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET); + addr_hit[325] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET); + addr_hit[326] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET); + addr_hit[327] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET); + addr_hit[328] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET); + addr_hit[329] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET); + addr_hit[330] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET); + addr_hit[331] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET); + addr_hit[332] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET); + addr_hit[333] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET); + addr_hit[334] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET); + addr_hit[335] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET); + addr_hit[336] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET); + addr_hit[337] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET); + addr_hit[338] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET); + addr_hit[339] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET); + addr_hit[340] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET); + addr_hit[341] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET); + addr_hit[342] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET); + addr_hit[343] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET); + addr_hit[344] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET); + addr_hit[345] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -12148,7 +12272,11 @@ (addr_hit[338] & (|(ALERT_HANDLER_PERMIT[338] & ~reg_be))) | (addr_hit[339] & (|(ALERT_HANDLER_PERMIT[339] & ~reg_be))) | (addr_hit[340] & (|(ALERT_HANDLER_PERMIT[340] & ~reg_be))) | - (addr_hit[341] & (|(ALERT_HANDLER_PERMIT[341] & ~reg_be))))); + (addr_hit[341] & (|(ALERT_HANDLER_PERMIT[341] & ~reg_be))) | + (addr_hit[342] & (|(ALERT_HANDLER_PERMIT[342] & ~reg_be))) | + (addr_hit[343] & (|(ALERT_HANDLER_PERMIT[343] & ~reg_be))) | + (addr_hit[344] & (|(ALERT_HANDLER_PERMIT[344] & ~reg_be))) | + (addr_hit[345] & (|(ALERT_HANDLER_PERMIT[345] & ~reg_be))))); end assign intr_state_we = addr_hit[0] & reg_we & !reg_error; @@ -12384,664 +12512,676 @@ assign alert_regwen_65_we = addr_hit[71] & reg_we & !reg_error; assign alert_regwen_65_wd = reg_wdata[0]; - assign alert_en_0_we = addr_hit[72] & reg_we & !reg_error; + assign alert_regwen_66_we = addr_hit[72] & reg_we & !reg_error; + + assign alert_regwen_66_wd = reg_wdata[0]; + assign alert_en_0_we = addr_hit[73] & reg_we & !reg_error; assign alert_en_0_wd = reg_wdata[0]; - assign alert_en_1_we = addr_hit[73] & reg_we & !reg_error; + assign alert_en_1_we = addr_hit[74] & reg_we & !reg_error; assign alert_en_1_wd = reg_wdata[0]; - assign alert_en_2_we = addr_hit[74] & reg_we & !reg_error; + assign alert_en_2_we = addr_hit[75] & reg_we & !reg_error; assign alert_en_2_wd = reg_wdata[0]; - assign alert_en_3_we = addr_hit[75] & reg_we & !reg_error; + assign alert_en_3_we = addr_hit[76] & reg_we & !reg_error; assign alert_en_3_wd = reg_wdata[0]; - assign alert_en_4_we = addr_hit[76] & reg_we & !reg_error; + assign alert_en_4_we = addr_hit[77] & reg_we & !reg_error; assign alert_en_4_wd = reg_wdata[0]; - assign alert_en_5_we = addr_hit[77] & reg_we & !reg_error; + assign alert_en_5_we = addr_hit[78] & reg_we & !reg_error; assign alert_en_5_wd = reg_wdata[0]; - assign alert_en_6_we = addr_hit[78] & reg_we & !reg_error; + assign alert_en_6_we = addr_hit[79] & reg_we & !reg_error; assign alert_en_6_wd = reg_wdata[0]; - assign alert_en_7_we = addr_hit[79] & reg_we & !reg_error; + assign alert_en_7_we = addr_hit[80] & reg_we & !reg_error; assign alert_en_7_wd = reg_wdata[0]; - assign alert_en_8_we = addr_hit[80] & reg_we & !reg_error; + assign alert_en_8_we = addr_hit[81] & reg_we & !reg_error; assign alert_en_8_wd = reg_wdata[0]; - assign alert_en_9_we = addr_hit[81] & reg_we & !reg_error; + assign alert_en_9_we = addr_hit[82] & reg_we & !reg_error; assign alert_en_9_wd = reg_wdata[0]; - assign alert_en_10_we = addr_hit[82] & reg_we & !reg_error; + assign alert_en_10_we = addr_hit[83] & reg_we & !reg_error; assign alert_en_10_wd = reg_wdata[0]; - assign alert_en_11_we = addr_hit[83] & reg_we & !reg_error; + assign alert_en_11_we = addr_hit[84] & reg_we & !reg_error; assign alert_en_11_wd = reg_wdata[0]; - assign alert_en_12_we = addr_hit[84] & reg_we & !reg_error; + assign alert_en_12_we = addr_hit[85] & reg_we & !reg_error; assign alert_en_12_wd = reg_wdata[0]; - assign alert_en_13_we = addr_hit[85] & reg_we & !reg_error; + assign alert_en_13_we = addr_hit[86] & reg_we & !reg_error; assign alert_en_13_wd = reg_wdata[0]; - assign alert_en_14_we = addr_hit[86] & reg_we & !reg_error; + assign alert_en_14_we = addr_hit[87] & reg_we & !reg_error; assign alert_en_14_wd = reg_wdata[0]; - assign alert_en_15_we = addr_hit[87] & reg_we & !reg_error; + assign alert_en_15_we = addr_hit[88] & reg_we & !reg_error; assign alert_en_15_wd = reg_wdata[0]; - assign alert_en_16_we = addr_hit[88] & reg_we & !reg_error; + assign alert_en_16_we = addr_hit[89] & reg_we & !reg_error; assign alert_en_16_wd = reg_wdata[0]; - assign alert_en_17_we = addr_hit[89] & reg_we & !reg_error; + assign alert_en_17_we = addr_hit[90] & reg_we & !reg_error; assign alert_en_17_wd = reg_wdata[0]; - assign alert_en_18_we = addr_hit[90] & reg_we & !reg_error; + assign alert_en_18_we = addr_hit[91] & reg_we & !reg_error; assign alert_en_18_wd = reg_wdata[0]; - assign alert_en_19_we = addr_hit[91] & reg_we & !reg_error; + assign alert_en_19_we = addr_hit[92] & reg_we & !reg_error; assign alert_en_19_wd = reg_wdata[0]; - assign alert_en_20_we = addr_hit[92] & reg_we & !reg_error; + assign alert_en_20_we = addr_hit[93] & reg_we & !reg_error; assign alert_en_20_wd = reg_wdata[0]; - assign alert_en_21_we = addr_hit[93] & reg_we & !reg_error; + assign alert_en_21_we = addr_hit[94] & reg_we & !reg_error; assign alert_en_21_wd = reg_wdata[0]; - assign alert_en_22_we = addr_hit[94] & reg_we & !reg_error; + assign alert_en_22_we = addr_hit[95] & reg_we & !reg_error; assign alert_en_22_wd = reg_wdata[0]; - assign alert_en_23_we = addr_hit[95] & reg_we & !reg_error; + assign alert_en_23_we = addr_hit[96] & reg_we & !reg_error; assign alert_en_23_wd = reg_wdata[0]; - assign alert_en_24_we = addr_hit[96] & reg_we & !reg_error; + assign alert_en_24_we = addr_hit[97] & reg_we & !reg_error; assign alert_en_24_wd = reg_wdata[0]; - assign alert_en_25_we = addr_hit[97] & reg_we & !reg_error; + assign alert_en_25_we = addr_hit[98] & reg_we & !reg_error; assign alert_en_25_wd = reg_wdata[0]; - assign alert_en_26_we = addr_hit[98] & reg_we & !reg_error; + assign alert_en_26_we = addr_hit[99] & reg_we & !reg_error; assign alert_en_26_wd = reg_wdata[0]; - assign alert_en_27_we = addr_hit[99] & reg_we & !reg_error; + assign alert_en_27_we = addr_hit[100] & reg_we & !reg_error; assign alert_en_27_wd = reg_wdata[0]; - assign alert_en_28_we = addr_hit[100] & reg_we & !reg_error; + assign alert_en_28_we = addr_hit[101] & reg_we & !reg_error; assign alert_en_28_wd = reg_wdata[0]; - assign alert_en_29_we = addr_hit[101] & reg_we & !reg_error; + assign alert_en_29_we = addr_hit[102] & reg_we & !reg_error; assign alert_en_29_wd = reg_wdata[0]; - assign alert_en_30_we = addr_hit[102] & reg_we & !reg_error; + assign alert_en_30_we = addr_hit[103] & reg_we & !reg_error; assign alert_en_30_wd = reg_wdata[0]; - assign alert_en_31_we = addr_hit[103] & reg_we & !reg_error; + assign alert_en_31_we = addr_hit[104] & reg_we & !reg_error; assign alert_en_31_wd = reg_wdata[0]; - assign alert_en_32_we = addr_hit[104] & reg_we & !reg_error; + assign alert_en_32_we = addr_hit[105] & reg_we & !reg_error; assign alert_en_32_wd = reg_wdata[0]; - assign alert_en_33_we = addr_hit[105] & reg_we & !reg_error; + assign alert_en_33_we = addr_hit[106] & reg_we & !reg_error; assign alert_en_33_wd = reg_wdata[0]; - assign alert_en_34_we = addr_hit[106] & reg_we & !reg_error; + assign alert_en_34_we = addr_hit[107] & reg_we & !reg_error; assign alert_en_34_wd = reg_wdata[0]; - assign alert_en_35_we = addr_hit[107] & reg_we & !reg_error; + assign alert_en_35_we = addr_hit[108] & reg_we & !reg_error; assign alert_en_35_wd = reg_wdata[0]; - assign alert_en_36_we = addr_hit[108] & reg_we & !reg_error; + assign alert_en_36_we = addr_hit[109] & reg_we & !reg_error; assign alert_en_36_wd = reg_wdata[0]; - assign alert_en_37_we = addr_hit[109] & reg_we & !reg_error; + assign alert_en_37_we = addr_hit[110] & reg_we & !reg_error; assign alert_en_37_wd = reg_wdata[0]; - assign alert_en_38_we = addr_hit[110] & reg_we & !reg_error; + assign alert_en_38_we = addr_hit[111] & reg_we & !reg_error; assign alert_en_38_wd = reg_wdata[0]; - assign alert_en_39_we = addr_hit[111] & reg_we & !reg_error; + assign alert_en_39_we = addr_hit[112] & reg_we & !reg_error; assign alert_en_39_wd = reg_wdata[0]; - assign alert_en_40_we = addr_hit[112] & reg_we & !reg_error; + assign alert_en_40_we = addr_hit[113] & reg_we & !reg_error; assign alert_en_40_wd = reg_wdata[0]; - assign alert_en_41_we = addr_hit[113] & reg_we & !reg_error; + assign alert_en_41_we = addr_hit[114] & reg_we & !reg_error; assign alert_en_41_wd = reg_wdata[0]; - assign alert_en_42_we = addr_hit[114] & reg_we & !reg_error; + assign alert_en_42_we = addr_hit[115] & reg_we & !reg_error; assign alert_en_42_wd = reg_wdata[0]; - assign alert_en_43_we = addr_hit[115] & reg_we & !reg_error; + assign alert_en_43_we = addr_hit[116] & reg_we & !reg_error; assign alert_en_43_wd = reg_wdata[0]; - assign alert_en_44_we = addr_hit[116] & reg_we & !reg_error; + assign alert_en_44_we = addr_hit[117] & reg_we & !reg_error; assign alert_en_44_wd = reg_wdata[0]; - assign alert_en_45_we = addr_hit[117] & reg_we & !reg_error; + assign alert_en_45_we = addr_hit[118] & reg_we & !reg_error; assign alert_en_45_wd = reg_wdata[0]; - assign alert_en_46_we = addr_hit[118] & reg_we & !reg_error; + assign alert_en_46_we = addr_hit[119] & reg_we & !reg_error; assign alert_en_46_wd = reg_wdata[0]; - assign alert_en_47_we = addr_hit[119] & reg_we & !reg_error; + assign alert_en_47_we = addr_hit[120] & reg_we & !reg_error; assign alert_en_47_wd = reg_wdata[0]; - assign alert_en_48_we = addr_hit[120] & reg_we & !reg_error; + assign alert_en_48_we = addr_hit[121] & reg_we & !reg_error; assign alert_en_48_wd = reg_wdata[0]; - assign alert_en_49_we = addr_hit[121] & reg_we & !reg_error; + assign alert_en_49_we = addr_hit[122] & reg_we & !reg_error; assign alert_en_49_wd = reg_wdata[0]; - assign alert_en_50_we = addr_hit[122] & reg_we & !reg_error; + assign alert_en_50_we = addr_hit[123] & reg_we & !reg_error; assign alert_en_50_wd = reg_wdata[0]; - assign alert_en_51_we = addr_hit[123] & reg_we & !reg_error; + assign alert_en_51_we = addr_hit[124] & reg_we & !reg_error; assign alert_en_51_wd = reg_wdata[0]; - assign alert_en_52_we = addr_hit[124] & reg_we & !reg_error; + assign alert_en_52_we = addr_hit[125] & reg_we & !reg_error; assign alert_en_52_wd = reg_wdata[0]; - assign alert_en_53_we = addr_hit[125] & reg_we & !reg_error; + assign alert_en_53_we = addr_hit[126] & reg_we & !reg_error; assign alert_en_53_wd = reg_wdata[0]; - assign alert_en_54_we = addr_hit[126] & reg_we & !reg_error; + assign alert_en_54_we = addr_hit[127] & reg_we & !reg_error; assign alert_en_54_wd = reg_wdata[0]; - assign alert_en_55_we = addr_hit[127] & reg_we & !reg_error; + assign alert_en_55_we = addr_hit[128] & reg_we & !reg_error; assign alert_en_55_wd = reg_wdata[0]; - assign alert_en_56_we = addr_hit[128] & reg_we & !reg_error; + assign alert_en_56_we = addr_hit[129] & reg_we & !reg_error; assign alert_en_56_wd = reg_wdata[0]; - assign alert_en_57_we = addr_hit[129] & reg_we & !reg_error; + assign alert_en_57_we = addr_hit[130] & reg_we & !reg_error; assign alert_en_57_wd = reg_wdata[0]; - assign alert_en_58_we = addr_hit[130] & reg_we & !reg_error; + assign alert_en_58_we = addr_hit[131] & reg_we & !reg_error; assign alert_en_58_wd = reg_wdata[0]; - assign alert_en_59_we = addr_hit[131] & reg_we & !reg_error; + assign alert_en_59_we = addr_hit[132] & reg_we & !reg_error; assign alert_en_59_wd = reg_wdata[0]; - assign alert_en_60_we = addr_hit[132] & reg_we & !reg_error; + assign alert_en_60_we = addr_hit[133] & reg_we & !reg_error; assign alert_en_60_wd = reg_wdata[0]; - assign alert_en_61_we = addr_hit[133] & reg_we & !reg_error; + assign alert_en_61_we = addr_hit[134] & reg_we & !reg_error; assign alert_en_61_wd = reg_wdata[0]; - assign alert_en_62_we = addr_hit[134] & reg_we & !reg_error; + assign alert_en_62_we = addr_hit[135] & reg_we & !reg_error; assign alert_en_62_wd = reg_wdata[0]; - assign alert_en_63_we = addr_hit[135] & reg_we & !reg_error; + assign alert_en_63_we = addr_hit[136] & reg_we & !reg_error; assign alert_en_63_wd = reg_wdata[0]; - assign alert_en_64_we = addr_hit[136] & reg_we & !reg_error; + assign alert_en_64_we = addr_hit[137] & reg_we & !reg_error; assign alert_en_64_wd = reg_wdata[0]; - assign alert_en_65_we = addr_hit[137] & reg_we & !reg_error; + assign alert_en_65_we = addr_hit[138] & reg_we & !reg_error; assign alert_en_65_wd = reg_wdata[0]; - assign alert_class_0_we = addr_hit[138] & reg_we & !reg_error; + assign alert_en_66_we = addr_hit[139] & reg_we & !reg_error; + + assign alert_en_66_wd = reg_wdata[0]; + assign alert_class_0_we = addr_hit[140] & reg_we & !reg_error; assign alert_class_0_wd = reg_wdata[1:0]; - assign alert_class_1_we = addr_hit[139] & reg_we & !reg_error; + assign alert_class_1_we = addr_hit[141] & reg_we & !reg_error; assign alert_class_1_wd = reg_wdata[1:0]; - assign alert_class_2_we = addr_hit[140] & reg_we & !reg_error; + assign alert_class_2_we = addr_hit[142] & reg_we & !reg_error; assign alert_class_2_wd = reg_wdata[1:0]; - assign alert_class_3_we = addr_hit[141] & reg_we & !reg_error; + assign alert_class_3_we = addr_hit[143] & reg_we & !reg_error; assign alert_class_3_wd = reg_wdata[1:0]; - assign alert_class_4_we = addr_hit[142] & reg_we & !reg_error; + assign alert_class_4_we = addr_hit[144] & reg_we & !reg_error; assign alert_class_4_wd = reg_wdata[1:0]; - assign alert_class_5_we = addr_hit[143] & reg_we & !reg_error; + assign alert_class_5_we = addr_hit[145] & reg_we & !reg_error; assign alert_class_5_wd = reg_wdata[1:0]; - assign alert_class_6_we = addr_hit[144] & reg_we & !reg_error; + assign alert_class_6_we = addr_hit[146] & reg_we & !reg_error; assign alert_class_6_wd = reg_wdata[1:0]; - assign alert_class_7_we = addr_hit[145] & reg_we & !reg_error; + assign alert_class_7_we = addr_hit[147] & reg_we & !reg_error; assign alert_class_7_wd = reg_wdata[1:0]; - assign alert_class_8_we = addr_hit[146] & reg_we & !reg_error; + assign alert_class_8_we = addr_hit[148] & reg_we & !reg_error; assign alert_class_8_wd = reg_wdata[1:0]; - assign alert_class_9_we = addr_hit[147] & reg_we & !reg_error; + assign alert_class_9_we = addr_hit[149] & reg_we & !reg_error; assign alert_class_9_wd = reg_wdata[1:0]; - assign alert_class_10_we = addr_hit[148] & reg_we & !reg_error; + assign alert_class_10_we = addr_hit[150] & reg_we & !reg_error; assign alert_class_10_wd = reg_wdata[1:0]; - assign alert_class_11_we = addr_hit[149] & reg_we & !reg_error; + assign alert_class_11_we = addr_hit[151] & reg_we & !reg_error; assign alert_class_11_wd = reg_wdata[1:0]; - assign alert_class_12_we = addr_hit[150] & reg_we & !reg_error; + assign alert_class_12_we = addr_hit[152] & reg_we & !reg_error; assign alert_class_12_wd = reg_wdata[1:0]; - assign alert_class_13_we = addr_hit[151] & reg_we & !reg_error; + assign alert_class_13_we = addr_hit[153] & reg_we & !reg_error; assign alert_class_13_wd = reg_wdata[1:0]; - assign alert_class_14_we = addr_hit[152] & reg_we & !reg_error; + assign alert_class_14_we = addr_hit[154] & reg_we & !reg_error; assign alert_class_14_wd = reg_wdata[1:0]; - assign alert_class_15_we = addr_hit[153] & reg_we & !reg_error; + assign alert_class_15_we = addr_hit[155] & reg_we & !reg_error; assign alert_class_15_wd = reg_wdata[1:0]; - assign alert_class_16_we = addr_hit[154] & reg_we & !reg_error; + assign alert_class_16_we = addr_hit[156] & reg_we & !reg_error; assign alert_class_16_wd = reg_wdata[1:0]; - assign alert_class_17_we = addr_hit[155] & reg_we & !reg_error; + assign alert_class_17_we = addr_hit[157] & reg_we & !reg_error; assign alert_class_17_wd = reg_wdata[1:0]; - assign alert_class_18_we = addr_hit[156] & reg_we & !reg_error; + assign alert_class_18_we = addr_hit[158] & reg_we & !reg_error; assign alert_class_18_wd = reg_wdata[1:0]; - assign alert_class_19_we = addr_hit[157] & reg_we & !reg_error; + assign alert_class_19_we = addr_hit[159] & reg_we & !reg_error; assign alert_class_19_wd = reg_wdata[1:0]; - assign alert_class_20_we = addr_hit[158] & reg_we & !reg_error; + assign alert_class_20_we = addr_hit[160] & reg_we & !reg_error; assign alert_class_20_wd = reg_wdata[1:0]; - assign alert_class_21_we = addr_hit[159] & reg_we & !reg_error; + assign alert_class_21_we = addr_hit[161] & reg_we & !reg_error; assign alert_class_21_wd = reg_wdata[1:0]; - assign alert_class_22_we = addr_hit[160] & reg_we & !reg_error; + assign alert_class_22_we = addr_hit[162] & reg_we & !reg_error; assign alert_class_22_wd = reg_wdata[1:0]; - assign alert_class_23_we = addr_hit[161] & reg_we & !reg_error; + assign alert_class_23_we = addr_hit[163] & reg_we & !reg_error; assign alert_class_23_wd = reg_wdata[1:0]; - assign alert_class_24_we = addr_hit[162] & reg_we & !reg_error; + assign alert_class_24_we = addr_hit[164] & reg_we & !reg_error; assign alert_class_24_wd = reg_wdata[1:0]; - assign alert_class_25_we = addr_hit[163] & reg_we & !reg_error; + assign alert_class_25_we = addr_hit[165] & reg_we & !reg_error; assign alert_class_25_wd = reg_wdata[1:0]; - assign alert_class_26_we = addr_hit[164] & reg_we & !reg_error; + assign alert_class_26_we = addr_hit[166] & reg_we & !reg_error; assign alert_class_26_wd = reg_wdata[1:0]; - assign alert_class_27_we = addr_hit[165] & reg_we & !reg_error; + assign alert_class_27_we = addr_hit[167] & reg_we & !reg_error; assign alert_class_27_wd = reg_wdata[1:0]; - assign alert_class_28_we = addr_hit[166] & reg_we & !reg_error; + assign alert_class_28_we = addr_hit[168] & reg_we & !reg_error; assign alert_class_28_wd = reg_wdata[1:0]; - assign alert_class_29_we = addr_hit[167] & reg_we & !reg_error; + assign alert_class_29_we = addr_hit[169] & reg_we & !reg_error; assign alert_class_29_wd = reg_wdata[1:0]; - assign alert_class_30_we = addr_hit[168] & reg_we & !reg_error; + assign alert_class_30_we = addr_hit[170] & reg_we & !reg_error; assign alert_class_30_wd = reg_wdata[1:0]; - assign alert_class_31_we = addr_hit[169] & reg_we & !reg_error; + assign alert_class_31_we = addr_hit[171] & reg_we & !reg_error; assign alert_class_31_wd = reg_wdata[1:0]; - assign alert_class_32_we = addr_hit[170] & reg_we & !reg_error; + assign alert_class_32_we = addr_hit[172] & reg_we & !reg_error; assign alert_class_32_wd = reg_wdata[1:0]; - assign alert_class_33_we = addr_hit[171] & reg_we & !reg_error; + assign alert_class_33_we = addr_hit[173] & reg_we & !reg_error; assign alert_class_33_wd = reg_wdata[1:0]; - assign alert_class_34_we = addr_hit[172] & reg_we & !reg_error; + assign alert_class_34_we = addr_hit[174] & reg_we & !reg_error; assign alert_class_34_wd = reg_wdata[1:0]; - assign alert_class_35_we = addr_hit[173] & reg_we & !reg_error; + assign alert_class_35_we = addr_hit[175] & reg_we & !reg_error; assign alert_class_35_wd = reg_wdata[1:0]; - assign alert_class_36_we = addr_hit[174] & reg_we & !reg_error; + assign alert_class_36_we = addr_hit[176] & reg_we & !reg_error; assign alert_class_36_wd = reg_wdata[1:0]; - assign alert_class_37_we = addr_hit[175] & reg_we & !reg_error; + assign alert_class_37_we = addr_hit[177] & reg_we & !reg_error; assign alert_class_37_wd = reg_wdata[1:0]; - assign alert_class_38_we = addr_hit[176] & reg_we & !reg_error; + assign alert_class_38_we = addr_hit[178] & reg_we & !reg_error; assign alert_class_38_wd = reg_wdata[1:0]; - assign alert_class_39_we = addr_hit[177] & reg_we & !reg_error; + assign alert_class_39_we = addr_hit[179] & reg_we & !reg_error; assign alert_class_39_wd = reg_wdata[1:0]; - assign alert_class_40_we = addr_hit[178] & reg_we & !reg_error; + assign alert_class_40_we = addr_hit[180] & reg_we & !reg_error; assign alert_class_40_wd = reg_wdata[1:0]; - assign alert_class_41_we = addr_hit[179] & reg_we & !reg_error; + assign alert_class_41_we = addr_hit[181] & reg_we & !reg_error; assign alert_class_41_wd = reg_wdata[1:0]; - assign alert_class_42_we = addr_hit[180] & reg_we & !reg_error; + assign alert_class_42_we = addr_hit[182] & reg_we & !reg_error; assign alert_class_42_wd = reg_wdata[1:0]; - assign alert_class_43_we = addr_hit[181] & reg_we & !reg_error; + assign alert_class_43_we = addr_hit[183] & reg_we & !reg_error; assign alert_class_43_wd = reg_wdata[1:0]; - assign alert_class_44_we = addr_hit[182] & reg_we & !reg_error; + assign alert_class_44_we = addr_hit[184] & reg_we & !reg_error; assign alert_class_44_wd = reg_wdata[1:0]; - assign alert_class_45_we = addr_hit[183] & reg_we & !reg_error; + assign alert_class_45_we = addr_hit[185] & reg_we & !reg_error; assign alert_class_45_wd = reg_wdata[1:0]; - assign alert_class_46_we = addr_hit[184] & reg_we & !reg_error; + assign alert_class_46_we = addr_hit[186] & reg_we & !reg_error; assign alert_class_46_wd = reg_wdata[1:0]; - assign alert_class_47_we = addr_hit[185] & reg_we & !reg_error; + assign alert_class_47_we = addr_hit[187] & reg_we & !reg_error; assign alert_class_47_wd = reg_wdata[1:0]; - assign alert_class_48_we = addr_hit[186] & reg_we & !reg_error; + assign alert_class_48_we = addr_hit[188] & reg_we & !reg_error; assign alert_class_48_wd = reg_wdata[1:0]; - assign alert_class_49_we = addr_hit[187] & reg_we & !reg_error; + assign alert_class_49_we = addr_hit[189] & reg_we & !reg_error; assign alert_class_49_wd = reg_wdata[1:0]; - assign alert_class_50_we = addr_hit[188] & reg_we & !reg_error; + assign alert_class_50_we = addr_hit[190] & reg_we & !reg_error; assign alert_class_50_wd = reg_wdata[1:0]; - assign alert_class_51_we = addr_hit[189] & reg_we & !reg_error; + assign alert_class_51_we = addr_hit[191] & reg_we & !reg_error; assign alert_class_51_wd = reg_wdata[1:0]; - assign alert_class_52_we = addr_hit[190] & reg_we & !reg_error; + assign alert_class_52_we = addr_hit[192] & reg_we & !reg_error; assign alert_class_52_wd = reg_wdata[1:0]; - assign alert_class_53_we = addr_hit[191] & reg_we & !reg_error; + assign alert_class_53_we = addr_hit[193] & reg_we & !reg_error; assign alert_class_53_wd = reg_wdata[1:0]; - assign alert_class_54_we = addr_hit[192] & reg_we & !reg_error; + assign alert_class_54_we = addr_hit[194] & reg_we & !reg_error; assign alert_class_54_wd = reg_wdata[1:0]; - assign alert_class_55_we = addr_hit[193] & reg_we & !reg_error; + assign alert_class_55_we = addr_hit[195] & reg_we & !reg_error; assign alert_class_55_wd = reg_wdata[1:0]; - assign alert_class_56_we = addr_hit[194] & reg_we & !reg_error; + assign alert_class_56_we = addr_hit[196] & reg_we & !reg_error; assign alert_class_56_wd = reg_wdata[1:0]; - assign alert_class_57_we = addr_hit[195] & reg_we & !reg_error; + assign alert_class_57_we = addr_hit[197] & reg_we & !reg_error; assign alert_class_57_wd = reg_wdata[1:0]; - assign alert_class_58_we = addr_hit[196] & reg_we & !reg_error; + assign alert_class_58_we = addr_hit[198] & reg_we & !reg_error; assign alert_class_58_wd = reg_wdata[1:0]; - assign alert_class_59_we = addr_hit[197] & reg_we & !reg_error; + assign alert_class_59_we = addr_hit[199] & reg_we & !reg_error; assign alert_class_59_wd = reg_wdata[1:0]; - assign alert_class_60_we = addr_hit[198] & reg_we & !reg_error; + assign alert_class_60_we = addr_hit[200] & reg_we & !reg_error; assign alert_class_60_wd = reg_wdata[1:0]; - assign alert_class_61_we = addr_hit[199] & reg_we & !reg_error; + assign alert_class_61_we = addr_hit[201] & reg_we & !reg_error; assign alert_class_61_wd = reg_wdata[1:0]; - assign alert_class_62_we = addr_hit[200] & reg_we & !reg_error; + assign alert_class_62_we = addr_hit[202] & reg_we & !reg_error; assign alert_class_62_wd = reg_wdata[1:0]; - assign alert_class_63_we = addr_hit[201] & reg_we & !reg_error; + assign alert_class_63_we = addr_hit[203] & reg_we & !reg_error; assign alert_class_63_wd = reg_wdata[1:0]; - assign alert_class_64_we = addr_hit[202] & reg_we & !reg_error; + assign alert_class_64_we = addr_hit[204] & reg_we & !reg_error; assign alert_class_64_wd = reg_wdata[1:0]; - assign alert_class_65_we = addr_hit[203] & reg_we & !reg_error; + assign alert_class_65_we = addr_hit[205] & reg_we & !reg_error; assign alert_class_65_wd = reg_wdata[1:0]; - assign alert_cause_0_we = addr_hit[204] & reg_we & !reg_error; + assign alert_class_66_we = addr_hit[206] & reg_we & !reg_error; + + assign alert_class_66_wd = reg_wdata[1:0]; + assign alert_cause_0_we = addr_hit[207] & reg_we & !reg_error; assign alert_cause_0_wd = reg_wdata[0]; - assign alert_cause_1_we = addr_hit[205] & reg_we & !reg_error; + assign alert_cause_1_we = addr_hit[208] & reg_we & !reg_error; assign alert_cause_1_wd = reg_wdata[0]; - assign alert_cause_2_we = addr_hit[206] & reg_we & !reg_error; + assign alert_cause_2_we = addr_hit[209] & reg_we & !reg_error; assign alert_cause_2_wd = reg_wdata[0]; - assign alert_cause_3_we = addr_hit[207] & reg_we & !reg_error; + assign alert_cause_3_we = addr_hit[210] & reg_we & !reg_error; assign alert_cause_3_wd = reg_wdata[0]; - assign alert_cause_4_we = addr_hit[208] & reg_we & !reg_error; + assign alert_cause_4_we = addr_hit[211] & reg_we & !reg_error; assign alert_cause_4_wd = reg_wdata[0]; - assign alert_cause_5_we = addr_hit[209] & reg_we & !reg_error; + assign alert_cause_5_we = addr_hit[212] & reg_we & !reg_error; assign alert_cause_5_wd = reg_wdata[0]; - assign alert_cause_6_we = addr_hit[210] & reg_we & !reg_error; + assign alert_cause_6_we = addr_hit[213] & reg_we & !reg_error; assign alert_cause_6_wd = reg_wdata[0]; - assign alert_cause_7_we = addr_hit[211] & reg_we & !reg_error; + assign alert_cause_7_we = addr_hit[214] & reg_we & !reg_error; assign alert_cause_7_wd = reg_wdata[0]; - assign alert_cause_8_we = addr_hit[212] & reg_we & !reg_error; + assign alert_cause_8_we = addr_hit[215] & reg_we & !reg_error; assign alert_cause_8_wd = reg_wdata[0]; - assign alert_cause_9_we = addr_hit[213] & reg_we & !reg_error; + assign alert_cause_9_we = addr_hit[216] & reg_we & !reg_error; assign alert_cause_9_wd = reg_wdata[0]; - assign alert_cause_10_we = addr_hit[214] & reg_we & !reg_error; + assign alert_cause_10_we = addr_hit[217] & reg_we & !reg_error; assign alert_cause_10_wd = reg_wdata[0]; - assign alert_cause_11_we = addr_hit[215] & reg_we & !reg_error; + assign alert_cause_11_we = addr_hit[218] & reg_we & !reg_error; assign alert_cause_11_wd = reg_wdata[0]; - assign alert_cause_12_we = addr_hit[216] & reg_we & !reg_error; + assign alert_cause_12_we = addr_hit[219] & reg_we & !reg_error; assign alert_cause_12_wd = reg_wdata[0]; - assign alert_cause_13_we = addr_hit[217] & reg_we & !reg_error; + assign alert_cause_13_we = addr_hit[220] & reg_we & !reg_error; assign alert_cause_13_wd = reg_wdata[0]; - assign alert_cause_14_we = addr_hit[218] & reg_we & !reg_error; + assign alert_cause_14_we = addr_hit[221] & reg_we & !reg_error; assign alert_cause_14_wd = reg_wdata[0]; - assign alert_cause_15_we = addr_hit[219] & reg_we & !reg_error; + assign alert_cause_15_we = addr_hit[222] & reg_we & !reg_error; assign alert_cause_15_wd = reg_wdata[0]; - assign alert_cause_16_we = addr_hit[220] & reg_we & !reg_error; + assign alert_cause_16_we = addr_hit[223] & reg_we & !reg_error; assign alert_cause_16_wd = reg_wdata[0]; - assign alert_cause_17_we = addr_hit[221] & reg_we & !reg_error; + assign alert_cause_17_we = addr_hit[224] & reg_we & !reg_error; assign alert_cause_17_wd = reg_wdata[0]; - assign alert_cause_18_we = addr_hit[222] & reg_we & !reg_error; + assign alert_cause_18_we = addr_hit[225] & reg_we & !reg_error; assign alert_cause_18_wd = reg_wdata[0]; - assign alert_cause_19_we = addr_hit[223] & reg_we & !reg_error; + assign alert_cause_19_we = addr_hit[226] & reg_we & !reg_error; assign alert_cause_19_wd = reg_wdata[0]; - assign alert_cause_20_we = addr_hit[224] & reg_we & !reg_error; + assign alert_cause_20_we = addr_hit[227] & reg_we & !reg_error; assign alert_cause_20_wd = reg_wdata[0]; - assign alert_cause_21_we = addr_hit[225] & reg_we & !reg_error; + assign alert_cause_21_we = addr_hit[228] & reg_we & !reg_error; assign alert_cause_21_wd = reg_wdata[0]; - assign alert_cause_22_we = addr_hit[226] & reg_we & !reg_error; + assign alert_cause_22_we = addr_hit[229] & reg_we & !reg_error; assign alert_cause_22_wd = reg_wdata[0]; - assign alert_cause_23_we = addr_hit[227] & reg_we & !reg_error; + assign alert_cause_23_we = addr_hit[230] & reg_we & !reg_error; assign alert_cause_23_wd = reg_wdata[0]; - assign alert_cause_24_we = addr_hit[228] & reg_we & !reg_error; + assign alert_cause_24_we = addr_hit[231] & reg_we & !reg_error; assign alert_cause_24_wd = reg_wdata[0]; - assign alert_cause_25_we = addr_hit[229] & reg_we & !reg_error; + assign alert_cause_25_we = addr_hit[232] & reg_we & !reg_error; assign alert_cause_25_wd = reg_wdata[0]; - assign alert_cause_26_we = addr_hit[230] & reg_we & !reg_error; + assign alert_cause_26_we = addr_hit[233] & reg_we & !reg_error; assign alert_cause_26_wd = reg_wdata[0]; - assign alert_cause_27_we = addr_hit[231] & reg_we & !reg_error; + assign alert_cause_27_we = addr_hit[234] & reg_we & !reg_error; assign alert_cause_27_wd = reg_wdata[0]; - assign alert_cause_28_we = addr_hit[232] & reg_we & !reg_error; + assign alert_cause_28_we = addr_hit[235] & reg_we & !reg_error; assign alert_cause_28_wd = reg_wdata[0]; - assign alert_cause_29_we = addr_hit[233] & reg_we & !reg_error; + assign alert_cause_29_we = addr_hit[236] & reg_we & !reg_error; assign alert_cause_29_wd = reg_wdata[0]; - assign alert_cause_30_we = addr_hit[234] & reg_we & !reg_error; + assign alert_cause_30_we = addr_hit[237] & reg_we & !reg_error; assign alert_cause_30_wd = reg_wdata[0]; - assign alert_cause_31_we = addr_hit[235] & reg_we & !reg_error; + assign alert_cause_31_we = addr_hit[238] & reg_we & !reg_error; assign alert_cause_31_wd = reg_wdata[0]; - assign alert_cause_32_we = addr_hit[236] & reg_we & !reg_error; + assign alert_cause_32_we = addr_hit[239] & reg_we & !reg_error; assign alert_cause_32_wd = reg_wdata[0]; - assign alert_cause_33_we = addr_hit[237] & reg_we & !reg_error; + assign alert_cause_33_we = addr_hit[240] & reg_we & !reg_error; assign alert_cause_33_wd = reg_wdata[0]; - assign alert_cause_34_we = addr_hit[238] & reg_we & !reg_error; + assign alert_cause_34_we = addr_hit[241] & reg_we & !reg_error; assign alert_cause_34_wd = reg_wdata[0]; - assign alert_cause_35_we = addr_hit[239] & reg_we & !reg_error; + assign alert_cause_35_we = addr_hit[242] & reg_we & !reg_error; assign alert_cause_35_wd = reg_wdata[0]; - assign alert_cause_36_we = addr_hit[240] & reg_we & !reg_error; + assign alert_cause_36_we = addr_hit[243] & reg_we & !reg_error; assign alert_cause_36_wd = reg_wdata[0]; - assign alert_cause_37_we = addr_hit[241] & reg_we & !reg_error; + assign alert_cause_37_we = addr_hit[244] & reg_we & !reg_error; assign alert_cause_37_wd = reg_wdata[0]; - assign alert_cause_38_we = addr_hit[242] & reg_we & !reg_error; + assign alert_cause_38_we = addr_hit[245] & reg_we & !reg_error; assign alert_cause_38_wd = reg_wdata[0]; - assign alert_cause_39_we = addr_hit[243] & reg_we & !reg_error; + assign alert_cause_39_we = addr_hit[246] & reg_we & !reg_error; assign alert_cause_39_wd = reg_wdata[0]; - assign alert_cause_40_we = addr_hit[244] & reg_we & !reg_error; + assign alert_cause_40_we = addr_hit[247] & reg_we & !reg_error; assign alert_cause_40_wd = reg_wdata[0]; - assign alert_cause_41_we = addr_hit[245] & reg_we & !reg_error; + assign alert_cause_41_we = addr_hit[248] & reg_we & !reg_error; assign alert_cause_41_wd = reg_wdata[0]; - assign alert_cause_42_we = addr_hit[246] & reg_we & !reg_error; + assign alert_cause_42_we = addr_hit[249] & reg_we & !reg_error; assign alert_cause_42_wd = reg_wdata[0]; - assign alert_cause_43_we = addr_hit[247] & reg_we & !reg_error; + assign alert_cause_43_we = addr_hit[250] & reg_we & !reg_error; assign alert_cause_43_wd = reg_wdata[0]; - assign alert_cause_44_we = addr_hit[248] & reg_we & !reg_error; + assign alert_cause_44_we = addr_hit[251] & reg_we & !reg_error; assign alert_cause_44_wd = reg_wdata[0]; - assign alert_cause_45_we = addr_hit[249] & reg_we & !reg_error; + assign alert_cause_45_we = addr_hit[252] & reg_we & !reg_error; assign alert_cause_45_wd = reg_wdata[0]; - assign alert_cause_46_we = addr_hit[250] & reg_we & !reg_error; + assign alert_cause_46_we = addr_hit[253] & reg_we & !reg_error; assign alert_cause_46_wd = reg_wdata[0]; - assign alert_cause_47_we = addr_hit[251] & reg_we & !reg_error; + assign alert_cause_47_we = addr_hit[254] & reg_we & !reg_error; assign alert_cause_47_wd = reg_wdata[0]; - assign alert_cause_48_we = addr_hit[252] & reg_we & !reg_error; + assign alert_cause_48_we = addr_hit[255] & reg_we & !reg_error; assign alert_cause_48_wd = reg_wdata[0]; - assign alert_cause_49_we = addr_hit[253] & reg_we & !reg_error; + assign alert_cause_49_we = addr_hit[256] & reg_we & !reg_error; assign alert_cause_49_wd = reg_wdata[0]; - assign alert_cause_50_we = addr_hit[254] & reg_we & !reg_error; + assign alert_cause_50_we = addr_hit[257] & reg_we & !reg_error; assign alert_cause_50_wd = reg_wdata[0]; - assign alert_cause_51_we = addr_hit[255] & reg_we & !reg_error; + assign alert_cause_51_we = addr_hit[258] & reg_we & !reg_error; assign alert_cause_51_wd = reg_wdata[0]; - assign alert_cause_52_we = addr_hit[256] & reg_we & !reg_error; + assign alert_cause_52_we = addr_hit[259] & reg_we & !reg_error; assign alert_cause_52_wd = reg_wdata[0]; - assign alert_cause_53_we = addr_hit[257] & reg_we & !reg_error; + assign alert_cause_53_we = addr_hit[260] & reg_we & !reg_error; assign alert_cause_53_wd = reg_wdata[0]; - assign alert_cause_54_we = addr_hit[258] & reg_we & !reg_error; + assign alert_cause_54_we = addr_hit[261] & reg_we & !reg_error; assign alert_cause_54_wd = reg_wdata[0]; - assign alert_cause_55_we = addr_hit[259] & reg_we & !reg_error; + assign alert_cause_55_we = addr_hit[262] & reg_we & !reg_error; assign alert_cause_55_wd = reg_wdata[0]; - assign alert_cause_56_we = addr_hit[260] & reg_we & !reg_error; + assign alert_cause_56_we = addr_hit[263] & reg_we & !reg_error; assign alert_cause_56_wd = reg_wdata[0]; - assign alert_cause_57_we = addr_hit[261] & reg_we & !reg_error; + assign alert_cause_57_we = addr_hit[264] & reg_we & !reg_error; assign alert_cause_57_wd = reg_wdata[0]; - assign alert_cause_58_we = addr_hit[262] & reg_we & !reg_error; + assign alert_cause_58_we = addr_hit[265] & reg_we & !reg_error; assign alert_cause_58_wd = reg_wdata[0]; - assign alert_cause_59_we = addr_hit[263] & reg_we & !reg_error; + assign alert_cause_59_we = addr_hit[266] & reg_we & !reg_error; assign alert_cause_59_wd = reg_wdata[0]; - assign alert_cause_60_we = addr_hit[264] & reg_we & !reg_error; + assign alert_cause_60_we = addr_hit[267] & reg_we & !reg_error; assign alert_cause_60_wd = reg_wdata[0]; - assign alert_cause_61_we = addr_hit[265] & reg_we & !reg_error; + assign alert_cause_61_we = addr_hit[268] & reg_we & !reg_error; assign alert_cause_61_wd = reg_wdata[0]; - assign alert_cause_62_we = addr_hit[266] & reg_we & !reg_error; + assign alert_cause_62_we = addr_hit[269] & reg_we & !reg_error; assign alert_cause_62_wd = reg_wdata[0]; - assign alert_cause_63_we = addr_hit[267] & reg_we & !reg_error; + assign alert_cause_63_we = addr_hit[270] & reg_we & !reg_error; assign alert_cause_63_wd = reg_wdata[0]; - assign alert_cause_64_we = addr_hit[268] & reg_we & !reg_error; + assign alert_cause_64_we = addr_hit[271] & reg_we & !reg_error; assign alert_cause_64_wd = reg_wdata[0]; - assign alert_cause_65_we = addr_hit[269] & reg_we & !reg_error; + assign alert_cause_65_we = addr_hit[272] & reg_we & !reg_error; assign alert_cause_65_wd = reg_wdata[0]; - assign loc_alert_regwen_0_we = addr_hit[270] & reg_we & !reg_error; + assign alert_cause_66_we = addr_hit[273] & reg_we & !reg_error; + + assign alert_cause_66_wd = reg_wdata[0]; + assign loc_alert_regwen_0_we = addr_hit[274] & reg_we & !reg_error; assign loc_alert_regwen_0_wd = reg_wdata[0]; - assign loc_alert_regwen_1_we = addr_hit[271] & reg_we & !reg_error; + assign loc_alert_regwen_1_we = addr_hit[275] & reg_we & !reg_error; assign loc_alert_regwen_1_wd = reg_wdata[0]; - assign loc_alert_regwen_2_we = addr_hit[272] & reg_we & !reg_error; + assign loc_alert_regwen_2_we = addr_hit[276] & reg_we & !reg_error; assign loc_alert_regwen_2_wd = reg_wdata[0]; - assign loc_alert_regwen_3_we = addr_hit[273] & reg_we & !reg_error; + assign loc_alert_regwen_3_we = addr_hit[277] & reg_we & !reg_error; assign loc_alert_regwen_3_wd = reg_wdata[0]; - assign loc_alert_regwen_4_we = addr_hit[274] & reg_we & !reg_error; + assign loc_alert_regwen_4_we = addr_hit[278] & reg_we & !reg_error; assign loc_alert_regwen_4_wd = reg_wdata[0]; - assign loc_alert_en_0_we = addr_hit[275] & reg_we & !reg_error; + assign loc_alert_en_0_we = addr_hit[279] & reg_we & !reg_error; assign loc_alert_en_0_wd = reg_wdata[0]; - assign loc_alert_en_1_we = addr_hit[276] & reg_we & !reg_error; + assign loc_alert_en_1_we = addr_hit[280] & reg_we & !reg_error; assign loc_alert_en_1_wd = reg_wdata[0]; - assign loc_alert_en_2_we = addr_hit[277] & reg_we & !reg_error; + assign loc_alert_en_2_we = addr_hit[281] & reg_we & !reg_error; assign loc_alert_en_2_wd = reg_wdata[0]; - assign loc_alert_en_3_we = addr_hit[278] & reg_we & !reg_error; + assign loc_alert_en_3_we = addr_hit[282] & reg_we & !reg_error; assign loc_alert_en_3_wd = reg_wdata[0]; - assign loc_alert_en_4_we = addr_hit[279] & reg_we & !reg_error; + assign loc_alert_en_4_we = addr_hit[283] & reg_we & !reg_error; assign loc_alert_en_4_wd = reg_wdata[0]; - assign loc_alert_class_0_we = addr_hit[280] & reg_we & !reg_error; + assign loc_alert_class_0_we = addr_hit[284] & reg_we & !reg_error; assign loc_alert_class_0_wd = reg_wdata[1:0]; - assign loc_alert_class_1_we = addr_hit[281] & reg_we & !reg_error; + assign loc_alert_class_1_we = addr_hit[285] & reg_we & !reg_error; assign loc_alert_class_1_wd = reg_wdata[1:0]; - assign loc_alert_class_2_we = addr_hit[282] & reg_we & !reg_error; + assign loc_alert_class_2_we = addr_hit[286] & reg_we & !reg_error; assign loc_alert_class_2_wd = reg_wdata[1:0]; - assign loc_alert_class_3_we = addr_hit[283] & reg_we & !reg_error; + assign loc_alert_class_3_we = addr_hit[287] & reg_we & !reg_error; assign loc_alert_class_3_wd = reg_wdata[1:0]; - assign loc_alert_class_4_we = addr_hit[284] & reg_we & !reg_error; + assign loc_alert_class_4_we = addr_hit[288] & reg_we & !reg_error; assign loc_alert_class_4_wd = reg_wdata[1:0]; - assign loc_alert_cause_0_we = addr_hit[285] & reg_we & !reg_error; + assign loc_alert_cause_0_we = addr_hit[289] & reg_we & !reg_error; assign loc_alert_cause_0_wd = reg_wdata[0]; - assign loc_alert_cause_1_we = addr_hit[286] & reg_we & !reg_error; + assign loc_alert_cause_1_we = addr_hit[290] & reg_we & !reg_error; assign loc_alert_cause_1_wd = reg_wdata[0]; - assign loc_alert_cause_2_we = addr_hit[287] & reg_we & !reg_error; + assign loc_alert_cause_2_we = addr_hit[291] & reg_we & !reg_error; assign loc_alert_cause_2_wd = reg_wdata[0]; - assign loc_alert_cause_3_we = addr_hit[288] & reg_we & !reg_error; + assign loc_alert_cause_3_we = addr_hit[292] & reg_we & !reg_error; assign loc_alert_cause_3_wd = reg_wdata[0]; - assign loc_alert_cause_4_we = addr_hit[289] & reg_we & !reg_error; + assign loc_alert_cause_4_we = addr_hit[293] & reg_we & !reg_error; assign loc_alert_cause_4_wd = reg_wdata[0]; - assign classa_regwen_we = addr_hit[290] & reg_we & !reg_error; + assign classa_regwen_we = addr_hit[294] & reg_we & !reg_error; assign classa_regwen_wd = reg_wdata[0]; - assign classa_ctrl_we = addr_hit[291] & reg_we & !reg_error; + assign classa_ctrl_we = addr_hit[295] & reg_we & !reg_error; assign classa_ctrl_en_wd = reg_wdata[0]; @@ -13062,37 +13202,37 @@ assign classa_ctrl_map_e2_wd = reg_wdata[11:10]; assign classa_ctrl_map_e3_wd = reg_wdata[13:12]; - assign classa_clr_regwen_we = addr_hit[292] & reg_we & !reg_error; + assign classa_clr_regwen_we = addr_hit[296] & reg_we & !reg_error; assign classa_clr_regwen_wd = reg_wdata[0]; - assign classa_clr_we = addr_hit[293] & reg_we & !reg_error; + assign classa_clr_we = addr_hit[297] & reg_we & !reg_error; assign classa_clr_wd = reg_wdata[0]; - assign classa_accum_cnt_re = addr_hit[294] & reg_re & !reg_error; - assign classa_accum_thresh_we = addr_hit[295] & reg_we & !reg_error; + assign classa_accum_cnt_re = addr_hit[298] & reg_re & !reg_error; + assign classa_accum_thresh_we = addr_hit[299] & reg_we & !reg_error; assign classa_accum_thresh_wd = reg_wdata[15:0]; - assign classa_timeout_cyc_we = addr_hit[296] & reg_we & !reg_error; + assign classa_timeout_cyc_we = addr_hit[300] & reg_we & !reg_error; assign classa_timeout_cyc_wd = reg_wdata[31:0]; - assign classa_phase0_cyc_we = addr_hit[297] & reg_we & !reg_error; + assign classa_phase0_cyc_we = addr_hit[301] & reg_we & !reg_error; assign classa_phase0_cyc_wd = reg_wdata[31:0]; - assign classa_phase1_cyc_we = addr_hit[298] & reg_we & !reg_error; + assign classa_phase1_cyc_we = addr_hit[302] & reg_we & !reg_error; assign classa_phase1_cyc_wd = reg_wdata[31:0]; - assign classa_phase2_cyc_we = addr_hit[299] & reg_we & !reg_error; + assign classa_phase2_cyc_we = addr_hit[303] & reg_we & !reg_error; assign classa_phase2_cyc_wd = reg_wdata[31:0]; - assign classa_phase3_cyc_we = addr_hit[300] & reg_we & !reg_error; + assign classa_phase3_cyc_we = addr_hit[304] & reg_we & !reg_error; assign classa_phase3_cyc_wd = reg_wdata[31:0]; - assign classa_esc_cnt_re = addr_hit[301] & reg_re & !reg_error; - assign classa_state_re = addr_hit[302] & reg_re & !reg_error; - assign classb_regwen_we = addr_hit[303] & reg_we & !reg_error; + assign classa_esc_cnt_re = addr_hit[305] & reg_re & !reg_error; + assign classa_state_re = addr_hit[306] & reg_re & !reg_error; + assign classb_regwen_we = addr_hit[307] & reg_we & !reg_error; assign classb_regwen_wd = reg_wdata[0]; - assign classb_ctrl_we = addr_hit[304] & reg_we & !reg_error; + assign classb_ctrl_we = addr_hit[308] & reg_we & !reg_error; assign classb_ctrl_en_wd = reg_wdata[0]; @@ -13113,37 +13253,37 @@ assign classb_ctrl_map_e2_wd = reg_wdata[11:10]; assign classb_ctrl_map_e3_wd = reg_wdata[13:12]; - assign classb_clr_regwen_we = addr_hit[305] & reg_we & !reg_error; + assign classb_clr_regwen_we = addr_hit[309] & reg_we & !reg_error; assign classb_clr_regwen_wd = reg_wdata[0]; - assign classb_clr_we = addr_hit[306] & reg_we & !reg_error; + assign classb_clr_we = addr_hit[310] & reg_we & !reg_error; assign classb_clr_wd = reg_wdata[0]; - assign classb_accum_cnt_re = addr_hit[307] & reg_re & !reg_error; - assign classb_accum_thresh_we = addr_hit[308] & reg_we & !reg_error; + assign classb_accum_cnt_re = addr_hit[311] & reg_re & !reg_error; + assign classb_accum_thresh_we = addr_hit[312] & reg_we & !reg_error; assign classb_accum_thresh_wd = reg_wdata[15:0]; - assign classb_timeout_cyc_we = addr_hit[309] & reg_we & !reg_error; + assign classb_timeout_cyc_we = addr_hit[313] & reg_we & !reg_error; assign classb_timeout_cyc_wd = reg_wdata[31:0]; - assign classb_phase0_cyc_we = addr_hit[310] & reg_we & !reg_error; + assign classb_phase0_cyc_we = addr_hit[314] & reg_we & !reg_error; assign classb_phase0_cyc_wd = reg_wdata[31:0]; - assign classb_phase1_cyc_we = addr_hit[311] & reg_we & !reg_error; + assign classb_phase1_cyc_we = addr_hit[315] & reg_we & !reg_error; assign classb_phase1_cyc_wd = reg_wdata[31:0]; - assign classb_phase2_cyc_we = addr_hit[312] & reg_we & !reg_error; + assign classb_phase2_cyc_we = addr_hit[316] & reg_we & !reg_error; assign classb_phase2_cyc_wd = reg_wdata[31:0]; - assign classb_phase3_cyc_we = addr_hit[313] & reg_we & !reg_error; + assign classb_phase3_cyc_we = addr_hit[317] & reg_we & !reg_error; assign classb_phase3_cyc_wd = reg_wdata[31:0]; - assign classb_esc_cnt_re = addr_hit[314] & reg_re & !reg_error; - assign classb_state_re = addr_hit[315] & reg_re & !reg_error; - assign classc_regwen_we = addr_hit[316] & reg_we & !reg_error; + assign classb_esc_cnt_re = addr_hit[318] & reg_re & !reg_error; + assign classb_state_re = addr_hit[319] & reg_re & !reg_error; + assign classc_regwen_we = addr_hit[320] & reg_we & !reg_error; assign classc_regwen_wd = reg_wdata[0]; - assign classc_ctrl_we = addr_hit[317] & reg_we & !reg_error; + assign classc_ctrl_we = addr_hit[321] & reg_we & !reg_error; assign classc_ctrl_en_wd = reg_wdata[0]; @@ -13164,37 +13304,37 @@ assign classc_ctrl_map_e2_wd = reg_wdata[11:10]; assign classc_ctrl_map_e3_wd = reg_wdata[13:12]; - assign classc_clr_regwen_we = addr_hit[318] & reg_we & !reg_error; + assign classc_clr_regwen_we = addr_hit[322] & reg_we & !reg_error; assign classc_clr_regwen_wd = reg_wdata[0]; - assign classc_clr_we = addr_hit[319] & reg_we & !reg_error; + assign classc_clr_we = addr_hit[323] & reg_we & !reg_error; assign classc_clr_wd = reg_wdata[0]; - assign classc_accum_cnt_re = addr_hit[320] & reg_re & !reg_error; - assign classc_accum_thresh_we = addr_hit[321] & reg_we & !reg_error; + assign classc_accum_cnt_re = addr_hit[324] & reg_re & !reg_error; + assign classc_accum_thresh_we = addr_hit[325] & reg_we & !reg_error; assign classc_accum_thresh_wd = reg_wdata[15:0]; - assign classc_timeout_cyc_we = addr_hit[322] & reg_we & !reg_error; + assign classc_timeout_cyc_we = addr_hit[326] & reg_we & !reg_error; assign classc_timeout_cyc_wd = reg_wdata[31:0]; - assign classc_phase0_cyc_we = addr_hit[323] & reg_we & !reg_error; + assign classc_phase0_cyc_we = addr_hit[327] & reg_we & !reg_error; assign classc_phase0_cyc_wd = reg_wdata[31:0]; - assign classc_phase1_cyc_we = addr_hit[324] & reg_we & !reg_error; + assign classc_phase1_cyc_we = addr_hit[328] & reg_we & !reg_error; assign classc_phase1_cyc_wd = reg_wdata[31:0]; - assign classc_phase2_cyc_we = addr_hit[325] & reg_we & !reg_error; + assign classc_phase2_cyc_we = addr_hit[329] & reg_we & !reg_error; assign classc_phase2_cyc_wd = reg_wdata[31:0]; - assign classc_phase3_cyc_we = addr_hit[326] & reg_we & !reg_error; + assign classc_phase3_cyc_we = addr_hit[330] & reg_we & !reg_error; assign classc_phase3_cyc_wd = reg_wdata[31:0]; - assign classc_esc_cnt_re = addr_hit[327] & reg_re & !reg_error; - assign classc_state_re = addr_hit[328] & reg_re & !reg_error; - assign classd_regwen_we = addr_hit[329] & reg_we & !reg_error; + assign classc_esc_cnt_re = addr_hit[331] & reg_re & !reg_error; + assign classc_state_re = addr_hit[332] & reg_re & !reg_error; + assign classd_regwen_we = addr_hit[333] & reg_we & !reg_error; assign classd_regwen_wd = reg_wdata[0]; - assign classd_ctrl_we = addr_hit[330] & reg_we & !reg_error; + assign classd_ctrl_we = addr_hit[334] & reg_we & !reg_error; assign classd_ctrl_en_wd = reg_wdata[0]; @@ -13215,33 +13355,33 @@ assign classd_ctrl_map_e2_wd = reg_wdata[11:10]; assign classd_ctrl_map_e3_wd = reg_wdata[13:12]; - assign classd_clr_regwen_we = addr_hit[331] & reg_we & !reg_error; + assign classd_clr_regwen_we = addr_hit[335] & reg_we & !reg_error; assign classd_clr_regwen_wd = reg_wdata[0]; - assign classd_clr_we = addr_hit[332] & reg_we & !reg_error; + assign classd_clr_we = addr_hit[336] & reg_we & !reg_error; assign classd_clr_wd = reg_wdata[0]; - assign classd_accum_cnt_re = addr_hit[333] & reg_re & !reg_error; - assign classd_accum_thresh_we = addr_hit[334] & reg_we & !reg_error; + assign classd_accum_cnt_re = addr_hit[337] & reg_re & !reg_error; + assign classd_accum_thresh_we = addr_hit[338] & reg_we & !reg_error; assign classd_accum_thresh_wd = reg_wdata[15:0]; - assign classd_timeout_cyc_we = addr_hit[335] & reg_we & !reg_error; + assign classd_timeout_cyc_we = addr_hit[339] & reg_we & !reg_error; assign classd_timeout_cyc_wd = reg_wdata[31:0]; - assign classd_phase0_cyc_we = addr_hit[336] & reg_we & !reg_error; + assign classd_phase0_cyc_we = addr_hit[340] & reg_we & !reg_error; assign classd_phase0_cyc_wd = reg_wdata[31:0]; - assign classd_phase1_cyc_we = addr_hit[337] & reg_we & !reg_error; + assign classd_phase1_cyc_we = addr_hit[341] & reg_we & !reg_error; assign classd_phase1_cyc_wd = reg_wdata[31:0]; - assign classd_phase2_cyc_we = addr_hit[338] & reg_we & !reg_error; + assign classd_phase2_cyc_we = addr_hit[342] & reg_we & !reg_error; assign classd_phase2_cyc_wd = reg_wdata[31:0]; - assign classd_phase3_cyc_we = addr_hit[339] & reg_we & !reg_error; + assign classd_phase3_cyc_we = addr_hit[343] & reg_we & !reg_error; assign classd_phase3_cyc_wd = reg_wdata[31:0]; - assign classd_esc_cnt_re = addr_hit[340] & reg_re & !reg_error; - assign classd_state_re = addr_hit[341] & reg_re & !reg_error; + assign classd_esc_cnt_re = addr_hit[344] & reg_re & !reg_error; + assign classd_state_re = addr_hit[345] & reg_re & !reg_error; // Read data return always_comb begin @@ -13545,882 +13685,898 @@ end addr_hit[72]: begin - reg_rdata_next[0] = alert_en_0_qs; + reg_rdata_next[0] = alert_regwen_66_qs; end addr_hit[73]: begin - reg_rdata_next[0] = alert_en_1_qs; + reg_rdata_next[0] = alert_en_0_qs; end addr_hit[74]: begin - reg_rdata_next[0] = alert_en_2_qs; + reg_rdata_next[0] = alert_en_1_qs; end addr_hit[75]: begin - reg_rdata_next[0] = alert_en_3_qs; + reg_rdata_next[0] = alert_en_2_qs; end addr_hit[76]: begin - reg_rdata_next[0] = alert_en_4_qs; + reg_rdata_next[0] = alert_en_3_qs; end addr_hit[77]: begin - reg_rdata_next[0] = alert_en_5_qs; + reg_rdata_next[0] = alert_en_4_qs; end addr_hit[78]: begin - reg_rdata_next[0] = alert_en_6_qs; + reg_rdata_next[0] = alert_en_5_qs; end addr_hit[79]: begin - reg_rdata_next[0] = alert_en_7_qs; + reg_rdata_next[0] = alert_en_6_qs; end addr_hit[80]: begin - reg_rdata_next[0] = alert_en_8_qs; + reg_rdata_next[0] = alert_en_7_qs; end addr_hit[81]: begin - reg_rdata_next[0] = alert_en_9_qs; + reg_rdata_next[0] = alert_en_8_qs; end addr_hit[82]: begin - reg_rdata_next[0] = alert_en_10_qs; + reg_rdata_next[0] = alert_en_9_qs; end addr_hit[83]: begin - reg_rdata_next[0] = alert_en_11_qs; + reg_rdata_next[0] = alert_en_10_qs; end addr_hit[84]: begin - reg_rdata_next[0] = alert_en_12_qs; + reg_rdata_next[0] = alert_en_11_qs; end addr_hit[85]: begin - reg_rdata_next[0] = alert_en_13_qs; + reg_rdata_next[0] = alert_en_12_qs; end addr_hit[86]: begin - reg_rdata_next[0] = alert_en_14_qs; + reg_rdata_next[0] = alert_en_13_qs; end addr_hit[87]: begin - reg_rdata_next[0] = alert_en_15_qs; + reg_rdata_next[0] = alert_en_14_qs; end addr_hit[88]: begin - reg_rdata_next[0] = alert_en_16_qs; + reg_rdata_next[0] = alert_en_15_qs; end addr_hit[89]: begin - reg_rdata_next[0] = alert_en_17_qs; + reg_rdata_next[0] = alert_en_16_qs; end addr_hit[90]: begin - reg_rdata_next[0] = alert_en_18_qs; + reg_rdata_next[0] = alert_en_17_qs; end addr_hit[91]: begin - reg_rdata_next[0] = alert_en_19_qs; + reg_rdata_next[0] = alert_en_18_qs; end addr_hit[92]: begin - reg_rdata_next[0] = alert_en_20_qs; + reg_rdata_next[0] = alert_en_19_qs; end addr_hit[93]: begin - reg_rdata_next[0] = alert_en_21_qs; + reg_rdata_next[0] = alert_en_20_qs; end addr_hit[94]: begin - reg_rdata_next[0] = alert_en_22_qs; + reg_rdata_next[0] = alert_en_21_qs; end addr_hit[95]: begin - reg_rdata_next[0] = alert_en_23_qs; + reg_rdata_next[0] = alert_en_22_qs; end addr_hit[96]: begin - reg_rdata_next[0] = alert_en_24_qs; + reg_rdata_next[0] = alert_en_23_qs; end addr_hit[97]: begin - reg_rdata_next[0] = alert_en_25_qs; + reg_rdata_next[0] = alert_en_24_qs; end addr_hit[98]: begin - reg_rdata_next[0] = alert_en_26_qs; + reg_rdata_next[0] = alert_en_25_qs; end addr_hit[99]: begin - reg_rdata_next[0] = alert_en_27_qs; + reg_rdata_next[0] = alert_en_26_qs; end addr_hit[100]: begin - reg_rdata_next[0] = alert_en_28_qs; + reg_rdata_next[0] = alert_en_27_qs; end addr_hit[101]: begin - reg_rdata_next[0] = alert_en_29_qs; + reg_rdata_next[0] = alert_en_28_qs; end addr_hit[102]: begin - reg_rdata_next[0] = alert_en_30_qs; + reg_rdata_next[0] = alert_en_29_qs; end addr_hit[103]: begin - reg_rdata_next[0] = alert_en_31_qs; + reg_rdata_next[0] = alert_en_30_qs; end addr_hit[104]: begin - reg_rdata_next[0] = alert_en_32_qs; + reg_rdata_next[0] = alert_en_31_qs; end addr_hit[105]: begin - reg_rdata_next[0] = alert_en_33_qs; + reg_rdata_next[0] = alert_en_32_qs; end addr_hit[106]: begin - reg_rdata_next[0] = alert_en_34_qs; + reg_rdata_next[0] = alert_en_33_qs; end addr_hit[107]: begin - reg_rdata_next[0] = alert_en_35_qs; + reg_rdata_next[0] = alert_en_34_qs; end addr_hit[108]: begin - reg_rdata_next[0] = alert_en_36_qs; + reg_rdata_next[0] = alert_en_35_qs; end addr_hit[109]: begin - reg_rdata_next[0] = alert_en_37_qs; + reg_rdata_next[0] = alert_en_36_qs; end addr_hit[110]: begin - reg_rdata_next[0] = alert_en_38_qs; + reg_rdata_next[0] = alert_en_37_qs; end addr_hit[111]: begin - reg_rdata_next[0] = alert_en_39_qs; + reg_rdata_next[0] = alert_en_38_qs; end addr_hit[112]: begin - reg_rdata_next[0] = alert_en_40_qs; + reg_rdata_next[0] = alert_en_39_qs; end addr_hit[113]: begin - reg_rdata_next[0] = alert_en_41_qs; + reg_rdata_next[0] = alert_en_40_qs; end addr_hit[114]: begin - reg_rdata_next[0] = alert_en_42_qs; + reg_rdata_next[0] = alert_en_41_qs; end addr_hit[115]: begin - reg_rdata_next[0] = alert_en_43_qs; + reg_rdata_next[0] = alert_en_42_qs; end addr_hit[116]: begin - reg_rdata_next[0] = alert_en_44_qs; + reg_rdata_next[0] = alert_en_43_qs; end addr_hit[117]: begin - reg_rdata_next[0] = alert_en_45_qs; + reg_rdata_next[0] = alert_en_44_qs; end addr_hit[118]: begin - reg_rdata_next[0] = alert_en_46_qs; + reg_rdata_next[0] = alert_en_45_qs; end addr_hit[119]: begin - reg_rdata_next[0] = alert_en_47_qs; + reg_rdata_next[0] = alert_en_46_qs; end addr_hit[120]: begin - reg_rdata_next[0] = alert_en_48_qs; + reg_rdata_next[0] = alert_en_47_qs; end addr_hit[121]: begin - reg_rdata_next[0] = alert_en_49_qs; + reg_rdata_next[0] = alert_en_48_qs; end addr_hit[122]: begin - reg_rdata_next[0] = alert_en_50_qs; + reg_rdata_next[0] = alert_en_49_qs; end addr_hit[123]: begin - reg_rdata_next[0] = alert_en_51_qs; + reg_rdata_next[0] = alert_en_50_qs; end addr_hit[124]: begin - reg_rdata_next[0] = alert_en_52_qs; + reg_rdata_next[0] = alert_en_51_qs; end addr_hit[125]: begin - reg_rdata_next[0] = alert_en_53_qs; + reg_rdata_next[0] = alert_en_52_qs; end addr_hit[126]: begin - reg_rdata_next[0] = alert_en_54_qs; + reg_rdata_next[0] = alert_en_53_qs; end addr_hit[127]: begin - reg_rdata_next[0] = alert_en_55_qs; + reg_rdata_next[0] = alert_en_54_qs; end addr_hit[128]: begin - reg_rdata_next[0] = alert_en_56_qs; + reg_rdata_next[0] = alert_en_55_qs; end addr_hit[129]: begin - reg_rdata_next[0] = alert_en_57_qs; + reg_rdata_next[0] = alert_en_56_qs; end addr_hit[130]: begin - reg_rdata_next[0] = alert_en_58_qs; + reg_rdata_next[0] = alert_en_57_qs; end addr_hit[131]: begin - reg_rdata_next[0] = alert_en_59_qs; + reg_rdata_next[0] = alert_en_58_qs; end addr_hit[132]: begin - reg_rdata_next[0] = alert_en_60_qs; + reg_rdata_next[0] = alert_en_59_qs; end addr_hit[133]: begin - reg_rdata_next[0] = alert_en_61_qs; + reg_rdata_next[0] = alert_en_60_qs; end addr_hit[134]: begin - reg_rdata_next[0] = alert_en_62_qs; + reg_rdata_next[0] = alert_en_61_qs; end addr_hit[135]: begin - reg_rdata_next[0] = alert_en_63_qs; + reg_rdata_next[0] = alert_en_62_qs; end addr_hit[136]: begin - reg_rdata_next[0] = alert_en_64_qs; + reg_rdata_next[0] = alert_en_63_qs; end addr_hit[137]: begin - reg_rdata_next[0] = alert_en_65_qs; + reg_rdata_next[0] = alert_en_64_qs; end addr_hit[138]: begin - reg_rdata_next[1:0] = alert_class_0_qs; + reg_rdata_next[0] = alert_en_65_qs; end addr_hit[139]: begin - reg_rdata_next[1:0] = alert_class_1_qs; + reg_rdata_next[0] = alert_en_66_qs; end addr_hit[140]: begin - reg_rdata_next[1:0] = alert_class_2_qs; + reg_rdata_next[1:0] = alert_class_0_qs; end addr_hit[141]: begin - reg_rdata_next[1:0] = alert_class_3_qs; + reg_rdata_next[1:0] = alert_class_1_qs; end addr_hit[142]: begin - reg_rdata_next[1:0] = alert_class_4_qs; + reg_rdata_next[1:0] = alert_class_2_qs; end addr_hit[143]: begin - reg_rdata_next[1:0] = alert_class_5_qs; + reg_rdata_next[1:0] = alert_class_3_qs; end addr_hit[144]: begin - reg_rdata_next[1:0] = alert_class_6_qs; + reg_rdata_next[1:0] = alert_class_4_qs; end addr_hit[145]: begin - reg_rdata_next[1:0] = alert_class_7_qs; + reg_rdata_next[1:0] = alert_class_5_qs; end addr_hit[146]: begin - reg_rdata_next[1:0] = alert_class_8_qs; + reg_rdata_next[1:0] = alert_class_6_qs; end addr_hit[147]: begin - reg_rdata_next[1:0] = alert_class_9_qs; + reg_rdata_next[1:0] = alert_class_7_qs; end addr_hit[148]: begin - reg_rdata_next[1:0] = alert_class_10_qs; + reg_rdata_next[1:0] = alert_class_8_qs; end addr_hit[149]: begin - reg_rdata_next[1:0] = alert_class_11_qs; + reg_rdata_next[1:0] = alert_class_9_qs; end addr_hit[150]: begin - reg_rdata_next[1:0] = alert_class_12_qs; + reg_rdata_next[1:0] = alert_class_10_qs; end addr_hit[151]: begin - reg_rdata_next[1:0] = alert_class_13_qs; + reg_rdata_next[1:0] = alert_class_11_qs; end addr_hit[152]: begin - reg_rdata_next[1:0] = alert_class_14_qs; + reg_rdata_next[1:0] = alert_class_12_qs; end addr_hit[153]: begin - reg_rdata_next[1:0] = alert_class_15_qs; + reg_rdata_next[1:0] = alert_class_13_qs; end addr_hit[154]: begin - reg_rdata_next[1:0] = alert_class_16_qs; + reg_rdata_next[1:0] = alert_class_14_qs; end addr_hit[155]: begin - reg_rdata_next[1:0] = alert_class_17_qs; + reg_rdata_next[1:0] = alert_class_15_qs; end addr_hit[156]: begin - reg_rdata_next[1:0] = alert_class_18_qs; + reg_rdata_next[1:0] = alert_class_16_qs; end addr_hit[157]: begin - reg_rdata_next[1:0] = alert_class_19_qs; + reg_rdata_next[1:0] = alert_class_17_qs; end addr_hit[158]: begin - reg_rdata_next[1:0] = alert_class_20_qs; + reg_rdata_next[1:0] = alert_class_18_qs; end addr_hit[159]: begin - reg_rdata_next[1:0] = alert_class_21_qs; + reg_rdata_next[1:0] = alert_class_19_qs; end addr_hit[160]: begin - reg_rdata_next[1:0] = alert_class_22_qs; + reg_rdata_next[1:0] = alert_class_20_qs; end addr_hit[161]: begin - reg_rdata_next[1:0] = alert_class_23_qs; + reg_rdata_next[1:0] = alert_class_21_qs; end addr_hit[162]: begin - reg_rdata_next[1:0] = alert_class_24_qs; + reg_rdata_next[1:0] = alert_class_22_qs; end addr_hit[163]: begin - reg_rdata_next[1:0] = alert_class_25_qs; + reg_rdata_next[1:0] = alert_class_23_qs; end addr_hit[164]: begin - reg_rdata_next[1:0] = alert_class_26_qs; + reg_rdata_next[1:0] = alert_class_24_qs; end addr_hit[165]: begin - reg_rdata_next[1:0] = alert_class_27_qs; + reg_rdata_next[1:0] = alert_class_25_qs; end addr_hit[166]: begin - reg_rdata_next[1:0] = alert_class_28_qs; + reg_rdata_next[1:0] = alert_class_26_qs; end addr_hit[167]: begin - reg_rdata_next[1:0] = alert_class_29_qs; + reg_rdata_next[1:0] = alert_class_27_qs; end addr_hit[168]: begin - reg_rdata_next[1:0] = alert_class_30_qs; + reg_rdata_next[1:0] = alert_class_28_qs; end addr_hit[169]: begin - reg_rdata_next[1:0] = alert_class_31_qs; + reg_rdata_next[1:0] = alert_class_29_qs; end addr_hit[170]: begin - reg_rdata_next[1:0] = alert_class_32_qs; + reg_rdata_next[1:0] = alert_class_30_qs; end addr_hit[171]: begin - reg_rdata_next[1:0] = alert_class_33_qs; + reg_rdata_next[1:0] = alert_class_31_qs; end addr_hit[172]: begin - reg_rdata_next[1:0] = alert_class_34_qs; + reg_rdata_next[1:0] = alert_class_32_qs; end addr_hit[173]: begin - reg_rdata_next[1:0] = alert_class_35_qs; + reg_rdata_next[1:0] = alert_class_33_qs; end addr_hit[174]: begin - reg_rdata_next[1:0] = alert_class_36_qs; + reg_rdata_next[1:0] = alert_class_34_qs; end addr_hit[175]: begin - reg_rdata_next[1:0] = alert_class_37_qs; + reg_rdata_next[1:0] = alert_class_35_qs; end addr_hit[176]: begin - reg_rdata_next[1:0] = alert_class_38_qs; + reg_rdata_next[1:0] = alert_class_36_qs; end addr_hit[177]: begin - reg_rdata_next[1:0] = alert_class_39_qs; + reg_rdata_next[1:0] = alert_class_37_qs; end addr_hit[178]: begin - reg_rdata_next[1:0] = alert_class_40_qs; + reg_rdata_next[1:0] = alert_class_38_qs; end addr_hit[179]: begin - reg_rdata_next[1:0] = alert_class_41_qs; + reg_rdata_next[1:0] = alert_class_39_qs; end addr_hit[180]: begin - reg_rdata_next[1:0] = alert_class_42_qs; + reg_rdata_next[1:0] = alert_class_40_qs; end addr_hit[181]: begin - reg_rdata_next[1:0] = alert_class_43_qs; + reg_rdata_next[1:0] = alert_class_41_qs; end addr_hit[182]: begin - reg_rdata_next[1:0] = alert_class_44_qs; + reg_rdata_next[1:0] = alert_class_42_qs; end addr_hit[183]: begin - reg_rdata_next[1:0] = alert_class_45_qs; + reg_rdata_next[1:0] = alert_class_43_qs; end addr_hit[184]: begin - reg_rdata_next[1:0] = alert_class_46_qs; + reg_rdata_next[1:0] = alert_class_44_qs; end addr_hit[185]: begin - reg_rdata_next[1:0] = alert_class_47_qs; + reg_rdata_next[1:0] = alert_class_45_qs; end addr_hit[186]: begin - reg_rdata_next[1:0] = alert_class_48_qs; + reg_rdata_next[1:0] = alert_class_46_qs; end addr_hit[187]: begin - reg_rdata_next[1:0] = alert_class_49_qs; + reg_rdata_next[1:0] = alert_class_47_qs; end addr_hit[188]: begin - reg_rdata_next[1:0] = alert_class_50_qs; + reg_rdata_next[1:0] = alert_class_48_qs; end addr_hit[189]: begin - reg_rdata_next[1:0] = alert_class_51_qs; + reg_rdata_next[1:0] = alert_class_49_qs; end addr_hit[190]: begin - reg_rdata_next[1:0] = alert_class_52_qs; + reg_rdata_next[1:0] = alert_class_50_qs; end addr_hit[191]: begin - reg_rdata_next[1:0] = alert_class_53_qs; + reg_rdata_next[1:0] = alert_class_51_qs; end addr_hit[192]: begin - reg_rdata_next[1:0] = alert_class_54_qs; + reg_rdata_next[1:0] = alert_class_52_qs; end addr_hit[193]: begin - reg_rdata_next[1:0] = alert_class_55_qs; + reg_rdata_next[1:0] = alert_class_53_qs; end addr_hit[194]: begin - reg_rdata_next[1:0] = alert_class_56_qs; + reg_rdata_next[1:0] = alert_class_54_qs; end addr_hit[195]: begin - reg_rdata_next[1:0] = alert_class_57_qs; + reg_rdata_next[1:0] = alert_class_55_qs; end addr_hit[196]: begin - reg_rdata_next[1:0] = alert_class_58_qs; + reg_rdata_next[1:0] = alert_class_56_qs; end addr_hit[197]: begin - reg_rdata_next[1:0] = alert_class_59_qs; + reg_rdata_next[1:0] = alert_class_57_qs; end addr_hit[198]: begin - reg_rdata_next[1:0] = alert_class_60_qs; + reg_rdata_next[1:0] = alert_class_58_qs; end addr_hit[199]: begin - reg_rdata_next[1:0] = alert_class_61_qs; + reg_rdata_next[1:0] = alert_class_59_qs; end addr_hit[200]: begin - reg_rdata_next[1:0] = alert_class_62_qs; + reg_rdata_next[1:0] = alert_class_60_qs; end addr_hit[201]: begin - reg_rdata_next[1:0] = alert_class_63_qs; + reg_rdata_next[1:0] = alert_class_61_qs; end addr_hit[202]: begin - reg_rdata_next[1:0] = alert_class_64_qs; + reg_rdata_next[1:0] = alert_class_62_qs; end addr_hit[203]: begin - reg_rdata_next[1:0] = alert_class_65_qs; + reg_rdata_next[1:0] = alert_class_63_qs; end addr_hit[204]: begin - reg_rdata_next[0] = alert_cause_0_qs; + reg_rdata_next[1:0] = alert_class_64_qs; end addr_hit[205]: begin - reg_rdata_next[0] = alert_cause_1_qs; + reg_rdata_next[1:0] = alert_class_65_qs; end addr_hit[206]: begin - reg_rdata_next[0] = alert_cause_2_qs; + reg_rdata_next[1:0] = alert_class_66_qs; end addr_hit[207]: begin - reg_rdata_next[0] = alert_cause_3_qs; + reg_rdata_next[0] = alert_cause_0_qs; end addr_hit[208]: begin - reg_rdata_next[0] = alert_cause_4_qs; + reg_rdata_next[0] = alert_cause_1_qs; end addr_hit[209]: begin - reg_rdata_next[0] = alert_cause_5_qs; + reg_rdata_next[0] = alert_cause_2_qs; end addr_hit[210]: begin - reg_rdata_next[0] = alert_cause_6_qs; + reg_rdata_next[0] = alert_cause_3_qs; end addr_hit[211]: begin - reg_rdata_next[0] = alert_cause_7_qs; + reg_rdata_next[0] = alert_cause_4_qs; end addr_hit[212]: begin - reg_rdata_next[0] = alert_cause_8_qs; + reg_rdata_next[0] = alert_cause_5_qs; end addr_hit[213]: begin - reg_rdata_next[0] = alert_cause_9_qs; + reg_rdata_next[0] = alert_cause_6_qs; end addr_hit[214]: begin - reg_rdata_next[0] = alert_cause_10_qs; + reg_rdata_next[0] = alert_cause_7_qs; end addr_hit[215]: begin - reg_rdata_next[0] = alert_cause_11_qs; + reg_rdata_next[0] = alert_cause_8_qs; end addr_hit[216]: begin - reg_rdata_next[0] = alert_cause_12_qs; + reg_rdata_next[0] = alert_cause_9_qs; end addr_hit[217]: begin - reg_rdata_next[0] = alert_cause_13_qs; + reg_rdata_next[0] = alert_cause_10_qs; end addr_hit[218]: begin - reg_rdata_next[0] = alert_cause_14_qs; + reg_rdata_next[0] = alert_cause_11_qs; end addr_hit[219]: begin - reg_rdata_next[0] = alert_cause_15_qs; + reg_rdata_next[0] = alert_cause_12_qs; end addr_hit[220]: begin - reg_rdata_next[0] = alert_cause_16_qs; + reg_rdata_next[0] = alert_cause_13_qs; end addr_hit[221]: begin - reg_rdata_next[0] = alert_cause_17_qs; + reg_rdata_next[0] = alert_cause_14_qs; end addr_hit[222]: begin - reg_rdata_next[0] = alert_cause_18_qs; + reg_rdata_next[0] = alert_cause_15_qs; end addr_hit[223]: begin - reg_rdata_next[0] = alert_cause_19_qs; + reg_rdata_next[0] = alert_cause_16_qs; end addr_hit[224]: begin - reg_rdata_next[0] = alert_cause_20_qs; + reg_rdata_next[0] = alert_cause_17_qs; end addr_hit[225]: begin - reg_rdata_next[0] = alert_cause_21_qs; + reg_rdata_next[0] = alert_cause_18_qs; end addr_hit[226]: begin - reg_rdata_next[0] = alert_cause_22_qs; + reg_rdata_next[0] = alert_cause_19_qs; end addr_hit[227]: begin - reg_rdata_next[0] = alert_cause_23_qs; + reg_rdata_next[0] = alert_cause_20_qs; end addr_hit[228]: begin - reg_rdata_next[0] = alert_cause_24_qs; + reg_rdata_next[0] = alert_cause_21_qs; end addr_hit[229]: begin - reg_rdata_next[0] = alert_cause_25_qs; + reg_rdata_next[0] = alert_cause_22_qs; end addr_hit[230]: begin - reg_rdata_next[0] = alert_cause_26_qs; + reg_rdata_next[0] = alert_cause_23_qs; end addr_hit[231]: begin - reg_rdata_next[0] = alert_cause_27_qs; + reg_rdata_next[0] = alert_cause_24_qs; end addr_hit[232]: begin - reg_rdata_next[0] = alert_cause_28_qs; + reg_rdata_next[0] = alert_cause_25_qs; end addr_hit[233]: begin - reg_rdata_next[0] = alert_cause_29_qs; + reg_rdata_next[0] = alert_cause_26_qs; end addr_hit[234]: begin - reg_rdata_next[0] = alert_cause_30_qs; + reg_rdata_next[0] = alert_cause_27_qs; end addr_hit[235]: begin - reg_rdata_next[0] = alert_cause_31_qs; + reg_rdata_next[0] = alert_cause_28_qs; end addr_hit[236]: begin - reg_rdata_next[0] = alert_cause_32_qs; + reg_rdata_next[0] = alert_cause_29_qs; end addr_hit[237]: begin - reg_rdata_next[0] = alert_cause_33_qs; + reg_rdata_next[0] = alert_cause_30_qs; end addr_hit[238]: begin - reg_rdata_next[0] = alert_cause_34_qs; + reg_rdata_next[0] = alert_cause_31_qs; end addr_hit[239]: begin - reg_rdata_next[0] = alert_cause_35_qs; + reg_rdata_next[0] = alert_cause_32_qs; end addr_hit[240]: begin - reg_rdata_next[0] = alert_cause_36_qs; + reg_rdata_next[0] = alert_cause_33_qs; end addr_hit[241]: begin - reg_rdata_next[0] = alert_cause_37_qs; + reg_rdata_next[0] = alert_cause_34_qs; end addr_hit[242]: begin - reg_rdata_next[0] = alert_cause_38_qs; + reg_rdata_next[0] = alert_cause_35_qs; end addr_hit[243]: begin - reg_rdata_next[0] = alert_cause_39_qs; + reg_rdata_next[0] = alert_cause_36_qs; end addr_hit[244]: begin - reg_rdata_next[0] = alert_cause_40_qs; + reg_rdata_next[0] = alert_cause_37_qs; end addr_hit[245]: begin - reg_rdata_next[0] = alert_cause_41_qs; + reg_rdata_next[0] = alert_cause_38_qs; end addr_hit[246]: begin - reg_rdata_next[0] = alert_cause_42_qs; + reg_rdata_next[0] = alert_cause_39_qs; end addr_hit[247]: begin - reg_rdata_next[0] = alert_cause_43_qs; + reg_rdata_next[0] = alert_cause_40_qs; end addr_hit[248]: begin - reg_rdata_next[0] = alert_cause_44_qs; + reg_rdata_next[0] = alert_cause_41_qs; end addr_hit[249]: begin - reg_rdata_next[0] = alert_cause_45_qs; + reg_rdata_next[0] = alert_cause_42_qs; end addr_hit[250]: begin - reg_rdata_next[0] = alert_cause_46_qs; + reg_rdata_next[0] = alert_cause_43_qs; end addr_hit[251]: begin - reg_rdata_next[0] = alert_cause_47_qs; + reg_rdata_next[0] = alert_cause_44_qs; end addr_hit[252]: begin - reg_rdata_next[0] = alert_cause_48_qs; + reg_rdata_next[0] = alert_cause_45_qs; end addr_hit[253]: begin - reg_rdata_next[0] = alert_cause_49_qs; + reg_rdata_next[0] = alert_cause_46_qs; end addr_hit[254]: begin - reg_rdata_next[0] = alert_cause_50_qs; + reg_rdata_next[0] = alert_cause_47_qs; end addr_hit[255]: begin - reg_rdata_next[0] = alert_cause_51_qs; + reg_rdata_next[0] = alert_cause_48_qs; end addr_hit[256]: begin - reg_rdata_next[0] = alert_cause_52_qs; + reg_rdata_next[0] = alert_cause_49_qs; end addr_hit[257]: begin - reg_rdata_next[0] = alert_cause_53_qs; + reg_rdata_next[0] = alert_cause_50_qs; end addr_hit[258]: begin - reg_rdata_next[0] = alert_cause_54_qs; + reg_rdata_next[0] = alert_cause_51_qs; end addr_hit[259]: begin - reg_rdata_next[0] = alert_cause_55_qs; + reg_rdata_next[0] = alert_cause_52_qs; end addr_hit[260]: begin - reg_rdata_next[0] = alert_cause_56_qs; + reg_rdata_next[0] = alert_cause_53_qs; end addr_hit[261]: begin - reg_rdata_next[0] = alert_cause_57_qs; + reg_rdata_next[0] = alert_cause_54_qs; end addr_hit[262]: begin - reg_rdata_next[0] = alert_cause_58_qs; + reg_rdata_next[0] = alert_cause_55_qs; end addr_hit[263]: begin - reg_rdata_next[0] = alert_cause_59_qs; + reg_rdata_next[0] = alert_cause_56_qs; end addr_hit[264]: begin - reg_rdata_next[0] = alert_cause_60_qs; + reg_rdata_next[0] = alert_cause_57_qs; end addr_hit[265]: begin - reg_rdata_next[0] = alert_cause_61_qs; + reg_rdata_next[0] = alert_cause_58_qs; end addr_hit[266]: begin - reg_rdata_next[0] = alert_cause_62_qs; + reg_rdata_next[0] = alert_cause_59_qs; end addr_hit[267]: begin - reg_rdata_next[0] = alert_cause_63_qs; + reg_rdata_next[0] = alert_cause_60_qs; end addr_hit[268]: begin - reg_rdata_next[0] = alert_cause_64_qs; + reg_rdata_next[0] = alert_cause_61_qs; end addr_hit[269]: begin - reg_rdata_next[0] = alert_cause_65_qs; + reg_rdata_next[0] = alert_cause_62_qs; end addr_hit[270]: begin - reg_rdata_next[0] = loc_alert_regwen_0_qs; + reg_rdata_next[0] = alert_cause_63_qs; end addr_hit[271]: begin - reg_rdata_next[0] = loc_alert_regwen_1_qs; + reg_rdata_next[0] = alert_cause_64_qs; end addr_hit[272]: begin - reg_rdata_next[0] = loc_alert_regwen_2_qs; + reg_rdata_next[0] = alert_cause_65_qs; end addr_hit[273]: begin - reg_rdata_next[0] = loc_alert_regwen_3_qs; + reg_rdata_next[0] = alert_cause_66_qs; end addr_hit[274]: begin - reg_rdata_next[0] = loc_alert_regwen_4_qs; + reg_rdata_next[0] = loc_alert_regwen_0_qs; end addr_hit[275]: begin - reg_rdata_next[0] = loc_alert_en_0_qs; + reg_rdata_next[0] = loc_alert_regwen_1_qs; end addr_hit[276]: begin - reg_rdata_next[0] = loc_alert_en_1_qs; + reg_rdata_next[0] = loc_alert_regwen_2_qs; end addr_hit[277]: begin - reg_rdata_next[0] = loc_alert_en_2_qs; + reg_rdata_next[0] = loc_alert_regwen_3_qs; end addr_hit[278]: begin - reg_rdata_next[0] = loc_alert_en_3_qs; + reg_rdata_next[0] = loc_alert_regwen_4_qs; end addr_hit[279]: begin - reg_rdata_next[0] = loc_alert_en_4_qs; + reg_rdata_next[0] = loc_alert_en_0_qs; end addr_hit[280]: begin - reg_rdata_next[1:0] = loc_alert_class_0_qs; + reg_rdata_next[0] = loc_alert_en_1_qs; end addr_hit[281]: begin - reg_rdata_next[1:0] = loc_alert_class_1_qs; + reg_rdata_next[0] = loc_alert_en_2_qs; end addr_hit[282]: begin - reg_rdata_next[1:0] = loc_alert_class_2_qs; + reg_rdata_next[0] = loc_alert_en_3_qs; end addr_hit[283]: begin - reg_rdata_next[1:0] = loc_alert_class_3_qs; + reg_rdata_next[0] = loc_alert_en_4_qs; end addr_hit[284]: begin - reg_rdata_next[1:0] = loc_alert_class_4_qs; + reg_rdata_next[1:0] = loc_alert_class_0_qs; end addr_hit[285]: begin - reg_rdata_next[0] = loc_alert_cause_0_qs; + reg_rdata_next[1:0] = loc_alert_class_1_qs; end addr_hit[286]: begin - reg_rdata_next[0] = loc_alert_cause_1_qs; + reg_rdata_next[1:0] = loc_alert_class_2_qs; end addr_hit[287]: begin - reg_rdata_next[0] = loc_alert_cause_2_qs; + reg_rdata_next[1:0] = loc_alert_class_3_qs; end addr_hit[288]: begin - reg_rdata_next[0] = loc_alert_cause_3_qs; + reg_rdata_next[1:0] = loc_alert_class_4_qs; end addr_hit[289]: begin - reg_rdata_next[0] = loc_alert_cause_4_qs; + reg_rdata_next[0] = loc_alert_cause_0_qs; end addr_hit[290]: begin - reg_rdata_next[0] = classa_regwen_qs; + reg_rdata_next[0] = loc_alert_cause_1_qs; end addr_hit[291]: begin + reg_rdata_next[0] = loc_alert_cause_2_qs; + end + + addr_hit[292]: begin + reg_rdata_next[0] = loc_alert_cause_3_qs; + end + + addr_hit[293]: begin + reg_rdata_next[0] = loc_alert_cause_4_qs; + end + + addr_hit[294]: begin + reg_rdata_next[0] = classa_regwen_qs; + end + + addr_hit[295]: begin reg_rdata_next[0] = classa_ctrl_en_qs; reg_rdata_next[1] = classa_ctrl_lock_qs; reg_rdata_next[2] = classa_ctrl_en_e0_qs; @@ -14433,55 +14589,55 @@ reg_rdata_next[13:12] = classa_ctrl_map_e3_qs; end - addr_hit[292]: begin + addr_hit[296]: begin reg_rdata_next[0] = classa_clr_regwen_qs; end - addr_hit[293]: begin + addr_hit[297]: begin reg_rdata_next[0] = '0; end - addr_hit[294]: begin + addr_hit[298]: begin reg_rdata_next[15:0] = classa_accum_cnt_qs; end - addr_hit[295]: begin + addr_hit[299]: begin reg_rdata_next[15:0] = classa_accum_thresh_qs; end - addr_hit[296]: begin + addr_hit[300]: begin reg_rdata_next[31:0] = classa_timeout_cyc_qs; end - addr_hit[297]: begin + addr_hit[301]: begin reg_rdata_next[31:0] = classa_phase0_cyc_qs; end - addr_hit[298]: begin + addr_hit[302]: begin reg_rdata_next[31:0] = classa_phase1_cyc_qs; end - addr_hit[299]: begin + addr_hit[303]: begin reg_rdata_next[31:0] = classa_phase2_cyc_qs; end - addr_hit[300]: begin + addr_hit[304]: begin reg_rdata_next[31:0] = classa_phase3_cyc_qs; end - addr_hit[301]: begin + addr_hit[305]: begin reg_rdata_next[31:0] = classa_esc_cnt_qs; end - addr_hit[302]: begin + addr_hit[306]: begin reg_rdata_next[2:0] = classa_state_qs; end - addr_hit[303]: begin + addr_hit[307]: begin reg_rdata_next[0] = classb_regwen_qs; end - addr_hit[304]: begin + addr_hit[308]: begin reg_rdata_next[0] = classb_ctrl_en_qs; reg_rdata_next[1] = classb_ctrl_lock_qs; reg_rdata_next[2] = classb_ctrl_en_e0_qs; @@ -14494,55 +14650,55 @@ reg_rdata_next[13:12] = classb_ctrl_map_e3_qs; end - addr_hit[305]: begin + addr_hit[309]: begin reg_rdata_next[0] = classb_clr_regwen_qs; end - addr_hit[306]: begin + addr_hit[310]: begin reg_rdata_next[0] = '0; end - addr_hit[307]: begin + addr_hit[311]: begin reg_rdata_next[15:0] = classb_accum_cnt_qs; end - addr_hit[308]: begin + addr_hit[312]: begin reg_rdata_next[15:0] = classb_accum_thresh_qs; end - addr_hit[309]: begin + addr_hit[313]: begin reg_rdata_next[31:0] = classb_timeout_cyc_qs; end - addr_hit[310]: begin + addr_hit[314]: begin reg_rdata_next[31:0] = classb_phase0_cyc_qs; end - addr_hit[311]: begin + addr_hit[315]: begin reg_rdata_next[31:0] = classb_phase1_cyc_qs; end - addr_hit[312]: begin + addr_hit[316]: begin reg_rdata_next[31:0] = classb_phase2_cyc_qs; end - addr_hit[313]: begin + addr_hit[317]: begin reg_rdata_next[31:0] = classb_phase3_cyc_qs; end - addr_hit[314]: begin + addr_hit[318]: begin reg_rdata_next[31:0] = classb_esc_cnt_qs; end - addr_hit[315]: begin + addr_hit[319]: begin reg_rdata_next[2:0] = classb_state_qs; end - addr_hit[316]: begin + addr_hit[320]: begin reg_rdata_next[0] = classc_regwen_qs; end - addr_hit[317]: begin + addr_hit[321]: begin reg_rdata_next[0] = classc_ctrl_en_qs; reg_rdata_next[1] = classc_ctrl_lock_qs; reg_rdata_next[2] = classc_ctrl_en_e0_qs; @@ -14555,55 +14711,55 @@ reg_rdata_next[13:12] = classc_ctrl_map_e3_qs; end - addr_hit[318]: begin + addr_hit[322]: begin reg_rdata_next[0] = classc_clr_regwen_qs; end - addr_hit[319]: begin + addr_hit[323]: begin reg_rdata_next[0] = '0; end - addr_hit[320]: begin + addr_hit[324]: begin reg_rdata_next[15:0] = classc_accum_cnt_qs; end - addr_hit[321]: begin + addr_hit[325]: begin reg_rdata_next[15:0] = classc_accum_thresh_qs; end - addr_hit[322]: begin + addr_hit[326]: begin reg_rdata_next[31:0] = classc_timeout_cyc_qs; end - addr_hit[323]: begin + addr_hit[327]: begin reg_rdata_next[31:0] = classc_phase0_cyc_qs; end - addr_hit[324]: begin + addr_hit[328]: begin reg_rdata_next[31:0] = classc_phase1_cyc_qs; end - addr_hit[325]: begin + addr_hit[329]: begin reg_rdata_next[31:0] = classc_phase2_cyc_qs; end - addr_hit[326]: begin + addr_hit[330]: begin reg_rdata_next[31:0] = classc_phase3_cyc_qs; end - addr_hit[327]: begin + addr_hit[331]: begin reg_rdata_next[31:0] = classc_esc_cnt_qs; end - addr_hit[328]: begin + addr_hit[332]: begin reg_rdata_next[2:0] = classc_state_qs; end - addr_hit[329]: begin + addr_hit[333]: begin reg_rdata_next[0] = classd_regwen_qs; end - addr_hit[330]: begin + addr_hit[334]: begin reg_rdata_next[0] = classd_ctrl_en_qs; reg_rdata_next[1] = classd_ctrl_lock_qs; reg_rdata_next[2] = classd_ctrl_en_e0_qs; @@ -14616,47 +14772,47 @@ reg_rdata_next[13:12] = classd_ctrl_map_e3_qs; end - addr_hit[331]: begin + addr_hit[335]: begin reg_rdata_next[0] = classd_clr_regwen_qs; end - addr_hit[332]: begin + addr_hit[336]: begin reg_rdata_next[0] = '0; end - addr_hit[333]: begin + addr_hit[337]: begin reg_rdata_next[15:0] = classd_accum_cnt_qs; end - addr_hit[334]: begin + addr_hit[338]: begin reg_rdata_next[15:0] = classd_accum_thresh_qs; end - addr_hit[335]: begin + addr_hit[339]: begin reg_rdata_next[31:0] = classd_timeout_cyc_qs; end - addr_hit[336]: begin + addr_hit[340]: begin reg_rdata_next[31:0] = classd_phase0_cyc_qs; end - addr_hit[337]: begin + addr_hit[341]: begin reg_rdata_next[31:0] = classd_phase1_cyc_qs; end - addr_hit[338]: begin + addr_hit[342]: begin reg_rdata_next[31:0] = classd_phase2_cyc_qs; end - addr_hit[339]: begin + addr_hit[343]: begin reg_rdata_next[31:0] = classd_phase3_cyc_qs; end - addr_hit[340]: begin + addr_hit[344]: begin reg_rdata_next[31:0] = classd_esc_cnt_qs; end - addr_hit[341]: begin + addr_hit[345]: begin reg_rdata_next[2:0] = classd_state_qs; end
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index e734dc0..ab5d1c1 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -1526,7 +1526,9 @@ .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]) ); - usbdev u_usbdev ( + usbdev #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[12:12]) + ) u_usbdev ( // Input .cio_sense_i (cio_usbdev_sense_p2d), @@ -1572,6 +1574,9 @@ .intr_frame_o (intr_usbdev_frame), .intr_connected_o (intr_usbdev_connected), .intr_link_out_err_o (intr_usbdev_link_out_err), + // [12]: fatal_fault + .alert_tx_o ( alert_tx[12:12] ), + .alert_rx_i ( alert_rx[12:12] ), // Inter-module signals .usb_ref_val_o(usbdev_usb_ref_val_o), @@ -1595,7 +1600,7 @@ ); otp_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[14:12]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[15:13]), .MemInitFile(OtpCtrlMemInitFile), .RndCnstLfsrSeed(RndCnstOtpCtrlLfsrSeed), .RndCnstLfsrPerm(RndCnstOtpCtrlLfsrPerm) @@ -1604,11 +1609,11 @@ // Interrupt .intr_otp_operation_done_o (intr_otp_ctrl_otp_operation_done), .intr_otp_error_o (intr_otp_ctrl_otp_error), - // [12]: fatal_macro_error - // [13]: fatal_check_error - // [14]: fatal_bus_integ_error - .alert_tx_o ( alert_tx[14:12] ), - .alert_rx_i ( alert_rx[14:12] ), + // [13]: fatal_macro_error + // [14]: fatal_check_error + // [15]: fatal_bus_integ_error + .alert_tx_o ( alert_tx[15:13] ), + .alert_rx_i ( alert_rx[15:13] ), // Inter-module signals .otp_ast_pwr_seq_o(otp_ctrl_otp_ast_pwr_seq_o), @@ -1649,16 +1654,16 @@ ); lc_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[17:15]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[18:16]), .RndCnstLcKeymgrDivInvalid(RndCnstLcCtrlLcKeymgrDivInvalid), .RndCnstLcKeymgrDivTestDevRma(RndCnstLcCtrlLcKeymgrDivTestDevRma), .RndCnstLcKeymgrDivProduction(RndCnstLcCtrlLcKeymgrDivProduction) ) u_lc_ctrl ( - // [15]: fatal_prog_error - // [16]: fatal_state_error - // [17]: fatal_bus_integ_error - .alert_tx_o ( alert_tx[17:15] ), - .alert_rx_i ( alert_rx[17:15] ), + // [16]: fatal_prog_error + // [17]: fatal_state_error + // [18]: fatal_bus_integ_error + .alert_tx_o ( alert_tx[18:16] ), + .alert_rx_i ( alert_rx[18:16] ), // Inter-module signals .jtag_i(pinmux_aon_lc_jtag_req), @@ -1736,14 +1741,14 @@ ); pwrmgr #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[18:18]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[19:19]) ) u_pwrmgr_aon ( // Interrupt .intr_wakeup_o (intr_pwrmgr_aon_wakeup), - // [18]: fatal_fault - .alert_tx_o ( alert_tx[18:18] ), - .alert_rx_i ( alert_rx[18:18] ), + // [19]: fatal_fault + .alert_tx_o ( alert_tx[19:19] ), + .alert_rx_i ( alert_rx[19:19] ), // Inter-module signals .pwr_ast_o(pwrmgr_ast_req_o), @@ -1777,11 +1782,11 @@ ); rstmgr #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[19:19]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[20:20]) ) u_rstmgr_aon ( - // [19]: fatal_fault - .alert_tx_o ( alert_tx[19:19] ), - .alert_rx_i ( alert_rx[19:19] ), + // [20]: fatal_fault + .alert_tx_o ( alert_tx[20:20] ), + .alert_rx_i ( alert_rx[20:20] ), // Inter-module signals .pwr_i(pwrmgr_aon_pwr_rst_req), @@ -1808,11 +1813,11 @@ ); clkmgr #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[20:20]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[21:21]) ) u_clkmgr_aon ( - // [20]: fatal_fault - .alert_tx_o ( alert_tx[20:20] ), - .alert_rx_i ( alert_rx[20:20] ), + // [21]: fatal_fault + .alert_tx_o ( alert_tx[21:21] ), + .alert_rx_i ( alert_rx[21:21] ), // Inter-module signals .clocks_o(clkmgr_aon_clocks), @@ -1845,7 +1850,7 @@ ); sysrst_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[21:21]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[22:22]) ) u_sysrst_ctrl_aon ( // Input @@ -1875,9 +1880,9 @@ // Interrupt .intr_sysrst_ctrl_o (intr_sysrst_ctrl_aon_sysrst_ctrl), - // [21]: fatal_fault - .alert_tx_o ( alert_tx[21:21] ), - .alert_rx_i ( alert_rx[21:21] ), + // [22]: fatal_fault + .alert_tx_o ( alert_tx[22:22] ), + .alert_rx_i ( alert_rx[22:22] ), // Inter-module signals .gsc_wk_o(pwrmgr_aon_wakeups[0]), @@ -1893,14 +1898,14 @@ ); adc_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[22:22]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[23:23]) ) u_adc_ctrl_aon ( // Interrupt .intr_debug_cable_o (intr_adc_ctrl_aon_debug_cable), - // [22]: fatal_fault - .alert_tx_o ( alert_tx[22:22] ), - .alert_rx_i ( alert_rx[22:22] ), + // [23]: fatal_fault + .alert_tx_o ( alert_tx[23:23] ), + .alert_rx_i ( alert_rx[23:23] ), // Inter-module signals .adc_o(adc_req_o), @@ -1917,15 +1922,15 @@ ); pwm #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[23:23]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[24:24]) ) u_pwm_aon ( // Output .cio_pwm_o (cio_pwm_aon_pwm_d2p), .cio_pwm_en_o (cio_pwm_aon_pwm_en_d2p), - // [23]: fatal_fault - .alert_tx_o ( alert_tx[23:23] ), - .alert_rx_i ( alert_rx[23:23] ), + // [24]: fatal_fault + .alert_tx_o ( alert_tx[24:24] ), + .alert_rx_i ( alert_rx[24:24] ), // Inter-module signals .tl_i(pwm_aon_tl_req), @@ -1939,12 +1944,12 @@ ); pinmux #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[24:24]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[25:25]), .TargetCfg(PinmuxAonTargetCfg) ) u_pinmux_aon ( - // [24]: fatal_fault - .alert_tx_o ( alert_tx[24:24] ), - .alert_rx_i ( alert_rx[24:24] ), + // [25]: fatal_fault + .alert_tx_o ( alert_tx[25:25] ), + .alert_rx_i ( alert_rx[25:25] ), // Inter-module signals .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), @@ -1997,15 +2002,15 @@ ); aon_timer #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[25:25]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[26:26]) ) u_aon_timer_aon ( // Interrupt .intr_wkup_timer_expired_o (intr_aon_timer_aon_wkup_timer_expired), .intr_wdog_timer_bark_o (intr_aon_timer_aon_wdog_timer_bark), - // [25]: fatal_fault - .alert_tx_o ( alert_tx[25:25] ), - .alert_rx_i ( alert_rx[25:25] ), + // [26]: fatal_fault + .alert_tx_o ( alert_tx[26:26] ), + .alert_rx_i ( alert_rx[26:26] ), // Inter-module signals .aon_timer_wkup_req_o(pwrmgr_aon_wakeups[4]), @@ -2023,27 +2028,27 @@ ); sensor_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[38:26]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[39:27]) ) u_sensor_ctrl_aon ( // Output .cio_ast_debug_out_o (cio_sensor_ctrl_aon_ast_debug_out_d2p), .cio_ast_debug_out_en_o (cio_sensor_ctrl_aon_ast_debug_out_en_d2p), - // [26]: recov_as - // [27]: recov_cg - // [28]: recov_gd - // [29]: recov_ts_hi - // [30]: recov_ts_lo - // [31]: recov_fla - // [32]: recov_otp - // [33]: recov_ot0 - // [34]: recov_ot1 - // [35]: recov_ot2 - // [36]: recov_ot3 - // [37]: recov_ot4 - // [38]: recov_ot5 - .alert_tx_o ( alert_tx[38:26] ), - .alert_rx_i ( alert_rx[38:26] ), + // [27]: recov_as + // [28]: recov_cg + // [29]: recov_gd + // [30]: recov_ts_hi + // [31]: recov_ts_lo + // [32]: recov_fla + // [33]: recov_otp + // [34]: recov_ot0 + // [35]: recov_ot1 + // [36]: recov_ot2 + // [37]: recov_ot3 + // [38]: recov_ot4 + // [39]: recov_ot5 + .alert_tx_o ( alert_tx[39:27] ), + .alert_rx_i ( alert_rx[39:27] ), // Inter-module signals .ast_alert_i(sensor_ctrl_ast_alert_req_i), @@ -2060,16 +2065,16 @@ ); sram_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[40:39]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[41:40]), .RndCnstSramKey(RndCnstSramCtrlRetAonSramKey), .RndCnstSramNonce(RndCnstSramCtrlRetAonSramNonce), .RndCnstSramLfsrPerm(RndCnstSramCtrlRetAonSramLfsrPerm), .InstrExec(SramCtrlRetAonInstrExec) ) u_sram_ctrl_ret_aon ( - // [39]: fatal_intg_error - // [40]: fatal_parity_error - .alert_tx_o ( alert_tx[40:39] ), - .alert_rx_i ( alert_rx[40:39] ), + // [40]: fatal_intg_error + // [41]: fatal_parity_error + .alert_tx_o ( alert_tx[41:40] ), + .alert_rx_i ( alert_rx[41:40] ), // Inter-module signals .sram_otp_key_o(otp_ctrl_sram_otp_key_req[1]), @@ -2094,7 +2099,7 @@ ); flash_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[44:41]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[45:42]), .RndCnstAddrKey(RndCnstFlashCtrlAddrKey), .RndCnstDataKey(RndCnstFlashCtrlDataKey), .RndCnstLfsrSeed(RndCnstFlashCtrlLfsrSeed), @@ -2117,12 +2122,12 @@ .intr_rd_lvl_o (intr_flash_ctrl_rd_lvl), .intr_op_done_o (intr_flash_ctrl_op_done), .intr_err_o (intr_flash_ctrl_err), - // [41]: recov_err - // [42]: recov_mp_err - // [43]: recov_ecc_err - // [44]: fatal_intg_err - .alert_tx_o ( alert_tx[44:41] ), - .alert_rx_i ( alert_rx[44:41] ), + // [42]: recov_err + // [43]: recov_mp_err + // [44]: recov_ecc_err + // [45]: fatal_intg_err + .alert_tx_o ( alert_tx[45:42] ), + .alert_rx_i ( alert_rx[45:42] ), // Inter-module signals .flash_o(flash_ctrl_flash_req), @@ -2153,11 +2158,11 @@ ); rv_plic #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[45:45]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:46]) ) u_rv_plic ( - // [45]: fatal_fault - .alert_tx_o ( alert_tx[45:45] ), - .alert_rx_i ( alert_rx[45:45] ), + // [46]: fatal_fault + .alert_tx_o ( alert_tx[46:46] ), + .alert_rx_i ( alert_rx[46:46] ), // Inter-module signals .tl_i(rv_plic_tl_req), @@ -2174,7 +2179,7 @@ ); aes #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[47:46]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[48:47]), .AES192Enable(1'b1), .Masking(AesMasking), .SBoxImpl(AesSBoxImpl), @@ -2187,10 +2192,10 @@ .RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed), .RndCnstMskgChunkLfsrPerm(RndCnstAesMskgChunkLfsrPerm) ) u_aes ( - // [46]: recov_ctrl_update_err - // [47]: fatal_fault - .alert_tx_o ( alert_tx[47:46] ), - .alert_rx_i ( alert_rx[47:46] ), + // [47]: recov_ctrl_update_err + // [48]: fatal_fault + .alert_tx_o ( alert_tx[48:47] ), + .alert_rx_i ( alert_rx[48:47] ), // Inter-module signals .idle_o(clkmgr_aon_idle[0]), @@ -2208,16 +2213,16 @@ ); hmac #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[48:48]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[49:49]) ) u_hmac ( // Interrupt .intr_hmac_done_o (intr_hmac_hmac_done), .intr_fifo_empty_o (intr_hmac_fifo_empty), .intr_hmac_err_o (intr_hmac_hmac_err), - // [48]: fatal_fault - .alert_tx_o ( alert_tx[48:48] ), - .alert_rx_i ( alert_rx[48:48] ), + // [49]: fatal_fault + .alert_tx_o ( alert_tx[49:49] ), + .alert_rx_i ( alert_rx[49:49] ), // Inter-module signals .idle_o(clkmgr_aon_idle[1]), @@ -2230,7 +2235,7 @@ ); kmac #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[49:49]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[50:50]), .EnMasking(KmacEnMasking), .ReuseShare(KmacReuseShare) ) u_kmac ( @@ -2239,9 +2244,9 @@ .intr_kmac_done_o (intr_kmac_kmac_done), .intr_fifo_empty_o (intr_kmac_fifo_empty), .intr_kmac_err_o (intr_kmac_kmac_err), - // [49]: fatal_fault - .alert_tx_o ( alert_tx[49:49] ), - .alert_rx_i ( alert_rx[49:49] ), + // [50]: fatal_fault + .alert_tx_o ( alert_tx[50:50] ), + .alert_rx_i ( alert_rx[50:50] ), // Inter-module signals .keymgr_key_i(keymgr_kmac_key), @@ -2261,7 +2266,7 @@ ); keymgr #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[51:50]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:51]), .RndCnstLfsrSeed(RndCnstKeymgrLfsrSeed), .RndCnstLfsrPerm(RndCnstKeymgrLfsrPerm), .RndCnstRandPerm(RndCnstKeymgrRandPerm), @@ -2279,10 +2284,10 @@ // Interrupt .intr_op_done_o (intr_keymgr_op_done), - // [50]: fatal_fault_err - // [51]: recov_operation_err - .alert_tx_o ( alert_tx[51:50] ), - .alert_rx_i ( alert_rx[51:50] ), + // [51]: fatal_fault_err + // [52]: recov_operation_err + .alert_tx_o ( alert_tx[52:51] ), + .alert_rx_i ( alert_rx[52:51] ), // Inter-module signals .edn_o(edn0_edn_req[0]), @@ -2309,7 +2314,7 @@ ); csrng #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:52]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[53:53]), .RndCnstCsKeymgrDivNonProduction(RndCnstCsrngCsKeymgrDivNonProduction), .RndCnstCsKeymgrDivProduction(RndCnstCsrngCsKeymgrDivProduction), .SBoxImpl(CsrngSBoxImpl) @@ -2320,9 +2325,9 @@ .intr_cs_entropy_req_o (intr_csrng_cs_entropy_req), .intr_cs_hw_inst_exc_o (intr_csrng_cs_hw_inst_exc), .intr_cs_fatal_err_o (intr_csrng_cs_fatal_err), - // [52]: fatal_alert - .alert_tx_o ( alert_tx[52:52] ), - .alert_rx_i ( alert_rx[52:52] ), + // [53]: fatal_alert + .alert_tx_o ( alert_tx[53:53] ), + .alert_rx_i ( alert_rx[53:53] ), // Inter-module signals .csrng_cmd_i(csrng_csrng_cmd_req), @@ -2342,7 +2347,7 @@ ); entropy_src #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[54:53]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[55:54]), .Stub(EntropySrcStub) ) u_entropy_src ( @@ -2351,10 +2356,10 @@ .intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed), .intr_es_observe_fifo_ready_o (intr_entropy_src_es_observe_fifo_ready), .intr_es_fatal_err_o (intr_entropy_src_es_fatal_err), - // [53]: recov_alert - // [54]: fatal_alert - .alert_tx_o ( alert_tx[54:53] ), - .alert_rx_i ( alert_rx[54:53] ), + // [54]: recov_alert + // [55]: fatal_alert + .alert_tx_o ( alert_tx[55:54] ), + .alert_rx_i ( alert_rx[55:54] ), // Inter-module signals .entropy_src_hw_if_i(csrng_entropy_src_hw_if_req), @@ -2377,15 +2382,15 @@ ); edn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[55:55]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[56:56]) ) u_edn0 ( // Interrupt .intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done), .intr_edn_fatal_err_o (intr_edn0_edn_fatal_err), - // [55]: fatal_alert - .alert_tx_o ( alert_tx[55:55] ), - .alert_rx_i ( alert_rx[55:55] ), + // [56]: fatal_alert + .alert_tx_o ( alert_tx[56:56] ), + .alert_rx_i ( alert_rx[56:56] ), // Inter-module signals .csrng_cmd_o(csrng_csrng_cmd_req[0]), @@ -2401,15 +2406,15 @@ ); edn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[56:56]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[57:57]) ) u_edn1 ( // Interrupt .intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done), .intr_edn_fatal_err_o (intr_edn1_edn_fatal_err), - // [56]: fatal_alert - .alert_tx_o ( alert_tx[56:56] ), - .alert_rx_i ( alert_rx[56:56] ), + // [57]: fatal_alert + .alert_tx_o ( alert_tx[57:57] ), + .alert_rx_i ( alert_rx[57:57] ), // Inter-module signals .csrng_cmd_o(csrng_csrng_cmd_req[1]), @@ -2425,16 +2430,16 @@ ); sram_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[58:57]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[59:58]), .RndCnstSramKey(RndCnstSramCtrlMainSramKey), .RndCnstSramNonce(RndCnstSramCtrlMainSramNonce), .RndCnstSramLfsrPerm(RndCnstSramCtrlMainSramLfsrPerm), .InstrExec(SramCtrlMainInstrExec) ) u_sram_ctrl_main ( - // [57]: fatal_intg_error - // [58]: fatal_parity_error - .alert_tx_o ( alert_tx[58:57] ), - .alert_rx_i ( alert_rx[58:57] ), + // [58]: fatal_intg_error + // [59]: fatal_parity_error + .alert_tx_o ( alert_tx[59:58] ), + .alert_rx_i ( alert_rx[59:58] ), // Inter-module signals .sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]), @@ -2459,7 +2464,7 @@ ); otbn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[60:59]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[61:60]), .Stub(OtbnStub), .RegFile(OtbnRegFile), .RndCnstUrndLfsrSeed(RndCnstOtbnUrndLfsrSeed), @@ -2470,10 +2475,10 @@ // Interrupt .intr_done_o (intr_otbn_done), - // [59]: fatal - // [60]: recov - .alert_tx_o ( alert_tx[60:59] ), - .alert_rx_i ( alert_rx[60:59] ), + // [60]: fatal + // [61]: recov + .alert_tx_o ( alert_tx[61:60] ), + .alert_rx_i ( alert_rx[61:60] ), // Inter-module signals .otbn_otp_key_o(otp_ctrl_otbn_otp_key_req), @@ -2497,14 +2502,14 @@ ); rom_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[61:61]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[62:62]), .BootRomInitFile(RomCtrlBootRomInitFile), .RndCnstScrNonce(RndCnstRomCtrlScrNonce), .RndCnstScrKey(RndCnstRomCtrlScrKey) ) u_rom_ctrl ( - // [61]: fatal - .alert_tx_o ( alert_tx[61:61] ), - .alert_rx_i ( alert_rx[61:61] ), + // [62]: fatal + .alert_tx_o ( alert_tx[62:62] ), + .alert_rx_i ( alert_rx[62:62] ), // Inter-module signals .rom_cfg_i(ast_rom_cfg), @@ -2523,14 +2528,14 @@ ); rv_core_ibex_peri #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[65:62]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[66:63]) ) u_rv_core_ibex_peri ( - // [62]: fatal_sw_err - // [63]: recov_sw_err - // [64]: fatal_hw_err - // [65]: recov_hw_err - .alert_tx_o ( alert_tx[65:62] ), - .alert_rx_i ( alert_rx[65:62] ), + // [63]: fatal_sw_err + // [64]: recov_sw_err + // [65]: fatal_hw_err + // [66]: recov_hw_err + .alert_tx_o ( alert_tx[66:63] ), + .alert_rx_i ( alert_rx[66:63] ), // Inter-module signals .fatal_intg_event_i(rv_core_ibex_fatal_intg_event),
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c index c0dbea7..989f0f4 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -202,7 +202,7 @@ * `top_earlgrey_alert_peripheral_t`. */ const top_earlgrey_alert_peripheral_t - top_earlgrey_alert_for_peripheral[66] = { + top_earlgrey_alert_for_peripheral[67] = { [kTopEarlgreyAlertIdUart0FatalFault] = kTopEarlgreyAlertPeripheralUart0, [kTopEarlgreyAlertIdUart1FatalFault] = kTopEarlgreyAlertPeripheralUart1, [kTopEarlgreyAlertIdUart2FatalFault] = kTopEarlgreyAlertPeripheralUart2, @@ -215,6 +215,7 @@ [kTopEarlgreyAlertIdI2c1FatalFault] = kTopEarlgreyAlertPeripheralI2c1, [kTopEarlgreyAlertIdI2c2FatalFault] = kTopEarlgreyAlertPeripheralI2c2, [kTopEarlgreyAlertIdPattgenFatalFault] = kTopEarlgreyAlertPeripheralPattgen, + [kTopEarlgreyAlertIdUsbdevFatalFault] = kTopEarlgreyAlertPeripheralUsbdev, [kTopEarlgreyAlertIdOtpCtrlFatalMacroError] = kTopEarlgreyAlertPeripheralOtpCtrl, [kTopEarlgreyAlertIdOtpCtrlFatalCheckError] = kTopEarlgreyAlertPeripheralOtpCtrl, [kTopEarlgreyAlertIdOtpCtrlFatalBusIntegError] = kTopEarlgreyAlertPeripheralOtpCtrl,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h index f6ee209..97bd54b 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -1118,33 +1118,34 @@ kTopEarlgreyAlertPeripheralI2c1 = 9, /**< i2c1 */ kTopEarlgreyAlertPeripheralI2c2 = 10, /**< i2c2 */ kTopEarlgreyAlertPeripheralPattgen = 11, /**< pattgen */ - kTopEarlgreyAlertPeripheralOtpCtrl = 12, /**< otp_ctrl */ - kTopEarlgreyAlertPeripheralLcCtrl = 13, /**< lc_ctrl */ - kTopEarlgreyAlertPeripheralPwrmgrAon = 14, /**< pwrmgr_aon */ - kTopEarlgreyAlertPeripheralRstmgrAon = 15, /**< rstmgr_aon */ - kTopEarlgreyAlertPeripheralClkmgrAon = 16, /**< clkmgr_aon */ - kTopEarlgreyAlertPeripheralSysrstCtrlAon = 17, /**< sysrst_ctrl_aon */ - kTopEarlgreyAlertPeripheralAdcCtrlAon = 18, /**< adc_ctrl_aon */ - kTopEarlgreyAlertPeripheralPwmAon = 19, /**< pwm_aon */ - kTopEarlgreyAlertPeripheralPinmuxAon = 20, /**< pinmux_aon */ - kTopEarlgreyAlertPeripheralAonTimerAon = 21, /**< aon_timer_aon */ - kTopEarlgreyAlertPeripheralSensorCtrlAon = 22, /**< sensor_ctrl_aon */ - kTopEarlgreyAlertPeripheralSramCtrlRetAon = 23, /**< sram_ctrl_ret_aon */ - kTopEarlgreyAlertPeripheralFlashCtrl = 24, /**< flash_ctrl */ - kTopEarlgreyAlertPeripheralRvPlic = 25, /**< rv_plic */ - kTopEarlgreyAlertPeripheralAes = 26, /**< aes */ - kTopEarlgreyAlertPeripheralHmac = 27, /**< hmac */ - kTopEarlgreyAlertPeripheralKmac = 28, /**< kmac */ - kTopEarlgreyAlertPeripheralKeymgr = 29, /**< keymgr */ - kTopEarlgreyAlertPeripheralCsrng = 30, /**< csrng */ - kTopEarlgreyAlertPeripheralEntropySrc = 31, /**< entropy_src */ - kTopEarlgreyAlertPeripheralEdn0 = 32, /**< edn0 */ - kTopEarlgreyAlertPeripheralEdn1 = 33, /**< edn1 */ - kTopEarlgreyAlertPeripheralSramCtrlMain = 34, /**< sram_ctrl_main */ - kTopEarlgreyAlertPeripheralOtbn = 35, /**< otbn */ - kTopEarlgreyAlertPeripheralRomCtrl = 36, /**< rom_ctrl */ - kTopEarlgreyAlertPeripheralRvCoreIbexPeri = 37, /**< rv_core_ibex_peri */ - kTopEarlgreyAlertPeripheralLast = 37, /**< \internal Final Alert peripheral */ + kTopEarlgreyAlertPeripheralUsbdev = 12, /**< usbdev */ + kTopEarlgreyAlertPeripheralOtpCtrl = 13, /**< otp_ctrl */ + kTopEarlgreyAlertPeripheralLcCtrl = 14, /**< lc_ctrl */ + kTopEarlgreyAlertPeripheralPwrmgrAon = 15, /**< pwrmgr_aon */ + kTopEarlgreyAlertPeripheralRstmgrAon = 16, /**< rstmgr_aon */ + kTopEarlgreyAlertPeripheralClkmgrAon = 17, /**< clkmgr_aon */ + kTopEarlgreyAlertPeripheralSysrstCtrlAon = 18, /**< sysrst_ctrl_aon */ + kTopEarlgreyAlertPeripheralAdcCtrlAon = 19, /**< adc_ctrl_aon */ + kTopEarlgreyAlertPeripheralPwmAon = 20, /**< pwm_aon */ + kTopEarlgreyAlertPeripheralPinmuxAon = 21, /**< pinmux_aon */ + kTopEarlgreyAlertPeripheralAonTimerAon = 22, /**< aon_timer_aon */ + kTopEarlgreyAlertPeripheralSensorCtrlAon = 23, /**< sensor_ctrl_aon */ + kTopEarlgreyAlertPeripheralSramCtrlRetAon = 24, /**< sram_ctrl_ret_aon */ + kTopEarlgreyAlertPeripheralFlashCtrl = 25, /**< flash_ctrl */ + kTopEarlgreyAlertPeripheralRvPlic = 26, /**< rv_plic */ + kTopEarlgreyAlertPeripheralAes = 27, /**< aes */ + kTopEarlgreyAlertPeripheralHmac = 28, /**< hmac */ + kTopEarlgreyAlertPeripheralKmac = 29, /**< kmac */ + kTopEarlgreyAlertPeripheralKeymgr = 30, /**< keymgr */ + kTopEarlgreyAlertPeripheralCsrng = 31, /**< csrng */ + kTopEarlgreyAlertPeripheralEntropySrc = 32, /**< entropy_src */ + kTopEarlgreyAlertPeripheralEdn0 = 33, /**< edn0 */ + kTopEarlgreyAlertPeripheralEdn1 = 34, /**< edn1 */ + kTopEarlgreyAlertPeripheralSramCtrlMain = 35, /**< sram_ctrl_main */ + kTopEarlgreyAlertPeripheralOtbn = 36, /**< otbn */ + kTopEarlgreyAlertPeripheralRomCtrl = 37, /**< rom_ctrl */ + kTopEarlgreyAlertPeripheralRvCoreIbexPeri = 38, /**< rv_core_ibex_peri */ + kTopEarlgreyAlertPeripheralLast = 38, /**< \internal Final Alert peripheral */ } top_earlgrey_alert_peripheral_t; /** @@ -1166,61 +1167,62 @@ kTopEarlgreyAlertIdI2c1FatalFault = 9, /**< i2c1_fatal_fault */ kTopEarlgreyAlertIdI2c2FatalFault = 10, /**< i2c2_fatal_fault */ kTopEarlgreyAlertIdPattgenFatalFault = 11, /**< pattgen_fatal_fault */ - kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 12, /**< otp_ctrl_fatal_macro_error */ - kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 13, /**< otp_ctrl_fatal_check_error */ - kTopEarlgreyAlertIdOtpCtrlFatalBusIntegError = 14, /**< otp_ctrl_fatal_bus_integ_error */ - kTopEarlgreyAlertIdLcCtrlFatalProgError = 15, /**< lc_ctrl_fatal_prog_error */ - kTopEarlgreyAlertIdLcCtrlFatalStateError = 16, /**< lc_ctrl_fatal_state_error */ - kTopEarlgreyAlertIdLcCtrlFatalBusIntegError = 17, /**< lc_ctrl_fatal_bus_integ_error */ - kTopEarlgreyAlertIdPwrmgrAonFatalFault = 18, /**< pwrmgr_aon_fatal_fault */ - kTopEarlgreyAlertIdRstmgrAonFatalFault = 19, /**< rstmgr_aon_fatal_fault */ - kTopEarlgreyAlertIdClkmgrAonFatalFault = 20, /**< clkmgr_aon_fatal_fault */ - kTopEarlgreyAlertIdSysrstCtrlAonFatalFault = 21, /**< sysrst_ctrl_aon_fatal_fault */ - kTopEarlgreyAlertIdAdcCtrlAonFatalFault = 22, /**< adc_ctrl_aon_fatal_fault */ - kTopEarlgreyAlertIdPwmAonFatalFault = 23, /**< pwm_aon_fatal_fault */ - kTopEarlgreyAlertIdPinmuxAonFatalFault = 24, /**< pinmux_aon_fatal_fault */ - kTopEarlgreyAlertIdAonTimerAonFatalFault = 25, /**< aon_timer_aon_fatal_fault */ - kTopEarlgreyAlertIdSensorCtrlAonRecovAs = 26, /**< sensor_ctrl_aon_recov_as */ - kTopEarlgreyAlertIdSensorCtrlAonRecovCg = 27, /**< sensor_ctrl_aon_recov_cg */ - kTopEarlgreyAlertIdSensorCtrlAonRecovGd = 28, /**< sensor_ctrl_aon_recov_gd */ - kTopEarlgreyAlertIdSensorCtrlAonRecovTsHi = 29, /**< sensor_ctrl_aon_recov_ts_hi */ - kTopEarlgreyAlertIdSensorCtrlAonRecovTsLo = 30, /**< sensor_ctrl_aon_recov_ts_lo */ - kTopEarlgreyAlertIdSensorCtrlAonRecovFla = 31, /**< sensor_ctrl_aon_recov_fla */ - kTopEarlgreyAlertIdSensorCtrlAonRecovOtp = 32, /**< sensor_ctrl_aon_recov_otp */ - kTopEarlgreyAlertIdSensorCtrlAonRecovOt0 = 33, /**< sensor_ctrl_aon_recov_ot0 */ - kTopEarlgreyAlertIdSensorCtrlAonRecovOt1 = 34, /**< sensor_ctrl_aon_recov_ot1 */ - kTopEarlgreyAlertIdSensorCtrlAonRecovOt2 = 35, /**< sensor_ctrl_aon_recov_ot2 */ - kTopEarlgreyAlertIdSensorCtrlAonRecovOt3 = 36, /**< sensor_ctrl_aon_recov_ot3 */ - kTopEarlgreyAlertIdSensorCtrlAonRecovOt4 = 37, /**< sensor_ctrl_aon_recov_ot4 */ - kTopEarlgreyAlertIdSensorCtrlAonRecovOt5 = 38, /**< sensor_ctrl_aon_recov_ot5 */ - kTopEarlgreyAlertIdSramCtrlRetAonFatalIntgError = 39, /**< sram_ctrl_ret_aon_fatal_intg_error */ - kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 40, /**< sram_ctrl_ret_aon_fatal_parity_error */ - kTopEarlgreyAlertIdFlashCtrlRecovErr = 41, /**< flash_ctrl_recov_err */ - kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 42, /**< flash_ctrl_recov_mp_err */ - kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 43, /**< flash_ctrl_recov_ecc_err */ - kTopEarlgreyAlertIdFlashCtrlFatalIntgErr = 44, /**< flash_ctrl_fatal_intg_err */ - kTopEarlgreyAlertIdRvPlicFatalFault = 45, /**< rv_plic_fatal_fault */ - kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 46, /**< aes_recov_ctrl_update_err */ - kTopEarlgreyAlertIdAesFatalFault = 47, /**< aes_fatal_fault */ - kTopEarlgreyAlertIdHmacFatalFault = 48, /**< hmac_fatal_fault */ - kTopEarlgreyAlertIdKmacFatalFault = 49, /**< kmac_fatal_fault */ - kTopEarlgreyAlertIdKeymgrFatalFaultErr = 50, /**< keymgr_fatal_fault_err */ - kTopEarlgreyAlertIdKeymgrRecovOperationErr = 51, /**< keymgr_recov_operation_err */ - kTopEarlgreyAlertIdCsrngFatalAlert = 52, /**< csrng_fatal_alert */ - kTopEarlgreyAlertIdEntropySrcRecovAlert = 53, /**< entropy_src_recov_alert */ - kTopEarlgreyAlertIdEntropySrcFatalAlert = 54, /**< entropy_src_fatal_alert */ - kTopEarlgreyAlertIdEdn0FatalAlert = 55, /**< edn0_fatal_alert */ - kTopEarlgreyAlertIdEdn1FatalAlert = 56, /**< edn1_fatal_alert */ - kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 57, /**< sram_ctrl_main_fatal_intg_error */ - kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 58, /**< sram_ctrl_main_fatal_parity_error */ - kTopEarlgreyAlertIdOtbnFatal = 59, /**< otbn_fatal */ - kTopEarlgreyAlertIdOtbnRecov = 60, /**< otbn_recov */ - kTopEarlgreyAlertIdRomCtrlFatal = 61, /**< rom_ctrl_fatal */ - kTopEarlgreyAlertIdRvCoreIbexPeriFatalSwErr = 62, /**< rv_core_ibex_peri_fatal_sw_err */ - kTopEarlgreyAlertIdRvCoreIbexPeriRecovSwErr = 63, /**< rv_core_ibex_peri_recov_sw_err */ - kTopEarlgreyAlertIdRvCoreIbexPeriFatalHwErr = 64, /**< rv_core_ibex_peri_fatal_hw_err */ - kTopEarlgreyAlertIdRvCoreIbexPeriRecovHwErr = 65, /**< rv_core_ibex_peri_recov_hw_err */ - kTopEarlgreyAlertIdLast = 65, /**< \internal The Last Valid Alert ID. */ + kTopEarlgreyAlertIdUsbdevFatalFault = 12, /**< usbdev_fatal_fault */ + kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 13, /**< otp_ctrl_fatal_macro_error */ + kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 14, /**< otp_ctrl_fatal_check_error */ + kTopEarlgreyAlertIdOtpCtrlFatalBusIntegError = 15, /**< otp_ctrl_fatal_bus_integ_error */ + kTopEarlgreyAlertIdLcCtrlFatalProgError = 16, /**< lc_ctrl_fatal_prog_error */ + kTopEarlgreyAlertIdLcCtrlFatalStateError = 17, /**< lc_ctrl_fatal_state_error */ + kTopEarlgreyAlertIdLcCtrlFatalBusIntegError = 18, /**< lc_ctrl_fatal_bus_integ_error */ + kTopEarlgreyAlertIdPwrmgrAonFatalFault = 19, /**< pwrmgr_aon_fatal_fault */ + kTopEarlgreyAlertIdRstmgrAonFatalFault = 20, /**< rstmgr_aon_fatal_fault */ + kTopEarlgreyAlertIdClkmgrAonFatalFault = 21, /**< clkmgr_aon_fatal_fault */ + kTopEarlgreyAlertIdSysrstCtrlAonFatalFault = 22, /**< sysrst_ctrl_aon_fatal_fault */ + kTopEarlgreyAlertIdAdcCtrlAonFatalFault = 23, /**< adc_ctrl_aon_fatal_fault */ + kTopEarlgreyAlertIdPwmAonFatalFault = 24, /**< pwm_aon_fatal_fault */ + kTopEarlgreyAlertIdPinmuxAonFatalFault = 25, /**< pinmux_aon_fatal_fault */ + kTopEarlgreyAlertIdAonTimerAonFatalFault = 26, /**< aon_timer_aon_fatal_fault */ + kTopEarlgreyAlertIdSensorCtrlAonRecovAs = 27, /**< sensor_ctrl_aon_recov_as */ + kTopEarlgreyAlertIdSensorCtrlAonRecovCg = 28, /**< sensor_ctrl_aon_recov_cg */ + kTopEarlgreyAlertIdSensorCtrlAonRecovGd = 29, /**< sensor_ctrl_aon_recov_gd */ + kTopEarlgreyAlertIdSensorCtrlAonRecovTsHi = 30, /**< sensor_ctrl_aon_recov_ts_hi */ + kTopEarlgreyAlertIdSensorCtrlAonRecovTsLo = 31, /**< sensor_ctrl_aon_recov_ts_lo */ + kTopEarlgreyAlertIdSensorCtrlAonRecovFla = 32, /**< sensor_ctrl_aon_recov_fla */ + kTopEarlgreyAlertIdSensorCtrlAonRecovOtp = 33, /**< sensor_ctrl_aon_recov_otp */ + kTopEarlgreyAlertIdSensorCtrlAonRecovOt0 = 34, /**< sensor_ctrl_aon_recov_ot0 */ + kTopEarlgreyAlertIdSensorCtrlAonRecovOt1 = 35, /**< sensor_ctrl_aon_recov_ot1 */ + kTopEarlgreyAlertIdSensorCtrlAonRecovOt2 = 36, /**< sensor_ctrl_aon_recov_ot2 */ + kTopEarlgreyAlertIdSensorCtrlAonRecovOt3 = 37, /**< sensor_ctrl_aon_recov_ot3 */ + kTopEarlgreyAlertIdSensorCtrlAonRecovOt4 = 38, /**< sensor_ctrl_aon_recov_ot4 */ + kTopEarlgreyAlertIdSensorCtrlAonRecovOt5 = 39, /**< sensor_ctrl_aon_recov_ot5 */ + kTopEarlgreyAlertIdSramCtrlRetAonFatalIntgError = 40, /**< sram_ctrl_ret_aon_fatal_intg_error */ + kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 41, /**< sram_ctrl_ret_aon_fatal_parity_error */ + kTopEarlgreyAlertIdFlashCtrlRecovErr = 42, /**< flash_ctrl_recov_err */ + kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 43, /**< flash_ctrl_recov_mp_err */ + kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 44, /**< flash_ctrl_recov_ecc_err */ + kTopEarlgreyAlertIdFlashCtrlFatalIntgErr = 45, /**< flash_ctrl_fatal_intg_err */ + kTopEarlgreyAlertIdRvPlicFatalFault = 46, /**< rv_plic_fatal_fault */ + kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 47, /**< aes_recov_ctrl_update_err */ + kTopEarlgreyAlertIdAesFatalFault = 48, /**< aes_fatal_fault */ + kTopEarlgreyAlertIdHmacFatalFault = 49, /**< hmac_fatal_fault */ + kTopEarlgreyAlertIdKmacFatalFault = 50, /**< kmac_fatal_fault */ + kTopEarlgreyAlertIdKeymgrFatalFaultErr = 51, /**< keymgr_fatal_fault_err */ + kTopEarlgreyAlertIdKeymgrRecovOperationErr = 52, /**< keymgr_recov_operation_err */ + kTopEarlgreyAlertIdCsrngFatalAlert = 53, /**< csrng_fatal_alert */ + kTopEarlgreyAlertIdEntropySrcRecovAlert = 54, /**< entropy_src_recov_alert */ + kTopEarlgreyAlertIdEntropySrcFatalAlert = 55, /**< entropy_src_fatal_alert */ + kTopEarlgreyAlertIdEdn0FatalAlert = 56, /**< edn0_fatal_alert */ + kTopEarlgreyAlertIdEdn1FatalAlert = 57, /**< edn1_fatal_alert */ + kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 58, /**< sram_ctrl_main_fatal_intg_error */ + kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 59, /**< sram_ctrl_main_fatal_parity_error */ + kTopEarlgreyAlertIdOtbnFatal = 60, /**< otbn_fatal */ + kTopEarlgreyAlertIdOtbnRecov = 61, /**< otbn_recov */ + kTopEarlgreyAlertIdRomCtrlFatal = 62, /**< rom_ctrl_fatal */ + kTopEarlgreyAlertIdRvCoreIbexPeriFatalSwErr = 63, /**< rv_core_ibex_peri_fatal_sw_err */ + kTopEarlgreyAlertIdRvCoreIbexPeriRecovSwErr = 64, /**< rv_core_ibex_peri_recov_sw_err */ + kTopEarlgreyAlertIdRvCoreIbexPeriFatalHwErr = 65, /**< rv_core_ibex_peri_fatal_hw_err */ + kTopEarlgreyAlertIdRvCoreIbexPeriRecovHwErr = 66, /**< rv_core_ibex_peri_recov_hw_err */ + kTopEarlgreyAlertIdLast = 66, /**< \internal The Last Valid Alert ID. */ } top_earlgrey_alert_id_t; /** @@ -1230,7 +1232,7 @@ * `top_earlgrey_alert_peripheral_t`. */ extern const top_earlgrey_alert_peripheral_t - top_earlgrey_alert_for_peripheral[66]; + top_earlgrey_alert_for_peripheral[67]; #define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2