[chip_earlgrey_asic/lint] Fix/waive remaining AST-related lint messages
Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/hw/top_earlgrey/ip/ast/lint/ast.waiver b/hw/top_earlgrey/ip/ast/lint/ast.waiver
index fdd938b..d2b4de2 100644
--- a/hw/top_earlgrey/ip/ast/lint/ast.waiver
+++ b/hw/top_earlgrey/ip/ast/lint/ast.waiver
@@ -25,11 +25,11 @@
-comment {This is a valid clock signal and the LFSR runs on the bus clock here.}
waive -rules CLOCK_USE -location {ast.sv} \
- -regexp {'clk_aon' is connected to 'rglts_pdm_3p3v' port 'clk_src_aon_h_i', and used as a clock 'clk_i' at prim_generic_flop} \
+ -regexp {'clk_aon' is connected to 'rglts_pdm_3p3v' port 'clk_src_aon_h_i', and used as a clock} \
-comment {This is a valid clock signal and the connection is ok here.}
waive -rules RESET_DRIVER -location {aon_clk.sv io_clk.sv sys_clk.sv usb_clk.sv} \
- -msg {'rst_val_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \
+ -msg {'rst_val_n' is driven here, and used as an asynchronous reset} \
-comment {This is reset generation logic, hence it needs to drive this reset signal.}
waive -rules RESET_DRIVER -location {rng.sv} \
@@ -61,7 +61,7 @@
-comment {This is reset generation logic, hence it needs to drive this reset signal.}
waive -rules RESET_MUX -location {aon_clk.sv io_clk.sv sys_clk.sv usb_clk.sv} \
- -msg {Asynchronous reset 'rst_val_n' is driven by a multiplexer here, used as a reset 'rst_ni' at prim_generic_flop.sv} \
+ -msg {Asynchronous reset 'rst_val_n' is driven by a multiplexer here, used as a reset} \
-comment {This is reset generation logic, hence reset muxes are allowed.}
waive -rules RESET_MUX -location {ast.sv} \
@@ -77,11 +77,11 @@
-comment {This is reset / clock generation logic, hence special reset usage is allowed.}
waive -rules RESET_USE -location {ast.sv} \
- -msg {'vcmain_pok_por' is connected to 'rglts_pdm_3p3v' port 'vcmain_pok_o_h_i', and used as an asynchronous reset or set 'rst_ni' at prim_generic_flop.} \
+ -msg {'vcmain_pok_por' is connected to 'rglts_pdm_3p3v' port 'vcmain_pok_o_h_i', and used as an asynchronous reset or set} \
-comment {This is reset / clock generation logic, hence special reset usage is allowed.}
waive -rules RESET_USE -location {ast.sv} \
- -msg {'vcmain_pok_por' is connected to 'rglts_pdm_3p3v' port 'vcmain_pok_o_h_i', and used as an asynchronous reset or set 'rst_ni' at prim_generic_flop.} \
+ -msg {'vcmain_pok_por' is connected to 'rglts_pdm_3p3v' port 'vcmain_pok_o_h_i', and used as an asynchronous reset or set} \
-comment {This is reset / clock generation logic, hence special reset usage is allowed.}
waive -rules RESET_USE -location {ast.sv} \
@@ -100,6 +100,10 @@
-msg {'rst_ast_tlul_ni' is connected to 'ast_dft' port 'rst_ni', and used as an asynchronous reset or set 'rst_n' at rng} \
-comment {This is a valid reset connection.}
+waive -rules RESET_USE -location {ast.sv} \
+ -regexp {('rst_sys_clk_n'|'rst_usb_clk_n') is connected to ('sys_clk'|'usb_clk') port ('rst_sys_clk_ni'|'rst_usb_clk_ni'), and used as an asynchronous reset or set} \
+ -comment {This is a valid reset connection.}
+
waive -rules {TRI_DRIVER} -location {ast.sv} \
-regexp {'ast2pad_(t0|t1)_ao' is driven by a tristate driver} \
-comment {This part models a tristate driver.}
diff --git a/hw/top_earlgrey/lint/chip_earlgrey_asic.waiver b/hw/top_earlgrey/lint/chip_earlgrey_asic.waiver
index e4c0b0a..e7370e8 100644
--- a/hw/top_earlgrey/lint/chip_earlgrey_asic.waiver
+++ b/hw/top_earlgrey/lint/chip_earlgrey_asic.waiver
@@ -7,7 +7,54 @@
waive -rules {MULTI_DRIVEN} -location {chip_earlgrey_asic.sv} -regexp {'(IOA2|IOA3)' has 2 drivers, also driven at} \
-comment "These two pads are shorted to AST, hence this multiple driver warning is OK."
-# COMBO_LOOP waiver on the Passthrough port
waive -rules {COMBO_LOOP} -location {chip_earlgrey_asic.sv} \
-regexp {port 'u_passthrough.host_s_i.*' driven in module 'spi_device'} \
-comment "In the passthrough mode, SPI 4 lines are connected from pads to pads."
+
+waive -rules {CLOCK_DRIVER} -location {chip_earlgrey_asic.sv} \
+ -msg {'mio_in_raw[28]' is driven by instance 'u_padring' of module 'padring', and used as a clock 'clk_ast_ext_i' at ast_dft} \
+ -comment "This is due to the external clock input pin."
+
+waive -rules {CLOCK_DRIVER} -location {chip_earlgrey_asic.sv} \
+ -msg {'mio_in_raw_o[28]' driven in module 'padring' by port 'gen_mio_pads[28].u_mio_pad.in_raw_o' at padring} \
+ -comment "This is due to the external clock input pin."
+
+waive -rules {CLOCK_DRIVER} -location {chip_earlgrey_asic.sv} \
+ -msg {'in_raw_o' driven in module 'prim_pad_wrapper' by port 'gen_.*.u_impl_.*.in_raw_o' at prim_pad_wrapper} \
+ -comment "This is due to the external clock input pin."
+
+waive -rules {CLOCK_DRIVER} -location {chip_earlgrey_asic.sv} \
+ -msg {'in_raw_o' driven in module 'prim_.*_pad_wrapper' by port} \
+ -comment "This is due to the external clock input pin."
+
+waive -rules {CLOCK_DRIVER} -location {chip_earlgrey_asic.sv} \
+ -msg {'ast_base_clks.clk_io' is driven by instance 'u_ast' of module 'ast', and used as a clock} \
+ -comment "This is a clock source."
+
+waive -rules {CLOCK_DRIVER} -location {chip_earlgrey_asic.sv} \
+ -msg {'clk_src_io_o' driven in module 'ast' by port 'u_ast_dft.clk_src_io_o' at ast} \
+ -comment "This is a clock source."
+
+waive -rules {CLOCK_DRIVER} -location {chip_earlgrey_asic.sv} \
+ -msg {'clk_src_io_o' driven in module 'ast_dft' at ast_dft} \
+ -comment "This is a clock source."
+
+waive -rules {CLOCK_USE} -location {chip_earlgrey_asic.sv} \
+ -msg {'mio_in_raw[28]' is used for some other purpose, and as clock 'clk_ast_ext_i' at ast_dft} \
+ -comment "This is due to the external clock input pin."
+
+waive -rules {CLOCK_USE} -location {chip_earlgrey_asic.sv} \
+ -msg {'clks_ast.clk_ast_usbdev_usb_peri' is connected to 'ast' port 'clk_ast_usb_i', and used as a clock} \
+ -comment "This is a valid clock signal."
+
+waive -rules {CLOCK_USE} -location {chip_earlgrey_asic.sv} \
+ -msg {'clks_ast.clk_ast_usbdev_usb_peri' is connected to 'ast' port 'clk_ast_usb_i', and used as a clock} \
+ -comment "This is a valid clock signal."
+
+waive -rules {RESET_DRIVER} -location {chip_earlgrey_asic.sv} \
+ -msg {'scan_rst_n' is driven by instance 'u_ast' of module 'ast', and used as an asynchronous reset} \
+ -comment "This is a valid reset signal."
+
+waive -rules {RESET_DRIVER} -location {chip_earlgrey_asic.sv} \
+ -msg {'scan_reset_no' driven in module 'ast' at ast} \
+ -comment "This is a valid reset signal."
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
index 4d2895f..0ff33a3 100644
--- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
+++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
@@ -925,13 +925,16 @@
logic unused_slow_clk_en;
logic unused_usb_clk_aon;
logic unused_usb_clk_io_div4;
+ logic unused_adc_clk_aon;
assign unused_slow_clk_en = base_ast_pwr.slow_clk_en;
assign unused_usb_clk_aon = clks_ast.clk_ast_usbdev_aon_peri;
assign unused_usb_clk_io_div4 = clks_ast.clk_ast_usbdev_io_div4_peri;
+ assign unused_adc_clk_aon = clks_ast.clk_ast_adc_ctrl_aon_aon_peri;
logic unused_usb_usb_rst;
logic [PowerDomains-1:0] unused_usb_sys_io_div4_rst;
logic [PowerDomains-1:0] unused_usb_sys_aon_rst;
+ logic [PowerDomains-1:0] unused_adc_ctrl_sys_aon_rst;
logic unused_ast_sys_io_div4_rst;
logic unused_sensor_ctrl_sys_io_div4_rst;
logic unused_adc_ctrl_sys_io_div4_rst;
@@ -940,6 +943,7 @@
assign unused_usb_usb_rst = rsts_ast.rst_ast_usbdev_usb_n[DomainAonSel];
assign unused_usb_sys_io_div4_rst = rsts_ast.rst_ast_usbdev_sys_io_div4_n;
assign unused_usb_sys_aon_rst = rsts_ast.rst_ast_usbdev_sys_aon_n;
+ assign unused_adc_ctrl_sys_aon_rst = rsts_ast.rst_ast_adc_ctrl_aon_sys_aon_n;
assign unused_ast_sys_io_div4_rst =
rsts_ast.rst_ast_ast_sys_io_div4_n[Domain0Sel];
assign unused_sensor_ctrl_sys_io_div4_rst =
@@ -949,6 +953,9 @@
assign unused_entropy_sys_rst = rsts_ast.rst_ast_entropy_src_sys_n[DomainAonSel];
assign unused_edn_sys_rst = rsts_ast.rst_ast_edn0_sys_n[DomainAonSel];
+ logic unused_pwr_clamp;
+ assign unused_pwr_clamp = base_ast_pwr.pwr_clamp;
+
ast_pkg::ast_dif_t flash_alert;
ast_pkg::ast_dif_t otp_alert;
logic ast_init_done;
diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl
index 8e05307..2bd7596 100644
--- a/util/topgen/templates/chiplevel.sv.tpl
+++ b/util/topgen/templates/chiplevel.sv.tpl
@@ -773,13 +773,16 @@
logic unused_slow_clk_en;
logic unused_usb_clk_aon;
logic unused_usb_clk_io_div4;
+ logic unused_adc_clk_aon;
assign unused_slow_clk_en = base_ast_pwr.slow_clk_en;
assign unused_usb_clk_aon = clks_ast.clk_ast_usbdev_aon_peri;
assign unused_usb_clk_io_div4 = clks_ast.clk_ast_usbdev_io_div4_peri;
+ assign unused_adc_clk_aon = clks_ast.clk_ast_adc_ctrl_aon_aon_peri;
logic unused_usb_usb_rst;
logic [PowerDomains-1:0] unused_usb_sys_io_div4_rst;
logic [PowerDomains-1:0] unused_usb_sys_aon_rst;
+ logic [PowerDomains-1:0] unused_adc_ctrl_sys_aon_rst;
logic unused_ast_sys_io_div4_rst;
logic unused_sensor_ctrl_sys_io_div4_rst;
logic unused_adc_ctrl_sys_io_div4_rst;
@@ -788,6 +791,7 @@
assign unused_usb_usb_rst = rsts_ast.rst_ast_usbdev_usb_n[DomainAonSel];
assign unused_usb_sys_io_div4_rst = rsts_ast.rst_ast_usbdev_sys_io_div4_n;
assign unused_usb_sys_aon_rst = rsts_ast.rst_ast_usbdev_sys_aon_n;
+ assign unused_adc_ctrl_sys_aon_rst = rsts_ast.rst_ast_adc_ctrl_aon_sys_aon_n;
assign unused_ast_sys_io_div4_rst =
rsts_ast.rst_ast_ast_sys_io_div4_n[Domain0Sel];
assign unused_sensor_ctrl_sys_io_div4_rst =
@@ -797,6 +801,9 @@
assign unused_entropy_sys_rst = rsts_ast.rst_ast_entropy_src_sys_n[DomainAonSel];
assign unused_edn_sys_rst = rsts_ast.rst_ast_edn0_sys_n[DomainAonSel];
+ logic unused_pwr_clamp;
+ assign unused_pwr_clamp = base_ast_pwr.pwr_clamp;
+
ast_pkg::ast_dif_t flash_alert;
ast_pkg::ast_dif_t otp_alert;
logic ast_init_done;
