hw/ip/pwm/dv/pwm_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: pwm

  // Top level dut name (sv module).
  dut: pwm

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: xcelium

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:pwm_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/ip/pwm/data/pwm_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/ip/pwm/data/pwm.hjson"

  // Import additional common sim cfg files.
  // TODO: remove imported cfgs that do not apply.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson",
                // TODO : enable for V2
                //"{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson"]

  // Add additional tops for simulation.
  sim_tops: ["pwm_bind"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  // Default UVM test and seq class name.
  uvm_test: pwm_base_test
  uvm_test_seq: pwm_base_vseq

  // List of test specifications.
  tests: [
    {
      name: pwm_smoke
      uvm_test_seq: pwm_smoke_vseq
    }
  ]

  // List of regressions.
//  regressions: [
//    {
//      name: smoke
//      tests: ["pwm_smoke"]
//    }
//  ]
}