[flash_ctrl] Minor clean-up of the req/ack interface

Now all requests are single cycle pulse.
This is in preparation for a consistent interface as flash wrapper construction begins.

Signed-off-by: Timothy Chen <timothytim@google.com>

hw/ip/flash_ctrl/rtl/flash_phy_core.sv

diff --git a/hw/ip/flash_ctrl/rtl/flash_phy_core.sv b/hw/ip/flash_ctrl/rtl/flash_phy_core.sv
index 44d2e54..0b53421 100644
--- a/hw/ip/flash_ctrl/rtl/flash_phy_core.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_phy_core.sv
@@ -198,8 +198,6 @@
 
       // other controller operations directly interface with flash
       StCtrl: begin
-        reqs[PhyPgErase] = pg_erase_i;
-        reqs[PhyBkErase] = bk_erase_i;
         if (ack) begin
           ctrl_rsp_vld = 1'b1;
           state_d = StIdle;

hw/ip/flash_ctrl/rtl/flash_phy_prog.sv

diff --git a/hw/ip/flash_ctrl/rtl/flash_phy_prog.sv b/hw/ip/flash_ctrl/rtl/flash_phy_prog.sv
index cf273e9..5048456 100644
--- a/hw/ip/flash_ctrl/rtl/flash_phy_prog.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_phy_prog.sv
@@ -44,11 +44,12 @@
   output logic [FullDataWidth-1:0] data_o
 );
 
-  typedef enum logic [2:0] {
+  typedef enum logic [3:0] {
     StIdle,
     StPrePack,
     StPackData,
     StPostPack,
+    StReqFlash,
     StWaitFlash,
     StCalcMask,
     StScrambleData,
@@ -138,7 +139,7 @@
 
         if (req_i && idx == (WidthMultiple-1)) begin
           // last beat of a flash word
-          state_d = scramble_i ? StCalcMask : StWaitFlash;
+          state_d = scramble_i ? StCalcMask : StReqFlash;
         end else if (req_i && last_i) begin
           // last beat is not aligned with the last entry of flash word
           state_d = StPostPack;
@@ -154,7 +155,7 @@
 
         // finish packing remaining entries
         if (idx == (WidthMultiple-1)) begin
-          state_d = scramble_i ? StCalcMask : StWaitFlash;
+          state_d = scramble_i ? StCalcMask : StReqFlash;
         end
       end
 
@@ -175,11 +176,15 @@
       end
 
       StCalcEcc: begin
+        state_d = StReqFlash;
+      end
+
+      StReqFlash: begin
+        req_o = 1'b1;
         state_d = StWaitFlash;
       end
 
       StWaitFlash: begin
-        req_o = 1'b1;
 
         if (ack_i) begin
           ack_o = 1'b1;