[top] Select Ibex register file implementation based on target

This commit propagates the register file selection parameter of
rv_core_ibex up to the top to allow selecting a variant based on the
target. The register file itself has a big impact on the overall area
of Ibex (~30%) and we have different implementations FPGA (LUTRAM),
minimum size on ASIC (Latches), and a generic FF-based implementation.

This commit modifies all FPGA tops to use the FPGA register file. We
keep using the FF-based generic implementation for ASIC targets and RTL
simulation (see lowRISC/OpenTitan#2650).

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>

hw/top_earlgrey/rtl/autogen/top_earlgrey.sv

diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index b423882..4b0ca3c 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -9,6 +9,7 @@
   parameter int unsigned SecAesStartTriggerDelay = 0,
 
   // Manually defined parameters
+  parameter ibex_pkg::regfile_e IbexRegFile = ibex_pkg::RegFileFF,
   parameter bit IbexPipeLine = 0,
   parameter     BootRomInitFile = ""
 ) (
@@ -304,7 +305,7 @@
     .RV32E                    (0),
     .RV32M                    (ibex_pkg::RV32MSingleCycle),
     .RV32B                    (ibex_pkg::RV32BNone),
-    .RegFile                  (ibex_pkg::RegFileFF),
+    .RegFile                  (IbexRegFile),
     .BranchTargetALU          (1),
     .WritebackStage           (1),
     .ICache                   (0),