[top] Select Ibex register file implementation based on target

This commit propagates the register file selection parameter of
rv_core_ibex up to the top to allow selecting a variant based on the
target. The register file itself has a big impact on the overall area
of Ibex (~30%) and we have different implementations FPGA (LUTRAM),
minimum size on ASIC (Latches), and a generic FF-based implementation.

This commit modifies all FPGA tops to use the FPGA register file. We
keep using the FF-based generic implementation for ASIC targets and RTL
simulation (see lowRISC/OpenTitan#2650).

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>

hw/top_earlgrey/data/top_earlgrey.sv.tpl

diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index cabe033..500499f 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -38,6 +38,7 @@
 % endfor
 
   // Manually defined parameters
+  parameter ibex_pkg::regfile_e IbexRegFile = ibex_pkg::RegFileFF,
   parameter bit IbexPipeLine = 0,
   parameter     BootRomInitFile = ""
 ) (
@@ -202,7 +203,7 @@
     .RV32E                    (0),
     .RV32M                    (ibex_pkg::RV32MSingleCycle),
     .RV32B                    (ibex_pkg::RV32BNone),
-    .RegFile                  (ibex_pkg::RegFileFF),
+    .RegFile                  (IbexRegFile),
     .BranchTargetALU          (1),
     .WritebackStage           (1),
     .ICache                   (0),

hw/top_earlgrey/rtl/autogen/top_earlgrey.sv

diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index b423882..4b0ca3c 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -9,6 +9,7 @@
   parameter int unsigned SecAesStartTriggerDelay = 0,
 
   // Manually defined parameters
+  parameter ibex_pkg::regfile_e IbexRegFile = ibex_pkg::RegFileFF,
   parameter bit IbexPipeLine = 0,
   parameter     BootRomInitFile = ""
 ) (
@@ -304,7 +305,7 @@
     .RV32E                    (0),
     .RV32M                    (ibex_pkg::RV32MSingleCycle),
     .RV32B                    (ibex_pkg::RV32BNone),
-    .RegFile                  (ibex_pkg::RegFileFF),
+    .RegFile                  (IbexRegFile),
     .BranchTargetALU          (1),
     .WritebackStage           (1),
     .ICache                   (0),

hw/top_earlgrey/rtl/top_earlgrey_artys7.sv

diff --git a/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv b/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv
index f93e800..aafe515 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv
@@ -168,6 +168,7 @@
     .AesMasking(1'b0),
     .AesSBoxImpl(aes_pkg::SBoxImplLut),
     .SecAesStartTriggerDelay(0),
+    .IbexRegFile(ibex_pkg::RegFileFPGA),
     .IbexPipeLine(1),
     .BootRomInitFile(BootRomInitFile)
   ) top_earlgrey (

hw/top_earlgrey/rtl/top_earlgrey_cw305.sv

diff --git a/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv b/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv
index d5a1ed6..01e5a15 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv
@@ -230,6 +230,7 @@
     .AesMasking(1'b0),
     .AesSBoxImpl(aes_pkg::SBoxImplLut),
     .SecAesStartTriggerDelay(40),
+    .IbexRegFile(ibex_pkg::RegFileFPGA),
     .IbexPipeLine(1),
     .BootRomInitFile(BootRomInitFile)
   ) top_earlgrey (

hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv

diff --git a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
index 6000740..ea83ede 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
@@ -226,6 +226,7 @@
     .AesMasking(1'b0),
     .AesSBoxImpl(aes_pkg::SBoxImplLut),
     .SecAesStartTriggerDelay(0),
+    .IbexRegFile(ibex_pkg::RegFileFPGA),
     .IbexPipeLine(1),
     .BootRomInitFile(BootRomInitFile)
   ) top_earlgrey (