[reggen] Remove hwqe and hwre from Field objects in Python code This makes no change to the generated hardware, but slightly simplifies the plumbing in the Python itself. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/util/reggen/field.py b/util/reggen/field.py index a2beb73..084defc 100644 --- a/util/reggen/field.py +++ b/util/reggen/field.py
@@ -50,8 +50,6 @@ tags: List[str], swaccess: SWAccess, hwaccess: HWAccess, - hwqe: bool, - hwre: bool, bits: Bits, resval: Optional[int], enum: Optional[List[EnumEntry]]): @@ -60,8 +58,6 @@ self.tags = tags self.swaccess = swaccess self.hwaccess = hwaccess - self.hwqe = hwqe - self.hwre = hwre self.bits = bits self.resval = resval self.enum = enum @@ -74,8 +70,6 @@ default_hwaccess: HWAccess, reg_resval: Optional[int], reg_width: int, - reg_hwqe: bool, - reg_hwre: bool, params: ReggenParams, raw: object) -> 'Field': where = 'field {} of {} register'.format(field_idx, reg_name) @@ -177,15 +171,13 @@ enum.append(entry) enum_val_to_name[entry.value] = entry.name - return Field(name, desc, tags, - swaccess, hwaccess, - reg_hwqe, reg_hwre, bits, resval, enum) + return Field(name, desc, tags, swaccess, hwaccess, bits, resval, enum) def has_incomplete_enum(self) -> bool: return (self.enum is not None and len(self.enum) != 1 + self.bits.max_value()) - def get_n_bits(self, hwext: bool, bittype: List[str]) -> int: + def get_n_bits(self, hwext: bool, hwqe: bool, hwre: bool, bittype: List[str]) -> int: '''Get the size of this field in bits bittype should be a list of the types of signals to count. The elements @@ -197,12 +189,6 @@ - 'd': A signal for the next value of the field. Only needed if HW can write its contents. - - 'qe': A write enable signal for bus accesses. Only needed if HW can - read the field's contents and the field has the hwqe flag. - - - 're': A read enable signal for bus accesses. Only needed if HW can - read the field's contents and the field has the hwre flag. - - 'de': A write enable signal for hardware accesses. Only needed if HW can write the field's contents and the register data is stored in the register block (true if the hwext flag is false). @@ -214,9 +200,9 @@ if "d" in bittype and self.hwaccess.allows_write(): n_bits += self.bits.width() if "qe" in bittype and self.hwaccess.allows_read(): - n_bits += int(self.hwqe) + n_bits += int(hwqe) if "re" in bittype and self.hwaccess.allows_read(): - n_bits += int(self.hwre) + n_bits += int(hwre) if "de" in bittype and self.hwaccess.allows_write(): n_bits += int(not hwext) return n_bits @@ -258,7 +244,7 @@ ret.append(Field(name, desc, self.tags, self.swaccess, self.hwaccess, - self.hwqe, self.hwre, bits, self.resval, enum)) + bits, self.resval, enum)) return ret @@ -272,7 +258,7 @@ return Field(self.name + suffix, desc, self.tags, self.swaccess, self.hwaccess, - self.hwqe, self.hwre, self.bits, self.resval, enum) + self.bits, self.resval, enum) def _asdict(self) -> Dict[str, object]: rd = {
diff --git a/util/reggen/reg_block.py b/util/reggen/reg_block.py index 30a4f74..0264d01 100644 --- a/util/reggen/reg_block.py +++ b/util/reggen/reg_block.py
@@ -350,8 +350,6 @@ tags=[], swaccess=swaccess_obj, hwaccess=hwaccess_obj, - hwqe=is_testreg, - hwre=False, bits=signal.bits, resval=0, enum=None))
diff --git a/util/reggen/reg_pkg.sv.tpl b/util/reggen/reg_pkg.sv.tpl index 98b9963..e712c87 100644 --- a/util/reggen/reg_pkg.sv.tpl +++ b/util/reggen/reg_pkg.sv.tpl
@@ -51,14 +51,14 @@ ## field. <% field = r.get_field_list()[0] - field_q_width = field.get_n_bits(r0.hwext, ['q']) + field_q_width = field.get_n_bits(r0.hwext, r0.hwqe, r0.hwre, ['q']) field_q_bits = lib.bitarray(field_q_width, 2) %>\ logic ${field_q_bits} q; - % if field.hwqe: + % if r0.hwqe: logic qe; % endif - % if field.hwre or (r0.shadowed and r0.hwext): + % if r0.hwre or (r0.shadowed and r0.hwext): logic re; % endif % if r0.shadowed and not r0.hwext: @@ -70,19 +70,20 @@ ## field. Generate a reg2hw typedef that packs together all the fields of ## the register. % for f in r0.fields: - % if f.get_n_bits(r0.hwext, ["q"]) >= 1: <% - field_q_width = f.get_n_bits(r0.hwext, ['q']) - field_q_bits = lib.bitarray(field_q_width, 2) - - struct_name = f.name.lower() + field_q_width = f.get_n_bits(r0.hwext, r0.hwqe, r0.hwre, ["q"]) +%>\ + % if field_q_width: +<% + field_q_bits = lib.bitarray(field_q_width, 2) + struct_name = f.name.lower() %>\ struct packed { logic ${field_q_bits} q; - % if f.hwqe: + % if r0.hwqe: logic qe; % endif - % if f.hwre or (r0.shadowed and r0.hwext): + % if r0.hwre or (r0.shadowed and r0.hwext): logic re; % endif % if r0.shadowed and not r0.hwext: @@ -114,7 +115,7 @@ ## field. <% field = r.get_field_list()[0] - field_d_width = field.get_n_bits(r0.hwext, ['d']) + field_d_width = field.get_n_bits(r0.hwext, r0.hwqe, r0.hwre, ['d']) field_d_bits = lib.bitarray(field_d_width, 2) %>\ logic ${field_d_bits} d; @@ -126,12 +127,13 @@ ## field. Generate a hw2reg typedef that packs together all the fields of ## the register. % for f in r0.fields: - % if f.get_n_bits(r0.hwext, ["d"]) >= 1: <% - field_d_width = f.get_n_bits(r0.hwext, ['d']) - field_d_bits = lib.bitarray(field_d_width, 2) - - struct_name = f.name.lower() + field_d_width = f.get_n_bits(r0.hwext, r0.hwqe, r0.hwre, ["d"]) +%>\ + % if field_d_width: +<% + field_d_bits = lib.bitarray(field_d_width, 2) + struct_name = f.name.lower() %>\ struct packed { logic ${field_d_bits} d;
diff --git a/util/reggen/reg_top.sv.tpl b/util/reggen/reg_top.sv.tpl index add7122..5ad2e87 100644 --- a/util/reggen/reg_top.sv.tpl +++ b/util/reggen/reg_top.sv.tpl
@@ -274,7 +274,7 @@ fsig_name = r.reg.name.lower() + "[%d]" % k k = k + 1 %> -${finst_gen(f, finst_name, fsig_name, sr.hwext, sr.regwen, sr.shadowed)} +${finst_gen(f, finst_name, fsig_name, sr.hwext, sr.hwre, sr.hwqe, sr.regwen, sr.shadowed)} % else: % for f in sr.fields: <% @@ -286,7 +286,7 @@ fsig_name = r.reg.name.lower() + "[%d]" % k + "." + get_basename(f.name.lower()) %> // F[${f.name.lower()}]: ${f.bits.msb}:${f.bits.lsb} -${finst_gen(f, finst_name, fsig_name, sr.hwext, sr.regwen, sr.shadowed)} +${finst_gen(f, finst_name, fsig_name, sr.hwext, sr.hwre, sr.hwqe, sr.regwen, sr.shadowed)} % endfor <% if not r.is_homogeneous(): @@ -303,7 +303,7 @@ finst_name = r.name.lower() fsig_name = r.name.lower() %> -${finst_gen(f, finst_name, fsig_name, r.hwext, r.regwen, r.shadowed)} +${finst_gen(f, finst_name, fsig_name, r.hwext, r.hwre, r.hwqe, r.regwen, r.shadowed)} ######################## register with multiple fields ########################### % else: // R[${r.name.lower()}]: V(${str(r.hwext)}) @@ -313,7 +313,7 @@ fsig_name = r.name.lower() + "." + f.name.lower() %> // F[${f.name.lower()}]: ${f.bits.msb}:${f.bits.lsb} -${finst_gen(f, finst_name, fsig_name, r.hwext, r.regwen, r.shadowed)} +${finst_gen(f, finst_name, fsig_name, r.hwext, r.hwre, r.hwqe, r.regwen, r.shadowed)} % endfor % endif @@ -442,7 +442,7 @@ logic ${sig_name}_re; % endif </%def>\ -<%def name="finst_gen(field, finst_name, fsig_name, hwext, regwen, shadowed)">\ +<%def name="finst_gen(field, finst_name, fsig_name, hwext, hwre, hwqe, regwen, shadowed)">\ <% re_expr = f'{finst_name}_re' if field.swaccess.allows_read() else "1'b0" @@ -463,10 +463,10 @@ de_expr = "1'b0" d_expr = "'0" - qre_expr = f'reg2hw.{fsig_name}.re' if field.hwre or shadowed else "" + qre_expr = f'reg2hw.{fsig_name}.re' if hwre or shadowed else "" if field.hwaccess.allows_read(): - qe_expr = f'reg2hw.{fsig_name}.qe' if field.hwqe else '' + qe_expr = f'reg2hw.{fsig_name}.qe' if hwqe else '' q_expr = f'reg2hw.{fsig_name}.q' else: qe_expr = ''
diff --git a/util/reggen/register.py b/util/reggen/register.py index e067704..5f092d5 100644 --- a/util/reggen/register.py +++ b/util/reggen/register.py
@@ -239,8 +239,6 @@ hwaccess, resval, reg_width, - hwqe, - hwre, params, rf) for idx, rf in enumerate(raw_fields)] @@ -279,7 +277,7 @@ return self.swaccess.dv_rights() def get_n_bits(self, bittype: List[str]) -> int: - return sum(field.get_n_bits(self.hwext, bittype) + return sum(field.get_n_bits(self.hwext, self.hwqe, self.hwre, bittype) for field in self.fields) def get_field_list(self) -> List[Field]: