| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| // Register Package auto-generated by `reggen` containing data structure |
| |
| package edn_reg_pkg; |
| |
| // Param list |
| parameter int NumAlerts = 2; |
| |
| // Address widths within the block |
| parameter int BlockAw = 7; |
| |
| //////////////////////////// |
| // Typedefs for registers // |
| //////////////////////////// |
| |
| typedef struct packed { |
| struct packed { |
| logic q; |
| } edn_cmd_req_done; |
| struct packed { |
| logic q; |
| } edn_fatal_err; |
| } edn_reg2hw_intr_state_reg_t; |
| |
| typedef struct packed { |
| struct packed { |
| logic q; |
| } edn_cmd_req_done; |
| struct packed { |
| logic q; |
| } edn_fatal_err; |
| } edn_reg2hw_intr_enable_reg_t; |
| |
| typedef struct packed { |
| struct packed { |
| logic q; |
| logic qe; |
| } edn_cmd_req_done; |
| struct packed { |
| logic q; |
| logic qe; |
| } edn_fatal_err; |
| } edn_reg2hw_intr_test_reg_t; |
| |
| typedef struct packed { |
| struct packed { |
| logic q; |
| logic qe; |
| } recov_alert; |
| struct packed { |
| logic q; |
| logic qe; |
| } fatal_alert; |
| } edn_reg2hw_alert_test_reg_t; |
| |
| typedef struct packed { |
| struct packed { |
| logic [3:0] q; |
| } edn_enable; |
| struct packed { |
| logic [3:0] q; |
| } boot_req_mode; |
| struct packed { |
| logic [3:0] q; |
| } auto_req_mode; |
| struct packed { |
| logic [3:0] q; |
| } cmd_fifo_rst; |
| } edn_reg2hw_ctrl_reg_t; |
| |
| typedef struct packed { |
| logic [31:0] q; |
| } edn_reg2hw_boot_ins_cmd_reg_t; |
| |
| typedef struct packed { |
| logic [31:0] q; |
| } edn_reg2hw_boot_gen_cmd_reg_t; |
| |
| typedef struct packed { |
| logic [31:0] q; |
| logic qe; |
| } edn_reg2hw_sw_cmd_req_reg_t; |
| |
| typedef struct packed { |
| logic [31:0] q; |
| logic qe; |
| } edn_reg2hw_reseed_cmd_reg_t; |
| |
| typedef struct packed { |
| logic [31:0] q; |
| logic qe; |
| } edn_reg2hw_generate_cmd_reg_t; |
| |
| typedef struct packed { |
| logic [31:0] q; |
| logic qe; |
| } edn_reg2hw_max_num_reqs_between_reseeds_reg_t; |
| |
| typedef struct packed { |
| logic [4:0] q; |
| logic qe; |
| } edn_reg2hw_err_code_test_reg_t; |
| |
| typedef struct packed { |
| struct packed { |
| logic d; |
| logic de; |
| } edn_cmd_req_done; |
| struct packed { |
| logic d; |
| logic de; |
| } edn_fatal_err; |
| } edn_hw2reg_intr_state_reg_t; |
| |
| typedef struct packed { |
| struct packed { |
| logic d; |
| logic de; |
| } cmd_rdy; |
| struct packed { |
| logic d; |
| logic de; |
| } cmd_sts; |
| } edn_hw2reg_sw_cmd_sts_reg_t; |
| |
| typedef struct packed { |
| struct packed { |
| logic d; |
| logic de; |
| } edn_enable_field_alert; |
| struct packed { |
| logic d; |
| logic de; |
| } boot_req_mode_field_alert; |
| struct packed { |
| logic d; |
| logic de; |
| } auto_req_mode_field_alert; |
| struct packed { |
| logic d; |
| logic de; |
| } cmd_fifo_rst_field_alert; |
| struct packed { |
| logic d; |
| logic de; |
| } edn_bus_cmp_alert; |
| } edn_hw2reg_recov_alert_sts_reg_t; |
| |
| typedef struct packed { |
| struct packed { |
| logic d; |
| logic de; |
| } sfifo_rescmd_err; |
| struct packed { |
| logic d; |
| logic de; |
| } sfifo_gencmd_err; |
| struct packed { |
| logic d; |
| logic de; |
| } sfifo_output_err; |
| struct packed { |
| logic d; |
| logic de; |
| } edn_ack_sm_err; |
| struct packed { |
| logic d; |
| logic de; |
| } edn_main_sm_err; |
| struct packed { |
| logic d; |
| logic de; |
| } edn_cntr_err; |
| struct packed { |
| logic d; |
| logic de; |
| } fifo_write_err; |
| struct packed { |
| logic d; |
| logic de; |
| } fifo_read_err; |
| struct packed { |
| logic d; |
| logic de; |
| } fifo_state_err; |
| } edn_hw2reg_err_code_reg_t; |
| |
| typedef struct packed { |
| logic [8:0] d; |
| logic de; |
| } edn_hw2reg_main_sm_state_reg_t; |
| |
| // Register -> HW type |
| typedef struct packed { |
| edn_reg2hw_intr_state_reg_t intr_state; // [229:228] |
| edn_reg2hw_intr_enable_reg_t intr_enable; // [227:226] |
| edn_reg2hw_intr_test_reg_t intr_test; // [225:222] |
| edn_reg2hw_alert_test_reg_t alert_test; // [221:218] |
| edn_reg2hw_ctrl_reg_t ctrl; // [217:202] |
| edn_reg2hw_boot_ins_cmd_reg_t boot_ins_cmd; // [201:170] |
| edn_reg2hw_boot_gen_cmd_reg_t boot_gen_cmd; // [169:138] |
| edn_reg2hw_sw_cmd_req_reg_t sw_cmd_req; // [137:105] |
| edn_reg2hw_reseed_cmd_reg_t reseed_cmd; // [104:72] |
| edn_reg2hw_generate_cmd_reg_t generate_cmd; // [71:39] |
| edn_reg2hw_max_num_reqs_between_reseeds_reg_t max_num_reqs_between_reseeds; // [38:6] |
| edn_reg2hw_err_code_test_reg_t err_code_test; // [5:0] |
| } edn_reg2hw_t; |
| |
| // HW -> register type |
| typedef struct packed { |
| edn_hw2reg_intr_state_reg_t intr_state; // [45:42] |
| edn_hw2reg_sw_cmd_sts_reg_t sw_cmd_sts; // [41:38] |
| edn_hw2reg_recov_alert_sts_reg_t recov_alert_sts; // [37:28] |
| edn_hw2reg_err_code_reg_t err_code; // [27:10] |
| edn_hw2reg_main_sm_state_reg_t main_sm_state; // [9:0] |
| } edn_hw2reg_t; |
| |
| // Register offsets |
| parameter logic [BlockAw-1:0] EDN_INTR_STATE_OFFSET = 7'h 0; |
| parameter logic [BlockAw-1:0] EDN_INTR_ENABLE_OFFSET = 7'h 4; |
| parameter logic [BlockAw-1:0] EDN_INTR_TEST_OFFSET = 7'h 8; |
| parameter logic [BlockAw-1:0] EDN_ALERT_TEST_OFFSET = 7'h c; |
| parameter logic [BlockAw-1:0] EDN_REGWEN_OFFSET = 7'h 10; |
| parameter logic [BlockAw-1:0] EDN_CTRL_OFFSET = 7'h 14; |
| parameter logic [BlockAw-1:0] EDN_BOOT_INS_CMD_OFFSET = 7'h 18; |
| parameter logic [BlockAw-1:0] EDN_BOOT_GEN_CMD_OFFSET = 7'h 1c; |
| parameter logic [BlockAw-1:0] EDN_SW_CMD_REQ_OFFSET = 7'h 20; |
| parameter logic [BlockAw-1:0] EDN_SW_CMD_STS_OFFSET = 7'h 24; |
| parameter logic [BlockAw-1:0] EDN_RESEED_CMD_OFFSET = 7'h 28; |
| parameter logic [BlockAw-1:0] EDN_GENERATE_CMD_OFFSET = 7'h 2c; |
| parameter logic [BlockAw-1:0] EDN_MAX_NUM_REQS_BETWEEN_RESEEDS_OFFSET = 7'h 30; |
| parameter logic [BlockAw-1:0] EDN_RECOV_ALERT_STS_OFFSET = 7'h 34; |
| parameter logic [BlockAw-1:0] EDN_ERR_CODE_OFFSET = 7'h 38; |
| parameter logic [BlockAw-1:0] EDN_ERR_CODE_TEST_OFFSET = 7'h 3c; |
| parameter logic [BlockAw-1:0] EDN_MAIN_SM_STATE_OFFSET = 7'h 40; |
| |
| // Reset values for hwext registers and their fields |
| parameter logic [1:0] EDN_INTR_TEST_RESVAL = 2'h 0; |
| parameter logic [0:0] EDN_INTR_TEST_EDN_CMD_REQ_DONE_RESVAL = 1'h 0; |
| parameter logic [0:0] EDN_INTR_TEST_EDN_FATAL_ERR_RESVAL = 1'h 0; |
| parameter logic [1:0] EDN_ALERT_TEST_RESVAL = 2'h 0; |
| parameter logic [0:0] EDN_ALERT_TEST_RECOV_ALERT_RESVAL = 1'h 0; |
| parameter logic [0:0] EDN_ALERT_TEST_FATAL_ALERT_RESVAL = 1'h 0; |
| parameter logic [31:0] EDN_SW_CMD_REQ_RESVAL = 32'h 0; |
| parameter logic [31:0] EDN_RESEED_CMD_RESVAL = 32'h 0; |
| parameter logic [31:0] EDN_GENERATE_CMD_RESVAL = 32'h 0; |
| |
| // Register index |
| typedef enum int { |
| EDN_INTR_STATE, |
| EDN_INTR_ENABLE, |
| EDN_INTR_TEST, |
| EDN_ALERT_TEST, |
| EDN_REGWEN, |
| EDN_CTRL, |
| EDN_BOOT_INS_CMD, |
| EDN_BOOT_GEN_CMD, |
| EDN_SW_CMD_REQ, |
| EDN_SW_CMD_STS, |
| EDN_RESEED_CMD, |
| EDN_GENERATE_CMD, |
| EDN_MAX_NUM_REQS_BETWEEN_RESEEDS, |
| EDN_RECOV_ALERT_STS, |
| EDN_ERR_CODE, |
| EDN_ERR_CODE_TEST, |
| EDN_MAIN_SM_STATE |
| } edn_id_e; |
| |
| // Register width information to check illegal writes |
| parameter logic [3:0] EDN_PERMIT [17] = '{ |
| 4'b 0001, // index[ 0] EDN_INTR_STATE |
| 4'b 0001, // index[ 1] EDN_INTR_ENABLE |
| 4'b 0001, // index[ 2] EDN_INTR_TEST |
| 4'b 0001, // index[ 3] EDN_ALERT_TEST |
| 4'b 0001, // index[ 4] EDN_REGWEN |
| 4'b 0011, // index[ 5] EDN_CTRL |
| 4'b 1111, // index[ 6] EDN_BOOT_INS_CMD |
| 4'b 1111, // index[ 7] EDN_BOOT_GEN_CMD |
| 4'b 1111, // index[ 8] EDN_SW_CMD_REQ |
| 4'b 0001, // index[ 9] EDN_SW_CMD_STS |
| 4'b 1111, // index[10] EDN_RESEED_CMD |
| 4'b 1111, // index[11] EDN_GENERATE_CMD |
| 4'b 1111, // index[12] EDN_MAX_NUM_REQS_BETWEEN_RESEEDS |
| 4'b 0011, // index[13] EDN_RECOV_ALERT_STS |
| 4'b 1111, // index[14] EDN_ERR_CODE |
| 4'b 0001, // index[15] EDN_ERR_CODE_TEST |
| 4'b 0011 // index[16] EDN_MAIN_SM_STATE |
| }; |
| |
| endpackage |
