| commit | 470d6d63c8943ba664e9b8a2cd06df59468e6878 | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Tue Sep 28 13:21:09 2021 +0100 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Mon Oct 04 09:29:04 2021 +0100 |
| tree | 12feb4cee197df3363fdd42eb7fb7c3859651aa3 | |
| parent | e7a3c5a29af51dc10f09fe9826255ee5eb561942 [diff] |
[otbn,dv] Properly mirror STATUS reg from ISS to SystemVerilog Also, mirror all the other registers in a slightly less ad-hoc fashion in ISSWrapper. There's a bit of churn in the model connection, because we were using a signal called "status" to mean "the current state of the model". This signal is now called model_state. The status_o signal isn't actually connected in the UVM or Verilator testbenches yet (so doesn't really do anything): this will be connected in a subsequent commit. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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