tree 12feb4cee197df3363fdd42eb7fb7c3859651aa3
parent e7a3c5a29af51dc10f09fe9826255ee5eb561942
author Rupert Swarbrick <rswarbrick@lowrisc.org> 1632831669 +0100
committer Rupert Swarbrick <rswarbrick@gmail.com> 1633336144 +0100

[otbn,dv] Properly mirror STATUS reg from ISS to SystemVerilog

Also, mirror all the other registers in a slightly less ad-hoc fashion
in ISSWrapper.

There's a bit of churn in the model connection, because we were using
a signal called "status" to mean "the current state of the model".
This signal is now called model_state.

The status_o signal isn't actually connected in the UVM or Verilator
testbenches yet (so doesn't really do anything): this will be
connected in a subsequent commit.

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>