[top] Auto-generate top Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index a511fc6..b0c53c0 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -349,6 +349,42 @@ clk: usb sw: 1 } + { + name: i2c0 + gen: true + type: top + domains: + [ + "0" + ] + parent: sys_src + clk: io_div2 + sw: 1 + } + { + name: i2c1 + gen: true + type: top + domains: + [ + "0" + ] + parent: sys_src + clk: io_div2 + sw: 1 + } + { + name: i2c2 + gen: true + type: top + domains: + [ + "0" + ] + parent: sys_src + clk: io_div2 + sw: 1 + } ] } num_cores: "1" @@ -1251,6 +1287,860 @@ ] } { + name: i2c0 + type: i2c + clock_srcs: + { + clk_i: io_div4 + } + clock_group: peri + reset_connections: + { + rst_ni: rstmgr_resets.rst_i2c0_n[rstmgr_pkg::Domain0Sel] + } + base_addr: 0x40080000 + clock_connections: + { + clk_i: clkmgr_clocks.clk_io_div4_peri + } + domain: "0" + size: 0x1000 + bus_device: tlul + bus_host: none + available_input_list: [] + available_output_list: [] + available_inout_list: + [ + { + name: sda + width: 1 + type: inout + } + { + name: scl + width: 1 + type: inout + } + ] + param_list: [] + interrupt_list: + [ + { + name: fmt_watermark + width: 1 + bits: "0" + bitinfo: + [ + 1 + 1 + 0 + ] + type: interrupt + } + { + name: rx_watermark + width: 1 + bits: "1" + bitinfo: + [ + 2 + 1 + 1 + ] + type: interrupt + } + { + name: fmt_overflow + width: 1 + bits: "2" + bitinfo: + [ + 4 + 1 + 2 + ] + type: interrupt + } + { + name: rx_overflow + width: 1 + bits: "3" + bitinfo: + [ + 8 + 1 + 3 + ] + type: interrupt + } + { + name: nak + width: 1 + bits: "4" + bitinfo: + [ + 16 + 1 + 4 + ] + type: interrupt + } + { + name: scl_interference + width: 1 + bits: "5" + bitinfo: + [ + 32 + 1 + 5 + ] + type: interrupt + } + { + name: sda_interference + width: 1 + bits: "6" + bitinfo: + [ + 64 + 1 + 6 + ] + type: interrupt + } + { + name: stretch_timeout + width: 1 + bits: "7" + bitinfo: + [ + 128 + 1 + 7 + ] + type: interrupt + } + { + name: sda_unstable + width: 1 + bits: "8" + bitinfo: + [ + 256 + 1 + 8 + ] + type: interrupt + } + { + name: trans_complete + width: 1 + bits: "9" + bitinfo: + [ + 512 + 1 + 9 + ] + type: interrupt + } + { + name: tx_empty + width: 1 + bits: "10" + bitinfo: + [ + 1024 + 1 + 10 + ] + type: interrupt + } + { + name: tx_nonempty + width: 1 + bits: "11" + bitinfo: + [ + 2048 + 1 + 11 + ] + type: interrupt + } + { + name: tx_overflow + width: 1 + bits: "12" + bitinfo: + [ + 4096 + 1 + 12 + ] + type: interrupt + } + { + name: acq_overflow + width: 1 + bits: "13" + bitinfo: + [ + 8192 + 1 + 13 + ] + type: interrupt + } + { + name: ack_stop + width: 1 + bits: "14" + bitinfo: + [ + 16384 + 1 + 14 + ] + type: interrupt + } + { + name: host_timeout + width: 1 + bits: "15" + bitinfo: + [ + 32768 + 1 + 15 + ] + type: interrupt + } + ] + alert_list: [] + wakeup_list: [] + reset_request_list: [] + scan: "false" + scan_reset: "false" + inter_signal_list: + [ + { + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + name: tl + inst_name: i2c0 + width: 1 + default: "" + top_signame: i2c0_tl + index: -1 + } + ] + } + { + name: i2c1 + type: i2c + clock_srcs: + { + clk_i: io_div4 + } + clock_group: peri + reset_connections: + { + rst_ni: rstmgr_resets.rst_i2c1_n[rstmgr_pkg::Domain0Sel] + } + base_addr: 0x40090000 + clock_connections: + { + clk_i: clkmgr_clocks.clk_io_div4_peri + } + domain: "0" + size: 0x1000 + bus_device: tlul + bus_host: none + available_input_list: [] + available_output_list: [] + available_inout_list: + [ + { + name: sda + width: 1 + type: inout + } + { + name: scl + width: 1 + type: inout + } + ] + param_list: [] + interrupt_list: + [ + { + name: fmt_watermark + width: 1 + bits: "0" + bitinfo: + [ + 1 + 1 + 0 + ] + type: interrupt + } + { + name: rx_watermark + width: 1 + bits: "1" + bitinfo: + [ + 2 + 1 + 1 + ] + type: interrupt + } + { + name: fmt_overflow + width: 1 + bits: "2" + bitinfo: + [ + 4 + 1 + 2 + ] + type: interrupt + } + { + name: rx_overflow + width: 1 + bits: "3" + bitinfo: + [ + 8 + 1 + 3 + ] + type: interrupt + } + { + name: nak + width: 1 + bits: "4" + bitinfo: + [ + 16 + 1 + 4 + ] + type: interrupt + } + { + name: scl_interference + width: 1 + bits: "5" + bitinfo: + [ + 32 + 1 + 5 + ] + type: interrupt + } + { + name: sda_interference + width: 1 + bits: "6" + bitinfo: + [ + 64 + 1 + 6 + ] + type: interrupt + } + { + name: stretch_timeout + width: 1 + bits: "7" + bitinfo: + [ + 128 + 1 + 7 + ] + type: interrupt + } + { + name: sda_unstable + width: 1 + bits: "8" + bitinfo: + [ + 256 + 1 + 8 + ] + type: interrupt + } + { + name: trans_complete + width: 1 + bits: "9" + bitinfo: + [ + 512 + 1 + 9 + ] + type: interrupt + } + { + name: tx_empty + width: 1 + bits: "10" + bitinfo: + [ + 1024 + 1 + 10 + ] + type: interrupt + } + { + name: tx_nonempty + width: 1 + bits: "11" + bitinfo: + [ + 2048 + 1 + 11 + ] + type: interrupt + } + { + name: tx_overflow + width: 1 + bits: "12" + bitinfo: + [ + 4096 + 1 + 12 + ] + type: interrupt + } + { + name: acq_overflow + width: 1 + bits: "13" + bitinfo: + [ + 8192 + 1 + 13 + ] + type: interrupt + } + { + name: ack_stop + width: 1 + bits: "14" + bitinfo: + [ + 16384 + 1 + 14 + ] + type: interrupt + } + { + name: host_timeout + width: 1 + bits: "15" + bitinfo: + [ + 32768 + 1 + 15 + ] + type: interrupt + } + ] + alert_list: [] + wakeup_list: [] + reset_request_list: [] + scan: "false" + scan_reset: "false" + inter_signal_list: + [ + { + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + name: tl + inst_name: i2c1 + width: 1 + default: "" + top_signame: i2c1_tl + index: -1 + } + ] + } + { + name: i2c2 + type: i2c + clock_srcs: + { + clk_i: io_div4 + } + clock_group: peri + reset_connections: + { + rst_ni: rstmgr_resets.rst_i2c2_n[rstmgr_pkg::Domain0Sel] + } + base_addr: 0x400A0000 + clock_connections: + { + clk_i: clkmgr_clocks.clk_io_div4_peri + } + domain: "0" + size: 0x1000 + bus_device: tlul + bus_host: none + available_input_list: [] + available_output_list: [] + available_inout_list: + [ + { + name: sda + width: 1 + type: inout + } + { + name: scl + width: 1 + type: inout + } + ] + param_list: [] + interrupt_list: + [ + { + name: fmt_watermark + width: 1 + bits: "0" + bitinfo: + [ + 1 + 1 + 0 + ] + type: interrupt + } + { + name: rx_watermark + width: 1 + bits: "1" + bitinfo: + [ + 2 + 1 + 1 + ] + type: interrupt + } + { + name: fmt_overflow + width: 1 + bits: "2" + bitinfo: + [ + 4 + 1 + 2 + ] + type: interrupt + } + { + name: rx_overflow + width: 1 + bits: "3" + bitinfo: + [ + 8 + 1 + 3 + ] + type: interrupt + } + { + name: nak + width: 1 + bits: "4" + bitinfo: + [ + 16 + 1 + 4 + ] + type: interrupt + } + { + name: scl_interference + width: 1 + bits: "5" + bitinfo: + [ + 32 + 1 + 5 + ] + type: interrupt + } + { + name: sda_interference + width: 1 + bits: "6" + bitinfo: + [ + 64 + 1 + 6 + ] + type: interrupt + } + { + name: stretch_timeout + width: 1 + bits: "7" + bitinfo: + [ + 128 + 1 + 7 + ] + type: interrupt + } + { + name: sda_unstable + width: 1 + bits: "8" + bitinfo: + [ + 256 + 1 + 8 + ] + type: interrupt + } + { + name: trans_complete + width: 1 + bits: "9" + bitinfo: + [ + 512 + 1 + 9 + ] + type: interrupt + } + { + name: tx_empty + width: 1 + bits: "10" + bitinfo: + [ + 1024 + 1 + 10 + ] + type: interrupt + } + { + name: tx_nonempty + width: 1 + bits: "11" + bitinfo: + [ + 2048 + 1 + 11 + ] + type: interrupt + } + { + name: tx_overflow + width: 1 + bits: "12" + bitinfo: + [ + 4096 + 1 + 12 + ] + type: interrupt + } + { + name: acq_overflow + width: 1 + bits: "13" + bitinfo: + [ + 8192 + 1 + 13 + ] + type: interrupt + } + { + name: ack_stop + width: 1 + bits: "14" + bitinfo: + [ + 16384 + 1 + 14 + ] + type: interrupt + } + { + name: host_timeout + width: 1 + bits: "15" + bitinfo: + [ + 32768 + 1 + 15 + ] + type: interrupt + } + ] + alert_list: [] + wakeup_list: [] + reset_request_list: [] + scan: "false" + scan_reset: "false" + inter_signal_list: + [ + { + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + name: tl + inst_name: i2c2 + width: 1 + default: "" + top_signame: i2c2_tl + index: -1 + } + ] + } + { + name: pattgen + type: pattgen + clock_srcs: + { + clk_i: io_div4 + } + clock_group: peri + reset_connections: + { + rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel] + } + base_addr: 0x400E0000 + clock_connections: + { + clk_i: clkmgr_clocks.clk_io_div4_peri + } + domain: "0" + size: 0x1000 + bus_device: tlul + bus_host: none + available_input_list: [] + available_output_list: + [ + { + name: pda0_tx + width: 1 + type: output + } + { + name: pcl0_tx + width: 1 + type: output + } + { + name: pda1_tx + width: 1 + type: output + } + { + name: pcl1_tx + width: 1 + type: output + } + ] + available_inout_list: [] + param_list: [] + interrupt_list: + [ + { + name: done_ch0 + width: 1 + bits: "0" + bitinfo: + [ + 1 + 1 + 0 + ] + type: interrupt + } + { + name: done_ch1 + width: 1 + bits: "1" + bitinfo: + [ + 2 + 1 + 1 + ] + type: interrupt + } + ] + alert_list: [] + wakeup_list: [] + reset_request_list: [] + scan: "false" + scan_reset: "false" + inter_signal_list: + [ + { + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + name: tl + inst_name: pattgen + width: 1 + default: "" + top_signame: pattgen_tl + index: -1 + } + ] + } + { name: rv_timer type: rv_timer clock_srcs: @@ -6404,6 +7294,22 @@ [ peri.tl_uart3 ] + i2c0.tl: + [ + peri.tl_i2c0 + ] + i2c1.tl: + [ + peri.tl_i2c1 + ] + i2c2.tl: + [ + peri.tl_i2c2 + ] + pattgen.tl: + [ + peri.tl_pattgen + ] gpio.tl: [ peri.tl_gpio @@ -7246,6 +8152,10 @@ uart1 uart2 uart3 + i2c0 + i2c1 + i2c2 + pattgen gpio spi_device rv_timer @@ -7349,6 +8259,78 @@ pipeline_byp: "true" } { + name: i2c0 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: "false" + inst_type: i2c + addr_range: + [ + { + base_addr: 0x40080000 + size_byte: 0x1000 + } + ] + xbar: false + stub: false + pipeline_byp: "true" + } + { + name: i2c1 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: "false" + inst_type: i2c + addr_range: + [ + { + base_addr: 0x40090000 + size_byte: 0x1000 + } + ] + xbar: false + stub: false + pipeline_byp: "true" + } + { + name: i2c2 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: "false" + inst_type: i2c + addr_range: + [ + { + base_addr: 0x400A0000 + size_byte: 0x1000 + } + ] + xbar: false + stub: false + pipeline_byp: "true" + } + { + name: pattgen + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: "false" + inst_type: pattgen + addr_range: + [ + { + base_addr: 0x400E0000 + size_byte: 0x1000 + } + ] + xbar: false + stub: false + pipeline_byp: "true" + } + { name: gpio type: device clock: clk_peri_i @@ -7685,6 +8667,54 @@ { struct: tl type: req_rsp + name: tl_i2c0 + act: req + package: tlul_pkg + inst_name: peri + width: 1 + default: "" + top_signame: i2c0_tl + index: -1 + } + { + struct: tl + type: req_rsp + name: tl_i2c1 + act: req + package: tlul_pkg + inst_name: peri + width: 1 + default: "" + top_signame: i2c1_tl + index: -1 + } + { + struct: tl + type: req_rsp + name: tl_i2c2 + act: req + package: tlul_pkg + inst_name: peri + width: 1 + default: "" + top_signame: i2c2_tl + index: -1 + } + { + struct: tl + type: req_rsp + name: tl_pattgen + act: req + package: tlul_pkg + inst_name: peri + width: 1 + default: "" + top_signame: pattgen_tl + index: -1 + } + { + struct: tl + type: req_rsp name: tl_gpio act: req package: tlul_pkg @@ -7874,6 +8904,10 @@ uart3 gpio spi_device + i2c0 + i2c1 + i2c2 + pattgen flash_ctrl hmac alert_handler @@ -8399,6 +9433,656 @@ module_name: spi_device } { + name: i2c0_fmt_watermark + width: 1 + bits: "0" + bitinfo: + [ + 1 + 1 + 0 + ] + type: interrupt + module_name: i2c0 + } + { + name: i2c0_rx_watermark + width: 1 + bits: "1" + bitinfo: + [ + 2 + 1 + 1 + ] + type: interrupt + module_name: i2c0 + } + { + name: i2c0_fmt_overflow + width: 1 + bits: "2" + bitinfo: + [ + 4 + 1 + 2 + ] + type: interrupt + module_name: i2c0 + } + { + name: i2c0_rx_overflow + width: 1 + bits: "3" + bitinfo: + [ + 8 + 1 + 3 + ] + type: interrupt + module_name: i2c0 + } + { + name: i2c0_nak + width: 1 + bits: "4" + bitinfo: + [ + 16 + 1 + 4 + ] + type: interrupt + module_name: i2c0 + } + { + name: i2c0_scl_interference + width: 1 + bits: "5" + bitinfo: + [ + 32 + 1 + 5 + ] + type: interrupt + module_name: i2c0 + } + { + name: i2c0_sda_interference + width: 1 + bits: "6" + bitinfo: + [ + 64 + 1 + 6 + ] + type: interrupt + module_name: i2c0 + } + { + name: i2c0_stretch_timeout + width: 1 + bits: "7" + bitinfo: + [ + 128 + 1 + 7 + ] + type: interrupt + module_name: i2c0 + } + { + name: i2c0_sda_unstable + width: 1 + bits: "8" + bitinfo: + [ + 256 + 1 + 8 + ] + type: interrupt + module_name: i2c0 + } + { + name: i2c0_trans_complete + width: 1 + bits: "9" + bitinfo: + [ + 512 + 1 + 9 + ] + type: interrupt + module_name: i2c0 + } + { + name: i2c0_tx_empty + width: 1 + bits: "10" + bitinfo: + [ + 1024 + 1 + 10 + ] + type: interrupt + module_name: i2c0 + } + { + name: i2c0_tx_nonempty + width: 1 + bits: "11" + bitinfo: + [ + 2048 + 1 + 11 + ] + type: interrupt + module_name: i2c0 + } + { + name: i2c0_tx_overflow + width: 1 + bits: "12" + bitinfo: + [ + 4096 + 1 + 12 + ] + type: interrupt + module_name: i2c0 + } + { + name: i2c0_acq_overflow + width: 1 + bits: "13" + bitinfo: + [ + 8192 + 1 + 13 + ] + type: interrupt + module_name: i2c0 + } + { + name: i2c0_ack_stop + width: 1 + bits: "14" + bitinfo: + [ + 16384 + 1 + 14 + ] + type: interrupt + module_name: i2c0 + } + { + name: i2c0_host_timeout + width: 1 + bits: "15" + bitinfo: + [ + 32768 + 1 + 15 + ] + type: interrupt + module_name: i2c0 + } + { + name: i2c1_fmt_watermark + width: 1 + bits: "0" + bitinfo: + [ + 1 + 1 + 0 + ] + type: interrupt + module_name: i2c1 + } + { + name: i2c1_rx_watermark + width: 1 + bits: "1" + bitinfo: + [ + 2 + 1 + 1 + ] + type: interrupt + module_name: i2c1 + } + { + name: i2c1_fmt_overflow + width: 1 + bits: "2" + bitinfo: + [ + 4 + 1 + 2 + ] + type: interrupt + module_name: i2c1 + } + { + name: i2c1_rx_overflow + width: 1 + bits: "3" + bitinfo: + [ + 8 + 1 + 3 + ] + type: interrupt + module_name: i2c1 + } + { + name: i2c1_nak + width: 1 + bits: "4" + bitinfo: + [ + 16 + 1 + 4 + ] + type: interrupt + module_name: i2c1 + } + { + name: i2c1_scl_interference + width: 1 + bits: "5" + bitinfo: + [ + 32 + 1 + 5 + ] + type: interrupt + module_name: i2c1 + } + { + name: i2c1_sda_interference + width: 1 + bits: "6" + bitinfo: + [ + 64 + 1 + 6 + ] + type: interrupt + module_name: i2c1 + } + { + name: i2c1_stretch_timeout + width: 1 + bits: "7" + bitinfo: + [ + 128 + 1 + 7 + ] + type: interrupt + module_name: i2c1 + } + { + name: i2c1_sda_unstable + width: 1 + bits: "8" + bitinfo: + [ + 256 + 1 + 8 + ] + type: interrupt + module_name: i2c1 + } + { + name: i2c1_trans_complete + width: 1 + bits: "9" + bitinfo: + [ + 512 + 1 + 9 + ] + type: interrupt + module_name: i2c1 + } + { + name: i2c1_tx_empty + width: 1 + bits: "10" + bitinfo: + [ + 1024 + 1 + 10 + ] + type: interrupt + module_name: i2c1 + } + { + name: i2c1_tx_nonempty + width: 1 + bits: "11" + bitinfo: + [ + 2048 + 1 + 11 + ] + type: interrupt + module_name: i2c1 + } + { + name: i2c1_tx_overflow + width: 1 + bits: "12" + bitinfo: + [ + 4096 + 1 + 12 + ] + type: interrupt + module_name: i2c1 + } + { + name: i2c1_acq_overflow + width: 1 + bits: "13" + bitinfo: + [ + 8192 + 1 + 13 + ] + type: interrupt + module_name: i2c1 + } + { + name: i2c1_ack_stop + width: 1 + bits: "14" + bitinfo: + [ + 16384 + 1 + 14 + ] + type: interrupt + module_name: i2c1 + } + { + name: i2c1_host_timeout + width: 1 + bits: "15" + bitinfo: + [ + 32768 + 1 + 15 + ] + type: interrupt + module_name: i2c1 + } + { + name: i2c2_fmt_watermark + width: 1 + bits: "0" + bitinfo: + [ + 1 + 1 + 0 + ] + type: interrupt + module_name: i2c2 + } + { + name: i2c2_rx_watermark + width: 1 + bits: "1" + bitinfo: + [ + 2 + 1 + 1 + ] + type: interrupt + module_name: i2c2 + } + { + name: i2c2_fmt_overflow + width: 1 + bits: "2" + bitinfo: + [ + 4 + 1 + 2 + ] + type: interrupt + module_name: i2c2 + } + { + name: i2c2_rx_overflow + width: 1 + bits: "3" + bitinfo: + [ + 8 + 1 + 3 + ] + type: interrupt + module_name: i2c2 + } + { + name: i2c2_nak + width: 1 + bits: "4" + bitinfo: + [ + 16 + 1 + 4 + ] + type: interrupt + module_name: i2c2 + } + { + name: i2c2_scl_interference + width: 1 + bits: "5" + bitinfo: + [ + 32 + 1 + 5 + ] + type: interrupt + module_name: i2c2 + } + { + name: i2c2_sda_interference + width: 1 + bits: "6" + bitinfo: + [ + 64 + 1 + 6 + ] + type: interrupt + module_name: i2c2 + } + { + name: i2c2_stretch_timeout + width: 1 + bits: "7" + bitinfo: + [ + 128 + 1 + 7 + ] + type: interrupt + module_name: i2c2 + } + { + name: i2c2_sda_unstable + width: 1 + bits: "8" + bitinfo: + [ + 256 + 1 + 8 + ] + type: interrupt + module_name: i2c2 + } + { + name: i2c2_trans_complete + width: 1 + bits: "9" + bitinfo: + [ + 512 + 1 + 9 + ] + type: interrupt + module_name: i2c2 + } + { + name: i2c2_tx_empty + width: 1 + bits: "10" + bitinfo: + [ + 1024 + 1 + 10 + ] + type: interrupt + module_name: i2c2 + } + { + name: i2c2_tx_nonempty + width: 1 + bits: "11" + bitinfo: + [ + 2048 + 1 + 11 + ] + type: interrupt + module_name: i2c2 + } + { + name: i2c2_tx_overflow + width: 1 + bits: "12" + bitinfo: + [ + 4096 + 1 + 12 + ] + type: interrupt + module_name: i2c2 + } + { + name: i2c2_acq_overflow + width: 1 + bits: "13" + bitinfo: + [ + 8192 + 1 + 13 + ] + type: interrupt + module_name: i2c2 + } + { + name: i2c2_ack_stop + width: 1 + bits: "14" + bitinfo: + [ + 16384 + 1 + 14 + ] + type: interrupt + module_name: i2c2 + } + { + name: i2c2_host_timeout + width: 1 + bits: "15" + bitinfo: + [ + 32768 + 1 + 15 + ] + type: interrupt + module_name: i2c2 + } + { + name: pattgen_done_ch0 + width: 1 + bits: "0" + bitinfo: + [ + 1 + 1 + 0 + ] + type: interrupt + module_name: pattgen + } + { + name: pattgen_done_ch1 + width: 1 + bits: "1" + bitinfo: + [ + 2 + 1 + 1 + ] + type: interrupt + module_name: pattgen + } + { name: flash_ctrl_prog_empty width: 1 bits: "0" @@ -9433,6 +11117,10 @@ uart1 uart2 uart3 + i2c0 + i2c1 + i2c2 + pattgen ] nc_modules: [ @@ -9680,6 +11368,30 @@ type: output module_name: uart3 } + { + name: pattgen_pda0_tx + width: 1 + type: output + module_name: pattgen + } + { + name: pattgen_pcl0_tx + width: 1 + type: output + module_name: pattgen + } + { + name: pattgen_pda1_tx + width: 1 + type: output + module_name: pattgen + } + { + name: pattgen_pcl1_tx + width: 1 + type: output + module_name: pattgen + } ] inouts: [ @@ -9689,6 +11401,42 @@ type: inout module_name: gpio } + { + name: i2c0_sda + width: 1 + type: inout + module_name: i2c0 + } + { + name: i2c0_scl + width: 1 + type: inout + module_name: i2c0 + } + { + name: i2c1_sda + width: 1 + type: inout + module_name: i2c1 + } + { + name: i2c1_scl + width: 1 + type: inout + module_name: i2c1 + } + { + name: i2c2_sda + width: 1 + type: inout + module_name: i2c2 + } + { + name: i2c2_scl + width: 1 + type: inout + module_name: i2c2 + } ] } padctrl: @@ -9789,6 +11537,9 @@ sys_aon: rstmgr_resets.rst_sys_aon_n spi_device: rstmgr_resets.rst_spi_device_n usb: rstmgr_resets.rst_usb_n + i2c0: rstmgr_resets.rst_i2c0_n + i2c1: rstmgr_resets.rst_i2c1_n + i2c2: rstmgr_resets.rst_i2c2_n } inter_signal: { @@ -9872,6 +11623,54 @@ type: req_rsp act: rsp name: tl + inst_name: i2c0 + width: 1 + default: "" + top_signame: i2c0_tl + index: -1 + } + { + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + name: tl + inst_name: i2c1 + width: 1 + default: "" + top_signame: i2c1_tl + index: -1 + } + { + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + name: tl + inst_name: i2c2 + width: 1 + default: "" + top_signame: i2c2_tl + index: -1 + } + { + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + name: tl + inst_name: pattgen + width: 1 + default: "" + top_signame: pattgen_tl + index: -1 + } + { + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + name: tl inst_name: rv_timer width: 1 default: "" @@ -12425,6 +14224,54 @@ { struct: tl type: req_rsp + name: tl_i2c0 + act: req + package: tlul_pkg + inst_name: peri + width: 1 + default: "" + top_signame: i2c0_tl + index: -1 + } + { + struct: tl + type: req_rsp + name: tl_i2c1 + act: req + package: tlul_pkg + inst_name: peri + width: 1 + default: "" + top_signame: i2c1_tl + index: -1 + } + { + struct: tl + type: req_rsp + name: tl_i2c2 + act: req + package: tlul_pkg + inst_name: peri + width: 1 + default: "" + top_signame: i2c2_tl + index: -1 + } + { + struct: tl + type: req_rsp + name: tl_pattgen + act: req + package: tlul_pkg + inst_name: peri + width: 1 + default: "" + top_signame: pattgen_tl + index: -1 + } + { + struct: tl + type: req_rsp name: tl_gpio act: req package: tlul_pkg @@ -13720,6 +15567,70 @@ { package: tlul_pkg struct: tl_h2d + signame: i2c0_tl_req + width: 1 + type: req_rsp + default: "" + } + { + package: tlul_pkg + struct: tl_d2h + signame: i2c0_tl_rsp + width: 1 + type: req_rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: i2c1_tl_req + width: 1 + type: req_rsp + default: "" + } + { + package: tlul_pkg + struct: tl_d2h + signame: i2c1_tl_rsp + width: 1 + type: req_rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: i2c2_tl_req + width: 1 + type: req_rsp + default: "" + } + { + package: tlul_pkg + struct: tl_d2h + signame: i2c2_tl_rsp + width: 1 + type: req_rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: pattgen_tl_req + width: 1 + type: req_rsp + default: "" + } + { + package: tlul_pkg + struct: tl_d2h + signame: pattgen_tl_rsp + width: 1 + type: req_rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d signame: gpio_tl_req width: 1 type: req_rsp
diff --git a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv index 11fee16..0259a9f 100644 --- a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
@@ -55,6 +55,10 @@ tl_if uart1_tl_if(clk_io_div4, rst_n); tl_if uart2_tl_if(clk_io_div4, rst_n); tl_if uart3_tl_if(clk_io_div4, rst_n); +tl_if i2c0_tl_if(clk_io_div4, rst_n); +tl_if i2c1_tl_if(clk_io_div4, rst_n); +tl_if i2c2_tl_if(clk_io_div4, rst_n); +tl_if pattgen_tl_if(clk_io_div4, rst_n); tl_if gpio_tl_if(clk_io_div4, rst_n); tl_if spi_device_tl_if(clk_io_div4, rst_n); tl_if rv_timer_tl_if(clk_io_div4, rst_n); @@ -120,6 +124,10 @@ `DRIVE_CHIP_TL_DEVICE_IF(uart1, uart1, tl) `DRIVE_CHIP_TL_DEVICE_IF(uart2, uart2, tl) `DRIVE_CHIP_TL_DEVICE_IF(uart3, uart3, tl) + `DRIVE_CHIP_TL_DEVICE_IF(i2c0, i2c0, tl) + `DRIVE_CHIP_TL_DEVICE_IF(i2c1, i2c1, tl) + `DRIVE_CHIP_TL_DEVICE_IF(i2c2, i2c2, tl) + `DRIVE_CHIP_TL_DEVICE_IF(pattgen, pattgen, tl) `DRIVE_CHIP_TL_DEVICE_IF(gpio, gpio, tl) `DRIVE_CHIP_TL_DEVICE_IF(spi_device, spi_device, tl) `DRIVE_CHIP_TL_DEVICE_IF(rv_timer, rv_timer, tl)
diff --git a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv index 92716bb..8440ace 100644 --- a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
@@ -73,6 +73,18 @@ '{"uart3", '{ '{32'h40030000, 32'h40030fff} }}, + '{"i2c0", '{ + '{32'h40080000, 32'h40080fff} + }}, + '{"i2c1", '{ + '{32'h40090000, 32'h40090fff} + }}, + '{"i2c2", '{ + '{32'h400a0000, 32'h400a0fff} + }}, + '{"pattgen", '{ + '{32'h400e0000, 32'h400e0fff} + }}, '{"gpio", '{ '{32'h40040000, 32'h40040fff} }}, @@ -136,6 +148,10 @@ "uart1", "uart2", "uart3", + "i2c0", + "i2c1", + "i2c2", + "pattgen", "gpio", "spi_device", "rv_timer", @@ -174,6 +190,10 @@ "uart1", "uart2", "uart3", + "i2c0", + "i2c1", + "i2c2", + "pattgen", "gpio", "spi_device", "rv_timer",
diff --git a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson index 4a79e89..cbb855b 100644 --- a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson +++ b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
@@ -129,13 +129,13 @@ { name: "NMioPeriphIn", desc: "Number of muxed peripheral inputs", type: "int", - default: "35", + default: "41", local: "true" }, { name: "NMioPeriphOut", desc: "Number of muxed peripheral outputs", type: "int", - default: "35", + default: "45", local: "true" }, { name: "NMioPads",
diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv index d6ee44c..4f1394a 100644 --- a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv +++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
@@ -7,8 +7,8 @@ package pinmux_reg_pkg; // Param list - parameter int NMioPeriphIn = 35; - parameter int NMioPeriphOut = 35; + parameter int NMioPeriphIn = 41; + parameter int NMioPeriphOut = 45; parameter int NMioPads = 32; parameter int NDioPads = 15; parameter int NWkupDetect = 8; @@ -21,7 +21,7 @@ parameter int UsbDnPullUpSel = 5; // Address width within the block - parameter int BlockAw = 7; + parameter int BlockAw = 8; //////////////////////////// // Typedefs for registers // @@ -86,7 +86,7 @@ // Register to internal design logic // /////////////////////////////////////// typedef struct packed { - pinmux_reg2hw_periph_insel_mreg_t [34:0] periph_insel; // [678:469] + pinmux_reg2hw_periph_insel_mreg_t [40:0] periph_insel; // [714:469] pinmux_reg2hw_mio_outsel_mreg_t [31:0] mio_outsel; // [468:277] pinmux_reg2hw_mio_out_sleep_val_mreg_t [31:0] mio_out_sleep_val; // [276:213] pinmux_reg2hw_dio_out_sleep_val_mreg_t [14:0] dio_out_sleep_val; // [212:168] @@ -106,38 +106,40 @@ } pinmux_hw2reg_t; // Register Address - parameter logic [BlockAw-1:0] PINMUX_REGEN_OFFSET = 7'h 0; - parameter logic [BlockAw-1:0] PINMUX_PERIPH_INSEL_0_OFFSET = 7'h 4; - parameter logic [BlockAw-1:0] PINMUX_PERIPH_INSEL_1_OFFSET = 7'h 8; - parameter logic [BlockAw-1:0] PINMUX_PERIPH_INSEL_2_OFFSET = 7'h c; - parameter logic [BlockAw-1:0] PINMUX_PERIPH_INSEL_3_OFFSET = 7'h 10; - parameter logic [BlockAw-1:0] PINMUX_PERIPH_INSEL_4_OFFSET = 7'h 14; - parameter logic [BlockAw-1:0] PINMUX_PERIPH_INSEL_5_OFFSET = 7'h 18; - parameter logic [BlockAw-1:0] PINMUX_PERIPH_INSEL_6_OFFSET = 7'h 1c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 7'h 20; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 7'h 24; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 7'h 28; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 7'h 2c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 7'h 30; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 7'h 34; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 7'h 38; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_0_OFFSET = 7'h 3c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_1_OFFSET = 7'h 40; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_OFFSET = 7'h 44; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_OFFSET = 7'h 48; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 7'h 4c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 7'h 50; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 7'h 54; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 7'h 58; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 7'h 5c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 7'h 60; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 7'h 64; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 7'h 68; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 7'h 6c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 7'h 70; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 7'h 74; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 7'h 78; - parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 7'h 7c; + parameter logic [BlockAw-1:0] PINMUX_REGEN_OFFSET = 8'h 0; + parameter logic [BlockAw-1:0] PINMUX_PERIPH_INSEL_0_OFFSET = 8'h 4; + parameter logic [BlockAw-1:0] PINMUX_PERIPH_INSEL_1_OFFSET = 8'h 8; + parameter logic [BlockAw-1:0] PINMUX_PERIPH_INSEL_2_OFFSET = 8'h c; + parameter logic [BlockAw-1:0] PINMUX_PERIPH_INSEL_3_OFFSET = 8'h 10; + parameter logic [BlockAw-1:0] PINMUX_PERIPH_INSEL_4_OFFSET = 8'h 14; + parameter logic [BlockAw-1:0] PINMUX_PERIPH_INSEL_5_OFFSET = 8'h 18; + parameter logic [BlockAw-1:0] PINMUX_PERIPH_INSEL_6_OFFSET = 8'h 1c; + parameter logic [BlockAw-1:0] PINMUX_PERIPH_INSEL_7_OFFSET = 8'h 20; + parameter logic [BlockAw-1:0] PINMUX_PERIPH_INSEL_8_OFFSET = 8'h 24; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 8'h 28; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 8'h 2c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 8'h 30; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 8'h 34; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 8'h 38; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 8'h 3c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 8'h 40; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_0_OFFSET = 8'h 44; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_1_OFFSET = 8'h 48; + parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_OFFSET = 8'h 4c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_OFFSET = 8'h 50; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 8'h 54; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 8'h 58; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 8'h 5c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 8'h 60; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 8'h 64; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 8'h 68; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 8'h 6c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 8'h 70; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 8'h 74; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 8'h 78; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 8'h 7c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 8'h 80; + parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 8'h 84; // Register Index @@ -150,6 +152,8 @@ PINMUX_PERIPH_INSEL_4, PINMUX_PERIPH_INSEL_5, PINMUX_PERIPH_INSEL_6, + PINMUX_PERIPH_INSEL_7, + PINMUX_PERIPH_INSEL_8, PINMUX_MIO_OUTSEL_0, PINMUX_MIO_OUTSEL_1, PINMUX_MIO_OUTSEL_2, @@ -177,7 +181,7 @@ } pinmux_id_e; // Register width information to check illegal writes - parameter logic [3:0] PINMUX_PERMIT [32] = '{ + parameter logic [3:0] PINMUX_PERMIT [34] = '{ 4'b 0001, // index[ 0] PINMUX_REGEN 4'b 1111, // index[ 1] PINMUX_PERIPH_INSEL_0 4'b 1111, // index[ 2] PINMUX_PERIPH_INSEL_1 @@ -186,30 +190,32 @@ 4'b 1111, // index[ 5] PINMUX_PERIPH_INSEL_4 4'b 1111, // index[ 6] PINMUX_PERIPH_INSEL_5 4'b 1111, // index[ 7] PINMUX_PERIPH_INSEL_6 - 4'b 1111, // index[ 8] PINMUX_MIO_OUTSEL_0 - 4'b 1111, // index[ 9] PINMUX_MIO_OUTSEL_1 - 4'b 1111, // index[10] PINMUX_MIO_OUTSEL_2 - 4'b 1111, // index[11] PINMUX_MIO_OUTSEL_3 - 4'b 1111, // index[12] PINMUX_MIO_OUTSEL_4 - 4'b 1111, // index[13] PINMUX_MIO_OUTSEL_5 - 4'b 0011, // index[14] PINMUX_MIO_OUTSEL_6 - 4'b 1111, // index[15] PINMUX_MIO_OUT_SLEEP_VAL_0 - 4'b 1111, // index[16] PINMUX_MIO_OUT_SLEEP_VAL_1 - 4'b 1111, // index[17] PINMUX_DIO_OUT_SLEEP_VAL - 4'b 0001, // index[18] PINMUX_WKUP_DETECTOR_EN - 4'b 0001, // index[19] PINMUX_WKUP_DETECTOR_0 - 4'b 0001, // index[20] PINMUX_WKUP_DETECTOR_1 - 4'b 0001, // index[21] PINMUX_WKUP_DETECTOR_2 - 4'b 0001, // index[22] PINMUX_WKUP_DETECTOR_3 - 4'b 0001, // index[23] PINMUX_WKUP_DETECTOR_4 - 4'b 0001, // index[24] PINMUX_WKUP_DETECTOR_5 - 4'b 0001, // index[25] PINMUX_WKUP_DETECTOR_6 - 4'b 0001, // index[26] PINMUX_WKUP_DETECTOR_7 - 4'b 1111, // index[27] PINMUX_WKUP_DETECTOR_CNT_TH_0 - 4'b 1111, // index[28] PINMUX_WKUP_DETECTOR_CNT_TH_1 - 4'b 1111, // index[29] PINMUX_WKUP_DETECTOR_PADSEL_0 - 4'b 0011, // index[30] PINMUX_WKUP_DETECTOR_PADSEL_1 - 4'b 0001 // index[31] PINMUX_WKUP_CAUSE + 4'b 1111, // index[ 8] PINMUX_PERIPH_INSEL_7 + 4'b 0001, // index[ 9] PINMUX_PERIPH_INSEL_8 + 4'b 1111, // index[10] PINMUX_MIO_OUTSEL_0 + 4'b 1111, // index[11] PINMUX_MIO_OUTSEL_1 + 4'b 1111, // index[12] PINMUX_MIO_OUTSEL_2 + 4'b 1111, // index[13] PINMUX_MIO_OUTSEL_3 + 4'b 1111, // index[14] PINMUX_MIO_OUTSEL_4 + 4'b 1111, // index[15] PINMUX_MIO_OUTSEL_5 + 4'b 0011, // index[16] PINMUX_MIO_OUTSEL_6 + 4'b 1111, // index[17] PINMUX_MIO_OUT_SLEEP_VAL_0 + 4'b 1111, // index[18] PINMUX_MIO_OUT_SLEEP_VAL_1 + 4'b 1111, // index[19] PINMUX_DIO_OUT_SLEEP_VAL + 4'b 0001, // index[20] PINMUX_WKUP_DETECTOR_EN + 4'b 0001, // index[21] PINMUX_WKUP_DETECTOR_0 + 4'b 0001, // index[22] PINMUX_WKUP_DETECTOR_1 + 4'b 0001, // index[23] PINMUX_WKUP_DETECTOR_2 + 4'b 0001, // index[24] PINMUX_WKUP_DETECTOR_3 + 4'b 0001, // index[25] PINMUX_WKUP_DETECTOR_4 + 4'b 0001, // index[26] PINMUX_WKUP_DETECTOR_5 + 4'b 0001, // index[27] PINMUX_WKUP_DETECTOR_6 + 4'b 0001, // index[28] PINMUX_WKUP_DETECTOR_7 + 4'b 1111, // index[29] PINMUX_WKUP_DETECTOR_CNT_TH_0 + 4'b 1111, // index[30] PINMUX_WKUP_DETECTOR_CNT_TH_1 + 4'b 1111, // index[31] PINMUX_WKUP_DETECTOR_PADSEL_0 + 4'b 0011, // index[32] PINMUX_WKUP_DETECTOR_PADSEL_1 + 4'b 0001 // index[33] PINMUX_WKUP_CAUSE }; endpackage
diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv index f959fc5..506ca06 100644 --- a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv +++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
@@ -23,7 +23,7 @@ import pinmux_reg_pkg::* ; - localparam int AW = 7; + localparam int AW = 8; localparam int DW = 32; localparam int DBW = DW/8; // Byte Width @@ -179,6 +179,24 @@ logic [5:0] periph_insel_6_in_34_qs; logic [5:0] periph_insel_6_in_34_wd; logic periph_insel_6_in_34_we; + logic [5:0] periph_insel_7_in_35_qs; + logic [5:0] periph_insel_7_in_35_wd; + logic periph_insel_7_in_35_we; + logic [5:0] periph_insel_7_in_36_qs; + logic [5:0] periph_insel_7_in_36_wd; + logic periph_insel_7_in_36_we; + logic [5:0] periph_insel_7_in_37_qs; + logic [5:0] periph_insel_7_in_37_wd; + logic periph_insel_7_in_37_we; + logic [5:0] periph_insel_7_in_38_qs; + logic [5:0] periph_insel_7_in_38_wd; + logic periph_insel_7_in_38_we; + logic [5:0] periph_insel_7_in_39_qs; + logic [5:0] periph_insel_7_in_39_wd; + logic periph_insel_7_in_39_we; + logic [5:0] periph_insel_8_qs; + logic [5:0] periph_insel_8_wd; + logic periph_insel_8_we; logic [5:0] mio_outsel_0_out_0_qs; logic [5:0] mio_outsel_0_out_0_wd; logic mio_outsel_0_out_0_we; @@ -1568,6 +1586,166 @@ ); + // Subregister 35 of Multireg periph_insel + // R[periph_insel_7]: V(False) + + // F[in_35]: 5:0 + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h0) + ) u_periph_insel_7_in_35 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (periph_insel_7_in_35_we & regen_qs), + .wd (periph_insel_7_in_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.periph_insel[35].q ), + + // to register interface (read) + .qs (periph_insel_7_in_35_qs) + ); + + + // F[in_36]: 11:6 + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h0) + ) u_periph_insel_7_in_36 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (periph_insel_7_in_36_we & regen_qs), + .wd (periph_insel_7_in_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.periph_insel[36].q ), + + // to register interface (read) + .qs (periph_insel_7_in_36_qs) + ); + + + // F[in_37]: 17:12 + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h0) + ) u_periph_insel_7_in_37 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (periph_insel_7_in_37_we & regen_qs), + .wd (periph_insel_7_in_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.periph_insel[37].q ), + + // to register interface (read) + .qs (periph_insel_7_in_37_qs) + ); + + + // F[in_38]: 23:18 + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h0) + ) u_periph_insel_7_in_38 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (periph_insel_7_in_38_we & regen_qs), + .wd (periph_insel_7_in_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.periph_insel[38].q ), + + // to register interface (read) + .qs (periph_insel_7_in_38_qs) + ); + + + // F[in_39]: 29:24 + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h0) + ) u_periph_insel_7_in_39 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (periph_insel_7_in_39_we & regen_qs), + .wd (periph_insel_7_in_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.periph_insel[39].q ), + + // to register interface (read) + .qs (periph_insel_7_in_39_qs) + ); + + + // Subregister 40 of Multireg periph_insel + // R[periph_insel_8]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h0) + ) u_periph_insel_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (periph_insel_8_we & regen_qs), + .wd (periph_insel_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.periph_insel[40].q ), + + // to register interface (read) + .qs (periph_insel_8_qs) + ); + // Subregister 0 of Multireg mio_outsel @@ -4939,7 +5117,7 @@ - logic [31:0] addr_hit; + logic [33:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == PINMUX_REGEN_OFFSET); @@ -4950,30 +5128,32 @@ addr_hit[ 5] = (reg_addr == PINMUX_PERIPH_INSEL_4_OFFSET); addr_hit[ 6] = (reg_addr == PINMUX_PERIPH_INSEL_5_OFFSET); addr_hit[ 7] = (reg_addr == PINMUX_PERIPH_INSEL_6_OFFSET); - addr_hit[ 8] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET); - addr_hit[ 9] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET); - addr_hit[10] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET); - addr_hit[11] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET); - addr_hit[12] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET); - addr_hit[13] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET); - addr_hit[14] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET); - addr_hit[15] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_0_OFFSET); - addr_hit[16] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_1_OFFSET); - addr_hit[17] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_OFFSET); - addr_hit[18] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_OFFSET); - addr_hit[19] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET); - addr_hit[20] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET); - addr_hit[21] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET); - addr_hit[22] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET); - addr_hit[23] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET); - addr_hit[24] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET); - addr_hit[25] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET); - addr_hit[26] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET); - addr_hit[27] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET); - addr_hit[28] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET); - addr_hit[29] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET); - addr_hit[30] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET); - addr_hit[31] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET); + addr_hit[ 8] = (reg_addr == PINMUX_PERIPH_INSEL_7_OFFSET); + addr_hit[ 9] = (reg_addr == PINMUX_PERIPH_INSEL_8_OFFSET); + addr_hit[10] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET); + addr_hit[11] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET); + addr_hit[12] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET); + addr_hit[13] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET); + addr_hit[14] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET); + addr_hit[15] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET); + addr_hit[16] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET); + addr_hit[17] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_0_OFFSET); + addr_hit[18] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_1_OFFSET); + addr_hit[19] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_OFFSET); + addr_hit[20] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_OFFSET); + addr_hit[21] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET); + addr_hit[22] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET); + addr_hit[23] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET); + addr_hit[24] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET); + addr_hit[25] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET); + addr_hit[26] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET); + addr_hit[27] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET); + addr_hit[28] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET); + addr_hit[29] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET); + addr_hit[30] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET); + addr_hit[31] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET); + addr_hit[32] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET); + addr_hit[33] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -5013,6 +5193,8 @@ if (addr_hit[29] && reg_we && (PINMUX_PERMIT[29] != (PINMUX_PERMIT[29] & reg_be))) wr_err = 1'b1 ; if (addr_hit[30] && reg_we && (PINMUX_PERMIT[30] != (PINMUX_PERMIT[30] & reg_be))) wr_err = 1'b1 ; if (addr_hit[31] && reg_we && (PINMUX_PERMIT[31] != (PINMUX_PERMIT[31] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[32] && reg_we && (PINMUX_PERMIT[32] != (PINMUX_PERMIT[32] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[33] && reg_we && (PINMUX_PERMIT[33] != (PINMUX_PERMIT[33] & reg_be))) wr_err = 1'b1 ; end assign regen_we = addr_hit[0] & reg_we & ~wr_err; @@ -5123,433 +5305,451 @@ assign periph_insel_6_in_34_we = addr_hit[7] & reg_we & ~wr_err; assign periph_insel_6_in_34_wd = reg_wdata[29:24]; - assign mio_outsel_0_out_0_we = addr_hit[8] & reg_we & ~wr_err; + assign periph_insel_7_in_35_we = addr_hit[8] & reg_we & ~wr_err; + assign periph_insel_7_in_35_wd = reg_wdata[5:0]; + + assign periph_insel_7_in_36_we = addr_hit[8] & reg_we & ~wr_err; + assign periph_insel_7_in_36_wd = reg_wdata[11:6]; + + assign periph_insel_7_in_37_we = addr_hit[8] & reg_we & ~wr_err; + assign periph_insel_7_in_37_wd = reg_wdata[17:12]; + + assign periph_insel_7_in_38_we = addr_hit[8] & reg_we & ~wr_err; + assign periph_insel_7_in_38_wd = reg_wdata[23:18]; + + assign periph_insel_7_in_39_we = addr_hit[8] & reg_we & ~wr_err; + assign periph_insel_7_in_39_wd = reg_wdata[29:24]; + + assign periph_insel_8_we = addr_hit[9] & reg_we & ~wr_err; + assign periph_insel_8_wd = reg_wdata[5:0]; + + assign mio_outsel_0_out_0_we = addr_hit[10] & reg_we & ~wr_err; assign mio_outsel_0_out_0_wd = reg_wdata[5:0]; - assign mio_outsel_0_out_1_we = addr_hit[8] & reg_we & ~wr_err; + assign mio_outsel_0_out_1_we = addr_hit[10] & reg_we & ~wr_err; assign mio_outsel_0_out_1_wd = reg_wdata[11:6]; - assign mio_outsel_0_out_2_we = addr_hit[8] & reg_we & ~wr_err; + assign mio_outsel_0_out_2_we = addr_hit[10] & reg_we & ~wr_err; assign mio_outsel_0_out_2_wd = reg_wdata[17:12]; - assign mio_outsel_0_out_3_we = addr_hit[8] & reg_we & ~wr_err; + assign mio_outsel_0_out_3_we = addr_hit[10] & reg_we & ~wr_err; assign mio_outsel_0_out_3_wd = reg_wdata[23:18]; - assign mio_outsel_0_out_4_we = addr_hit[8] & reg_we & ~wr_err; + assign mio_outsel_0_out_4_we = addr_hit[10] & reg_we & ~wr_err; assign mio_outsel_0_out_4_wd = reg_wdata[29:24]; - assign mio_outsel_1_out_5_we = addr_hit[9] & reg_we & ~wr_err; + assign mio_outsel_1_out_5_we = addr_hit[11] & reg_we & ~wr_err; assign mio_outsel_1_out_5_wd = reg_wdata[5:0]; - assign mio_outsel_1_out_6_we = addr_hit[9] & reg_we & ~wr_err; + assign mio_outsel_1_out_6_we = addr_hit[11] & reg_we & ~wr_err; assign mio_outsel_1_out_6_wd = reg_wdata[11:6]; - assign mio_outsel_1_out_7_we = addr_hit[9] & reg_we & ~wr_err; + assign mio_outsel_1_out_7_we = addr_hit[11] & reg_we & ~wr_err; assign mio_outsel_1_out_7_wd = reg_wdata[17:12]; - assign mio_outsel_1_out_8_we = addr_hit[9] & reg_we & ~wr_err; + assign mio_outsel_1_out_8_we = addr_hit[11] & reg_we & ~wr_err; assign mio_outsel_1_out_8_wd = reg_wdata[23:18]; - assign mio_outsel_1_out_9_we = addr_hit[9] & reg_we & ~wr_err; + assign mio_outsel_1_out_9_we = addr_hit[11] & reg_we & ~wr_err; assign mio_outsel_1_out_9_wd = reg_wdata[29:24]; - assign mio_outsel_2_out_10_we = addr_hit[10] & reg_we & ~wr_err; + assign mio_outsel_2_out_10_we = addr_hit[12] & reg_we & ~wr_err; assign mio_outsel_2_out_10_wd = reg_wdata[5:0]; - assign mio_outsel_2_out_11_we = addr_hit[10] & reg_we & ~wr_err; + assign mio_outsel_2_out_11_we = addr_hit[12] & reg_we & ~wr_err; assign mio_outsel_2_out_11_wd = reg_wdata[11:6]; - assign mio_outsel_2_out_12_we = addr_hit[10] & reg_we & ~wr_err; + assign mio_outsel_2_out_12_we = addr_hit[12] & reg_we & ~wr_err; assign mio_outsel_2_out_12_wd = reg_wdata[17:12]; - assign mio_outsel_2_out_13_we = addr_hit[10] & reg_we & ~wr_err; + assign mio_outsel_2_out_13_we = addr_hit[12] & reg_we & ~wr_err; assign mio_outsel_2_out_13_wd = reg_wdata[23:18]; - assign mio_outsel_2_out_14_we = addr_hit[10] & reg_we & ~wr_err; + assign mio_outsel_2_out_14_we = addr_hit[12] & reg_we & ~wr_err; assign mio_outsel_2_out_14_wd = reg_wdata[29:24]; - assign mio_outsel_3_out_15_we = addr_hit[11] & reg_we & ~wr_err; + assign mio_outsel_3_out_15_we = addr_hit[13] & reg_we & ~wr_err; assign mio_outsel_3_out_15_wd = reg_wdata[5:0]; - assign mio_outsel_3_out_16_we = addr_hit[11] & reg_we & ~wr_err; + assign mio_outsel_3_out_16_we = addr_hit[13] & reg_we & ~wr_err; assign mio_outsel_3_out_16_wd = reg_wdata[11:6]; - assign mio_outsel_3_out_17_we = addr_hit[11] & reg_we & ~wr_err; + assign mio_outsel_3_out_17_we = addr_hit[13] & reg_we & ~wr_err; assign mio_outsel_3_out_17_wd = reg_wdata[17:12]; - assign mio_outsel_3_out_18_we = addr_hit[11] & reg_we & ~wr_err; + assign mio_outsel_3_out_18_we = addr_hit[13] & reg_we & ~wr_err; assign mio_outsel_3_out_18_wd = reg_wdata[23:18]; - assign mio_outsel_3_out_19_we = addr_hit[11] & reg_we & ~wr_err; + assign mio_outsel_3_out_19_we = addr_hit[13] & reg_we & ~wr_err; assign mio_outsel_3_out_19_wd = reg_wdata[29:24]; - assign mio_outsel_4_out_20_we = addr_hit[12] & reg_we & ~wr_err; + assign mio_outsel_4_out_20_we = addr_hit[14] & reg_we & ~wr_err; assign mio_outsel_4_out_20_wd = reg_wdata[5:0]; - assign mio_outsel_4_out_21_we = addr_hit[12] & reg_we & ~wr_err; + assign mio_outsel_4_out_21_we = addr_hit[14] & reg_we & ~wr_err; assign mio_outsel_4_out_21_wd = reg_wdata[11:6]; - assign mio_outsel_4_out_22_we = addr_hit[12] & reg_we & ~wr_err; + assign mio_outsel_4_out_22_we = addr_hit[14] & reg_we & ~wr_err; assign mio_outsel_4_out_22_wd = reg_wdata[17:12]; - assign mio_outsel_4_out_23_we = addr_hit[12] & reg_we & ~wr_err; + assign mio_outsel_4_out_23_we = addr_hit[14] & reg_we & ~wr_err; assign mio_outsel_4_out_23_wd = reg_wdata[23:18]; - assign mio_outsel_4_out_24_we = addr_hit[12] & reg_we & ~wr_err; + assign mio_outsel_4_out_24_we = addr_hit[14] & reg_we & ~wr_err; assign mio_outsel_4_out_24_wd = reg_wdata[29:24]; - assign mio_outsel_5_out_25_we = addr_hit[13] & reg_we & ~wr_err; + assign mio_outsel_5_out_25_we = addr_hit[15] & reg_we & ~wr_err; assign mio_outsel_5_out_25_wd = reg_wdata[5:0]; - assign mio_outsel_5_out_26_we = addr_hit[13] & reg_we & ~wr_err; + assign mio_outsel_5_out_26_we = addr_hit[15] & reg_we & ~wr_err; assign mio_outsel_5_out_26_wd = reg_wdata[11:6]; - assign mio_outsel_5_out_27_we = addr_hit[13] & reg_we & ~wr_err; + assign mio_outsel_5_out_27_we = addr_hit[15] & reg_we & ~wr_err; assign mio_outsel_5_out_27_wd = reg_wdata[17:12]; - assign mio_outsel_5_out_28_we = addr_hit[13] & reg_we & ~wr_err; + assign mio_outsel_5_out_28_we = addr_hit[15] & reg_we & ~wr_err; assign mio_outsel_5_out_28_wd = reg_wdata[23:18]; - assign mio_outsel_5_out_29_we = addr_hit[13] & reg_we & ~wr_err; + assign mio_outsel_5_out_29_we = addr_hit[15] & reg_we & ~wr_err; assign mio_outsel_5_out_29_wd = reg_wdata[29:24]; - assign mio_outsel_6_out_30_we = addr_hit[14] & reg_we & ~wr_err; + assign mio_outsel_6_out_30_we = addr_hit[16] & reg_we & ~wr_err; assign mio_outsel_6_out_30_wd = reg_wdata[5:0]; - assign mio_outsel_6_out_31_we = addr_hit[14] & reg_we & ~wr_err; + assign mio_outsel_6_out_31_we = addr_hit[16] & reg_we & ~wr_err; assign mio_outsel_6_out_31_wd = reg_wdata[11:6]; - assign mio_out_sleep_val_0_out_0_we = addr_hit[15] & reg_we & ~wr_err; + assign mio_out_sleep_val_0_out_0_we = addr_hit[17] & reg_we & ~wr_err; assign mio_out_sleep_val_0_out_0_wd = reg_wdata[1:0]; - assign mio_out_sleep_val_0_out_1_we = addr_hit[15] & reg_we & ~wr_err; + assign mio_out_sleep_val_0_out_1_we = addr_hit[17] & reg_we & ~wr_err; assign mio_out_sleep_val_0_out_1_wd = reg_wdata[3:2]; - assign mio_out_sleep_val_0_out_2_we = addr_hit[15] & reg_we & ~wr_err; + assign mio_out_sleep_val_0_out_2_we = addr_hit[17] & reg_we & ~wr_err; assign mio_out_sleep_val_0_out_2_wd = reg_wdata[5:4]; - assign mio_out_sleep_val_0_out_3_we = addr_hit[15] & reg_we & ~wr_err; + assign mio_out_sleep_val_0_out_3_we = addr_hit[17] & reg_we & ~wr_err; assign mio_out_sleep_val_0_out_3_wd = reg_wdata[7:6]; - assign mio_out_sleep_val_0_out_4_we = addr_hit[15] & reg_we & ~wr_err; + assign mio_out_sleep_val_0_out_4_we = addr_hit[17] & reg_we & ~wr_err; assign mio_out_sleep_val_0_out_4_wd = reg_wdata[9:8]; - assign mio_out_sleep_val_0_out_5_we = addr_hit[15] & reg_we & ~wr_err; + assign mio_out_sleep_val_0_out_5_we = addr_hit[17] & reg_we & ~wr_err; assign mio_out_sleep_val_0_out_5_wd = reg_wdata[11:10]; - assign mio_out_sleep_val_0_out_6_we = addr_hit[15] & reg_we & ~wr_err; + assign mio_out_sleep_val_0_out_6_we = addr_hit[17] & reg_we & ~wr_err; assign mio_out_sleep_val_0_out_6_wd = reg_wdata[13:12]; - assign mio_out_sleep_val_0_out_7_we = addr_hit[15] & reg_we & ~wr_err; + assign mio_out_sleep_val_0_out_7_we = addr_hit[17] & reg_we & ~wr_err; assign mio_out_sleep_val_0_out_7_wd = reg_wdata[15:14]; - assign mio_out_sleep_val_0_out_8_we = addr_hit[15] & reg_we & ~wr_err; + assign mio_out_sleep_val_0_out_8_we = addr_hit[17] & reg_we & ~wr_err; assign mio_out_sleep_val_0_out_8_wd = reg_wdata[17:16]; - assign mio_out_sleep_val_0_out_9_we = addr_hit[15] & reg_we & ~wr_err; + assign mio_out_sleep_val_0_out_9_we = addr_hit[17] & reg_we & ~wr_err; assign mio_out_sleep_val_0_out_9_wd = reg_wdata[19:18]; - assign mio_out_sleep_val_0_out_10_we = addr_hit[15] & reg_we & ~wr_err; + assign mio_out_sleep_val_0_out_10_we = addr_hit[17] & reg_we & ~wr_err; assign mio_out_sleep_val_0_out_10_wd = reg_wdata[21:20]; - assign mio_out_sleep_val_0_out_11_we = addr_hit[15] & reg_we & ~wr_err; + assign mio_out_sleep_val_0_out_11_we = addr_hit[17] & reg_we & ~wr_err; assign mio_out_sleep_val_0_out_11_wd = reg_wdata[23:22]; - assign mio_out_sleep_val_0_out_12_we = addr_hit[15] & reg_we & ~wr_err; + assign mio_out_sleep_val_0_out_12_we = addr_hit[17] & reg_we & ~wr_err; assign mio_out_sleep_val_0_out_12_wd = reg_wdata[25:24]; - assign mio_out_sleep_val_0_out_13_we = addr_hit[15] & reg_we & ~wr_err; + assign mio_out_sleep_val_0_out_13_we = addr_hit[17] & reg_we & ~wr_err; assign mio_out_sleep_val_0_out_13_wd = reg_wdata[27:26]; - assign mio_out_sleep_val_0_out_14_we = addr_hit[15] & reg_we & ~wr_err; + assign mio_out_sleep_val_0_out_14_we = addr_hit[17] & reg_we & ~wr_err; assign mio_out_sleep_val_0_out_14_wd = reg_wdata[29:28]; - assign mio_out_sleep_val_0_out_15_we = addr_hit[15] & reg_we & ~wr_err; + assign mio_out_sleep_val_0_out_15_we = addr_hit[17] & reg_we & ~wr_err; assign mio_out_sleep_val_0_out_15_wd = reg_wdata[31:30]; - assign mio_out_sleep_val_1_out_16_we = addr_hit[16] & reg_we & ~wr_err; + assign mio_out_sleep_val_1_out_16_we = addr_hit[18] & reg_we & ~wr_err; assign mio_out_sleep_val_1_out_16_wd = reg_wdata[1:0]; - assign mio_out_sleep_val_1_out_17_we = addr_hit[16] & reg_we & ~wr_err; + assign mio_out_sleep_val_1_out_17_we = addr_hit[18] & reg_we & ~wr_err; assign mio_out_sleep_val_1_out_17_wd = reg_wdata[3:2]; - assign mio_out_sleep_val_1_out_18_we = addr_hit[16] & reg_we & ~wr_err; + assign mio_out_sleep_val_1_out_18_we = addr_hit[18] & reg_we & ~wr_err; assign mio_out_sleep_val_1_out_18_wd = reg_wdata[5:4]; - assign mio_out_sleep_val_1_out_19_we = addr_hit[16] & reg_we & ~wr_err; + assign mio_out_sleep_val_1_out_19_we = addr_hit[18] & reg_we & ~wr_err; assign mio_out_sleep_val_1_out_19_wd = reg_wdata[7:6]; - assign mio_out_sleep_val_1_out_20_we = addr_hit[16] & reg_we & ~wr_err; + assign mio_out_sleep_val_1_out_20_we = addr_hit[18] & reg_we & ~wr_err; assign mio_out_sleep_val_1_out_20_wd = reg_wdata[9:8]; - assign mio_out_sleep_val_1_out_21_we = addr_hit[16] & reg_we & ~wr_err; + assign mio_out_sleep_val_1_out_21_we = addr_hit[18] & reg_we & ~wr_err; assign mio_out_sleep_val_1_out_21_wd = reg_wdata[11:10]; - assign mio_out_sleep_val_1_out_22_we = addr_hit[16] & reg_we & ~wr_err; + assign mio_out_sleep_val_1_out_22_we = addr_hit[18] & reg_we & ~wr_err; assign mio_out_sleep_val_1_out_22_wd = reg_wdata[13:12]; - assign mio_out_sleep_val_1_out_23_we = addr_hit[16] & reg_we & ~wr_err; + assign mio_out_sleep_val_1_out_23_we = addr_hit[18] & reg_we & ~wr_err; assign mio_out_sleep_val_1_out_23_wd = reg_wdata[15:14]; - assign mio_out_sleep_val_1_out_24_we = addr_hit[16] & reg_we & ~wr_err; + assign mio_out_sleep_val_1_out_24_we = addr_hit[18] & reg_we & ~wr_err; assign mio_out_sleep_val_1_out_24_wd = reg_wdata[17:16]; - assign mio_out_sleep_val_1_out_25_we = addr_hit[16] & reg_we & ~wr_err; + assign mio_out_sleep_val_1_out_25_we = addr_hit[18] & reg_we & ~wr_err; assign mio_out_sleep_val_1_out_25_wd = reg_wdata[19:18]; - assign mio_out_sleep_val_1_out_26_we = addr_hit[16] & reg_we & ~wr_err; + assign mio_out_sleep_val_1_out_26_we = addr_hit[18] & reg_we & ~wr_err; assign mio_out_sleep_val_1_out_26_wd = reg_wdata[21:20]; - assign mio_out_sleep_val_1_out_27_we = addr_hit[16] & reg_we & ~wr_err; + assign mio_out_sleep_val_1_out_27_we = addr_hit[18] & reg_we & ~wr_err; assign mio_out_sleep_val_1_out_27_wd = reg_wdata[23:22]; - assign mio_out_sleep_val_1_out_28_we = addr_hit[16] & reg_we & ~wr_err; + assign mio_out_sleep_val_1_out_28_we = addr_hit[18] & reg_we & ~wr_err; assign mio_out_sleep_val_1_out_28_wd = reg_wdata[25:24]; - assign mio_out_sleep_val_1_out_29_we = addr_hit[16] & reg_we & ~wr_err; + assign mio_out_sleep_val_1_out_29_we = addr_hit[18] & reg_we & ~wr_err; assign mio_out_sleep_val_1_out_29_wd = reg_wdata[27:26]; - assign mio_out_sleep_val_1_out_30_we = addr_hit[16] & reg_we & ~wr_err; + assign mio_out_sleep_val_1_out_30_we = addr_hit[18] & reg_we & ~wr_err; assign mio_out_sleep_val_1_out_30_wd = reg_wdata[29:28]; - assign mio_out_sleep_val_1_out_31_we = addr_hit[16] & reg_we & ~wr_err; + assign mio_out_sleep_val_1_out_31_we = addr_hit[18] & reg_we & ~wr_err; assign mio_out_sleep_val_1_out_31_wd = reg_wdata[31:30]; - assign dio_out_sleep_val_out_0_we = addr_hit[17] & reg_we & ~wr_err; + assign dio_out_sleep_val_out_0_we = addr_hit[19] & reg_we & ~wr_err; assign dio_out_sleep_val_out_0_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_out_0_re = addr_hit[17] && reg_re; + assign dio_out_sleep_val_out_0_re = addr_hit[19] && reg_re; - assign dio_out_sleep_val_out_1_we = addr_hit[17] & reg_we & ~wr_err; + assign dio_out_sleep_val_out_1_we = addr_hit[19] & reg_we & ~wr_err; assign dio_out_sleep_val_out_1_wd = reg_wdata[3:2]; - assign dio_out_sleep_val_out_1_re = addr_hit[17] && reg_re; + assign dio_out_sleep_val_out_1_re = addr_hit[19] && reg_re; - assign dio_out_sleep_val_out_2_we = addr_hit[17] & reg_we & ~wr_err; + assign dio_out_sleep_val_out_2_we = addr_hit[19] & reg_we & ~wr_err; assign dio_out_sleep_val_out_2_wd = reg_wdata[5:4]; - assign dio_out_sleep_val_out_2_re = addr_hit[17] && reg_re; + assign dio_out_sleep_val_out_2_re = addr_hit[19] && reg_re; - assign dio_out_sleep_val_out_3_we = addr_hit[17] & reg_we & ~wr_err; + assign dio_out_sleep_val_out_3_we = addr_hit[19] & reg_we & ~wr_err; assign dio_out_sleep_val_out_3_wd = reg_wdata[7:6]; - assign dio_out_sleep_val_out_3_re = addr_hit[17] && reg_re; + assign dio_out_sleep_val_out_3_re = addr_hit[19] && reg_re; - assign dio_out_sleep_val_out_4_we = addr_hit[17] & reg_we & ~wr_err; + assign dio_out_sleep_val_out_4_we = addr_hit[19] & reg_we & ~wr_err; assign dio_out_sleep_val_out_4_wd = reg_wdata[9:8]; - assign dio_out_sleep_val_out_4_re = addr_hit[17] && reg_re; + assign dio_out_sleep_val_out_4_re = addr_hit[19] && reg_re; - assign dio_out_sleep_val_out_5_we = addr_hit[17] & reg_we & ~wr_err; + assign dio_out_sleep_val_out_5_we = addr_hit[19] & reg_we & ~wr_err; assign dio_out_sleep_val_out_5_wd = reg_wdata[11:10]; - assign dio_out_sleep_val_out_5_re = addr_hit[17] && reg_re; + assign dio_out_sleep_val_out_5_re = addr_hit[19] && reg_re; - assign dio_out_sleep_val_out_6_we = addr_hit[17] & reg_we & ~wr_err; + assign dio_out_sleep_val_out_6_we = addr_hit[19] & reg_we & ~wr_err; assign dio_out_sleep_val_out_6_wd = reg_wdata[13:12]; - assign dio_out_sleep_val_out_6_re = addr_hit[17] && reg_re; + assign dio_out_sleep_val_out_6_re = addr_hit[19] && reg_re; - assign dio_out_sleep_val_out_7_we = addr_hit[17] & reg_we & ~wr_err; + assign dio_out_sleep_val_out_7_we = addr_hit[19] & reg_we & ~wr_err; assign dio_out_sleep_val_out_7_wd = reg_wdata[15:14]; - assign dio_out_sleep_val_out_7_re = addr_hit[17] && reg_re; + assign dio_out_sleep_val_out_7_re = addr_hit[19] && reg_re; - assign dio_out_sleep_val_out_8_we = addr_hit[17] & reg_we & ~wr_err; + assign dio_out_sleep_val_out_8_we = addr_hit[19] & reg_we & ~wr_err; assign dio_out_sleep_val_out_8_wd = reg_wdata[17:16]; - assign dio_out_sleep_val_out_8_re = addr_hit[17] && reg_re; + assign dio_out_sleep_val_out_8_re = addr_hit[19] && reg_re; - assign dio_out_sleep_val_out_9_we = addr_hit[17] & reg_we & ~wr_err; + assign dio_out_sleep_val_out_9_we = addr_hit[19] & reg_we & ~wr_err; assign dio_out_sleep_val_out_9_wd = reg_wdata[19:18]; - assign dio_out_sleep_val_out_9_re = addr_hit[17] && reg_re; + assign dio_out_sleep_val_out_9_re = addr_hit[19] && reg_re; - assign dio_out_sleep_val_out_10_we = addr_hit[17] & reg_we & ~wr_err; + assign dio_out_sleep_val_out_10_we = addr_hit[19] & reg_we & ~wr_err; assign dio_out_sleep_val_out_10_wd = reg_wdata[21:20]; - assign dio_out_sleep_val_out_10_re = addr_hit[17] && reg_re; + assign dio_out_sleep_val_out_10_re = addr_hit[19] && reg_re; - assign dio_out_sleep_val_out_11_we = addr_hit[17] & reg_we & ~wr_err; + assign dio_out_sleep_val_out_11_we = addr_hit[19] & reg_we & ~wr_err; assign dio_out_sleep_val_out_11_wd = reg_wdata[23:22]; - assign dio_out_sleep_val_out_11_re = addr_hit[17] && reg_re; + assign dio_out_sleep_val_out_11_re = addr_hit[19] && reg_re; - assign dio_out_sleep_val_out_12_we = addr_hit[17] & reg_we & ~wr_err; + assign dio_out_sleep_val_out_12_we = addr_hit[19] & reg_we & ~wr_err; assign dio_out_sleep_val_out_12_wd = reg_wdata[25:24]; - assign dio_out_sleep_val_out_12_re = addr_hit[17] && reg_re; + assign dio_out_sleep_val_out_12_re = addr_hit[19] && reg_re; - assign dio_out_sleep_val_out_13_we = addr_hit[17] & reg_we & ~wr_err; + assign dio_out_sleep_val_out_13_we = addr_hit[19] & reg_we & ~wr_err; assign dio_out_sleep_val_out_13_wd = reg_wdata[27:26]; - assign dio_out_sleep_val_out_13_re = addr_hit[17] && reg_re; + assign dio_out_sleep_val_out_13_re = addr_hit[19] && reg_re; - assign dio_out_sleep_val_out_14_we = addr_hit[17] & reg_we & ~wr_err; + assign dio_out_sleep_val_out_14_we = addr_hit[19] & reg_we & ~wr_err; assign dio_out_sleep_val_out_14_wd = reg_wdata[29:28]; - assign dio_out_sleep_val_out_14_re = addr_hit[17] && reg_re; + assign dio_out_sleep_val_out_14_re = addr_hit[19] && reg_re; - assign wkup_detector_en_en_0_we = addr_hit[18] & reg_we & ~wr_err; + assign wkup_detector_en_en_0_we = addr_hit[20] & reg_we & ~wr_err; assign wkup_detector_en_en_0_wd = reg_wdata[0]; - assign wkup_detector_en_en_1_we = addr_hit[18] & reg_we & ~wr_err; + assign wkup_detector_en_en_1_we = addr_hit[20] & reg_we & ~wr_err; assign wkup_detector_en_en_1_wd = reg_wdata[1]; - assign wkup_detector_en_en_2_we = addr_hit[18] & reg_we & ~wr_err; + assign wkup_detector_en_en_2_we = addr_hit[20] & reg_we & ~wr_err; assign wkup_detector_en_en_2_wd = reg_wdata[2]; - assign wkup_detector_en_en_3_we = addr_hit[18] & reg_we & ~wr_err; + assign wkup_detector_en_en_3_we = addr_hit[20] & reg_we & ~wr_err; assign wkup_detector_en_en_3_wd = reg_wdata[3]; - assign wkup_detector_en_en_4_we = addr_hit[18] & reg_we & ~wr_err; + assign wkup_detector_en_en_4_we = addr_hit[20] & reg_we & ~wr_err; assign wkup_detector_en_en_4_wd = reg_wdata[4]; - assign wkup_detector_en_en_5_we = addr_hit[18] & reg_we & ~wr_err; + assign wkup_detector_en_en_5_we = addr_hit[20] & reg_we & ~wr_err; assign wkup_detector_en_en_5_wd = reg_wdata[5]; - assign wkup_detector_en_en_6_we = addr_hit[18] & reg_we & ~wr_err; + assign wkup_detector_en_en_6_we = addr_hit[20] & reg_we & ~wr_err; assign wkup_detector_en_en_6_wd = reg_wdata[6]; - assign wkup_detector_en_en_7_we = addr_hit[18] & reg_we & ~wr_err; + assign wkup_detector_en_en_7_we = addr_hit[20] & reg_we & ~wr_err; assign wkup_detector_en_en_7_wd = reg_wdata[7]; - assign wkup_detector_0_mode_0_we = addr_hit[19] & reg_we & ~wr_err; + assign wkup_detector_0_mode_0_we = addr_hit[21] & reg_we & ~wr_err; assign wkup_detector_0_mode_0_wd = reg_wdata[2:0]; - assign wkup_detector_0_filter_0_we = addr_hit[19] & reg_we & ~wr_err; + assign wkup_detector_0_filter_0_we = addr_hit[21] & reg_we & ~wr_err; assign wkup_detector_0_filter_0_wd = reg_wdata[3]; - assign wkup_detector_0_miodio_0_we = addr_hit[19] & reg_we & ~wr_err; + assign wkup_detector_0_miodio_0_we = addr_hit[21] & reg_we & ~wr_err; assign wkup_detector_0_miodio_0_wd = reg_wdata[4]; - assign wkup_detector_1_mode_1_we = addr_hit[20] & reg_we & ~wr_err; + assign wkup_detector_1_mode_1_we = addr_hit[22] & reg_we & ~wr_err; assign wkup_detector_1_mode_1_wd = reg_wdata[2:0]; - assign wkup_detector_1_filter_1_we = addr_hit[20] & reg_we & ~wr_err; + assign wkup_detector_1_filter_1_we = addr_hit[22] & reg_we & ~wr_err; assign wkup_detector_1_filter_1_wd = reg_wdata[3]; - assign wkup_detector_1_miodio_1_we = addr_hit[20] & reg_we & ~wr_err; + assign wkup_detector_1_miodio_1_we = addr_hit[22] & reg_we & ~wr_err; assign wkup_detector_1_miodio_1_wd = reg_wdata[4]; - assign wkup_detector_2_mode_2_we = addr_hit[21] & reg_we & ~wr_err; + assign wkup_detector_2_mode_2_we = addr_hit[23] & reg_we & ~wr_err; assign wkup_detector_2_mode_2_wd = reg_wdata[2:0]; - assign wkup_detector_2_filter_2_we = addr_hit[21] & reg_we & ~wr_err; + assign wkup_detector_2_filter_2_we = addr_hit[23] & reg_we & ~wr_err; assign wkup_detector_2_filter_2_wd = reg_wdata[3]; - assign wkup_detector_2_miodio_2_we = addr_hit[21] & reg_we & ~wr_err; + assign wkup_detector_2_miodio_2_we = addr_hit[23] & reg_we & ~wr_err; assign wkup_detector_2_miodio_2_wd = reg_wdata[4]; - assign wkup_detector_3_mode_3_we = addr_hit[22] & reg_we & ~wr_err; + assign wkup_detector_3_mode_3_we = addr_hit[24] & reg_we & ~wr_err; assign wkup_detector_3_mode_3_wd = reg_wdata[2:0]; - assign wkup_detector_3_filter_3_we = addr_hit[22] & reg_we & ~wr_err; + assign wkup_detector_3_filter_3_we = addr_hit[24] & reg_we & ~wr_err; assign wkup_detector_3_filter_3_wd = reg_wdata[3]; - assign wkup_detector_3_miodio_3_we = addr_hit[22] & reg_we & ~wr_err; + assign wkup_detector_3_miodio_3_we = addr_hit[24] & reg_we & ~wr_err; assign wkup_detector_3_miodio_3_wd = reg_wdata[4]; - assign wkup_detector_4_mode_4_we = addr_hit[23] & reg_we & ~wr_err; + assign wkup_detector_4_mode_4_we = addr_hit[25] & reg_we & ~wr_err; assign wkup_detector_4_mode_4_wd = reg_wdata[2:0]; - assign wkup_detector_4_filter_4_we = addr_hit[23] & reg_we & ~wr_err; + assign wkup_detector_4_filter_4_we = addr_hit[25] & reg_we & ~wr_err; assign wkup_detector_4_filter_4_wd = reg_wdata[3]; - assign wkup_detector_4_miodio_4_we = addr_hit[23] & reg_we & ~wr_err; + assign wkup_detector_4_miodio_4_we = addr_hit[25] & reg_we & ~wr_err; assign wkup_detector_4_miodio_4_wd = reg_wdata[4]; - assign wkup_detector_5_mode_5_we = addr_hit[24] & reg_we & ~wr_err; + assign wkup_detector_5_mode_5_we = addr_hit[26] & reg_we & ~wr_err; assign wkup_detector_5_mode_5_wd = reg_wdata[2:0]; - assign wkup_detector_5_filter_5_we = addr_hit[24] & reg_we & ~wr_err; + assign wkup_detector_5_filter_5_we = addr_hit[26] & reg_we & ~wr_err; assign wkup_detector_5_filter_5_wd = reg_wdata[3]; - assign wkup_detector_5_miodio_5_we = addr_hit[24] & reg_we & ~wr_err; + assign wkup_detector_5_miodio_5_we = addr_hit[26] & reg_we & ~wr_err; assign wkup_detector_5_miodio_5_wd = reg_wdata[4]; - assign wkup_detector_6_mode_6_we = addr_hit[25] & reg_we & ~wr_err; + assign wkup_detector_6_mode_6_we = addr_hit[27] & reg_we & ~wr_err; assign wkup_detector_6_mode_6_wd = reg_wdata[2:0]; - assign wkup_detector_6_filter_6_we = addr_hit[25] & reg_we & ~wr_err; + assign wkup_detector_6_filter_6_we = addr_hit[27] & reg_we & ~wr_err; assign wkup_detector_6_filter_6_wd = reg_wdata[3]; - assign wkup_detector_6_miodio_6_we = addr_hit[25] & reg_we & ~wr_err; + assign wkup_detector_6_miodio_6_we = addr_hit[27] & reg_we & ~wr_err; assign wkup_detector_6_miodio_6_wd = reg_wdata[4]; - assign wkup_detector_7_mode_7_we = addr_hit[26] & reg_we & ~wr_err; + assign wkup_detector_7_mode_7_we = addr_hit[28] & reg_we & ~wr_err; assign wkup_detector_7_mode_7_wd = reg_wdata[2:0]; - assign wkup_detector_7_filter_7_we = addr_hit[26] & reg_we & ~wr_err; + assign wkup_detector_7_filter_7_we = addr_hit[28] & reg_we & ~wr_err; assign wkup_detector_7_filter_7_wd = reg_wdata[3]; - assign wkup_detector_7_miodio_7_we = addr_hit[26] & reg_we & ~wr_err; + assign wkup_detector_7_miodio_7_we = addr_hit[28] & reg_we & ~wr_err; assign wkup_detector_7_miodio_7_wd = reg_wdata[4]; - assign wkup_detector_cnt_th_0_th_0_we = addr_hit[27] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_0_th_0_we = addr_hit[29] & reg_we & ~wr_err; assign wkup_detector_cnt_th_0_th_0_wd = reg_wdata[7:0]; - assign wkup_detector_cnt_th_0_th_1_we = addr_hit[27] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_0_th_1_we = addr_hit[29] & reg_we & ~wr_err; assign wkup_detector_cnt_th_0_th_1_wd = reg_wdata[15:8]; - assign wkup_detector_cnt_th_0_th_2_we = addr_hit[27] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_0_th_2_we = addr_hit[29] & reg_we & ~wr_err; assign wkup_detector_cnt_th_0_th_2_wd = reg_wdata[23:16]; - assign wkup_detector_cnt_th_0_th_3_we = addr_hit[27] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_0_th_3_we = addr_hit[29] & reg_we & ~wr_err; assign wkup_detector_cnt_th_0_th_3_wd = reg_wdata[31:24]; - assign wkup_detector_cnt_th_1_th_4_we = addr_hit[28] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_1_th_4_we = addr_hit[30] & reg_we & ~wr_err; assign wkup_detector_cnt_th_1_th_4_wd = reg_wdata[7:0]; - assign wkup_detector_cnt_th_1_th_5_we = addr_hit[28] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_1_th_5_we = addr_hit[30] & reg_we & ~wr_err; assign wkup_detector_cnt_th_1_th_5_wd = reg_wdata[15:8]; - assign wkup_detector_cnt_th_1_th_6_we = addr_hit[28] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_1_th_6_we = addr_hit[30] & reg_we & ~wr_err; assign wkup_detector_cnt_th_1_th_6_wd = reg_wdata[23:16]; - assign wkup_detector_cnt_th_1_th_7_we = addr_hit[28] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_1_th_7_we = addr_hit[30] & reg_we & ~wr_err; assign wkup_detector_cnt_th_1_th_7_wd = reg_wdata[31:24]; - assign wkup_detector_padsel_0_sel_0_we = addr_hit[29] & reg_we & ~wr_err; + assign wkup_detector_padsel_0_sel_0_we = addr_hit[31] & reg_we & ~wr_err; assign wkup_detector_padsel_0_sel_0_wd = reg_wdata[4:0]; - assign wkup_detector_padsel_0_sel_1_we = addr_hit[29] & reg_we & ~wr_err; + assign wkup_detector_padsel_0_sel_1_we = addr_hit[31] & reg_we & ~wr_err; assign wkup_detector_padsel_0_sel_1_wd = reg_wdata[9:5]; - assign wkup_detector_padsel_0_sel_2_we = addr_hit[29] & reg_we & ~wr_err; + assign wkup_detector_padsel_0_sel_2_we = addr_hit[31] & reg_we & ~wr_err; assign wkup_detector_padsel_0_sel_2_wd = reg_wdata[14:10]; - assign wkup_detector_padsel_0_sel_3_we = addr_hit[29] & reg_we & ~wr_err; + assign wkup_detector_padsel_0_sel_3_we = addr_hit[31] & reg_we & ~wr_err; assign wkup_detector_padsel_0_sel_3_wd = reg_wdata[19:15]; - assign wkup_detector_padsel_0_sel_4_we = addr_hit[29] & reg_we & ~wr_err; + assign wkup_detector_padsel_0_sel_4_we = addr_hit[31] & reg_we & ~wr_err; assign wkup_detector_padsel_0_sel_4_wd = reg_wdata[24:20]; - assign wkup_detector_padsel_0_sel_5_we = addr_hit[29] & reg_we & ~wr_err; + assign wkup_detector_padsel_0_sel_5_we = addr_hit[31] & reg_we & ~wr_err; assign wkup_detector_padsel_0_sel_5_wd = reg_wdata[29:25]; - assign wkup_detector_padsel_1_sel_6_we = addr_hit[30] & reg_we & ~wr_err; + assign wkup_detector_padsel_1_sel_6_we = addr_hit[32] & reg_we & ~wr_err; assign wkup_detector_padsel_1_sel_6_wd = reg_wdata[4:0]; - assign wkup_detector_padsel_1_sel_7_we = addr_hit[30] & reg_we & ~wr_err; + assign wkup_detector_padsel_1_sel_7_we = addr_hit[32] & reg_we & ~wr_err; assign wkup_detector_padsel_1_sel_7_wd = reg_wdata[9:5]; - assign wkup_cause_cause_0_we = addr_hit[31] & reg_we & ~wr_err; + assign wkup_cause_cause_0_we = addr_hit[33] & reg_we & ~wr_err; assign wkup_cause_cause_0_wd = reg_wdata[0]; - assign wkup_cause_cause_0_re = addr_hit[31] && reg_re; + assign wkup_cause_cause_0_re = addr_hit[33] && reg_re; - assign wkup_cause_cause_1_we = addr_hit[31] & reg_we & ~wr_err; + assign wkup_cause_cause_1_we = addr_hit[33] & reg_we & ~wr_err; assign wkup_cause_cause_1_wd = reg_wdata[1]; - assign wkup_cause_cause_1_re = addr_hit[31] && reg_re; + assign wkup_cause_cause_1_re = addr_hit[33] && reg_re; - assign wkup_cause_cause_2_we = addr_hit[31] & reg_we & ~wr_err; + assign wkup_cause_cause_2_we = addr_hit[33] & reg_we & ~wr_err; assign wkup_cause_cause_2_wd = reg_wdata[2]; - assign wkup_cause_cause_2_re = addr_hit[31] && reg_re; + assign wkup_cause_cause_2_re = addr_hit[33] && reg_re; - assign wkup_cause_cause_3_we = addr_hit[31] & reg_we & ~wr_err; + assign wkup_cause_cause_3_we = addr_hit[33] & reg_we & ~wr_err; assign wkup_cause_cause_3_wd = reg_wdata[3]; - assign wkup_cause_cause_3_re = addr_hit[31] && reg_re; + assign wkup_cause_cause_3_re = addr_hit[33] && reg_re; - assign wkup_cause_cause_4_we = addr_hit[31] & reg_we & ~wr_err; + assign wkup_cause_cause_4_we = addr_hit[33] & reg_we & ~wr_err; assign wkup_cause_cause_4_wd = reg_wdata[4]; - assign wkup_cause_cause_4_re = addr_hit[31] && reg_re; + assign wkup_cause_cause_4_re = addr_hit[33] && reg_re; - assign wkup_cause_cause_5_we = addr_hit[31] & reg_we & ~wr_err; + assign wkup_cause_cause_5_we = addr_hit[33] & reg_we & ~wr_err; assign wkup_cause_cause_5_wd = reg_wdata[5]; - assign wkup_cause_cause_5_re = addr_hit[31] && reg_re; + assign wkup_cause_cause_5_re = addr_hit[33] && reg_re; - assign wkup_cause_cause_6_we = addr_hit[31] & reg_we & ~wr_err; + assign wkup_cause_cause_6_we = addr_hit[33] & reg_we & ~wr_err; assign wkup_cause_cause_6_wd = reg_wdata[6]; - assign wkup_cause_cause_6_re = addr_hit[31] && reg_re; + assign wkup_cause_cause_6_re = addr_hit[33] && reg_re; - assign wkup_cause_cause_7_we = addr_hit[31] & reg_we & ~wr_err; + assign wkup_cause_cause_7_we = addr_hit[33] & reg_we & ~wr_err; assign wkup_cause_cause_7_wd = reg_wdata[7]; - assign wkup_cause_cause_7_re = addr_hit[31] && reg_re; + assign wkup_cause_cause_7_re = addr_hit[33] && reg_re; // Read data return always_comb begin @@ -5616,6 +5816,18 @@ end addr_hit[8]: begin + reg_rdata_next[5:0] = periph_insel_7_in_35_qs; + reg_rdata_next[11:6] = periph_insel_7_in_36_qs; + reg_rdata_next[17:12] = periph_insel_7_in_37_qs; + reg_rdata_next[23:18] = periph_insel_7_in_38_qs; + reg_rdata_next[29:24] = periph_insel_7_in_39_qs; + end + + addr_hit[9]: begin + reg_rdata_next[5:0] = periph_insel_8_qs; + end + + addr_hit[10]: begin reg_rdata_next[5:0] = mio_outsel_0_out_0_qs; reg_rdata_next[11:6] = mio_outsel_0_out_1_qs; reg_rdata_next[17:12] = mio_outsel_0_out_2_qs; @@ -5623,7 +5835,7 @@ reg_rdata_next[29:24] = mio_outsel_0_out_4_qs; end - addr_hit[9]: begin + addr_hit[11]: begin reg_rdata_next[5:0] = mio_outsel_1_out_5_qs; reg_rdata_next[11:6] = mio_outsel_1_out_6_qs; reg_rdata_next[17:12] = mio_outsel_1_out_7_qs; @@ -5631,7 +5843,7 @@ reg_rdata_next[29:24] = mio_outsel_1_out_9_qs; end - addr_hit[10]: begin + addr_hit[12]: begin reg_rdata_next[5:0] = mio_outsel_2_out_10_qs; reg_rdata_next[11:6] = mio_outsel_2_out_11_qs; reg_rdata_next[17:12] = mio_outsel_2_out_12_qs; @@ -5639,7 +5851,7 @@ reg_rdata_next[29:24] = mio_outsel_2_out_14_qs; end - addr_hit[11]: begin + addr_hit[13]: begin reg_rdata_next[5:0] = mio_outsel_3_out_15_qs; reg_rdata_next[11:6] = mio_outsel_3_out_16_qs; reg_rdata_next[17:12] = mio_outsel_3_out_17_qs; @@ -5647,7 +5859,7 @@ reg_rdata_next[29:24] = mio_outsel_3_out_19_qs; end - addr_hit[12]: begin + addr_hit[14]: begin reg_rdata_next[5:0] = mio_outsel_4_out_20_qs; reg_rdata_next[11:6] = mio_outsel_4_out_21_qs; reg_rdata_next[17:12] = mio_outsel_4_out_22_qs; @@ -5655,7 +5867,7 @@ reg_rdata_next[29:24] = mio_outsel_4_out_24_qs; end - addr_hit[13]: begin + addr_hit[15]: begin reg_rdata_next[5:0] = mio_outsel_5_out_25_qs; reg_rdata_next[11:6] = mio_outsel_5_out_26_qs; reg_rdata_next[17:12] = mio_outsel_5_out_27_qs; @@ -5663,12 +5875,12 @@ reg_rdata_next[29:24] = mio_outsel_5_out_29_qs; end - addr_hit[14]: begin + addr_hit[16]: begin reg_rdata_next[5:0] = mio_outsel_6_out_30_qs; reg_rdata_next[11:6] = mio_outsel_6_out_31_qs; end - addr_hit[15]: begin + addr_hit[17]: begin reg_rdata_next[1:0] = mio_out_sleep_val_0_out_0_qs; reg_rdata_next[3:2] = mio_out_sleep_val_0_out_1_qs; reg_rdata_next[5:4] = mio_out_sleep_val_0_out_2_qs; @@ -5687,7 +5899,7 @@ reg_rdata_next[31:30] = mio_out_sleep_val_0_out_15_qs; end - addr_hit[16]: begin + addr_hit[18]: begin reg_rdata_next[1:0] = mio_out_sleep_val_1_out_16_qs; reg_rdata_next[3:2] = mio_out_sleep_val_1_out_17_qs; reg_rdata_next[5:4] = mio_out_sleep_val_1_out_18_qs; @@ -5706,7 +5918,7 @@ reg_rdata_next[31:30] = mio_out_sleep_val_1_out_31_qs; end - addr_hit[17]: begin + addr_hit[19]: begin reg_rdata_next[1:0] = dio_out_sleep_val_out_0_qs; reg_rdata_next[3:2] = dio_out_sleep_val_out_1_qs; reg_rdata_next[5:4] = dio_out_sleep_val_out_2_qs; @@ -5724,7 +5936,7 @@ reg_rdata_next[29:28] = dio_out_sleep_val_out_14_qs; end - addr_hit[18]: begin + addr_hit[20]: begin reg_rdata_next[0] = wkup_detector_en_en_0_qs; reg_rdata_next[1] = wkup_detector_en_en_1_qs; reg_rdata_next[2] = wkup_detector_en_en_2_qs; @@ -5735,69 +5947,69 @@ reg_rdata_next[7] = wkup_detector_en_en_7_qs; end - addr_hit[19]: begin + addr_hit[21]: begin reg_rdata_next[2:0] = wkup_detector_0_mode_0_qs; reg_rdata_next[3] = wkup_detector_0_filter_0_qs; reg_rdata_next[4] = wkup_detector_0_miodio_0_qs; end - addr_hit[20]: begin + addr_hit[22]: begin reg_rdata_next[2:0] = wkup_detector_1_mode_1_qs; reg_rdata_next[3] = wkup_detector_1_filter_1_qs; reg_rdata_next[4] = wkup_detector_1_miodio_1_qs; end - addr_hit[21]: begin + addr_hit[23]: begin reg_rdata_next[2:0] = wkup_detector_2_mode_2_qs; reg_rdata_next[3] = wkup_detector_2_filter_2_qs; reg_rdata_next[4] = wkup_detector_2_miodio_2_qs; end - addr_hit[22]: begin + addr_hit[24]: begin reg_rdata_next[2:0] = wkup_detector_3_mode_3_qs; reg_rdata_next[3] = wkup_detector_3_filter_3_qs; reg_rdata_next[4] = wkup_detector_3_miodio_3_qs; end - addr_hit[23]: begin + addr_hit[25]: begin reg_rdata_next[2:0] = wkup_detector_4_mode_4_qs; reg_rdata_next[3] = wkup_detector_4_filter_4_qs; reg_rdata_next[4] = wkup_detector_4_miodio_4_qs; end - addr_hit[24]: begin + addr_hit[26]: begin reg_rdata_next[2:0] = wkup_detector_5_mode_5_qs; reg_rdata_next[3] = wkup_detector_5_filter_5_qs; reg_rdata_next[4] = wkup_detector_5_miodio_5_qs; end - addr_hit[25]: begin + addr_hit[27]: begin reg_rdata_next[2:0] = wkup_detector_6_mode_6_qs; reg_rdata_next[3] = wkup_detector_6_filter_6_qs; reg_rdata_next[4] = wkup_detector_6_miodio_6_qs; end - addr_hit[26]: begin + addr_hit[28]: begin reg_rdata_next[2:0] = wkup_detector_7_mode_7_qs; reg_rdata_next[3] = wkup_detector_7_filter_7_qs; reg_rdata_next[4] = wkup_detector_7_miodio_7_qs; end - addr_hit[27]: begin + addr_hit[29]: begin reg_rdata_next[7:0] = wkup_detector_cnt_th_0_th_0_qs; reg_rdata_next[15:8] = wkup_detector_cnt_th_0_th_1_qs; reg_rdata_next[23:16] = wkup_detector_cnt_th_0_th_2_qs; reg_rdata_next[31:24] = wkup_detector_cnt_th_0_th_3_qs; end - addr_hit[28]: begin + addr_hit[30]: begin reg_rdata_next[7:0] = wkup_detector_cnt_th_1_th_4_qs; reg_rdata_next[15:8] = wkup_detector_cnt_th_1_th_5_qs; reg_rdata_next[23:16] = wkup_detector_cnt_th_1_th_6_qs; reg_rdata_next[31:24] = wkup_detector_cnt_th_1_th_7_qs; end - addr_hit[29]: begin + addr_hit[31]: begin reg_rdata_next[4:0] = wkup_detector_padsel_0_sel_0_qs; reg_rdata_next[9:5] = wkup_detector_padsel_0_sel_1_qs; reg_rdata_next[14:10] = wkup_detector_padsel_0_sel_2_qs; @@ -5806,12 +6018,12 @@ reg_rdata_next[29:25] = wkup_detector_padsel_0_sel_5_qs; end - addr_hit[30]: begin + addr_hit[32]: begin reg_rdata_next[4:0] = wkup_detector_padsel_1_sel_6_qs; reg_rdata_next[9:5] = wkup_detector_padsel_1_sel_7_qs; end - addr_hit[31]: begin + addr_hit[33]: begin reg_rdata_next[0] = wkup_cause_cause_0_qs; reg_rdata_next[1] = wkup_cause_cause_1_qs; reg_rdata_next[2] = wkup_cause_cause_2_qs;
diff --git a/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson b/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson index 68d0689..2e9c95d 100644 --- a/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson +++ b/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson
@@ -52,7 +52,7 @@ { name: "NumSwResets", desc: "Number of software resets", type: "int", - default: "2", + default: "5", local: "true" },
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv index c8975d3..ccf41e4 100644 --- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv +++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
@@ -529,6 +529,78 @@ .clk_o(resets_o.rst_usb_n[Domain0Sel]) ); + logic [PowerDomains-1:0] rst_i2c0_n; + assign rst_i2c0_n[DomainAonSel] = 1'b0; + assign resets_o.rst_i2c0_n[DomainAonSel] = rst_i2c0_n[DomainAonSel]; + + + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_0_i2c0 ( + .clk_i(clk_io_div2_i), + .rst_ni(rst_sys_src_n[Domain0Sel]), + .d_i(sw_rst_ctrl_n[I2C0]), + .q_o(rst_i2c0_n[Domain0Sel]) + ); + + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_0_i2c0_mux ( + .clk0_i(rst_i2c0_n[Domain0Sel]), + .clk1_i(scan_rst_ni), + .sel_i(scanmode_i), + .clk_o(resets_o.rst_i2c0_n[Domain0Sel]) + ); + + logic [PowerDomains-1:0] rst_i2c1_n; + assign rst_i2c1_n[DomainAonSel] = 1'b0; + assign resets_o.rst_i2c1_n[DomainAonSel] = rst_i2c1_n[DomainAonSel]; + + + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_0_i2c1 ( + .clk_i(clk_io_div2_i), + .rst_ni(rst_sys_src_n[Domain0Sel]), + .d_i(sw_rst_ctrl_n[I2C1]), + .q_o(rst_i2c1_n[Domain0Sel]) + ); + + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_0_i2c1_mux ( + .clk0_i(rst_i2c1_n[Domain0Sel]), + .clk1_i(scan_rst_ni), + .sel_i(scanmode_i), + .clk_o(resets_o.rst_i2c1_n[Domain0Sel]) + ); + + logic [PowerDomains-1:0] rst_i2c2_n; + assign rst_i2c2_n[DomainAonSel] = 1'b0; + assign resets_o.rst_i2c2_n[DomainAonSel] = rst_i2c2_n[DomainAonSel]; + + + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_0_i2c2 ( + .clk_i(clk_io_div2_i), + .rst_ni(rst_sys_src_n[Domain0Sel]), + .d_i(sw_rst_ctrl_n[I2C2]), + .q_o(rst_i2c2_n[Domain0Sel]) + ); + + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_0_i2c2_mux ( + .clk0_i(rst_i2c2_n[Domain0Sel]), + .clk1_i(scan_rst_ni), + .sel_i(scanmode_i), + .clk_o(resets_o.rst_i2c2_n[Domain0Sel]) + ); + //////////////////////////////////////////////////// // Reset info construction //
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv index cdead59..b4419c9 100644 --- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv +++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
@@ -25,6 +25,9 @@ // positions of software controllable reset bits parameter int SPI_DEVICE = 0; parameter int USB = 1; + parameter int I2C0 = 2; + parameter int I2C1 = 3; + parameter int I2C2 = 4; // ast interface typedef struct packed { @@ -52,6 +55,9 @@ logic [PowerDomains-1:0] rst_sys_aon_n; logic [PowerDomains-1:0] rst_spi_device_n; logic [PowerDomains-1:0] rst_usb_n; + logic [PowerDomains-1:0] rst_i2c0_n; + logic [PowerDomains-1:0] rst_i2c1_n; + logic [PowerDomains-1:0] rst_i2c2_n; } rstmgr_out_t; // cpu reset requests and status
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_pkg.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_pkg.sv index e862b29..448a202 100644 --- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_pkg.sv +++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_pkg.sv
@@ -10,7 +10,7 @@ parameter int RdWidth = 32; parameter int IdxWidth = 4; parameter int NumHwResets = 2; - parameter int NumSwResets = 2; + parameter int NumSwResets = 5; // Address width within the block parameter int BlockAw = 6; @@ -106,25 +106,25 @@ // Register to internal design logic // /////////////////////////////////////// typedef struct packed { - rstmgr_reg2hw_reset_info_reg_t reset_info; // [17:16] - rstmgr_reg2hw_alert_info_ctrl_reg_t alert_info_ctrl; // [15:11] - rstmgr_reg2hw_cpu_info_ctrl_reg_t cpu_info_ctrl; // [10:6] - rstmgr_reg2hw_sw_rst_regen_mreg_t [1:0] sw_rst_regen; // [5:4] - rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t [1:0] sw_rst_ctrl_n; // [3:0] + rstmgr_reg2hw_reset_info_reg_t reset_info; // [26:25] + rstmgr_reg2hw_alert_info_ctrl_reg_t alert_info_ctrl; // [24:20] + rstmgr_reg2hw_cpu_info_ctrl_reg_t cpu_info_ctrl; // [19:15] + rstmgr_reg2hw_sw_rst_regen_mreg_t [4:0] sw_rst_regen; // [14:10] + rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t [4:0] sw_rst_ctrl_n; // [9:0] } rstmgr_reg2hw_t; /////////////////////////////////////// // Internal design logic to register // /////////////////////////////////////// typedef struct packed { - rstmgr_hw2reg_reset_info_reg_t reset_info; // [84:78] - rstmgr_hw2reg_alert_info_ctrl_reg_t alert_info_ctrl; // [77:76] - rstmgr_hw2reg_alert_info_attr_reg_t alert_info_attr; // [75:72] - rstmgr_hw2reg_alert_info_reg_t alert_info; // [71:40] - rstmgr_hw2reg_cpu_info_ctrl_reg_t cpu_info_ctrl; // [39:38] - rstmgr_hw2reg_cpu_info_attr_reg_t cpu_info_attr; // [37:34] - rstmgr_hw2reg_cpu_info_reg_t cpu_info; // [33:2] - rstmgr_hw2reg_sw_rst_ctrl_n_mreg_t [1:0] sw_rst_ctrl_n; // [1:0] + rstmgr_hw2reg_reset_info_reg_t reset_info; // [87:81] + rstmgr_hw2reg_alert_info_ctrl_reg_t alert_info_ctrl; // [80:79] + rstmgr_hw2reg_alert_info_attr_reg_t alert_info_attr; // [78:75] + rstmgr_hw2reg_alert_info_reg_t alert_info; // [74:43] + rstmgr_hw2reg_cpu_info_ctrl_reg_t cpu_info_ctrl; // [42:41] + rstmgr_hw2reg_cpu_info_attr_reg_t cpu_info_attr; // [40:37] + rstmgr_hw2reg_cpu_info_reg_t cpu_info; // [36:5] + rstmgr_hw2reg_sw_rst_ctrl_n_mreg_t [4:0] sw_rst_ctrl_n; // [4:0] } rstmgr_hw2reg_t; // Register Address
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv index e9e673d..4727b20 100644 --- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv +++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv
@@ -109,6 +109,15 @@ logic sw_rst_regen_en_1_qs; logic sw_rst_regen_en_1_wd; logic sw_rst_regen_en_1_we; + logic sw_rst_regen_en_2_qs; + logic sw_rst_regen_en_2_wd; + logic sw_rst_regen_en_2_we; + logic sw_rst_regen_en_3_qs; + logic sw_rst_regen_en_3_wd; + logic sw_rst_regen_en_3_we; + logic sw_rst_regen_en_4_qs; + logic sw_rst_regen_en_4_wd; + logic sw_rst_regen_en_4_we; logic sw_rst_ctrl_n_val_0_qs; logic sw_rst_ctrl_n_val_0_wd; logic sw_rst_ctrl_n_val_0_we; @@ -117,6 +126,18 @@ logic sw_rst_ctrl_n_val_1_wd; logic sw_rst_ctrl_n_val_1_we; logic sw_rst_ctrl_n_val_1_re; + logic sw_rst_ctrl_n_val_2_qs; + logic sw_rst_ctrl_n_val_2_wd; + logic sw_rst_ctrl_n_val_2_we; + logic sw_rst_ctrl_n_val_2_re; + logic sw_rst_ctrl_n_val_3_qs; + logic sw_rst_ctrl_n_val_3_wd; + logic sw_rst_ctrl_n_val_3_we; + logic sw_rst_ctrl_n_val_3_re; + logic sw_rst_ctrl_n_val_4_qs; + logic sw_rst_ctrl_n_val_4_wd; + logic sw_rst_ctrl_n_val_4_we; + logic sw_rst_ctrl_n_val_4_re; // Register instances // R[reset_info]: V(False) @@ -453,6 +474,84 @@ ); + // F[en_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_sw_rst_regen_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (sw_rst_regen_en_2_we), + .wd (sw_rst_regen_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.sw_rst_regen[2].q ), + + // to register interface (read) + .qs (sw_rst_regen_en_2_qs) + ); + + + // F[en_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_sw_rst_regen_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (sw_rst_regen_en_3_we), + .wd (sw_rst_regen_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.sw_rst_regen[3].q ), + + // to register interface (read) + .qs (sw_rst_regen_en_3_qs) + ); + + + // F[en_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_sw_rst_regen_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (sw_rst_regen_en_4_we), + .wd (sw_rst_regen_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.sw_rst_regen[4].q ), + + // to register interface (read) + .qs (sw_rst_regen_en_4_qs) + ); + + // Subregister 0 of Multireg sw_rst_ctrl_n @@ -488,6 +587,51 @@ ); + // F[val_2]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_sw_rst_ctrl_n_val_2 ( + .re (sw_rst_ctrl_n_val_2_re), + .we (sw_rst_ctrl_n_val_2_we), + .wd (sw_rst_ctrl_n_val_2_wd), + .d (hw2reg.sw_rst_ctrl_n[2].d), + .qre (), + .qe (reg2hw.sw_rst_ctrl_n[2].qe), + .q (reg2hw.sw_rst_ctrl_n[2].q ), + .qs (sw_rst_ctrl_n_val_2_qs) + ); + + + // F[val_3]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_sw_rst_ctrl_n_val_3 ( + .re (sw_rst_ctrl_n_val_3_re), + .we (sw_rst_ctrl_n_val_3_we), + .wd (sw_rst_ctrl_n_val_3_wd), + .d (hw2reg.sw_rst_ctrl_n[3].d), + .qre (), + .qe (reg2hw.sw_rst_ctrl_n[3].qe), + .q (reg2hw.sw_rst_ctrl_n[3].q ), + .qs (sw_rst_ctrl_n_val_3_qs) + ); + + + // F[val_4]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_sw_rst_ctrl_n_val_4 ( + .re (sw_rst_ctrl_n_val_4_re), + .we (sw_rst_ctrl_n_val_4_we), + .wd (sw_rst_ctrl_n_val_4_wd), + .d (hw2reg.sw_rst_ctrl_n[4].d), + .qre (), + .qe (reg2hw.sw_rst_ctrl_n[4].qe), + .q (reg2hw.sw_rst_ctrl_n[4].q ), + .qs (sw_rst_ctrl_n_val_4_qs) + ); + + @@ -559,6 +703,15 @@ assign sw_rst_regen_en_1_we = addr_hit[7] & reg_we & ~wr_err; assign sw_rst_regen_en_1_wd = reg_wdata[1]; + assign sw_rst_regen_en_2_we = addr_hit[7] & reg_we & ~wr_err; + assign sw_rst_regen_en_2_wd = reg_wdata[2]; + + assign sw_rst_regen_en_3_we = addr_hit[7] & reg_we & ~wr_err; + assign sw_rst_regen_en_3_wd = reg_wdata[3]; + + assign sw_rst_regen_en_4_we = addr_hit[7] & reg_we & ~wr_err; + assign sw_rst_regen_en_4_wd = reg_wdata[4]; + assign sw_rst_ctrl_n_val_0_we = addr_hit[8] & reg_we & ~wr_err; assign sw_rst_ctrl_n_val_0_wd = reg_wdata[0]; assign sw_rst_ctrl_n_val_0_re = addr_hit[8] && reg_re; @@ -567,6 +720,18 @@ assign sw_rst_ctrl_n_val_1_wd = reg_wdata[1]; assign sw_rst_ctrl_n_val_1_re = addr_hit[8] && reg_re; + assign sw_rst_ctrl_n_val_2_we = addr_hit[8] & reg_we & ~wr_err; + assign sw_rst_ctrl_n_val_2_wd = reg_wdata[2]; + assign sw_rst_ctrl_n_val_2_re = addr_hit[8] && reg_re; + + assign sw_rst_ctrl_n_val_3_we = addr_hit[8] & reg_we & ~wr_err; + assign sw_rst_ctrl_n_val_3_wd = reg_wdata[3]; + assign sw_rst_ctrl_n_val_3_re = addr_hit[8] && reg_re; + + assign sw_rst_ctrl_n_val_4_we = addr_hit[8] & reg_we & ~wr_err; + assign sw_rst_ctrl_n_val_4_wd = reg_wdata[4]; + assign sw_rst_ctrl_n_val_4_re = addr_hit[8] && reg_re; + // Read data return always_comb begin reg_rdata_next = '0; @@ -607,11 +772,17 @@ addr_hit[7]: begin reg_rdata_next[0] = sw_rst_regen_en_0_qs; reg_rdata_next[1] = sw_rst_regen_en_1_qs; + reg_rdata_next[2] = sw_rst_regen_en_2_qs; + reg_rdata_next[3] = sw_rst_regen_en_3_qs; + reg_rdata_next[4] = sw_rst_regen_en_4_qs; end addr_hit[8]: begin reg_rdata_next[0] = sw_rst_ctrl_n_val_0_qs; reg_rdata_next[1] = sw_rst_ctrl_n_val_1_qs; + reg_rdata_next[2] = sw_rst_ctrl_n_val_2_qs; + reg_rdata_next[3] = sw_rst_ctrl_n_val_3_qs; + reg_rdata_next[4] = sw_rst_ctrl_n_val_4_qs; end default: begin
diff --git a/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson b/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson index 5e786a5..c6ffa31 100644 --- a/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson +++ b/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson
@@ -25,7 +25,7 @@ { name: "NumSrc", desc: "Number of interrupt sources", type: "int", - default: "122", + default: "172", local: "true" }, { name: "NumTarget", @@ -1045,6 +1045,406 @@ { bits: "1:0" } ], } + { name: "PRIO122", + desc: "Interrupt Source 122 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO123", + desc: "Interrupt Source 123 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO124", + desc: "Interrupt Source 124 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO125", + desc: "Interrupt Source 125 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO126", + desc: "Interrupt Source 126 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO127", + desc: "Interrupt Source 127 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO128", + desc: "Interrupt Source 128 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO129", + desc: "Interrupt Source 129 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO130", + desc: "Interrupt Source 130 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO131", + desc: "Interrupt Source 131 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO132", + desc: "Interrupt Source 132 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO133", + desc: "Interrupt Source 133 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO134", + desc: "Interrupt Source 134 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO135", + desc: "Interrupt Source 135 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO136", + desc: "Interrupt Source 136 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO137", + desc: "Interrupt Source 137 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO138", + desc: "Interrupt Source 138 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO139", + desc: "Interrupt Source 139 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO140", + desc: "Interrupt Source 140 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO141", + desc: "Interrupt Source 141 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO142", + desc: "Interrupt Source 142 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO143", + desc: "Interrupt Source 143 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO144", + desc: "Interrupt Source 144 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO145", + desc: "Interrupt Source 145 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO146", + desc: "Interrupt Source 146 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO147", + desc: "Interrupt Source 147 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO148", + desc: "Interrupt Source 148 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO149", + desc: "Interrupt Source 149 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO150", + desc: "Interrupt Source 150 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO151", + desc: "Interrupt Source 151 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO152", + desc: "Interrupt Source 152 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO153", + desc: "Interrupt Source 153 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO154", + desc: "Interrupt Source 154 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO155", + desc: "Interrupt Source 155 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO156", + desc: "Interrupt Source 156 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO157", + desc: "Interrupt Source 157 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO158", + desc: "Interrupt Source 158 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO159", + desc: "Interrupt Source 159 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO160", + desc: "Interrupt Source 160 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO161", + desc: "Interrupt Source 161 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO162", + desc: "Interrupt Source 162 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO163", + desc: "Interrupt Source 163 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO164", + desc: "Interrupt Source 164 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO165", + desc: "Interrupt Source 165 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO166", + desc: "Interrupt Source 166 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO167", + desc: "Interrupt Source 167 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO168", + desc: "Interrupt Source 168 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO169", + desc: "Interrupt Source 169 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO170", + desc: "Interrupt Source 170 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO171", + desc: "Interrupt Source 171 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } { skipto: "768" } { multireg: { name: "IE0", @@ -1075,7 +1475,7 @@ hwqe: "true", hwre: "true", fields: [ - { bits: "6:0" } + { bits: "7:0" } ], tags: [// CC register value is related to IP "excl:CsrNonInitTests:CsrExclCheck"],
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv index db7b0a9..aa6ba09 100644 --- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv +++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
@@ -216,11 +216,61 @@ assign prio[119] = reg2hw.prio119.q; assign prio[120] = reg2hw.prio120.q; assign prio[121] = reg2hw.prio121.q; + assign prio[122] = reg2hw.prio122.q; + assign prio[123] = reg2hw.prio123.q; + assign prio[124] = reg2hw.prio124.q; + assign prio[125] = reg2hw.prio125.q; + assign prio[126] = reg2hw.prio126.q; + assign prio[127] = reg2hw.prio127.q; + assign prio[128] = reg2hw.prio128.q; + assign prio[129] = reg2hw.prio129.q; + assign prio[130] = reg2hw.prio130.q; + assign prio[131] = reg2hw.prio131.q; + assign prio[132] = reg2hw.prio132.q; + assign prio[133] = reg2hw.prio133.q; + assign prio[134] = reg2hw.prio134.q; + assign prio[135] = reg2hw.prio135.q; + assign prio[136] = reg2hw.prio136.q; + assign prio[137] = reg2hw.prio137.q; + assign prio[138] = reg2hw.prio138.q; + assign prio[139] = reg2hw.prio139.q; + assign prio[140] = reg2hw.prio140.q; + assign prio[141] = reg2hw.prio141.q; + assign prio[142] = reg2hw.prio142.q; + assign prio[143] = reg2hw.prio143.q; + assign prio[144] = reg2hw.prio144.q; + assign prio[145] = reg2hw.prio145.q; + assign prio[146] = reg2hw.prio146.q; + assign prio[147] = reg2hw.prio147.q; + assign prio[148] = reg2hw.prio148.q; + assign prio[149] = reg2hw.prio149.q; + assign prio[150] = reg2hw.prio150.q; + assign prio[151] = reg2hw.prio151.q; + assign prio[152] = reg2hw.prio152.q; + assign prio[153] = reg2hw.prio153.q; + assign prio[154] = reg2hw.prio154.q; + assign prio[155] = reg2hw.prio155.q; + assign prio[156] = reg2hw.prio156.q; + assign prio[157] = reg2hw.prio157.q; + assign prio[158] = reg2hw.prio158.q; + assign prio[159] = reg2hw.prio159.q; + assign prio[160] = reg2hw.prio160.q; + assign prio[161] = reg2hw.prio161.q; + assign prio[162] = reg2hw.prio162.q; + assign prio[163] = reg2hw.prio163.q; + assign prio[164] = reg2hw.prio164.q; + assign prio[165] = reg2hw.prio165.q; + assign prio[166] = reg2hw.prio166.q; + assign prio[167] = reg2hw.prio167.q; + assign prio[168] = reg2hw.prio168.q; + assign prio[169] = reg2hw.prio169.q; + assign prio[170] = reg2hw.prio170.q; + assign prio[171] = reg2hw.prio171.q; ////////////////////// // Interrupt Enable // ////////////////////// - for (genvar s = 0; s < 122; s++) begin : gen_ie0 + for (genvar s = 0; s < 172; s++) begin : gen_ie0 assign ie[0][s] = reg2hw.ie0[s].q; end @@ -246,7 +296,7 @@ //////// // IP // //////// - for (genvar s = 0; s < 122; s++) begin : gen_ip + for (genvar s = 0; s < 172; s++) begin : gen_ip assign hw2reg.ip[s].de = 1'b1; // Always write assign hw2reg.ip[s].d = ip[s]; end @@ -254,7 +304,7 @@ /////////////////////////////////// // Detection:: 0: Level, 1: Edge // /////////////////////////////////// - for (genvar s = 0; s < 122; s++) begin : gen_le + for (genvar s = 0; s < 172; s++) begin : gen_le assign le[s] = reg2hw.le[s].q; end
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv index 9093fa7..ea540b3 100644 --- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv +++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
@@ -7,7 +7,7 @@ package rv_plic_reg_pkg; // Param list - parameter int NumSrc = 122; + parameter int NumSrc = 172; parameter int NumTarget = 1; parameter int PrioWidth = 2; @@ -510,6 +510,206 @@ } rv_plic_reg2hw_prio121_reg_t; typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio122_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio123_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio124_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio125_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio126_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio127_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio128_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio129_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio130_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio131_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio132_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio133_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio134_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio135_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio136_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio137_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio138_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio139_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio140_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio141_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio142_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio143_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio144_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio145_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio146_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio147_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio148_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio149_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio150_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio151_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio152_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio153_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio154_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio155_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio156_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio157_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio158_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio159_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio160_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio161_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio162_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio163_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio164_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio165_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio166_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio167_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio168_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio169_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio170_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio171_reg_t; + + typedef struct packed { logic q; } rv_plic_reg2hw_ie0_mreg_t; @@ -518,7 +718,7 @@ } rv_plic_reg2hw_threshold0_reg_t; typedef struct packed { - logic [6:0] q; + logic [7:0] q; logic qe; logic re; } rv_plic_reg2hw_cc0_reg_t; @@ -534,7 +734,7 @@ } rv_plic_hw2reg_ip_mreg_t; typedef struct packed { - logic [6:0] d; + logic [7:0] d; } rv_plic_hw2reg_cc0_reg_t; @@ -542,132 +742,182 @@ // Register to internal design logic // /////////////////////////////////////// typedef struct packed { - rv_plic_reg2hw_le_mreg_t [121:0] le; // [499:378] - rv_plic_reg2hw_prio0_reg_t prio0; // [377:376] - rv_plic_reg2hw_prio1_reg_t prio1; // [375:374] - rv_plic_reg2hw_prio2_reg_t prio2; // [373:372] - rv_plic_reg2hw_prio3_reg_t prio3; // [371:370] - rv_plic_reg2hw_prio4_reg_t prio4; // [369:368] - rv_plic_reg2hw_prio5_reg_t prio5; // [367:366] - rv_plic_reg2hw_prio6_reg_t prio6; // [365:364] - rv_plic_reg2hw_prio7_reg_t prio7; // [363:362] - rv_plic_reg2hw_prio8_reg_t prio8; // [361:360] - rv_plic_reg2hw_prio9_reg_t prio9; // [359:358] - rv_plic_reg2hw_prio10_reg_t prio10; // [357:356] - rv_plic_reg2hw_prio11_reg_t prio11; // [355:354] - rv_plic_reg2hw_prio12_reg_t prio12; // [353:352] - rv_plic_reg2hw_prio13_reg_t prio13; // [351:350] - rv_plic_reg2hw_prio14_reg_t prio14; // [349:348] - rv_plic_reg2hw_prio15_reg_t prio15; // [347:346] - rv_plic_reg2hw_prio16_reg_t prio16; // [345:344] - rv_plic_reg2hw_prio17_reg_t prio17; // [343:342] - rv_plic_reg2hw_prio18_reg_t prio18; // [341:340] - rv_plic_reg2hw_prio19_reg_t prio19; // [339:338] - rv_plic_reg2hw_prio20_reg_t prio20; // [337:336] - rv_plic_reg2hw_prio21_reg_t prio21; // [335:334] - rv_plic_reg2hw_prio22_reg_t prio22; // [333:332] - rv_plic_reg2hw_prio23_reg_t prio23; // [331:330] - rv_plic_reg2hw_prio24_reg_t prio24; // [329:328] - rv_plic_reg2hw_prio25_reg_t prio25; // [327:326] - rv_plic_reg2hw_prio26_reg_t prio26; // [325:324] - rv_plic_reg2hw_prio27_reg_t prio27; // [323:322] - rv_plic_reg2hw_prio28_reg_t prio28; // [321:320] - rv_plic_reg2hw_prio29_reg_t prio29; // [319:318] - rv_plic_reg2hw_prio30_reg_t prio30; // [317:316] - rv_plic_reg2hw_prio31_reg_t prio31; // [315:314] - rv_plic_reg2hw_prio32_reg_t prio32; // [313:312] - rv_plic_reg2hw_prio33_reg_t prio33; // [311:310] - rv_plic_reg2hw_prio34_reg_t prio34; // [309:308] - rv_plic_reg2hw_prio35_reg_t prio35; // [307:306] - rv_plic_reg2hw_prio36_reg_t prio36; // [305:304] - rv_plic_reg2hw_prio37_reg_t prio37; // [303:302] - rv_plic_reg2hw_prio38_reg_t prio38; // [301:300] - rv_plic_reg2hw_prio39_reg_t prio39; // [299:298] - rv_plic_reg2hw_prio40_reg_t prio40; // [297:296] - rv_plic_reg2hw_prio41_reg_t prio41; // [295:294] - rv_plic_reg2hw_prio42_reg_t prio42; // [293:292] - rv_plic_reg2hw_prio43_reg_t prio43; // [291:290] - rv_plic_reg2hw_prio44_reg_t prio44; // [289:288] - rv_plic_reg2hw_prio45_reg_t prio45; // [287:286] - rv_plic_reg2hw_prio46_reg_t prio46; // [285:284] - rv_plic_reg2hw_prio47_reg_t prio47; // [283:282] - rv_plic_reg2hw_prio48_reg_t prio48; // [281:280] - rv_plic_reg2hw_prio49_reg_t prio49; // [279:278] - rv_plic_reg2hw_prio50_reg_t prio50; // [277:276] - rv_plic_reg2hw_prio51_reg_t prio51; // [275:274] - rv_plic_reg2hw_prio52_reg_t prio52; // [273:272] - rv_plic_reg2hw_prio53_reg_t prio53; // [271:270] - rv_plic_reg2hw_prio54_reg_t prio54; // [269:268] - rv_plic_reg2hw_prio55_reg_t prio55; // [267:266] - rv_plic_reg2hw_prio56_reg_t prio56; // [265:264] - rv_plic_reg2hw_prio57_reg_t prio57; // [263:262] - rv_plic_reg2hw_prio58_reg_t prio58; // [261:260] - rv_plic_reg2hw_prio59_reg_t prio59; // [259:258] - rv_plic_reg2hw_prio60_reg_t prio60; // [257:256] - rv_plic_reg2hw_prio61_reg_t prio61; // [255:254] - rv_plic_reg2hw_prio62_reg_t prio62; // [253:252] - rv_plic_reg2hw_prio63_reg_t prio63; // [251:250] - rv_plic_reg2hw_prio64_reg_t prio64; // [249:248] - rv_plic_reg2hw_prio65_reg_t prio65; // [247:246] - rv_plic_reg2hw_prio66_reg_t prio66; // [245:244] - rv_plic_reg2hw_prio67_reg_t prio67; // [243:242] - rv_plic_reg2hw_prio68_reg_t prio68; // [241:240] - rv_plic_reg2hw_prio69_reg_t prio69; // [239:238] - rv_plic_reg2hw_prio70_reg_t prio70; // [237:236] - rv_plic_reg2hw_prio71_reg_t prio71; // [235:234] - rv_plic_reg2hw_prio72_reg_t prio72; // [233:232] - rv_plic_reg2hw_prio73_reg_t prio73; // [231:230] - rv_plic_reg2hw_prio74_reg_t prio74; // [229:228] - rv_plic_reg2hw_prio75_reg_t prio75; // [227:226] - rv_plic_reg2hw_prio76_reg_t prio76; // [225:224] - rv_plic_reg2hw_prio77_reg_t prio77; // [223:222] - rv_plic_reg2hw_prio78_reg_t prio78; // [221:220] - rv_plic_reg2hw_prio79_reg_t prio79; // [219:218] - rv_plic_reg2hw_prio80_reg_t prio80; // [217:216] - rv_plic_reg2hw_prio81_reg_t prio81; // [215:214] - rv_plic_reg2hw_prio82_reg_t prio82; // [213:212] - rv_plic_reg2hw_prio83_reg_t prio83; // [211:210] - rv_plic_reg2hw_prio84_reg_t prio84; // [209:208] - rv_plic_reg2hw_prio85_reg_t prio85; // [207:206] - rv_plic_reg2hw_prio86_reg_t prio86; // [205:204] - rv_plic_reg2hw_prio87_reg_t prio87; // [203:202] - rv_plic_reg2hw_prio88_reg_t prio88; // [201:200] - rv_plic_reg2hw_prio89_reg_t prio89; // [199:198] - rv_plic_reg2hw_prio90_reg_t prio90; // [197:196] - rv_plic_reg2hw_prio91_reg_t prio91; // [195:194] - rv_plic_reg2hw_prio92_reg_t prio92; // [193:192] - rv_plic_reg2hw_prio93_reg_t prio93; // [191:190] - rv_plic_reg2hw_prio94_reg_t prio94; // [189:188] - rv_plic_reg2hw_prio95_reg_t prio95; // [187:186] - rv_plic_reg2hw_prio96_reg_t prio96; // [185:184] - rv_plic_reg2hw_prio97_reg_t prio97; // [183:182] - rv_plic_reg2hw_prio98_reg_t prio98; // [181:180] - rv_plic_reg2hw_prio99_reg_t prio99; // [179:178] - rv_plic_reg2hw_prio100_reg_t prio100; // [177:176] - rv_plic_reg2hw_prio101_reg_t prio101; // [175:174] - rv_plic_reg2hw_prio102_reg_t prio102; // [173:172] - rv_plic_reg2hw_prio103_reg_t prio103; // [171:170] - rv_plic_reg2hw_prio104_reg_t prio104; // [169:168] - rv_plic_reg2hw_prio105_reg_t prio105; // [167:166] - rv_plic_reg2hw_prio106_reg_t prio106; // [165:164] - rv_plic_reg2hw_prio107_reg_t prio107; // [163:162] - rv_plic_reg2hw_prio108_reg_t prio108; // [161:160] - rv_plic_reg2hw_prio109_reg_t prio109; // [159:158] - rv_plic_reg2hw_prio110_reg_t prio110; // [157:156] - rv_plic_reg2hw_prio111_reg_t prio111; // [155:154] - rv_plic_reg2hw_prio112_reg_t prio112; // [153:152] - rv_plic_reg2hw_prio113_reg_t prio113; // [151:150] - rv_plic_reg2hw_prio114_reg_t prio114; // [149:148] - rv_plic_reg2hw_prio115_reg_t prio115; // [147:146] - rv_plic_reg2hw_prio116_reg_t prio116; // [145:144] - rv_plic_reg2hw_prio117_reg_t prio117; // [143:142] - rv_plic_reg2hw_prio118_reg_t prio118; // [141:140] - rv_plic_reg2hw_prio119_reg_t prio119; // [139:138] - rv_plic_reg2hw_prio120_reg_t prio120; // [137:136] - rv_plic_reg2hw_prio121_reg_t prio121; // [135:134] - rv_plic_reg2hw_ie0_mreg_t [121:0] ie0; // [133:12] - rv_plic_reg2hw_threshold0_reg_t threshold0; // [11:10] - rv_plic_reg2hw_cc0_reg_t cc0; // [9:1] + rv_plic_reg2hw_le_mreg_t [171:0] le; // [700:529] + rv_plic_reg2hw_prio0_reg_t prio0; // [528:527] + rv_plic_reg2hw_prio1_reg_t prio1; // [526:525] + rv_plic_reg2hw_prio2_reg_t prio2; // [524:523] + rv_plic_reg2hw_prio3_reg_t prio3; // [522:521] + rv_plic_reg2hw_prio4_reg_t prio4; // [520:519] + rv_plic_reg2hw_prio5_reg_t prio5; // [518:517] + rv_plic_reg2hw_prio6_reg_t prio6; // [516:515] + rv_plic_reg2hw_prio7_reg_t prio7; // [514:513] + rv_plic_reg2hw_prio8_reg_t prio8; // [512:511] + rv_plic_reg2hw_prio9_reg_t prio9; // [510:509] + rv_plic_reg2hw_prio10_reg_t prio10; // [508:507] + rv_plic_reg2hw_prio11_reg_t prio11; // [506:505] + rv_plic_reg2hw_prio12_reg_t prio12; // [504:503] + rv_plic_reg2hw_prio13_reg_t prio13; // [502:501] + rv_plic_reg2hw_prio14_reg_t prio14; // [500:499] + rv_plic_reg2hw_prio15_reg_t prio15; // [498:497] + rv_plic_reg2hw_prio16_reg_t prio16; // [496:495] + rv_plic_reg2hw_prio17_reg_t prio17; // [494:493] + rv_plic_reg2hw_prio18_reg_t prio18; // [492:491] + rv_plic_reg2hw_prio19_reg_t prio19; // [490:489] + rv_plic_reg2hw_prio20_reg_t prio20; // [488:487] + rv_plic_reg2hw_prio21_reg_t prio21; // [486:485] + rv_plic_reg2hw_prio22_reg_t prio22; // [484:483] + rv_plic_reg2hw_prio23_reg_t prio23; // [482:481] + rv_plic_reg2hw_prio24_reg_t prio24; // [480:479] + rv_plic_reg2hw_prio25_reg_t prio25; // [478:477] + rv_plic_reg2hw_prio26_reg_t prio26; // [476:475] + rv_plic_reg2hw_prio27_reg_t prio27; // [474:473] + rv_plic_reg2hw_prio28_reg_t prio28; // [472:471] + rv_plic_reg2hw_prio29_reg_t prio29; // [470:469] + rv_plic_reg2hw_prio30_reg_t prio30; // [468:467] + rv_plic_reg2hw_prio31_reg_t prio31; // [466:465] + rv_plic_reg2hw_prio32_reg_t prio32; // [464:463] + rv_plic_reg2hw_prio33_reg_t prio33; // [462:461] + rv_plic_reg2hw_prio34_reg_t prio34; // [460:459] + rv_plic_reg2hw_prio35_reg_t prio35; // [458:457] + rv_plic_reg2hw_prio36_reg_t prio36; // [456:455] + rv_plic_reg2hw_prio37_reg_t prio37; // [454:453] + rv_plic_reg2hw_prio38_reg_t prio38; // [452:451] + rv_plic_reg2hw_prio39_reg_t prio39; // [450:449] + rv_plic_reg2hw_prio40_reg_t prio40; // [448:447] + rv_plic_reg2hw_prio41_reg_t prio41; // [446:445] + rv_plic_reg2hw_prio42_reg_t prio42; // [444:443] + rv_plic_reg2hw_prio43_reg_t prio43; // [442:441] + rv_plic_reg2hw_prio44_reg_t prio44; // [440:439] + rv_plic_reg2hw_prio45_reg_t prio45; // [438:437] + rv_plic_reg2hw_prio46_reg_t prio46; // [436:435] + rv_plic_reg2hw_prio47_reg_t prio47; // [434:433] + rv_plic_reg2hw_prio48_reg_t prio48; // [432:431] + rv_plic_reg2hw_prio49_reg_t prio49; // [430:429] + rv_plic_reg2hw_prio50_reg_t prio50; // [428:427] + rv_plic_reg2hw_prio51_reg_t prio51; // [426:425] + rv_plic_reg2hw_prio52_reg_t prio52; // [424:423] + rv_plic_reg2hw_prio53_reg_t prio53; // [422:421] + rv_plic_reg2hw_prio54_reg_t prio54; // [420:419] + rv_plic_reg2hw_prio55_reg_t prio55; // [418:417] + rv_plic_reg2hw_prio56_reg_t prio56; // [416:415] + rv_plic_reg2hw_prio57_reg_t prio57; // [414:413] + rv_plic_reg2hw_prio58_reg_t prio58; // [412:411] + rv_plic_reg2hw_prio59_reg_t prio59; // [410:409] + rv_plic_reg2hw_prio60_reg_t prio60; // [408:407] + rv_plic_reg2hw_prio61_reg_t prio61; // [406:405] + rv_plic_reg2hw_prio62_reg_t prio62; // [404:403] + rv_plic_reg2hw_prio63_reg_t prio63; // [402:401] + rv_plic_reg2hw_prio64_reg_t prio64; // [400:399] + rv_plic_reg2hw_prio65_reg_t prio65; // [398:397] + rv_plic_reg2hw_prio66_reg_t prio66; // [396:395] + rv_plic_reg2hw_prio67_reg_t prio67; // [394:393] + rv_plic_reg2hw_prio68_reg_t prio68; // [392:391] + rv_plic_reg2hw_prio69_reg_t prio69; // [390:389] + rv_plic_reg2hw_prio70_reg_t prio70; // [388:387] + rv_plic_reg2hw_prio71_reg_t prio71; // [386:385] + rv_plic_reg2hw_prio72_reg_t prio72; // [384:383] + rv_plic_reg2hw_prio73_reg_t prio73; // [382:381] + rv_plic_reg2hw_prio74_reg_t prio74; // [380:379] + rv_plic_reg2hw_prio75_reg_t prio75; // [378:377] + rv_plic_reg2hw_prio76_reg_t prio76; // [376:375] + rv_plic_reg2hw_prio77_reg_t prio77; // [374:373] + rv_plic_reg2hw_prio78_reg_t prio78; // [372:371] + rv_plic_reg2hw_prio79_reg_t prio79; // [370:369] + rv_plic_reg2hw_prio80_reg_t prio80; // [368:367] + rv_plic_reg2hw_prio81_reg_t prio81; // [366:365] + rv_plic_reg2hw_prio82_reg_t prio82; // [364:363] + rv_plic_reg2hw_prio83_reg_t prio83; // [362:361] + rv_plic_reg2hw_prio84_reg_t prio84; // [360:359] + rv_plic_reg2hw_prio85_reg_t prio85; // [358:357] + rv_plic_reg2hw_prio86_reg_t prio86; // [356:355] + rv_plic_reg2hw_prio87_reg_t prio87; // [354:353] + rv_plic_reg2hw_prio88_reg_t prio88; // [352:351] + rv_plic_reg2hw_prio89_reg_t prio89; // [350:349] + rv_plic_reg2hw_prio90_reg_t prio90; // [348:347] + rv_plic_reg2hw_prio91_reg_t prio91; // [346:345] + rv_plic_reg2hw_prio92_reg_t prio92; // [344:343] + rv_plic_reg2hw_prio93_reg_t prio93; // [342:341] + rv_plic_reg2hw_prio94_reg_t prio94; // [340:339] + rv_plic_reg2hw_prio95_reg_t prio95; // [338:337] + rv_plic_reg2hw_prio96_reg_t prio96; // [336:335] + rv_plic_reg2hw_prio97_reg_t prio97; // [334:333] + rv_plic_reg2hw_prio98_reg_t prio98; // [332:331] + rv_plic_reg2hw_prio99_reg_t prio99; // [330:329] + rv_plic_reg2hw_prio100_reg_t prio100; // [328:327] + rv_plic_reg2hw_prio101_reg_t prio101; // [326:325] + rv_plic_reg2hw_prio102_reg_t prio102; // [324:323] + rv_plic_reg2hw_prio103_reg_t prio103; // [322:321] + rv_plic_reg2hw_prio104_reg_t prio104; // [320:319] + rv_plic_reg2hw_prio105_reg_t prio105; // [318:317] + rv_plic_reg2hw_prio106_reg_t prio106; // [316:315] + rv_plic_reg2hw_prio107_reg_t prio107; // [314:313] + rv_plic_reg2hw_prio108_reg_t prio108; // [312:311] + rv_plic_reg2hw_prio109_reg_t prio109; // [310:309] + rv_plic_reg2hw_prio110_reg_t prio110; // [308:307] + rv_plic_reg2hw_prio111_reg_t prio111; // [306:305] + rv_plic_reg2hw_prio112_reg_t prio112; // [304:303] + rv_plic_reg2hw_prio113_reg_t prio113; // [302:301] + rv_plic_reg2hw_prio114_reg_t prio114; // [300:299] + rv_plic_reg2hw_prio115_reg_t prio115; // [298:297] + rv_plic_reg2hw_prio116_reg_t prio116; // [296:295] + rv_plic_reg2hw_prio117_reg_t prio117; // [294:293] + rv_plic_reg2hw_prio118_reg_t prio118; // [292:291] + rv_plic_reg2hw_prio119_reg_t prio119; // [290:289] + rv_plic_reg2hw_prio120_reg_t prio120; // [288:287] + rv_plic_reg2hw_prio121_reg_t prio121; // [286:285] + rv_plic_reg2hw_prio122_reg_t prio122; // [284:283] + rv_plic_reg2hw_prio123_reg_t prio123; // [282:281] + rv_plic_reg2hw_prio124_reg_t prio124; // [280:279] + rv_plic_reg2hw_prio125_reg_t prio125; // [278:277] + rv_plic_reg2hw_prio126_reg_t prio126; // [276:275] + rv_plic_reg2hw_prio127_reg_t prio127; // [274:273] + rv_plic_reg2hw_prio128_reg_t prio128; // [272:271] + rv_plic_reg2hw_prio129_reg_t prio129; // [270:269] + rv_plic_reg2hw_prio130_reg_t prio130; // [268:267] + rv_plic_reg2hw_prio131_reg_t prio131; // [266:265] + rv_plic_reg2hw_prio132_reg_t prio132; // [264:263] + rv_plic_reg2hw_prio133_reg_t prio133; // [262:261] + rv_plic_reg2hw_prio134_reg_t prio134; // [260:259] + rv_plic_reg2hw_prio135_reg_t prio135; // [258:257] + rv_plic_reg2hw_prio136_reg_t prio136; // [256:255] + rv_plic_reg2hw_prio137_reg_t prio137; // [254:253] + rv_plic_reg2hw_prio138_reg_t prio138; // [252:251] + rv_plic_reg2hw_prio139_reg_t prio139; // [250:249] + rv_plic_reg2hw_prio140_reg_t prio140; // [248:247] + rv_plic_reg2hw_prio141_reg_t prio141; // [246:245] + rv_plic_reg2hw_prio142_reg_t prio142; // [244:243] + rv_plic_reg2hw_prio143_reg_t prio143; // [242:241] + rv_plic_reg2hw_prio144_reg_t prio144; // [240:239] + rv_plic_reg2hw_prio145_reg_t prio145; // [238:237] + rv_plic_reg2hw_prio146_reg_t prio146; // [236:235] + rv_plic_reg2hw_prio147_reg_t prio147; // [234:233] + rv_plic_reg2hw_prio148_reg_t prio148; // [232:231] + rv_plic_reg2hw_prio149_reg_t prio149; // [230:229] + rv_plic_reg2hw_prio150_reg_t prio150; // [228:227] + rv_plic_reg2hw_prio151_reg_t prio151; // [226:225] + rv_plic_reg2hw_prio152_reg_t prio152; // [224:223] + rv_plic_reg2hw_prio153_reg_t prio153; // [222:221] + rv_plic_reg2hw_prio154_reg_t prio154; // [220:219] + rv_plic_reg2hw_prio155_reg_t prio155; // [218:217] + rv_plic_reg2hw_prio156_reg_t prio156; // [216:215] + rv_plic_reg2hw_prio157_reg_t prio157; // [214:213] + rv_plic_reg2hw_prio158_reg_t prio158; // [212:211] + rv_plic_reg2hw_prio159_reg_t prio159; // [210:209] + rv_plic_reg2hw_prio160_reg_t prio160; // [208:207] + rv_plic_reg2hw_prio161_reg_t prio161; // [206:205] + rv_plic_reg2hw_prio162_reg_t prio162; // [204:203] + rv_plic_reg2hw_prio163_reg_t prio163; // [202:201] + rv_plic_reg2hw_prio164_reg_t prio164; // [200:199] + rv_plic_reg2hw_prio165_reg_t prio165; // [198:197] + rv_plic_reg2hw_prio166_reg_t prio166; // [196:195] + rv_plic_reg2hw_prio167_reg_t prio167; // [194:193] + rv_plic_reg2hw_prio168_reg_t prio168; // [192:191] + rv_plic_reg2hw_prio169_reg_t prio169; // [190:189] + rv_plic_reg2hw_prio170_reg_t prio170; // [188:187] + rv_plic_reg2hw_prio171_reg_t prio171; // [186:185] + rv_plic_reg2hw_ie0_mreg_t [171:0] ie0; // [184:13] + rv_plic_reg2hw_threshold0_reg_t threshold0; // [12:11] + rv_plic_reg2hw_cc0_reg_t cc0; // [10:1] rv_plic_reg2hw_msip0_reg_t msip0; // [0:0] } rv_plic_reg2hw_t; @@ -675,8 +925,8 @@ // Internal design logic to register // /////////////////////////////////////// typedef struct packed { - rv_plic_hw2reg_ip_mreg_t [121:0] ip; // [250:7] - rv_plic_hw2reg_cc0_reg_t cc0; // [6:0] + rv_plic_hw2reg_ip_mreg_t [171:0] ip; // [351:8] + rv_plic_hw2reg_cc0_reg_t cc0; // [7:0] } rv_plic_hw2reg_t; // Register Address @@ -684,139 +934,195 @@ parameter logic [BlockAw-1:0] RV_PLIC_IP_1_OFFSET = 10'h 4; parameter logic [BlockAw-1:0] RV_PLIC_IP_2_OFFSET = 10'h 8; parameter logic [BlockAw-1:0] RV_PLIC_IP_3_OFFSET = 10'h c; - parameter logic [BlockAw-1:0] RV_PLIC_LE_0_OFFSET = 10'h 10; - parameter logic [BlockAw-1:0] RV_PLIC_LE_1_OFFSET = 10'h 14; - parameter logic [BlockAw-1:0] RV_PLIC_LE_2_OFFSET = 10'h 18; - parameter logic [BlockAw-1:0] RV_PLIC_LE_3_OFFSET = 10'h 1c; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO0_OFFSET = 10'h 20; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO1_OFFSET = 10'h 24; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO2_OFFSET = 10'h 28; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO3_OFFSET = 10'h 2c; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO4_OFFSET = 10'h 30; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO5_OFFSET = 10'h 34; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO6_OFFSET = 10'h 38; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO7_OFFSET = 10'h 3c; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO8_OFFSET = 10'h 40; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO9_OFFSET = 10'h 44; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO10_OFFSET = 10'h 48; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO11_OFFSET = 10'h 4c; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO12_OFFSET = 10'h 50; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO13_OFFSET = 10'h 54; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO14_OFFSET = 10'h 58; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO15_OFFSET = 10'h 5c; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO16_OFFSET = 10'h 60; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO17_OFFSET = 10'h 64; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO18_OFFSET = 10'h 68; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO19_OFFSET = 10'h 6c; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO20_OFFSET = 10'h 70; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO21_OFFSET = 10'h 74; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO22_OFFSET = 10'h 78; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO23_OFFSET = 10'h 7c; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO24_OFFSET = 10'h 80; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO25_OFFSET = 10'h 84; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO26_OFFSET = 10'h 88; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO27_OFFSET = 10'h 8c; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO28_OFFSET = 10'h 90; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO29_OFFSET = 10'h 94; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO30_OFFSET = 10'h 98; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO31_OFFSET = 10'h 9c; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO32_OFFSET = 10'h a0; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO33_OFFSET = 10'h a4; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO34_OFFSET = 10'h a8; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO35_OFFSET = 10'h ac; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO36_OFFSET = 10'h b0; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO37_OFFSET = 10'h b4; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO38_OFFSET = 10'h b8; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO39_OFFSET = 10'h bc; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO40_OFFSET = 10'h c0; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO41_OFFSET = 10'h c4; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO42_OFFSET = 10'h c8; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO43_OFFSET = 10'h cc; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO44_OFFSET = 10'h d0; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO45_OFFSET = 10'h d4; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO46_OFFSET = 10'h d8; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO47_OFFSET = 10'h dc; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO48_OFFSET = 10'h e0; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO49_OFFSET = 10'h e4; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO50_OFFSET = 10'h e8; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO51_OFFSET = 10'h ec; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO52_OFFSET = 10'h f0; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO53_OFFSET = 10'h f4; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO54_OFFSET = 10'h f8; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO55_OFFSET = 10'h fc; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO56_OFFSET = 10'h 100; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO57_OFFSET = 10'h 104; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO58_OFFSET = 10'h 108; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO59_OFFSET = 10'h 10c; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO60_OFFSET = 10'h 110; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO61_OFFSET = 10'h 114; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO62_OFFSET = 10'h 118; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO63_OFFSET = 10'h 11c; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO64_OFFSET = 10'h 120; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO65_OFFSET = 10'h 124; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO66_OFFSET = 10'h 128; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO67_OFFSET = 10'h 12c; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO68_OFFSET = 10'h 130; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO69_OFFSET = 10'h 134; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO70_OFFSET = 10'h 138; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO71_OFFSET = 10'h 13c; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO72_OFFSET = 10'h 140; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO73_OFFSET = 10'h 144; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO74_OFFSET = 10'h 148; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO75_OFFSET = 10'h 14c; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO76_OFFSET = 10'h 150; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO77_OFFSET = 10'h 154; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO78_OFFSET = 10'h 158; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO79_OFFSET = 10'h 15c; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO80_OFFSET = 10'h 160; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO81_OFFSET = 10'h 164; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO82_OFFSET = 10'h 168; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO83_OFFSET = 10'h 16c; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO84_OFFSET = 10'h 170; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO85_OFFSET = 10'h 174; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO86_OFFSET = 10'h 178; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO87_OFFSET = 10'h 17c; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO88_OFFSET = 10'h 180; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO89_OFFSET = 10'h 184; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO90_OFFSET = 10'h 188; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO91_OFFSET = 10'h 18c; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO92_OFFSET = 10'h 190; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO93_OFFSET = 10'h 194; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO94_OFFSET = 10'h 198; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO95_OFFSET = 10'h 19c; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO96_OFFSET = 10'h 1a0; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO97_OFFSET = 10'h 1a4; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO98_OFFSET = 10'h 1a8; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO99_OFFSET = 10'h 1ac; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO100_OFFSET = 10'h 1b0; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO101_OFFSET = 10'h 1b4; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO102_OFFSET = 10'h 1b8; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO103_OFFSET = 10'h 1bc; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO104_OFFSET = 10'h 1c0; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO105_OFFSET = 10'h 1c4; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO106_OFFSET = 10'h 1c8; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO107_OFFSET = 10'h 1cc; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO108_OFFSET = 10'h 1d0; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO109_OFFSET = 10'h 1d4; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO110_OFFSET = 10'h 1d8; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO111_OFFSET = 10'h 1dc; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO112_OFFSET = 10'h 1e0; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO113_OFFSET = 10'h 1e4; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO114_OFFSET = 10'h 1e8; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO115_OFFSET = 10'h 1ec; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO116_OFFSET = 10'h 1f0; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO117_OFFSET = 10'h 1f4; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO118_OFFSET = 10'h 1f8; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO119_OFFSET = 10'h 1fc; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO120_OFFSET = 10'h 200; - parameter logic [BlockAw-1:0] RV_PLIC_PRIO121_OFFSET = 10'h 204; + parameter logic [BlockAw-1:0] RV_PLIC_IP_4_OFFSET = 10'h 10; + parameter logic [BlockAw-1:0] RV_PLIC_IP_5_OFFSET = 10'h 14; + parameter logic [BlockAw-1:0] RV_PLIC_LE_0_OFFSET = 10'h 18; + parameter logic [BlockAw-1:0] RV_PLIC_LE_1_OFFSET = 10'h 1c; + parameter logic [BlockAw-1:0] RV_PLIC_LE_2_OFFSET = 10'h 20; + parameter logic [BlockAw-1:0] RV_PLIC_LE_3_OFFSET = 10'h 24; + parameter logic [BlockAw-1:0] RV_PLIC_LE_4_OFFSET = 10'h 28; + parameter logic [BlockAw-1:0] RV_PLIC_LE_5_OFFSET = 10'h 2c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO0_OFFSET = 10'h 30; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO1_OFFSET = 10'h 34; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO2_OFFSET = 10'h 38; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO3_OFFSET = 10'h 3c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO4_OFFSET = 10'h 40; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO5_OFFSET = 10'h 44; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO6_OFFSET = 10'h 48; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO7_OFFSET = 10'h 4c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO8_OFFSET = 10'h 50; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO9_OFFSET = 10'h 54; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO10_OFFSET = 10'h 58; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO11_OFFSET = 10'h 5c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO12_OFFSET = 10'h 60; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO13_OFFSET = 10'h 64; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO14_OFFSET = 10'h 68; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO15_OFFSET = 10'h 6c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO16_OFFSET = 10'h 70; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO17_OFFSET = 10'h 74; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO18_OFFSET = 10'h 78; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO19_OFFSET = 10'h 7c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO20_OFFSET = 10'h 80; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO21_OFFSET = 10'h 84; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO22_OFFSET = 10'h 88; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO23_OFFSET = 10'h 8c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO24_OFFSET = 10'h 90; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO25_OFFSET = 10'h 94; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO26_OFFSET = 10'h 98; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO27_OFFSET = 10'h 9c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO28_OFFSET = 10'h a0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO29_OFFSET = 10'h a4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO30_OFFSET = 10'h a8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO31_OFFSET = 10'h ac; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO32_OFFSET = 10'h b0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO33_OFFSET = 10'h b4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO34_OFFSET = 10'h b8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO35_OFFSET = 10'h bc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO36_OFFSET = 10'h c0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO37_OFFSET = 10'h c4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO38_OFFSET = 10'h c8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO39_OFFSET = 10'h cc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO40_OFFSET = 10'h d0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO41_OFFSET = 10'h d4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO42_OFFSET = 10'h d8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO43_OFFSET = 10'h dc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO44_OFFSET = 10'h e0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO45_OFFSET = 10'h e4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO46_OFFSET = 10'h e8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO47_OFFSET = 10'h ec; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO48_OFFSET = 10'h f0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO49_OFFSET = 10'h f4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO50_OFFSET = 10'h f8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO51_OFFSET = 10'h fc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO52_OFFSET = 10'h 100; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO53_OFFSET = 10'h 104; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO54_OFFSET = 10'h 108; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO55_OFFSET = 10'h 10c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO56_OFFSET = 10'h 110; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO57_OFFSET = 10'h 114; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO58_OFFSET = 10'h 118; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO59_OFFSET = 10'h 11c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO60_OFFSET = 10'h 120; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO61_OFFSET = 10'h 124; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO62_OFFSET = 10'h 128; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO63_OFFSET = 10'h 12c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO64_OFFSET = 10'h 130; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO65_OFFSET = 10'h 134; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO66_OFFSET = 10'h 138; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO67_OFFSET = 10'h 13c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO68_OFFSET = 10'h 140; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO69_OFFSET = 10'h 144; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO70_OFFSET = 10'h 148; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO71_OFFSET = 10'h 14c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO72_OFFSET = 10'h 150; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO73_OFFSET = 10'h 154; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO74_OFFSET = 10'h 158; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO75_OFFSET = 10'h 15c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO76_OFFSET = 10'h 160; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO77_OFFSET = 10'h 164; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO78_OFFSET = 10'h 168; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO79_OFFSET = 10'h 16c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO80_OFFSET = 10'h 170; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO81_OFFSET = 10'h 174; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO82_OFFSET = 10'h 178; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO83_OFFSET = 10'h 17c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO84_OFFSET = 10'h 180; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO85_OFFSET = 10'h 184; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO86_OFFSET = 10'h 188; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO87_OFFSET = 10'h 18c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO88_OFFSET = 10'h 190; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO89_OFFSET = 10'h 194; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO90_OFFSET = 10'h 198; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO91_OFFSET = 10'h 19c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO92_OFFSET = 10'h 1a0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO93_OFFSET = 10'h 1a4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO94_OFFSET = 10'h 1a8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO95_OFFSET = 10'h 1ac; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO96_OFFSET = 10'h 1b0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO97_OFFSET = 10'h 1b4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO98_OFFSET = 10'h 1b8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO99_OFFSET = 10'h 1bc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO100_OFFSET = 10'h 1c0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO101_OFFSET = 10'h 1c4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO102_OFFSET = 10'h 1c8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO103_OFFSET = 10'h 1cc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO104_OFFSET = 10'h 1d0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO105_OFFSET = 10'h 1d4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO106_OFFSET = 10'h 1d8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO107_OFFSET = 10'h 1dc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO108_OFFSET = 10'h 1e0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO109_OFFSET = 10'h 1e4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO110_OFFSET = 10'h 1e8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO111_OFFSET = 10'h 1ec; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO112_OFFSET = 10'h 1f0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO113_OFFSET = 10'h 1f4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO114_OFFSET = 10'h 1f8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO115_OFFSET = 10'h 1fc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO116_OFFSET = 10'h 200; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO117_OFFSET = 10'h 204; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO118_OFFSET = 10'h 208; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO119_OFFSET = 10'h 20c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO120_OFFSET = 10'h 210; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO121_OFFSET = 10'h 214; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO122_OFFSET = 10'h 218; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO123_OFFSET = 10'h 21c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO124_OFFSET = 10'h 220; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO125_OFFSET = 10'h 224; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO126_OFFSET = 10'h 228; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO127_OFFSET = 10'h 22c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO128_OFFSET = 10'h 230; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO129_OFFSET = 10'h 234; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO130_OFFSET = 10'h 238; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO131_OFFSET = 10'h 23c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO132_OFFSET = 10'h 240; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO133_OFFSET = 10'h 244; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO134_OFFSET = 10'h 248; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO135_OFFSET = 10'h 24c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO136_OFFSET = 10'h 250; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO137_OFFSET = 10'h 254; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO138_OFFSET = 10'h 258; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO139_OFFSET = 10'h 25c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO140_OFFSET = 10'h 260; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO141_OFFSET = 10'h 264; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO142_OFFSET = 10'h 268; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO143_OFFSET = 10'h 26c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO144_OFFSET = 10'h 270; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO145_OFFSET = 10'h 274; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO146_OFFSET = 10'h 278; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO147_OFFSET = 10'h 27c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO148_OFFSET = 10'h 280; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO149_OFFSET = 10'h 284; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO150_OFFSET = 10'h 288; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO151_OFFSET = 10'h 28c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO152_OFFSET = 10'h 290; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO153_OFFSET = 10'h 294; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO154_OFFSET = 10'h 298; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO155_OFFSET = 10'h 29c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO156_OFFSET = 10'h 2a0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO157_OFFSET = 10'h 2a4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO158_OFFSET = 10'h 2a8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO159_OFFSET = 10'h 2ac; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO160_OFFSET = 10'h 2b0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO161_OFFSET = 10'h 2b4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO162_OFFSET = 10'h 2b8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO163_OFFSET = 10'h 2bc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO164_OFFSET = 10'h 2c0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO165_OFFSET = 10'h 2c4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO166_OFFSET = 10'h 2c8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO167_OFFSET = 10'h 2cc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO168_OFFSET = 10'h 2d0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO169_OFFSET = 10'h 2d4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO170_OFFSET = 10'h 2d8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO171_OFFSET = 10'h 2dc; parameter logic [BlockAw-1:0] RV_PLIC_IE0_0_OFFSET = 10'h 300; parameter logic [BlockAw-1:0] RV_PLIC_IE0_1_OFFSET = 10'h 304; parameter logic [BlockAw-1:0] RV_PLIC_IE0_2_OFFSET = 10'h 308; parameter logic [BlockAw-1:0] RV_PLIC_IE0_3_OFFSET = 10'h 30c; - parameter logic [BlockAw-1:0] RV_PLIC_THRESHOLD0_OFFSET = 10'h 310; - parameter logic [BlockAw-1:0] RV_PLIC_CC0_OFFSET = 10'h 314; - parameter logic [BlockAw-1:0] RV_PLIC_MSIP0_OFFSET = 10'h 318; + parameter logic [BlockAw-1:0] RV_PLIC_IE0_4_OFFSET = 10'h 310; + parameter logic [BlockAw-1:0] RV_PLIC_IE0_5_OFFSET = 10'h 314; + parameter logic [BlockAw-1:0] RV_PLIC_THRESHOLD0_OFFSET = 10'h 318; + parameter logic [BlockAw-1:0] RV_PLIC_CC0_OFFSET = 10'h 31c; + parameter logic [BlockAw-1:0] RV_PLIC_MSIP0_OFFSET = 10'h 320; // Register Index @@ -825,10 +1131,14 @@ RV_PLIC_IP_1, RV_PLIC_IP_2, RV_PLIC_IP_3, + RV_PLIC_IP_4, + RV_PLIC_IP_5, RV_PLIC_LE_0, RV_PLIC_LE_1, RV_PLIC_LE_2, RV_PLIC_LE_3, + RV_PLIC_LE_4, + RV_PLIC_LE_5, RV_PLIC_PRIO0, RV_PLIC_PRIO1, RV_PLIC_PRIO2, @@ -951,154 +1261,262 @@ RV_PLIC_PRIO119, RV_PLIC_PRIO120, RV_PLIC_PRIO121, + RV_PLIC_PRIO122, + RV_PLIC_PRIO123, + RV_PLIC_PRIO124, + RV_PLIC_PRIO125, + RV_PLIC_PRIO126, + RV_PLIC_PRIO127, + RV_PLIC_PRIO128, + RV_PLIC_PRIO129, + RV_PLIC_PRIO130, + RV_PLIC_PRIO131, + RV_PLIC_PRIO132, + RV_PLIC_PRIO133, + RV_PLIC_PRIO134, + RV_PLIC_PRIO135, + RV_PLIC_PRIO136, + RV_PLIC_PRIO137, + RV_PLIC_PRIO138, + RV_PLIC_PRIO139, + RV_PLIC_PRIO140, + RV_PLIC_PRIO141, + RV_PLIC_PRIO142, + RV_PLIC_PRIO143, + RV_PLIC_PRIO144, + RV_PLIC_PRIO145, + RV_PLIC_PRIO146, + RV_PLIC_PRIO147, + RV_PLIC_PRIO148, + RV_PLIC_PRIO149, + RV_PLIC_PRIO150, + RV_PLIC_PRIO151, + RV_PLIC_PRIO152, + RV_PLIC_PRIO153, + RV_PLIC_PRIO154, + RV_PLIC_PRIO155, + RV_PLIC_PRIO156, + RV_PLIC_PRIO157, + RV_PLIC_PRIO158, + RV_PLIC_PRIO159, + RV_PLIC_PRIO160, + RV_PLIC_PRIO161, + RV_PLIC_PRIO162, + RV_PLIC_PRIO163, + RV_PLIC_PRIO164, + RV_PLIC_PRIO165, + RV_PLIC_PRIO166, + RV_PLIC_PRIO167, + RV_PLIC_PRIO168, + RV_PLIC_PRIO169, + RV_PLIC_PRIO170, + RV_PLIC_PRIO171, RV_PLIC_IE0_0, RV_PLIC_IE0_1, RV_PLIC_IE0_2, RV_PLIC_IE0_3, + RV_PLIC_IE0_4, + RV_PLIC_IE0_5, RV_PLIC_THRESHOLD0, RV_PLIC_CC0, RV_PLIC_MSIP0 } rv_plic_id_e; // Register width information to check illegal writes - parameter logic [3:0] RV_PLIC_PERMIT [137] = '{ + parameter logic [3:0] RV_PLIC_PERMIT [193] = '{ 4'b 1111, // index[ 0] RV_PLIC_IP_0 4'b 1111, // index[ 1] RV_PLIC_IP_1 4'b 1111, // index[ 2] RV_PLIC_IP_2 4'b 1111, // index[ 3] RV_PLIC_IP_3 - 4'b 1111, // index[ 4] RV_PLIC_LE_0 - 4'b 1111, // index[ 5] RV_PLIC_LE_1 - 4'b 1111, // index[ 6] RV_PLIC_LE_2 - 4'b 1111, // index[ 7] RV_PLIC_LE_3 - 4'b 0001, // index[ 8] RV_PLIC_PRIO0 - 4'b 0001, // index[ 9] RV_PLIC_PRIO1 - 4'b 0001, // index[ 10] RV_PLIC_PRIO2 - 4'b 0001, // index[ 11] RV_PLIC_PRIO3 - 4'b 0001, // index[ 12] RV_PLIC_PRIO4 - 4'b 0001, // index[ 13] RV_PLIC_PRIO5 - 4'b 0001, // index[ 14] RV_PLIC_PRIO6 - 4'b 0001, // index[ 15] RV_PLIC_PRIO7 - 4'b 0001, // index[ 16] RV_PLIC_PRIO8 - 4'b 0001, // index[ 17] RV_PLIC_PRIO9 - 4'b 0001, // index[ 18] RV_PLIC_PRIO10 - 4'b 0001, // index[ 19] RV_PLIC_PRIO11 - 4'b 0001, // index[ 20] RV_PLIC_PRIO12 - 4'b 0001, // index[ 21] RV_PLIC_PRIO13 - 4'b 0001, // index[ 22] RV_PLIC_PRIO14 - 4'b 0001, // index[ 23] RV_PLIC_PRIO15 - 4'b 0001, // index[ 24] RV_PLIC_PRIO16 - 4'b 0001, // index[ 25] RV_PLIC_PRIO17 - 4'b 0001, // index[ 26] RV_PLIC_PRIO18 - 4'b 0001, // index[ 27] RV_PLIC_PRIO19 - 4'b 0001, // index[ 28] RV_PLIC_PRIO20 - 4'b 0001, // index[ 29] RV_PLIC_PRIO21 - 4'b 0001, // index[ 30] RV_PLIC_PRIO22 - 4'b 0001, // index[ 31] RV_PLIC_PRIO23 - 4'b 0001, // index[ 32] RV_PLIC_PRIO24 - 4'b 0001, // index[ 33] RV_PLIC_PRIO25 - 4'b 0001, // index[ 34] RV_PLIC_PRIO26 - 4'b 0001, // index[ 35] RV_PLIC_PRIO27 - 4'b 0001, // index[ 36] RV_PLIC_PRIO28 - 4'b 0001, // index[ 37] RV_PLIC_PRIO29 - 4'b 0001, // index[ 38] RV_PLIC_PRIO30 - 4'b 0001, // index[ 39] RV_PLIC_PRIO31 - 4'b 0001, // index[ 40] RV_PLIC_PRIO32 - 4'b 0001, // index[ 41] RV_PLIC_PRIO33 - 4'b 0001, // index[ 42] RV_PLIC_PRIO34 - 4'b 0001, // index[ 43] RV_PLIC_PRIO35 - 4'b 0001, // index[ 44] RV_PLIC_PRIO36 - 4'b 0001, // index[ 45] RV_PLIC_PRIO37 - 4'b 0001, // index[ 46] RV_PLIC_PRIO38 - 4'b 0001, // index[ 47] RV_PLIC_PRIO39 - 4'b 0001, // index[ 48] RV_PLIC_PRIO40 - 4'b 0001, // index[ 49] RV_PLIC_PRIO41 - 4'b 0001, // index[ 50] RV_PLIC_PRIO42 - 4'b 0001, // index[ 51] RV_PLIC_PRIO43 - 4'b 0001, // index[ 52] RV_PLIC_PRIO44 - 4'b 0001, // index[ 53] RV_PLIC_PRIO45 - 4'b 0001, // index[ 54] RV_PLIC_PRIO46 - 4'b 0001, // index[ 55] RV_PLIC_PRIO47 - 4'b 0001, // index[ 56] RV_PLIC_PRIO48 - 4'b 0001, // index[ 57] RV_PLIC_PRIO49 - 4'b 0001, // index[ 58] RV_PLIC_PRIO50 - 4'b 0001, // index[ 59] RV_PLIC_PRIO51 - 4'b 0001, // index[ 60] RV_PLIC_PRIO52 - 4'b 0001, // index[ 61] RV_PLIC_PRIO53 - 4'b 0001, // index[ 62] RV_PLIC_PRIO54 - 4'b 0001, // index[ 63] RV_PLIC_PRIO55 - 4'b 0001, // index[ 64] RV_PLIC_PRIO56 - 4'b 0001, // index[ 65] RV_PLIC_PRIO57 - 4'b 0001, // index[ 66] RV_PLIC_PRIO58 - 4'b 0001, // index[ 67] RV_PLIC_PRIO59 - 4'b 0001, // index[ 68] RV_PLIC_PRIO60 - 4'b 0001, // index[ 69] RV_PLIC_PRIO61 - 4'b 0001, // index[ 70] RV_PLIC_PRIO62 - 4'b 0001, // index[ 71] RV_PLIC_PRIO63 - 4'b 0001, // index[ 72] RV_PLIC_PRIO64 - 4'b 0001, // index[ 73] RV_PLIC_PRIO65 - 4'b 0001, // index[ 74] RV_PLIC_PRIO66 - 4'b 0001, // index[ 75] RV_PLIC_PRIO67 - 4'b 0001, // index[ 76] RV_PLIC_PRIO68 - 4'b 0001, // index[ 77] RV_PLIC_PRIO69 - 4'b 0001, // index[ 78] RV_PLIC_PRIO70 - 4'b 0001, // index[ 79] RV_PLIC_PRIO71 - 4'b 0001, // index[ 80] RV_PLIC_PRIO72 - 4'b 0001, // index[ 81] RV_PLIC_PRIO73 - 4'b 0001, // index[ 82] RV_PLIC_PRIO74 - 4'b 0001, // index[ 83] RV_PLIC_PRIO75 - 4'b 0001, // index[ 84] RV_PLIC_PRIO76 - 4'b 0001, // index[ 85] RV_PLIC_PRIO77 - 4'b 0001, // index[ 86] RV_PLIC_PRIO78 - 4'b 0001, // index[ 87] RV_PLIC_PRIO79 - 4'b 0001, // index[ 88] RV_PLIC_PRIO80 - 4'b 0001, // index[ 89] RV_PLIC_PRIO81 - 4'b 0001, // index[ 90] RV_PLIC_PRIO82 - 4'b 0001, // index[ 91] RV_PLIC_PRIO83 - 4'b 0001, // index[ 92] RV_PLIC_PRIO84 - 4'b 0001, // index[ 93] RV_PLIC_PRIO85 - 4'b 0001, // index[ 94] RV_PLIC_PRIO86 - 4'b 0001, // index[ 95] RV_PLIC_PRIO87 - 4'b 0001, // index[ 96] RV_PLIC_PRIO88 - 4'b 0001, // index[ 97] RV_PLIC_PRIO89 - 4'b 0001, // index[ 98] RV_PLIC_PRIO90 - 4'b 0001, // index[ 99] RV_PLIC_PRIO91 - 4'b 0001, // index[100] RV_PLIC_PRIO92 - 4'b 0001, // index[101] RV_PLIC_PRIO93 - 4'b 0001, // index[102] RV_PLIC_PRIO94 - 4'b 0001, // index[103] RV_PLIC_PRIO95 - 4'b 0001, // index[104] RV_PLIC_PRIO96 - 4'b 0001, // index[105] RV_PLIC_PRIO97 - 4'b 0001, // index[106] RV_PLIC_PRIO98 - 4'b 0001, // index[107] RV_PLIC_PRIO99 - 4'b 0001, // index[108] RV_PLIC_PRIO100 - 4'b 0001, // index[109] RV_PLIC_PRIO101 - 4'b 0001, // index[110] RV_PLIC_PRIO102 - 4'b 0001, // index[111] RV_PLIC_PRIO103 - 4'b 0001, // index[112] RV_PLIC_PRIO104 - 4'b 0001, // index[113] RV_PLIC_PRIO105 - 4'b 0001, // index[114] RV_PLIC_PRIO106 - 4'b 0001, // index[115] RV_PLIC_PRIO107 - 4'b 0001, // index[116] RV_PLIC_PRIO108 - 4'b 0001, // index[117] RV_PLIC_PRIO109 - 4'b 0001, // index[118] RV_PLIC_PRIO110 - 4'b 0001, // index[119] RV_PLIC_PRIO111 - 4'b 0001, // index[120] RV_PLIC_PRIO112 - 4'b 0001, // index[121] RV_PLIC_PRIO113 - 4'b 0001, // index[122] RV_PLIC_PRIO114 - 4'b 0001, // index[123] RV_PLIC_PRIO115 - 4'b 0001, // index[124] RV_PLIC_PRIO116 - 4'b 0001, // index[125] RV_PLIC_PRIO117 - 4'b 0001, // index[126] RV_PLIC_PRIO118 - 4'b 0001, // index[127] RV_PLIC_PRIO119 - 4'b 0001, // index[128] RV_PLIC_PRIO120 - 4'b 0001, // index[129] RV_PLIC_PRIO121 - 4'b 1111, // index[130] RV_PLIC_IE0_0 - 4'b 1111, // index[131] RV_PLIC_IE0_1 - 4'b 1111, // index[132] RV_PLIC_IE0_2 - 4'b 1111, // index[133] RV_PLIC_IE0_3 - 4'b 0001, // index[134] RV_PLIC_THRESHOLD0 - 4'b 0001, // index[135] RV_PLIC_CC0 - 4'b 0001 // index[136] RV_PLIC_MSIP0 + 4'b 1111, // index[ 4] RV_PLIC_IP_4 + 4'b 0011, // index[ 5] RV_PLIC_IP_5 + 4'b 1111, // index[ 6] RV_PLIC_LE_0 + 4'b 1111, // index[ 7] RV_PLIC_LE_1 + 4'b 1111, // index[ 8] RV_PLIC_LE_2 + 4'b 1111, // index[ 9] RV_PLIC_LE_3 + 4'b 1111, // index[ 10] RV_PLIC_LE_4 + 4'b 0011, // index[ 11] RV_PLIC_LE_5 + 4'b 0001, // index[ 12] RV_PLIC_PRIO0 + 4'b 0001, // index[ 13] RV_PLIC_PRIO1 + 4'b 0001, // index[ 14] RV_PLIC_PRIO2 + 4'b 0001, // index[ 15] RV_PLIC_PRIO3 + 4'b 0001, // index[ 16] RV_PLIC_PRIO4 + 4'b 0001, // index[ 17] RV_PLIC_PRIO5 + 4'b 0001, // index[ 18] RV_PLIC_PRIO6 + 4'b 0001, // index[ 19] RV_PLIC_PRIO7 + 4'b 0001, // index[ 20] RV_PLIC_PRIO8 + 4'b 0001, // index[ 21] RV_PLIC_PRIO9 + 4'b 0001, // index[ 22] RV_PLIC_PRIO10 + 4'b 0001, // index[ 23] RV_PLIC_PRIO11 + 4'b 0001, // index[ 24] RV_PLIC_PRIO12 + 4'b 0001, // index[ 25] RV_PLIC_PRIO13 + 4'b 0001, // index[ 26] RV_PLIC_PRIO14 + 4'b 0001, // index[ 27] RV_PLIC_PRIO15 + 4'b 0001, // index[ 28] RV_PLIC_PRIO16 + 4'b 0001, // index[ 29] RV_PLIC_PRIO17 + 4'b 0001, // index[ 30] RV_PLIC_PRIO18 + 4'b 0001, // index[ 31] RV_PLIC_PRIO19 + 4'b 0001, // index[ 32] RV_PLIC_PRIO20 + 4'b 0001, // index[ 33] RV_PLIC_PRIO21 + 4'b 0001, // index[ 34] RV_PLIC_PRIO22 + 4'b 0001, // index[ 35] RV_PLIC_PRIO23 + 4'b 0001, // index[ 36] RV_PLIC_PRIO24 + 4'b 0001, // index[ 37] RV_PLIC_PRIO25 + 4'b 0001, // index[ 38] RV_PLIC_PRIO26 + 4'b 0001, // index[ 39] RV_PLIC_PRIO27 + 4'b 0001, // index[ 40] RV_PLIC_PRIO28 + 4'b 0001, // index[ 41] RV_PLIC_PRIO29 + 4'b 0001, // index[ 42] RV_PLIC_PRIO30 + 4'b 0001, // index[ 43] RV_PLIC_PRIO31 + 4'b 0001, // index[ 44] RV_PLIC_PRIO32 + 4'b 0001, // index[ 45] RV_PLIC_PRIO33 + 4'b 0001, // index[ 46] RV_PLIC_PRIO34 + 4'b 0001, // index[ 47] RV_PLIC_PRIO35 + 4'b 0001, // index[ 48] RV_PLIC_PRIO36 + 4'b 0001, // index[ 49] RV_PLIC_PRIO37 + 4'b 0001, // index[ 50] RV_PLIC_PRIO38 + 4'b 0001, // index[ 51] RV_PLIC_PRIO39 + 4'b 0001, // index[ 52] RV_PLIC_PRIO40 + 4'b 0001, // index[ 53] RV_PLIC_PRIO41 + 4'b 0001, // index[ 54] RV_PLIC_PRIO42 + 4'b 0001, // index[ 55] RV_PLIC_PRIO43 + 4'b 0001, // index[ 56] RV_PLIC_PRIO44 + 4'b 0001, // index[ 57] RV_PLIC_PRIO45 + 4'b 0001, // index[ 58] RV_PLIC_PRIO46 + 4'b 0001, // index[ 59] RV_PLIC_PRIO47 + 4'b 0001, // index[ 60] RV_PLIC_PRIO48 + 4'b 0001, // index[ 61] RV_PLIC_PRIO49 + 4'b 0001, // index[ 62] RV_PLIC_PRIO50 + 4'b 0001, // index[ 63] RV_PLIC_PRIO51 + 4'b 0001, // index[ 64] RV_PLIC_PRIO52 + 4'b 0001, // index[ 65] RV_PLIC_PRIO53 + 4'b 0001, // index[ 66] RV_PLIC_PRIO54 + 4'b 0001, // index[ 67] RV_PLIC_PRIO55 + 4'b 0001, // index[ 68] RV_PLIC_PRIO56 + 4'b 0001, // index[ 69] RV_PLIC_PRIO57 + 4'b 0001, // index[ 70] RV_PLIC_PRIO58 + 4'b 0001, // index[ 71] RV_PLIC_PRIO59 + 4'b 0001, // index[ 72] RV_PLIC_PRIO60 + 4'b 0001, // index[ 73] RV_PLIC_PRIO61 + 4'b 0001, // index[ 74] RV_PLIC_PRIO62 + 4'b 0001, // index[ 75] RV_PLIC_PRIO63 + 4'b 0001, // index[ 76] RV_PLIC_PRIO64 + 4'b 0001, // index[ 77] RV_PLIC_PRIO65 + 4'b 0001, // index[ 78] RV_PLIC_PRIO66 + 4'b 0001, // index[ 79] RV_PLIC_PRIO67 + 4'b 0001, // index[ 80] RV_PLIC_PRIO68 + 4'b 0001, // index[ 81] RV_PLIC_PRIO69 + 4'b 0001, // index[ 82] RV_PLIC_PRIO70 + 4'b 0001, // index[ 83] RV_PLIC_PRIO71 + 4'b 0001, // index[ 84] RV_PLIC_PRIO72 + 4'b 0001, // index[ 85] RV_PLIC_PRIO73 + 4'b 0001, // index[ 86] RV_PLIC_PRIO74 + 4'b 0001, // index[ 87] RV_PLIC_PRIO75 + 4'b 0001, // index[ 88] RV_PLIC_PRIO76 + 4'b 0001, // index[ 89] RV_PLIC_PRIO77 + 4'b 0001, // index[ 90] RV_PLIC_PRIO78 + 4'b 0001, // index[ 91] RV_PLIC_PRIO79 + 4'b 0001, // index[ 92] RV_PLIC_PRIO80 + 4'b 0001, // index[ 93] RV_PLIC_PRIO81 + 4'b 0001, // index[ 94] RV_PLIC_PRIO82 + 4'b 0001, // index[ 95] RV_PLIC_PRIO83 + 4'b 0001, // index[ 96] RV_PLIC_PRIO84 + 4'b 0001, // index[ 97] RV_PLIC_PRIO85 + 4'b 0001, // index[ 98] RV_PLIC_PRIO86 + 4'b 0001, // index[ 99] RV_PLIC_PRIO87 + 4'b 0001, // index[100] RV_PLIC_PRIO88 + 4'b 0001, // index[101] RV_PLIC_PRIO89 + 4'b 0001, // index[102] RV_PLIC_PRIO90 + 4'b 0001, // index[103] RV_PLIC_PRIO91 + 4'b 0001, // index[104] RV_PLIC_PRIO92 + 4'b 0001, // index[105] RV_PLIC_PRIO93 + 4'b 0001, // index[106] RV_PLIC_PRIO94 + 4'b 0001, // index[107] RV_PLIC_PRIO95 + 4'b 0001, // index[108] RV_PLIC_PRIO96 + 4'b 0001, // index[109] RV_PLIC_PRIO97 + 4'b 0001, // index[110] RV_PLIC_PRIO98 + 4'b 0001, // index[111] RV_PLIC_PRIO99 + 4'b 0001, // index[112] RV_PLIC_PRIO100 + 4'b 0001, // index[113] RV_PLIC_PRIO101 + 4'b 0001, // index[114] RV_PLIC_PRIO102 + 4'b 0001, // index[115] RV_PLIC_PRIO103 + 4'b 0001, // index[116] RV_PLIC_PRIO104 + 4'b 0001, // index[117] RV_PLIC_PRIO105 + 4'b 0001, // index[118] RV_PLIC_PRIO106 + 4'b 0001, // index[119] RV_PLIC_PRIO107 + 4'b 0001, // index[120] RV_PLIC_PRIO108 + 4'b 0001, // index[121] RV_PLIC_PRIO109 + 4'b 0001, // index[122] RV_PLIC_PRIO110 + 4'b 0001, // index[123] RV_PLIC_PRIO111 + 4'b 0001, // index[124] RV_PLIC_PRIO112 + 4'b 0001, // index[125] RV_PLIC_PRIO113 + 4'b 0001, // index[126] RV_PLIC_PRIO114 + 4'b 0001, // index[127] RV_PLIC_PRIO115 + 4'b 0001, // index[128] RV_PLIC_PRIO116 + 4'b 0001, // index[129] RV_PLIC_PRIO117 + 4'b 0001, // index[130] RV_PLIC_PRIO118 + 4'b 0001, // index[131] RV_PLIC_PRIO119 + 4'b 0001, // index[132] RV_PLIC_PRIO120 + 4'b 0001, // index[133] RV_PLIC_PRIO121 + 4'b 0001, // index[134] RV_PLIC_PRIO122 + 4'b 0001, // index[135] RV_PLIC_PRIO123 + 4'b 0001, // index[136] RV_PLIC_PRIO124 + 4'b 0001, // index[137] RV_PLIC_PRIO125 + 4'b 0001, // index[138] RV_PLIC_PRIO126 + 4'b 0001, // index[139] RV_PLIC_PRIO127 + 4'b 0001, // index[140] RV_PLIC_PRIO128 + 4'b 0001, // index[141] RV_PLIC_PRIO129 + 4'b 0001, // index[142] RV_PLIC_PRIO130 + 4'b 0001, // index[143] RV_PLIC_PRIO131 + 4'b 0001, // index[144] RV_PLIC_PRIO132 + 4'b 0001, // index[145] RV_PLIC_PRIO133 + 4'b 0001, // index[146] RV_PLIC_PRIO134 + 4'b 0001, // index[147] RV_PLIC_PRIO135 + 4'b 0001, // index[148] RV_PLIC_PRIO136 + 4'b 0001, // index[149] RV_PLIC_PRIO137 + 4'b 0001, // index[150] RV_PLIC_PRIO138 + 4'b 0001, // index[151] RV_PLIC_PRIO139 + 4'b 0001, // index[152] RV_PLIC_PRIO140 + 4'b 0001, // index[153] RV_PLIC_PRIO141 + 4'b 0001, // index[154] RV_PLIC_PRIO142 + 4'b 0001, // index[155] RV_PLIC_PRIO143 + 4'b 0001, // index[156] RV_PLIC_PRIO144 + 4'b 0001, // index[157] RV_PLIC_PRIO145 + 4'b 0001, // index[158] RV_PLIC_PRIO146 + 4'b 0001, // index[159] RV_PLIC_PRIO147 + 4'b 0001, // index[160] RV_PLIC_PRIO148 + 4'b 0001, // index[161] RV_PLIC_PRIO149 + 4'b 0001, // index[162] RV_PLIC_PRIO150 + 4'b 0001, // index[163] RV_PLIC_PRIO151 + 4'b 0001, // index[164] RV_PLIC_PRIO152 + 4'b 0001, // index[165] RV_PLIC_PRIO153 + 4'b 0001, // index[166] RV_PLIC_PRIO154 + 4'b 0001, // index[167] RV_PLIC_PRIO155 + 4'b 0001, // index[168] RV_PLIC_PRIO156 + 4'b 0001, // index[169] RV_PLIC_PRIO157 + 4'b 0001, // index[170] RV_PLIC_PRIO158 + 4'b 0001, // index[171] RV_PLIC_PRIO159 + 4'b 0001, // index[172] RV_PLIC_PRIO160 + 4'b 0001, // index[173] RV_PLIC_PRIO161 + 4'b 0001, // index[174] RV_PLIC_PRIO162 + 4'b 0001, // index[175] RV_PLIC_PRIO163 + 4'b 0001, // index[176] RV_PLIC_PRIO164 + 4'b 0001, // index[177] RV_PLIC_PRIO165 + 4'b 0001, // index[178] RV_PLIC_PRIO166 + 4'b 0001, // index[179] RV_PLIC_PRIO167 + 4'b 0001, // index[180] RV_PLIC_PRIO168 + 4'b 0001, // index[181] RV_PLIC_PRIO169 + 4'b 0001, // index[182] RV_PLIC_PRIO170 + 4'b 0001, // index[183] RV_PLIC_PRIO171 + 4'b 1111, // index[184] RV_PLIC_IE0_0 + 4'b 1111, // index[185] RV_PLIC_IE0_1 + 4'b 1111, // index[186] RV_PLIC_IE0_2 + 4'b 1111, // index[187] RV_PLIC_IE0_3 + 4'b 1111, // index[188] RV_PLIC_IE0_4 + 4'b 0011, // index[189] RV_PLIC_IE0_5 + 4'b 0001, // index[190] RV_PLIC_THRESHOLD0 + 4'b 0001, // index[191] RV_PLIC_CC0 + 4'b 0001 // index[192] RV_PLIC_MSIP0 }; endpackage
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv index 1438f13..1cdefbb 100644 --- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv +++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
@@ -193,6 +193,56 @@ logic ip_3_p_119_qs; logic ip_3_p_120_qs; logic ip_3_p_121_qs; + logic ip_3_p_122_qs; + logic ip_3_p_123_qs; + logic ip_3_p_124_qs; + logic ip_3_p_125_qs; + logic ip_3_p_126_qs; + logic ip_3_p_127_qs; + logic ip_4_p_128_qs; + logic ip_4_p_129_qs; + logic ip_4_p_130_qs; + logic ip_4_p_131_qs; + logic ip_4_p_132_qs; + logic ip_4_p_133_qs; + logic ip_4_p_134_qs; + logic ip_4_p_135_qs; + logic ip_4_p_136_qs; + logic ip_4_p_137_qs; + logic ip_4_p_138_qs; + logic ip_4_p_139_qs; + logic ip_4_p_140_qs; + logic ip_4_p_141_qs; + logic ip_4_p_142_qs; + logic ip_4_p_143_qs; + logic ip_4_p_144_qs; + logic ip_4_p_145_qs; + logic ip_4_p_146_qs; + logic ip_4_p_147_qs; + logic ip_4_p_148_qs; + logic ip_4_p_149_qs; + logic ip_4_p_150_qs; + logic ip_4_p_151_qs; + logic ip_4_p_152_qs; + logic ip_4_p_153_qs; + logic ip_4_p_154_qs; + logic ip_4_p_155_qs; + logic ip_4_p_156_qs; + logic ip_4_p_157_qs; + logic ip_4_p_158_qs; + logic ip_4_p_159_qs; + logic ip_5_p_160_qs; + logic ip_5_p_161_qs; + logic ip_5_p_162_qs; + logic ip_5_p_163_qs; + logic ip_5_p_164_qs; + logic ip_5_p_165_qs; + logic ip_5_p_166_qs; + logic ip_5_p_167_qs; + logic ip_5_p_168_qs; + logic ip_5_p_169_qs; + logic ip_5_p_170_qs; + logic ip_5_p_171_qs; logic le_0_le_0_qs; logic le_0_le_0_wd; logic le_0_le_0_we; @@ -559,6 +609,156 @@ logic le_3_le_121_qs; logic le_3_le_121_wd; logic le_3_le_121_we; + logic le_3_le_122_qs; + logic le_3_le_122_wd; + logic le_3_le_122_we; + logic le_3_le_123_qs; + logic le_3_le_123_wd; + logic le_3_le_123_we; + logic le_3_le_124_qs; + logic le_3_le_124_wd; + logic le_3_le_124_we; + logic le_3_le_125_qs; + logic le_3_le_125_wd; + logic le_3_le_125_we; + logic le_3_le_126_qs; + logic le_3_le_126_wd; + logic le_3_le_126_we; + logic le_3_le_127_qs; + logic le_3_le_127_wd; + logic le_3_le_127_we; + logic le_4_le_128_qs; + logic le_4_le_128_wd; + logic le_4_le_128_we; + logic le_4_le_129_qs; + logic le_4_le_129_wd; + logic le_4_le_129_we; + logic le_4_le_130_qs; + logic le_4_le_130_wd; + logic le_4_le_130_we; + logic le_4_le_131_qs; + logic le_4_le_131_wd; + logic le_4_le_131_we; + logic le_4_le_132_qs; + logic le_4_le_132_wd; + logic le_4_le_132_we; + logic le_4_le_133_qs; + logic le_4_le_133_wd; + logic le_4_le_133_we; + logic le_4_le_134_qs; + logic le_4_le_134_wd; + logic le_4_le_134_we; + logic le_4_le_135_qs; + logic le_4_le_135_wd; + logic le_4_le_135_we; + logic le_4_le_136_qs; + logic le_4_le_136_wd; + logic le_4_le_136_we; + logic le_4_le_137_qs; + logic le_4_le_137_wd; + logic le_4_le_137_we; + logic le_4_le_138_qs; + logic le_4_le_138_wd; + logic le_4_le_138_we; + logic le_4_le_139_qs; + logic le_4_le_139_wd; + logic le_4_le_139_we; + logic le_4_le_140_qs; + logic le_4_le_140_wd; + logic le_4_le_140_we; + logic le_4_le_141_qs; + logic le_4_le_141_wd; + logic le_4_le_141_we; + logic le_4_le_142_qs; + logic le_4_le_142_wd; + logic le_4_le_142_we; + logic le_4_le_143_qs; + logic le_4_le_143_wd; + logic le_4_le_143_we; + logic le_4_le_144_qs; + logic le_4_le_144_wd; + logic le_4_le_144_we; + logic le_4_le_145_qs; + logic le_4_le_145_wd; + logic le_4_le_145_we; + logic le_4_le_146_qs; + logic le_4_le_146_wd; + logic le_4_le_146_we; + logic le_4_le_147_qs; + logic le_4_le_147_wd; + logic le_4_le_147_we; + logic le_4_le_148_qs; + logic le_4_le_148_wd; + logic le_4_le_148_we; + logic le_4_le_149_qs; + logic le_4_le_149_wd; + logic le_4_le_149_we; + logic le_4_le_150_qs; + logic le_4_le_150_wd; + logic le_4_le_150_we; + logic le_4_le_151_qs; + logic le_4_le_151_wd; + logic le_4_le_151_we; + logic le_4_le_152_qs; + logic le_4_le_152_wd; + logic le_4_le_152_we; + logic le_4_le_153_qs; + logic le_4_le_153_wd; + logic le_4_le_153_we; + logic le_4_le_154_qs; + logic le_4_le_154_wd; + logic le_4_le_154_we; + logic le_4_le_155_qs; + logic le_4_le_155_wd; + logic le_4_le_155_we; + logic le_4_le_156_qs; + logic le_4_le_156_wd; + logic le_4_le_156_we; + logic le_4_le_157_qs; + logic le_4_le_157_wd; + logic le_4_le_157_we; + logic le_4_le_158_qs; + logic le_4_le_158_wd; + logic le_4_le_158_we; + logic le_4_le_159_qs; + logic le_4_le_159_wd; + logic le_4_le_159_we; + logic le_5_le_160_qs; + logic le_5_le_160_wd; + logic le_5_le_160_we; + logic le_5_le_161_qs; + logic le_5_le_161_wd; + logic le_5_le_161_we; + logic le_5_le_162_qs; + logic le_5_le_162_wd; + logic le_5_le_162_we; + logic le_5_le_163_qs; + logic le_5_le_163_wd; + logic le_5_le_163_we; + logic le_5_le_164_qs; + logic le_5_le_164_wd; + logic le_5_le_164_we; + logic le_5_le_165_qs; + logic le_5_le_165_wd; + logic le_5_le_165_we; + logic le_5_le_166_qs; + logic le_5_le_166_wd; + logic le_5_le_166_we; + logic le_5_le_167_qs; + logic le_5_le_167_wd; + logic le_5_le_167_we; + logic le_5_le_168_qs; + logic le_5_le_168_wd; + logic le_5_le_168_we; + logic le_5_le_169_qs; + logic le_5_le_169_wd; + logic le_5_le_169_we; + logic le_5_le_170_qs; + logic le_5_le_170_wd; + logic le_5_le_170_we; + logic le_5_le_171_qs; + logic le_5_le_171_wd; + logic le_5_le_171_we; logic [1:0] prio0_qs; logic [1:0] prio0_wd; logic prio0_we; @@ -925,6 +1125,156 @@ logic [1:0] prio121_qs; logic [1:0] prio121_wd; logic prio121_we; + logic [1:0] prio122_qs; + logic [1:0] prio122_wd; + logic prio122_we; + logic [1:0] prio123_qs; + logic [1:0] prio123_wd; + logic prio123_we; + logic [1:0] prio124_qs; + logic [1:0] prio124_wd; + logic prio124_we; + logic [1:0] prio125_qs; + logic [1:0] prio125_wd; + logic prio125_we; + logic [1:0] prio126_qs; + logic [1:0] prio126_wd; + logic prio126_we; + logic [1:0] prio127_qs; + logic [1:0] prio127_wd; + logic prio127_we; + logic [1:0] prio128_qs; + logic [1:0] prio128_wd; + logic prio128_we; + logic [1:0] prio129_qs; + logic [1:0] prio129_wd; + logic prio129_we; + logic [1:0] prio130_qs; + logic [1:0] prio130_wd; + logic prio130_we; + logic [1:0] prio131_qs; + logic [1:0] prio131_wd; + logic prio131_we; + logic [1:0] prio132_qs; + logic [1:0] prio132_wd; + logic prio132_we; + logic [1:0] prio133_qs; + logic [1:0] prio133_wd; + logic prio133_we; + logic [1:0] prio134_qs; + logic [1:0] prio134_wd; + logic prio134_we; + logic [1:0] prio135_qs; + logic [1:0] prio135_wd; + logic prio135_we; + logic [1:0] prio136_qs; + logic [1:0] prio136_wd; + logic prio136_we; + logic [1:0] prio137_qs; + logic [1:0] prio137_wd; + logic prio137_we; + logic [1:0] prio138_qs; + logic [1:0] prio138_wd; + logic prio138_we; + logic [1:0] prio139_qs; + logic [1:0] prio139_wd; + logic prio139_we; + logic [1:0] prio140_qs; + logic [1:0] prio140_wd; + logic prio140_we; + logic [1:0] prio141_qs; + logic [1:0] prio141_wd; + logic prio141_we; + logic [1:0] prio142_qs; + logic [1:0] prio142_wd; + logic prio142_we; + logic [1:0] prio143_qs; + logic [1:0] prio143_wd; + logic prio143_we; + logic [1:0] prio144_qs; + logic [1:0] prio144_wd; + logic prio144_we; + logic [1:0] prio145_qs; + logic [1:0] prio145_wd; + logic prio145_we; + logic [1:0] prio146_qs; + logic [1:0] prio146_wd; + logic prio146_we; + logic [1:0] prio147_qs; + logic [1:0] prio147_wd; + logic prio147_we; + logic [1:0] prio148_qs; + logic [1:0] prio148_wd; + logic prio148_we; + logic [1:0] prio149_qs; + logic [1:0] prio149_wd; + logic prio149_we; + logic [1:0] prio150_qs; + logic [1:0] prio150_wd; + logic prio150_we; + logic [1:0] prio151_qs; + logic [1:0] prio151_wd; + logic prio151_we; + logic [1:0] prio152_qs; + logic [1:0] prio152_wd; + logic prio152_we; + logic [1:0] prio153_qs; + logic [1:0] prio153_wd; + logic prio153_we; + logic [1:0] prio154_qs; + logic [1:0] prio154_wd; + logic prio154_we; + logic [1:0] prio155_qs; + logic [1:0] prio155_wd; + logic prio155_we; + logic [1:0] prio156_qs; + logic [1:0] prio156_wd; + logic prio156_we; + logic [1:0] prio157_qs; + logic [1:0] prio157_wd; + logic prio157_we; + logic [1:0] prio158_qs; + logic [1:0] prio158_wd; + logic prio158_we; + logic [1:0] prio159_qs; + logic [1:0] prio159_wd; + logic prio159_we; + logic [1:0] prio160_qs; + logic [1:0] prio160_wd; + logic prio160_we; + logic [1:0] prio161_qs; + logic [1:0] prio161_wd; + logic prio161_we; + logic [1:0] prio162_qs; + logic [1:0] prio162_wd; + logic prio162_we; + logic [1:0] prio163_qs; + logic [1:0] prio163_wd; + logic prio163_we; + logic [1:0] prio164_qs; + logic [1:0] prio164_wd; + logic prio164_we; + logic [1:0] prio165_qs; + logic [1:0] prio165_wd; + logic prio165_we; + logic [1:0] prio166_qs; + logic [1:0] prio166_wd; + logic prio166_we; + logic [1:0] prio167_qs; + logic [1:0] prio167_wd; + logic prio167_we; + logic [1:0] prio168_qs; + logic [1:0] prio168_wd; + logic prio168_we; + logic [1:0] prio169_qs; + logic [1:0] prio169_wd; + logic prio169_we; + logic [1:0] prio170_qs; + logic [1:0] prio170_wd; + logic prio170_we; + logic [1:0] prio171_qs; + logic [1:0] prio171_wd; + logic prio171_we; logic ie0_0_e_0_qs; logic ie0_0_e_0_wd; logic ie0_0_e_0_we; @@ -1291,11 +1641,161 @@ logic ie0_3_e_121_qs; logic ie0_3_e_121_wd; logic ie0_3_e_121_we; + logic ie0_3_e_122_qs; + logic ie0_3_e_122_wd; + logic ie0_3_e_122_we; + logic ie0_3_e_123_qs; + logic ie0_3_e_123_wd; + logic ie0_3_e_123_we; + logic ie0_3_e_124_qs; + logic ie0_3_e_124_wd; + logic ie0_3_e_124_we; + logic ie0_3_e_125_qs; + logic ie0_3_e_125_wd; + logic ie0_3_e_125_we; + logic ie0_3_e_126_qs; + logic ie0_3_e_126_wd; + logic ie0_3_e_126_we; + logic ie0_3_e_127_qs; + logic ie0_3_e_127_wd; + logic ie0_3_e_127_we; + logic ie0_4_e_128_qs; + logic ie0_4_e_128_wd; + logic ie0_4_e_128_we; + logic ie0_4_e_129_qs; + logic ie0_4_e_129_wd; + logic ie0_4_e_129_we; + logic ie0_4_e_130_qs; + logic ie0_4_e_130_wd; + logic ie0_4_e_130_we; + logic ie0_4_e_131_qs; + logic ie0_4_e_131_wd; + logic ie0_4_e_131_we; + logic ie0_4_e_132_qs; + logic ie0_4_e_132_wd; + logic ie0_4_e_132_we; + logic ie0_4_e_133_qs; + logic ie0_4_e_133_wd; + logic ie0_4_e_133_we; + logic ie0_4_e_134_qs; + logic ie0_4_e_134_wd; + logic ie0_4_e_134_we; + logic ie0_4_e_135_qs; + logic ie0_4_e_135_wd; + logic ie0_4_e_135_we; + logic ie0_4_e_136_qs; + logic ie0_4_e_136_wd; + logic ie0_4_e_136_we; + logic ie0_4_e_137_qs; + logic ie0_4_e_137_wd; + logic ie0_4_e_137_we; + logic ie0_4_e_138_qs; + logic ie0_4_e_138_wd; + logic ie0_4_e_138_we; + logic ie0_4_e_139_qs; + logic ie0_4_e_139_wd; + logic ie0_4_e_139_we; + logic ie0_4_e_140_qs; + logic ie0_4_e_140_wd; + logic ie0_4_e_140_we; + logic ie0_4_e_141_qs; + logic ie0_4_e_141_wd; + logic ie0_4_e_141_we; + logic ie0_4_e_142_qs; + logic ie0_4_e_142_wd; + logic ie0_4_e_142_we; + logic ie0_4_e_143_qs; + logic ie0_4_e_143_wd; + logic ie0_4_e_143_we; + logic ie0_4_e_144_qs; + logic ie0_4_e_144_wd; + logic ie0_4_e_144_we; + logic ie0_4_e_145_qs; + logic ie0_4_e_145_wd; + logic ie0_4_e_145_we; + logic ie0_4_e_146_qs; + logic ie0_4_e_146_wd; + logic ie0_4_e_146_we; + logic ie0_4_e_147_qs; + logic ie0_4_e_147_wd; + logic ie0_4_e_147_we; + logic ie0_4_e_148_qs; + logic ie0_4_e_148_wd; + logic ie0_4_e_148_we; + logic ie0_4_e_149_qs; + logic ie0_4_e_149_wd; + logic ie0_4_e_149_we; + logic ie0_4_e_150_qs; + logic ie0_4_e_150_wd; + logic ie0_4_e_150_we; + logic ie0_4_e_151_qs; + logic ie0_4_e_151_wd; + logic ie0_4_e_151_we; + logic ie0_4_e_152_qs; + logic ie0_4_e_152_wd; + logic ie0_4_e_152_we; + logic ie0_4_e_153_qs; + logic ie0_4_e_153_wd; + logic ie0_4_e_153_we; + logic ie0_4_e_154_qs; + logic ie0_4_e_154_wd; + logic ie0_4_e_154_we; + logic ie0_4_e_155_qs; + logic ie0_4_e_155_wd; + logic ie0_4_e_155_we; + logic ie0_4_e_156_qs; + logic ie0_4_e_156_wd; + logic ie0_4_e_156_we; + logic ie0_4_e_157_qs; + logic ie0_4_e_157_wd; + logic ie0_4_e_157_we; + logic ie0_4_e_158_qs; + logic ie0_4_e_158_wd; + logic ie0_4_e_158_we; + logic ie0_4_e_159_qs; + logic ie0_4_e_159_wd; + logic ie0_4_e_159_we; + logic ie0_5_e_160_qs; + logic ie0_5_e_160_wd; + logic ie0_5_e_160_we; + logic ie0_5_e_161_qs; + logic ie0_5_e_161_wd; + logic ie0_5_e_161_we; + logic ie0_5_e_162_qs; + logic ie0_5_e_162_wd; + logic ie0_5_e_162_we; + logic ie0_5_e_163_qs; + logic ie0_5_e_163_wd; + logic ie0_5_e_163_we; + logic ie0_5_e_164_qs; + logic ie0_5_e_164_wd; + logic ie0_5_e_164_we; + logic ie0_5_e_165_qs; + logic ie0_5_e_165_wd; + logic ie0_5_e_165_we; + logic ie0_5_e_166_qs; + logic ie0_5_e_166_wd; + logic ie0_5_e_166_we; + logic ie0_5_e_167_qs; + logic ie0_5_e_167_wd; + logic ie0_5_e_167_we; + logic ie0_5_e_168_qs; + logic ie0_5_e_168_wd; + logic ie0_5_e_168_we; + logic ie0_5_e_169_qs; + logic ie0_5_e_169_wd; + logic ie0_5_e_169_we; + logic ie0_5_e_170_qs; + logic ie0_5_e_170_wd; + logic ie0_5_e_170_we; + logic ie0_5_e_171_qs; + logic ie0_5_e_171_wd; + logic ie0_5_e_171_we; logic [1:0] threshold0_qs; logic [1:0] threshold0_wd; logic threshold0_we; - logic [6:0] cc0_qs; - logic [6:0] cc0_wd; + logic [7:0] cc0_qs; + logic [7:0] cc0_wd; logic cc0_we; logic cc0_re; logic msip0_qs; @@ -4366,6 +4866,1262 @@ ); + // F[p_122]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_3_p_122 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[122].de), + .d (hw2reg.ip[122].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_3_p_122_qs) + ); + + + // F[p_123]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_3_p_123 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[123].de), + .d (hw2reg.ip[123].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_3_p_123_qs) + ); + + + // F[p_124]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_3_p_124 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[124].de), + .d (hw2reg.ip[124].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_3_p_124_qs) + ); + + + // F[p_125]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_3_p_125 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[125].de), + .d (hw2reg.ip[125].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_3_p_125_qs) + ); + + + // F[p_126]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_3_p_126 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[126].de), + .d (hw2reg.ip[126].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_3_p_126_qs) + ); + + + // F[p_127]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_3_p_127 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[127].de), + .d (hw2reg.ip[127].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_3_p_127_qs) + ); + + + // Subregister 128 of Multireg ip + // R[ip_4]: V(False) + + // F[p_128]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_128 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[128].de), + .d (hw2reg.ip[128].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_128_qs) + ); + + + // F[p_129]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_129 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[129].de), + .d (hw2reg.ip[129].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_129_qs) + ); + + + // F[p_130]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_130 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[130].de), + .d (hw2reg.ip[130].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_130_qs) + ); + + + // F[p_131]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_131 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[131].de), + .d (hw2reg.ip[131].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_131_qs) + ); + + + // F[p_132]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_132 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[132].de), + .d (hw2reg.ip[132].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_132_qs) + ); + + + // F[p_133]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_133 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[133].de), + .d (hw2reg.ip[133].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_133_qs) + ); + + + // F[p_134]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_134 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[134].de), + .d (hw2reg.ip[134].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_134_qs) + ); + + + // F[p_135]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_135 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[135].de), + .d (hw2reg.ip[135].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_135_qs) + ); + + + // F[p_136]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_136 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[136].de), + .d (hw2reg.ip[136].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_136_qs) + ); + + + // F[p_137]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_137 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[137].de), + .d (hw2reg.ip[137].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_137_qs) + ); + + + // F[p_138]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_138 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[138].de), + .d (hw2reg.ip[138].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_138_qs) + ); + + + // F[p_139]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_139 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[139].de), + .d (hw2reg.ip[139].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_139_qs) + ); + + + // F[p_140]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_140 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[140].de), + .d (hw2reg.ip[140].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_140_qs) + ); + + + // F[p_141]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_141 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[141].de), + .d (hw2reg.ip[141].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_141_qs) + ); + + + // F[p_142]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_142 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[142].de), + .d (hw2reg.ip[142].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_142_qs) + ); + + + // F[p_143]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_143 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[143].de), + .d (hw2reg.ip[143].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_143_qs) + ); + + + // F[p_144]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_144 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[144].de), + .d (hw2reg.ip[144].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_144_qs) + ); + + + // F[p_145]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_145 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[145].de), + .d (hw2reg.ip[145].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_145_qs) + ); + + + // F[p_146]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_146 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[146].de), + .d (hw2reg.ip[146].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_146_qs) + ); + + + // F[p_147]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_147 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[147].de), + .d (hw2reg.ip[147].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_147_qs) + ); + + + // F[p_148]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_148 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[148].de), + .d (hw2reg.ip[148].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_148_qs) + ); + + + // F[p_149]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_149 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[149].de), + .d (hw2reg.ip[149].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_149_qs) + ); + + + // F[p_150]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_150 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[150].de), + .d (hw2reg.ip[150].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_150_qs) + ); + + + // F[p_151]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_151 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[151].de), + .d (hw2reg.ip[151].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_151_qs) + ); + + + // F[p_152]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_152 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[152].de), + .d (hw2reg.ip[152].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_152_qs) + ); + + + // F[p_153]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_153 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[153].de), + .d (hw2reg.ip[153].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_153_qs) + ); + + + // F[p_154]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_154 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[154].de), + .d (hw2reg.ip[154].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_154_qs) + ); + + + // F[p_155]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_155 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[155].de), + .d (hw2reg.ip[155].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_155_qs) + ); + + + // F[p_156]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_156 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[156].de), + .d (hw2reg.ip[156].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_156_qs) + ); + + + // F[p_157]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_157 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[157].de), + .d (hw2reg.ip[157].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_157_qs) + ); + + + // F[p_158]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_158 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[158].de), + .d (hw2reg.ip[158].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_158_qs) + ); + + + // F[p_159]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_4_p_159 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[159].de), + .d (hw2reg.ip[159].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_4_p_159_qs) + ); + + + // Subregister 160 of Multireg ip + // R[ip_5]: V(False) + + // F[p_160]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_5_p_160 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[160].de), + .d (hw2reg.ip[160].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_5_p_160_qs) + ); + + + // F[p_161]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_5_p_161 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[161].de), + .d (hw2reg.ip[161].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_5_p_161_qs) + ); + + + // F[p_162]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_5_p_162 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[162].de), + .d (hw2reg.ip[162].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_5_p_162_qs) + ); + + + // F[p_163]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_5_p_163 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[163].de), + .d (hw2reg.ip[163].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_5_p_163_qs) + ); + + + // F[p_164]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_5_p_164 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[164].de), + .d (hw2reg.ip[164].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_5_p_164_qs) + ); + + + // F[p_165]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_5_p_165 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[165].de), + .d (hw2reg.ip[165].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_5_p_165_qs) + ); + + + // F[p_166]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_5_p_166 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[166].de), + .d (hw2reg.ip[166].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_5_p_166_qs) + ); + + + // F[p_167]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_5_p_167 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[167].de), + .d (hw2reg.ip[167].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_5_p_167_qs) + ); + + + // F[p_168]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_5_p_168 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[168].de), + .d (hw2reg.ip[168].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_5_p_168_qs) + ); + + + // F[p_169]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_5_p_169 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[169].de), + .d (hw2reg.ip[169].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_5_p_169_qs) + ); + + + // F[p_170]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_5_p_170 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[170].de), + .d (hw2reg.ip[170].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_5_p_170_qs) + ); + + + // F[p_171]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_ip_5_p_171 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.ip[171].de), + .d (hw2reg.ip[171].d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (ip_5_p_171_qs) + ); + + // Subregister 0 of Multireg le @@ -7552,6 +9308,1312 @@ ); + // F[le_122]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_3_le_122 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_3_le_122_we), + .wd (le_3_le_122_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[122].q ), + + // to register interface (read) + .qs (le_3_le_122_qs) + ); + + + // F[le_123]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_3_le_123 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_3_le_123_we), + .wd (le_3_le_123_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[123].q ), + + // to register interface (read) + .qs (le_3_le_123_qs) + ); + + + // F[le_124]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_3_le_124 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_3_le_124_we), + .wd (le_3_le_124_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[124].q ), + + // to register interface (read) + .qs (le_3_le_124_qs) + ); + + + // F[le_125]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_3_le_125 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_3_le_125_we), + .wd (le_3_le_125_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[125].q ), + + // to register interface (read) + .qs (le_3_le_125_qs) + ); + + + // F[le_126]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_3_le_126 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_3_le_126_we), + .wd (le_3_le_126_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[126].q ), + + // to register interface (read) + .qs (le_3_le_126_qs) + ); + + + // F[le_127]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_3_le_127 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_3_le_127_we), + .wd (le_3_le_127_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[127].q ), + + // to register interface (read) + .qs (le_3_le_127_qs) + ); + + + // Subregister 128 of Multireg le + // R[le_4]: V(False) + + // F[le_128]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_128 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_128_we), + .wd (le_4_le_128_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[128].q ), + + // to register interface (read) + .qs (le_4_le_128_qs) + ); + + + // F[le_129]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_129 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_129_we), + .wd (le_4_le_129_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[129].q ), + + // to register interface (read) + .qs (le_4_le_129_qs) + ); + + + // F[le_130]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_130 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_130_we), + .wd (le_4_le_130_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[130].q ), + + // to register interface (read) + .qs (le_4_le_130_qs) + ); + + + // F[le_131]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_131 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_131_we), + .wd (le_4_le_131_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[131].q ), + + // to register interface (read) + .qs (le_4_le_131_qs) + ); + + + // F[le_132]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_132 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_132_we), + .wd (le_4_le_132_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[132].q ), + + // to register interface (read) + .qs (le_4_le_132_qs) + ); + + + // F[le_133]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_133 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_133_we), + .wd (le_4_le_133_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[133].q ), + + // to register interface (read) + .qs (le_4_le_133_qs) + ); + + + // F[le_134]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_134 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_134_we), + .wd (le_4_le_134_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[134].q ), + + // to register interface (read) + .qs (le_4_le_134_qs) + ); + + + // F[le_135]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_135 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_135_we), + .wd (le_4_le_135_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[135].q ), + + // to register interface (read) + .qs (le_4_le_135_qs) + ); + + + // F[le_136]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_136 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_136_we), + .wd (le_4_le_136_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[136].q ), + + // to register interface (read) + .qs (le_4_le_136_qs) + ); + + + // F[le_137]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_137 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_137_we), + .wd (le_4_le_137_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[137].q ), + + // to register interface (read) + .qs (le_4_le_137_qs) + ); + + + // F[le_138]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_138 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_138_we), + .wd (le_4_le_138_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[138].q ), + + // to register interface (read) + .qs (le_4_le_138_qs) + ); + + + // F[le_139]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_139 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_139_we), + .wd (le_4_le_139_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[139].q ), + + // to register interface (read) + .qs (le_4_le_139_qs) + ); + + + // F[le_140]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_140 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_140_we), + .wd (le_4_le_140_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[140].q ), + + // to register interface (read) + .qs (le_4_le_140_qs) + ); + + + // F[le_141]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_141 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_141_we), + .wd (le_4_le_141_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[141].q ), + + // to register interface (read) + .qs (le_4_le_141_qs) + ); + + + // F[le_142]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_142 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_142_we), + .wd (le_4_le_142_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[142].q ), + + // to register interface (read) + .qs (le_4_le_142_qs) + ); + + + // F[le_143]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_143 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_143_we), + .wd (le_4_le_143_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[143].q ), + + // to register interface (read) + .qs (le_4_le_143_qs) + ); + + + // F[le_144]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_144 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_144_we), + .wd (le_4_le_144_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[144].q ), + + // to register interface (read) + .qs (le_4_le_144_qs) + ); + + + // F[le_145]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_145 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_145_we), + .wd (le_4_le_145_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[145].q ), + + // to register interface (read) + .qs (le_4_le_145_qs) + ); + + + // F[le_146]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_146 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_146_we), + .wd (le_4_le_146_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[146].q ), + + // to register interface (read) + .qs (le_4_le_146_qs) + ); + + + // F[le_147]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_147 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_147_we), + .wd (le_4_le_147_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[147].q ), + + // to register interface (read) + .qs (le_4_le_147_qs) + ); + + + // F[le_148]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_148 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_148_we), + .wd (le_4_le_148_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[148].q ), + + // to register interface (read) + .qs (le_4_le_148_qs) + ); + + + // F[le_149]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_149 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_149_we), + .wd (le_4_le_149_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[149].q ), + + // to register interface (read) + .qs (le_4_le_149_qs) + ); + + + // F[le_150]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_150 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_150_we), + .wd (le_4_le_150_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[150].q ), + + // to register interface (read) + .qs (le_4_le_150_qs) + ); + + + // F[le_151]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_151 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_151_we), + .wd (le_4_le_151_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[151].q ), + + // to register interface (read) + .qs (le_4_le_151_qs) + ); + + + // F[le_152]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_152 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_152_we), + .wd (le_4_le_152_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[152].q ), + + // to register interface (read) + .qs (le_4_le_152_qs) + ); + + + // F[le_153]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_153 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_153_we), + .wd (le_4_le_153_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[153].q ), + + // to register interface (read) + .qs (le_4_le_153_qs) + ); + + + // F[le_154]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_154 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_154_we), + .wd (le_4_le_154_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[154].q ), + + // to register interface (read) + .qs (le_4_le_154_qs) + ); + + + // F[le_155]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_155 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_155_we), + .wd (le_4_le_155_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[155].q ), + + // to register interface (read) + .qs (le_4_le_155_qs) + ); + + + // F[le_156]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_156 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_156_we), + .wd (le_4_le_156_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[156].q ), + + // to register interface (read) + .qs (le_4_le_156_qs) + ); + + + // F[le_157]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_157 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_157_we), + .wd (le_4_le_157_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[157].q ), + + // to register interface (read) + .qs (le_4_le_157_qs) + ); + + + // F[le_158]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_158 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_158_we), + .wd (le_4_le_158_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[158].q ), + + // to register interface (read) + .qs (le_4_le_158_qs) + ); + + + // F[le_159]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_4_le_159 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_4_le_159_we), + .wd (le_4_le_159_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[159].q ), + + // to register interface (read) + .qs (le_4_le_159_qs) + ); + + + // Subregister 160 of Multireg le + // R[le_5]: V(False) + + // F[le_160]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_5_le_160 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_5_le_160_we), + .wd (le_5_le_160_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[160].q ), + + // to register interface (read) + .qs (le_5_le_160_qs) + ); + + + // F[le_161]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_5_le_161 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_5_le_161_we), + .wd (le_5_le_161_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[161].q ), + + // to register interface (read) + .qs (le_5_le_161_qs) + ); + + + // F[le_162]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_5_le_162 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_5_le_162_we), + .wd (le_5_le_162_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[162].q ), + + // to register interface (read) + .qs (le_5_le_162_qs) + ); + + + // F[le_163]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_5_le_163 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_5_le_163_we), + .wd (le_5_le_163_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[163].q ), + + // to register interface (read) + .qs (le_5_le_163_qs) + ); + + + // F[le_164]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_5_le_164 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_5_le_164_we), + .wd (le_5_le_164_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[164].q ), + + // to register interface (read) + .qs (le_5_le_164_qs) + ); + + + // F[le_165]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_5_le_165 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_5_le_165_we), + .wd (le_5_le_165_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[165].q ), + + // to register interface (read) + .qs (le_5_le_165_qs) + ); + + + // F[le_166]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_5_le_166 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_5_le_166_we), + .wd (le_5_le_166_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[166].q ), + + // to register interface (read) + .qs (le_5_le_166_qs) + ); + + + // F[le_167]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_5_le_167 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_5_le_167_we), + .wd (le_5_le_167_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[167].q ), + + // to register interface (read) + .qs (le_5_le_167_qs) + ); + + + // F[le_168]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_5_le_168 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_5_le_168_we), + .wd (le_5_le_168_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[168].q ), + + // to register interface (read) + .qs (le_5_le_168_qs) + ); + + + // F[le_169]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_5_le_169 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_5_le_169_we), + .wd (le_5_le_169_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[169].q ), + + // to register interface (read) + .qs (le_5_le_169_qs) + ); + + + // F[le_170]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_5_le_170 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_5_le_170_we), + .wd (le_5_le_170_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[170].q ), + + // to register interface (read) + .qs (le_5_le_170_qs) + ); + + + // F[le_171]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_le_5_le_171 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (le_5_le_171_we), + .wd (le_5_le_171_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.le[171].q ), + + // to register interface (read) + .qs (le_5_le_171_qs) + ); + + // R[prio0]: V(False) @@ -10847,6 +13909,1356 @@ ); + // R[prio122]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio122 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio122_we), + .wd (prio122_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio122.q ), + + // to register interface (read) + .qs (prio122_qs) + ); + + + // R[prio123]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio123 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio123_we), + .wd (prio123_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio123.q ), + + // to register interface (read) + .qs (prio123_qs) + ); + + + // R[prio124]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio124 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio124_we), + .wd (prio124_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio124.q ), + + // to register interface (read) + .qs (prio124_qs) + ); + + + // R[prio125]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio125 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio125_we), + .wd (prio125_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio125.q ), + + // to register interface (read) + .qs (prio125_qs) + ); + + + // R[prio126]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio126 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio126_we), + .wd (prio126_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio126.q ), + + // to register interface (read) + .qs (prio126_qs) + ); + + + // R[prio127]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio127 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio127_we), + .wd (prio127_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio127.q ), + + // to register interface (read) + .qs (prio127_qs) + ); + + + // R[prio128]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio128 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio128_we), + .wd (prio128_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio128.q ), + + // to register interface (read) + .qs (prio128_qs) + ); + + + // R[prio129]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio129 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio129_we), + .wd (prio129_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio129.q ), + + // to register interface (read) + .qs (prio129_qs) + ); + + + // R[prio130]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio130 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio130_we), + .wd (prio130_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio130.q ), + + // to register interface (read) + .qs (prio130_qs) + ); + + + // R[prio131]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio131 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio131_we), + .wd (prio131_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio131.q ), + + // to register interface (read) + .qs (prio131_qs) + ); + + + // R[prio132]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio132 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio132_we), + .wd (prio132_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio132.q ), + + // to register interface (read) + .qs (prio132_qs) + ); + + + // R[prio133]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio133 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio133_we), + .wd (prio133_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio133.q ), + + // to register interface (read) + .qs (prio133_qs) + ); + + + // R[prio134]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio134 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio134_we), + .wd (prio134_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio134.q ), + + // to register interface (read) + .qs (prio134_qs) + ); + + + // R[prio135]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio135 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio135_we), + .wd (prio135_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio135.q ), + + // to register interface (read) + .qs (prio135_qs) + ); + + + // R[prio136]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio136 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio136_we), + .wd (prio136_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio136.q ), + + // to register interface (read) + .qs (prio136_qs) + ); + + + // R[prio137]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio137 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio137_we), + .wd (prio137_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio137.q ), + + // to register interface (read) + .qs (prio137_qs) + ); + + + // R[prio138]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio138 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio138_we), + .wd (prio138_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio138.q ), + + // to register interface (read) + .qs (prio138_qs) + ); + + + // R[prio139]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio139 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio139_we), + .wd (prio139_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio139.q ), + + // to register interface (read) + .qs (prio139_qs) + ); + + + // R[prio140]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio140 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio140_we), + .wd (prio140_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio140.q ), + + // to register interface (read) + .qs (prio140_qs) + ); + + + // R[prio141]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio141 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio141_we), + .wd (prio141_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio141.q ), + + // to register interface (read) + .qs (prio141_qs) + ); + + + // R[prio142]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio142 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio142_we), + .wd (prio142_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio142.q ), + + // to register interface (read) + .qs (prio142_qs) + ); + + + // R[prio143]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio143 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio143_we), + .wd (prio143_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio143.q ), + + // to register interface (read) + .qs (prio143_qs) + ); + + + // R[prio144]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio144 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio144_we), + .wd (prio144_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio144.q ), + + // to register interface (read) + .qs (prio144_qs) + ); + + + // R[prio145]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio145 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio145_we), + .wd (prio145_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio145.q ), + + // to register interface (read) + .qs (prio145_qs) + ); + + + // R[prio146]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio146 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio146_we), + .wd (prio146_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio146.q ), + + // to register interface (read) + .qs (prio146_qs) + ); + + + // R[prio147]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio147 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio147_we), + .wd (prio147_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio147.q ), + + // to register interface (read) + .qs (prio147_qs) + ); + + + // R[prio148]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio148 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio148_we), + .wd (prio148_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio148.q ), + + // to register interface (read) + .qs (prio148_qs) + ); + + + // R[prio149]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio149 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio149_we), + .wd (prio149_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio149.q ), + + // to register interface (read) + .qs (prio149_qs) + ); + + + // R[prio150]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio150 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio150_we), + .wd (prio150_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio150.q ), + + // to register interface (read) + .qs (prio150_qs) + ); + + + // R[prio151]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio151 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio151_we), + .wd (prio151_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio151.q ), + + // to register interface (read) + .qs (prio151_qs) + ); + + + // R[prio152]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio152 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio152_we), + .wd (prio152_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio152.q ), + + // to register interface (read) + .qs (prio152_qs) + ); + + + // R[prio153]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio153 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio153_we), + .wd (prio153_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio153.q ), + + // to register interface (read) + .qs (prio153_qs) + ); + + + // R[prio154]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio154 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio154_we), + .wd (prio154_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio154.q ), + + // to register interface (read) + .qs (prio154_qs) + ); + + + // R[prio155]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio155 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio155_we), + .wd (prio155_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio155.q ), + + // to register interface (read) + .qs (prio155_qs) + ); + + + // R[prio156]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio156 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio156_we), + .wd (prio156_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio156.q ), + + // to register interface (read) + .qs (prio156_qs) + ); + + + // R[prio157]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio157 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio157_we), + .wd (prio157_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio157.q ), + + // to register interface (read) + .qs (prio157_qs) + ); + + + // R[prio158]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio158 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio158_we), + .wd (prio158_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio158.q ), + + // to register interface (read) + .qs (prio158_qs) + ); + + + // R[prio159]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio159 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio159_we), + .wd (prio159_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio159.q ), + + // to register interface (read) + .qs (prio159_qs) + ); + + + // R[prio160]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio160 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio160_we), + .wd (prio160_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio160.q ), + + // to register interface (read) + .qs (prio160_qs) + ); + + + // R[prio161]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio161 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio161_we), + .wd (prio161_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio161.q ), + + // to register interface (read) + .qs (prio161_qs) + ); + + + // R[prio162]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio162 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio162_we), + .wd (prio162_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio162.q ), + + // to register interface (read) + .qs (prio162_qs) + ); + + + // R[prio163]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio163 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio163_we), + .wd (prio163_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio163.q ), + + // to register interface (read) + .qs (prio163_qs) + ); + + + // R[prio164]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio164 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio164_we), + .wd (prio164_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio164.q ), + + // to register interface (read) + .qs (prio164_qs) + ); + + + // R[prio165]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio165 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio165_we), + .wd (prio165_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio165.q ), + + // to register interface (read) + .qs (prio165_qs) + ); + + + // R[prio166]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio166 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio166_we), + .wd (prio166_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio166.q ), + + // to register interface (read) + .qs (prio166_qs) + ); + + + // R[prio167]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio167 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio167_we), + .wd (prio167_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio167.q ), + + // to register interface (read) + .qs (prio167_qs) + ); + + + // R[prio168]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio168 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio168_we), + .wd (prio168_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio168.q ), + + // to register interface (read) + .qs (prio168_qs) + ); + + + // R[prio169]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio169 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio169_we), + .wd (prio169_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio169.q ), + + // to register interface (read) + .qs (prio169_qs) + ); + + + // R[prio170]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio170 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio170_we), + .wd (prio170_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio170.q ), + + // to register interface (read) + .qs (prio170_qs) + ); + + + // R[prio171]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_prio171 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (prio171_we), + .wd (prio171_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.prio171.q ), + + // to register interface (read) + .qs (prio171_qs) + ); + + // Subregister 0 of Multireg ie0 // R[ie0_0]: V(False) @@ -14032,6 +18444,1312 @@ ); + // F[e_122]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_3_e_122 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_3_e_122_we), + .wd (ie0_3_e_122_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[122].q ), + + // to register interface (read) + .qs (ie0_3_e_122_qs) + ); + + + // F[e_123]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_3_e_123 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_3_e_123_we), + .wd (ie0_3_e_123_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[123].q ), + + // to register interface (read) + .qs (ie0_3_e_123_qs) + ); + + + // F[e_124]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_3_e_124 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_3_e_124_we), + .wd (ie0_3_e_124_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[124].q ), + + // to register interface (read) + .qs (ie0_3_e_124_qs) + ); + + + // F[e_125]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_3_e_125 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_3_e_125_we), + .wd (ie0_3_e_125_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[125].q ), + + // to register interface (read) + .qs (ie0_3_e_125_qs) + ); + + + // F[e_126]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_3_e_126 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_3_e_126_we), + .wd (ie0_3_e_126_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[126].q ), + + // to register interface (read) + .qs (ie0_3_e_126_qs) + ); + + + // F[e_127]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_3_e_127 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_3_e_127_we), + .wd (ie0_3_e_127_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[127].q ), + + // to register interface (read) + .qs (ie0_3_e_127_qs) + ); + + + // Subregister 128 of Multireg ie0 + // R[ie0_4]: V(False) + + // F[e_128]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_128 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_128_we), + .wd (ie0_4_e_128_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[128].q ), + + // to register interface (read) + .qs (ie0_4_e_128_qs) + ); + + + // F[e_129]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_129 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_129_we), + .wd (ie0_4_e_129_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[129].q ), + + // to register interface (read) + .qs (ie0_4_e_129_qs) + ); + + + // F[e_130]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_130 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_130_we), + .wd (ie0_4_e_130_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[130].q ), + + // to register interface (read) + .qs (ie0_4_e_130_qs) + ); + + + // F[e_131]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_131 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_131_we), + .wd (ie0_4_e_131_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[131].q ), + + // to register interface (read) + .qs (ie0_4_e_131_qs) + ); + + + // F[e_132]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_132 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_132_we), + .wd (ie0_4_e_132_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[132].q ), + + // to register interface (read) + .qs (ie0_4_e_132_qs) + ); + + + // F[e_133]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_133 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_133_we), + .wd (ie0_4_e_133_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[133].q ), + + // to register interface (read) + .qs (ie0_4_e_133_qs) + ); + + + // F[e_134]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_134 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_134_we), + .wd (ie0_4_e_134_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[134].q ), + + // to register interface (read) + .qs (ie0_4_e_134_qs) + ); + + + // F[e_135]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_135 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_135_we), + .wd (ie0_4_e_135_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[135].q ), + + // to register interface (read) + .qs (ie0_4_e_135_qs) + ); + + + // F[e_136]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_136 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_136_we), + .wd (ie0_4_e_136_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[136].q ), + + // to register interface (read) + .qs (ie0_4_e_136_qs) + ); + + + // F[e_137]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_137 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_137_we), + .wd (ie0_4_e_137_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[137].q ), + + // to register interface (read) + .qs (ie0_4_e_137_qs) + ); + + + // F[e_138]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_138 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_138_we), + .wd (ie0_4_e_138_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[138].q ), + + // to register interface (read) + .qs (ie0_4_e_138_qs) + ); + + + // F[e_139]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_139 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_139_we), + .wd (ie0_4_e_139_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[139].q ), + + // to register interface (read) + .qs (ie0_4_e_139_qs) + ); + + + // F[e_140]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_140 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_140_we), + .wd (ie0_4_e_140_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[140].q ), + + // to register interface (read) + .qs (ie0_4_e_140_qs) + ); + + + // F[e_141]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_141 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_141_we), + .wd (ie0_4_e_141_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[141].q ), + + // to register interface (read) + .qs (ie0_4_e_141_qs) + ); + + + // F[e_142]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_142 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_142_we), + .wd (ie0_4_e_142_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[142].q ), + + // to register interface (read) + .qs (ie0_4_e_142_qs) + ); + + + // F[e_143]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_143 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_143_we), + .wd (ie0_4_e_143_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[143].q ), + + // to register interface (read) + .qs (ie0_4_e_143_qs) + ); + + + // F[e_144]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_144 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_144_we), + .wd (ie0_4_e_144_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[144].q ), + + // to register interface (read) + .qs (ie0_4_e_144_qs) + ); + + + // F[e_145]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_145 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_145_we), + .wd (ie0_4_e_145_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[145].q ), + + // to register interface (read) + .qs (ie0_4_e_145_qs) + ); + + + // F[e_146]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_146 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_146_we), + .wd (ie0_4_e_146_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[146].q ), + + // to register interface (read) + .qs (ie0_4_e_146_qs) + ); + + + // F[e_147]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_147 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_147_we), + .wd (ie0_4_e_147_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[147].q ), + + // to register interface (read) + .qs (ie0_4_e_147_qs) + ); + + + // F[e_148]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_148 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_148_we), + .wd (ie0_4_e_148_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[148].q ), + + // to register interface (read) + .qs (ie0_4_e_148_qs) + ); + + + // F[e_149]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_149 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_149_we), + .wd (ie0_4_e_149_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[149].q ), + + // to register interface (read) + .qs (ie0_4_e_149_qs) + ); + + + // F[e_150]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_150 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_150_we), + .wd (ie0_4_e_150_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[150].q ), + + // to register interface (read) + .qs (ie0_4_e_150_qs) + ); + + + // F[e_151]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_151 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_151_we), + .wd (ie0_4_e_151_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[151].q ), + + // to register interface (read) + .qs (ie0_4_e_151_qs) + ); + + + // F[e_152]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_152 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_152_we), + .wd (ie0_4_e_152_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[152].q ), + + // to register interface (read) + .qs (ie0_4_e_152_qs) + ); + + + // F[e_153]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_153 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_153_we), + .wd (ie0_4_e_153_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[153].q ), + + // to register interface (read) + .qs (ie0_4_e_153_qs) + ); + + + // F[e_154]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_154 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_154_we), + .wd (ie0_4_e_154_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[154].q ), + + // to register interface (read) + .qs (ie0_4_e_154_qs) + ); + + + // F[e_155]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_155 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_155_we), + .wd (ie0_4_e_155_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[155].q ), + + // to register interface (read) + .qs (ie0_4_e_155_qs) + ); + + + // F[e_156]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_156 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_156_we), + .wd (ie0_4_e_156_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[156].q ), + + // to register interface (read) + .qs (ie0_4_e_156_qs) + ); + + + // F[e_157]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_157 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_157_we), + .wd (ie0_4_e_157_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[157].q ), + + // to register interface (read) + .qs (ie0_4_e_157_qs) + ); + + + // F[e_158]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_158 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_158_we), + .wd (ie0_4_e_158_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[158].q ), + + // to register interface (read) + .qs (ie0_4_e_158_qs) + ); + + + // F[e_159]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_4_e_159 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_4_e_159_we), + .wd (ie0_4_e_159_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[159].q ), + + // to register interface (read) + .qs (ie0_4_e_159_qs) + ); + + + // Subregister 160 of Multireg ie0 + // R[ie0_5]: V(False) + + // F[e_160]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_5_e_160 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_5_e_160_we), + .wd (ie0_5_e_160_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[160].q ), + + // to register interface (read) + .qs (ie0_5_e_160_qs) + ); + + + // F[e_161]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_5_e_161 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_5_e_161_we), + .wd (ie0_5_e_161_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[161].q ), + + // to register interface (read) + .qs (ie0_5_e_161_qs) + ); + + + // F[e_162]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_5_e_162 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_5_e_162_we), + .wd (ie0_5_e_162_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[162].q ), + + // to register interface (read) + .qs (ie0_5_e_162_qs) + ); + + + // F[e_163]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_5_e_163 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_5_e_163_we), + .wd (ie0_5_e_163_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[163].q ), + + // to register interface (read) + .qs (ie0_5_e_163_qs) + ); + + + // F[e_164]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_5_e_164 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_5_e_164_we), + .wd (ie0_5_e_164_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[164].q ), + + // to register interface (read) + .qs (ie0_5_e_164_qs) + ); + + + // F[e_165]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_5_e_165 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_5_e_165_we), + .wd (ie0_5_e_165_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[165].q ), + + // to register interface (read) + .qs (ie0_5_e_165_qs) + ); + + + // F[e_166]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_5_e_166 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_5_e_166_we), + .wd (ie0_5_e_166_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[166].q ), + + // to register interface (read) + .qs (ie0_5_e_166_qs) + ); + + + // F[e_167]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_5_e_167 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_5_e_167_we), + .wd (ie0_5_e_167_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[167].q ), + + // to register interface (read) + .qs (ie0_5_e_167_qs) + ); + + + // F[e_168]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_5_e_168 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_5_e_168_we), + .wd (ie0_5_e_168_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[168].q ), + + // to register interface (read) + .qs (ie0_5_e_168_qs) + ); + + + // F[e_169]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_5_e_169 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_5_e_169_we), + .wd (ie0_5_e_169_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[169].q ), + + // to register interface (read) + .qs (ie0_5_e_169_qs) + ); + + + // F[e_170]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_5_e_170 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_5_e_170_we), + .wd (ie0_5_e_170_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[170].q ), + + // to register interface (read) + .qs (ie0_5_e_170_qs) + ); + + + // F[e_171]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ie0_5_e_171 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ie0_5_e_171_we), + .wd (ie0_5_e_171_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[171].q ), + + // to register interface (read) + .qs (ie0_5_e_171_qs) + ); + + // R[threshold0]: V(False) @@ -14063,7 +19781,7 @@ // R[cc0]: V(True) prim_subreg_ext #( - .DW (7) + .DW (8) ) u_cc0 ( .re (cc0_re), .we (cc0_we), @@ -14105,146 +19823,202 @@ - logic [136:0] addr_hit; + logic [192:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == RV_PLIC_IP_0_OFFSET); addr_hit[ 1] = (reg_addr == RV_PLIC_IP_1_OFFSET); addr_hit[ 2] = (reg_addr == RV_PLIC_IP_2_OFFSET); addr_hit[ 3] = (reg_addr == RV_PLIC_IP_3_OFFSET); - addr_hit[ 4] = (reg_addr == RV_PLIC_LE_0_OFFSET); - addr_hit[ 5] = (reg_addr == RV_PLIC_LE_1_OFFSET); - addr_hit[ 6] = (reg_addr == RV_PLIC_LE_2_OFFSET); - addr_hit[ 7] = (reg_addr == RV_PLIC_LE_3_OFFSET); - addr_hit[ 8] = (reg_addr == RV_PLIC_PRIO0_OFFSET); - addr_hit[ 9] = (reg_addr == RV_PLIC_PRIO1_OFFSET); - addr_hit[ 10] = (reg_addr == RV_PLIC_PRIO2_OFFSET); - addr_hit[ 11] = (reg_addr == RV_PLIC_PRIO3_OFFSET); - addr_hit[ 12] = (reg_addr == RV_PLIC_PRIO4_OFFSET); - addr_hit[ 13] = (reg_addr == RV_PLIC_PRIO5_OFFSET); - addr_hit[ 14] = (reg_addr == RV_PLIC_PRIO6_OFFSET); - addr_hit[ 15] = (reg_addr == RV_PLIC_PRIO7_OFFSET); - addr_hit[ 16] = (reg_addr == RV_PLIC_PRIO8_OFFSET); - addr_hit[ 17] = (reg_addr == RV_PLIC_PRIO9_OFFSET); - addr_hit[ 18] = (reg_addr == RV_PLIC_PRIO10_OFFSET); - addr_hit[ 19] = (reg_addr == RV_PLIC_PRIO11_OFFSET); - addr_hit[ 20] = (reg_addr == RV_PLIC_PRIO12_OFFSET); - addr_hit[ 21] = (reg_addr == RV_PLIC_PRIO13_OFFSET); - addr_hit[ 22] = (reg_addr == RV_PLIC_PRIO14_OFFSET); - addr_hit[ 23] = (reg_addr == RV_PLIC_PRIO15_OFFSET); - addr_hit[ 24] = (reg_addr == RV_PLIC_PRIO16_OFFSET); - addr_hit[ 25] = (reg_addr == RV_PLIC_PRIO17_OFFSET); - addr_hit[ 26] = (reg_addr == RV_PLIC_PRIO18_OFFSET); - addr_hit[ 27] = (reg_addr == RV_PLIC_PRIO19_OFFSET); - addr_hit[ 28] = (reg_addr == RV_PLIC_PRIO20_OFFSET); - addr_hit[ 29] = (reg_addr == RV_PLIC_PRIO21_OFFSET); - addr_hit[ 30] = (reg_addr == RV_PLIC_PRIO22_OFFSET); - addr_hit[ 31] = (reg_addr == RV_PLIC_PRIO23_OFFSET); - addr_hit[ 32] = (reg_addr == RV_PLIC_PRIO24_OFFSET); - addr_hit[ 33] = (reg_addr == RV_PLIC_PRIO25_OFFSET); - addr_hit[ 34] = (reg_addr == RV_PLIC_PRIO26_OFFSET); - addr_hit[ 35] = (reg_addr == RV_PLIC_PRIO27_OFFSET); - addr_hit[ 36] = (reg_addr == RV_PLIC_PRIO28_OFFSET); - addr_hit[ 37] = (reg_addr == RV_PLIC_PRIO29_OFFSET); - addr_hit[ 38] = (reg_addr == RV_PLIC_PRIO30_OFFSET); - addr_hit[ 39] = (reg_addr == RV_PLIC_PRIO31_OFFSET); - addr_hit[ 40] = (reg_addr == RV_PLIC_PRIO32_OFFSET); - addr_hit[ 41] = (reg_addr == RV_PLIC_PRIO33_OFFSET); - addr_hit[ 42] = (reg_addr == RV_PLIC_PRIO34_OFFSET); - addr_hit[ 43] = (reg_addr == RV_PLIC_PRIO35_OFFSET); - addr_hit[ 44] = (reg_addr == RV_PLIC_PRIO36_OFFSET); - addr_hit[ 45] = (reg_addr == RV_PLIC_PRIO37_OFFSET); - addr_hit[ 46] = (reg_addr == RV_PLIC_PRIO38_OFFSET); - addr_hit[ 47] = (reg_addr == RV_PLIC_PRIO39_OFFSET); - addr_hit[ 48] = (reg_addr == RV_PLIC_PRIO40_OFFSET); - addr_hit[ 49] = (reg_addr == RV_PLIC_PRIO41_OFFSET); - addr_hit[ 50] = (reg_addr == RV_PLIC_PRIO42_OFFSET); - addr_hit[ 51] = (reg_addr == RV_PLIC_PRIO43_OFFSET); - addr_hit[ 52] = (reg_addr == RV_PLIC_PRIO44_OFFSET); - addr_hit[ 53] = (reg_addr == RV_PLIC_PRIO45_OFFSET); - addr_hit[ 54] = (reg_addr == RV_PLIC_PRIO46_OFFSET); - addr_hit[ 55] = (reg_addr == RV_PLIC_PRIO47_OFFSET); - addr_hit[ 56] = (reg_addr == RV_PLIC_PRIO48_OFFSET); - addr_hit[ 57] = (reg_addr == RV_PLIC_PRIO49_OFFSET); - addr_hit[ 58] = (reg_addr == RV_PLIC_PRIO50_OFFSET); - addr_hit[ 59] = (reg_addr == RV_PLIC_PRIO51_OFFSET); - addr_hit[ 60] = (reg_addr == RV_PLIC_PRIO52_OFFSET); - addr_hit[ 61] = (reg_addr == RV_PLIC_PRIO53_OFFSET); - addr_hit[ 62] = (reg_addr == RV_PLIC_PRIO54_OFFSET); - addr_hit[ 63] = (reg_addr == RV_PLIC_PRIO55_OFFSET); - addr_hit[ 64] = (reg_addr == RV_PLIC_PRIO56_OFFSET); - addr_hit[ 65] = (reg_addr == RV_PLIC_PRIO57_OFFSET); - addr_hit[ 66] = (reg_addr == RV_PLIC_PRIO58_OFFSET); - addr_hit[ 67] = (reg_addr == RV_PLIC_PRIO59_OFFSET); - addr_hit[ 68] = (reg_addr == RV_PLIC_PRIO60_OFFSET); - addr_hit[ 69] = (reg_addr == RV_PLIC_PRIO61_OFFSET); - addr_hit[ 70] = (reg_addr == RV_PLIC_PRIO62_OFFSET); - addr_hit[ 71] = (reg_addr == RV_PLIC_PRIO63_OFFSET); - addr_hit[ 72] = (reg_addr == RV_PLIC_PRIO64_OFFSET); - addr_hit[ 73] = (reg_addr == RV_PLIC_PRIO65_OFFSET); - addr_hit[ 74] = (reg_addr == RV_PLIC_PRIO66_OFFSET); - addr_hit[ 75] = (reg_addr == RV_PLIC_PRIO67_OFFSET); - addr_hit[ 76] = (reg_addr == RV_PLIC_PRIO68_OFFSET); - addr_hit[ 77] = (reg_addr == RV_PLIC_PRIO69_OFFSET); - addr_hit[ 78] = (reg_addr == RV_PLIC_PRIO70_OFFSET); - addr_hit[ 79] = (reg_addr == RV_PLIC_PRIO71_OFFSET); - addr_hit[ 80] = (reg_addr == RV_PLIC_PRIO72_OFFSET); - addr_hit[ 81] = (reg_addr == RV_PLIC_PRIO73_OFFSET); - addr_hit[ 82] = (reg_addr == RV_PLIC_PRIO74_OFFSET); - addr_hit[ 83] = (reg_addr == RV_PLIC_PRIO75_OFFSET); - addr_hit[ 84] = (reg_addr == RV_PLIC_PRIO76_OFFSET); - addr_hit[ 85] = (reg_addr == RV_PLIC_PRIO77_OFFSET); - addr_hit[ 86] = (reg_addr == RV_PLIC_PRIO78_OFFSET); - addr_hit[ 87] = (reg_addr == RV_PLIC_PRIO79_OFFSET); - addr_hit[ 88] = (reg_addr == RV_PLIC_PRIO80_OFFSET); - addr_hit[ 89] = (reg_addr == RV_PLIC_PRIO81_OFFSET); - addr_hit[ 90] = (reg_addr == RV_PLIC_PRIO82_OFFSET); - addr_hit[ 91] = (reg_addr == RV_PLIC_PRIO83_OFFSET); - addr_hit[ 92] = (reg_addr == RV_PLIC_PRIO84_OFFSET); - addr_hit[ 93] = (reg_addr == RV_PLIC_PRIO85_OFFSET); - addr_hit[ 94] = (reg_addr == RV_PLIC_PRIO86_OFFSET); - addr_hit[ 95] = (reg_addr == RV_PLIC_PRIO87_OFFSET); - addr_hit[ 96] = (reg_addr == RV_PLIC_PRIO88_OFFSET); - addr_hit[ 97] = (reg_addr == RV_PLIC_PRIO89_OFFSET); - addr_hit[ 98] = (reg_addr == RV_PLIC_PRIO90_OFFSET); - addr_hit[ 99] = (reg_addr == RV_PLIC_PRIO91_OFFSET); - addr_hit[100] = (reg_addr == RV_PLIC_PRIO92_OFFSET); - addr_hit[101] = (reg_addr == RV_PLIC_PRIO93_OFFSET); - addr_hit[102] = (reg_addr == RV_PLIC_PRIO94_OFFSET); - addr_hit[103] = (reg_addr == RV_PLIC_PRIO95_OFFSET); - addr_hit[104] = (reg_addr == RV_PLIC_PRIO96_OFFSET); - addr_hit[105] = (reg_addr == RV_PLIC_PRIO97_OFFSET); - addr_hit[106] = (reg_addr == RV_PLIC_PRIO98_OFFSET); - addr_hit[107] = (reg_addr == RV_PLIC_PRIO99_OFFSET); - addr_hit[108] = (reg_addr == RV_PLIC_PRIO100_OFFSET); - addr_hit[109] = (reg_addr == RV_PLIC_PRIO101_OFFSET); - addr_hit[110] = (reg_addr == RV_PLIC_PRIO102_OFFSET); - addr_hit[111] = (reg_addr == RV_PLIC_PRIO103_OFFSET); - addr_hit[112] = (reg_addr == RV_PLIC_PRIO104_OFFSET); - addr_hit[113] = (reg_addr == RV_PLIC_PRIO105_OFFSET); - addr_hit[114] = (reg_addr == RV_PLIC_PRIO106_OFFSET); - addr_hit[115] = (reg_addr == RV_PLIC_PRIO107_OFFSET); - addr_hit[116] = (reg_addr == RV_PLIC_PRIO108_OFFSET); - addr_hit[117] = (reg_addr == RV_PLIC_PRIO109_OFFSET); - addr_hit[118] = (reg_addr == RV_PLIC_PRIO110_OFFSET); - addr_hit[119] = (reg_addr == RV_PLIC_PRIO111_OFFSET); - addr_hit[120] = (reg_addr == RV_PLIC_PRIO112_OFFSET); - addr_hit[121] = (reg_addr == RV_PLIC_PRIO113_OFFSET); - addr_hit[122] = (reg_addr == RV_PLIC_PRIO114_OFFSET); - addr_hit[123] = (reg_addr == RV_PLIC_PRIO115_OFFSET); - addr_hit[124] = (reg_addr == RV_PLIC_PRIO116_OFFSET); - addr_hit[125] = (reg_addr == RV_PLIC_PRIO117_OFFSET); - addr_hit[126] = (reg_addr == RV_PLIC_PRIO118_OFFSET); - addr_hit[127] = (reg_addr == RV_PLIC_PRIO119_OFFSET); - addr_hit[128] = (reg_addr == RV_PLIC_PRIO120_OFFSET); - addr_hit[129] = (reg_addr == RV_PLIC_PRIO121_OFFSET); - addr_hit[130] = (reg_addr == RV_PLIC_IE0_0_OFFSET); - addr_hit[131] = (reg_addr == RV_PLIC_IE0_1_OFFSET); - addr_hit[132] = (reg_addr == RV_PLIC_IE0_2_OFFSET); - addr_hit[133] = (reg_addr == RV_PLIC_IE0_3_OFFSET); - addr_hit[134] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET); - addr_hit[135] = (reg_addr == RV_PLIC_CC0_OFFSET); - addr_hit[136] = (reg_addr == RV_PLIC_MSIP0_OFFSET); + addr_hit[ 4] = (reg_addr == RV_PLIC_IP_4_OFFSET); + addr_hit[ 5] = (reg_addr == RV_PLIC_IP_5_OFFSET); + addr_hit[ 6] = (reg_addr == RV_PLIC_LE_0_OFFSET); + addr_hit[ 7] = (reg_addr == RV_PLIC_LE_1_OFFSET); + addr_hit[ 8] = (reg_addr == RV_PLIC_LE_2_OFFSET); + addr_hit[ 9] = (reg_addr == RV_PLIC_LE_3_OFFSET); + addr_hit[ 10] = (reg_addr == RV_PLIC_LE_4_OFFSET); + addr_hit[ 11] = (reg_addr == RV_PLIC_LE_5_OFFSET); + addr_hit[ 12] = (reg_addr == RV_PLIC_PRIO0_OFFSET); + addr_hit[ 13] = (reg_addr == RV_PLIC_PRIO1_OFFSET); + addr_hit[ 14] = (reg_addr == RV_PLIC_PRIO2_OFFSET); + addr_hit[ 15] = (reg_addr == RV_PLIC_PRIO3_OFFSET); + addr_hit[ 16] = (reg_addr == RV_PLIC_PRIO4_OFFSET); + addr_hit[ 17] = (reg_addr == RV_PLIC_PRIO5_OFFSET); + addr_hit[ 18] = (reg_addr == RV_PLIC_PRIO6_OFFSET); + addr_hit[ 19] = (reg_addr == RV_PLIC_PRIO7_OFFSET); + addr_hit[ 20] = (reg_addr == RV_PLIC_PRIO8_OFFSET); + addr_hit[ 21] = (reg_addr == RV_PLIC_PRIO9_OFFSET); + addr_hit[ 22] = (reg_addr == RV_PLIC_PRIO10_OFFSET); + addr_hit[ 23] = (reg_addr == RV_PLIC_PRIO11_OFFSET); + addr_hit[ 24] = (reg_addr == RV_PLIC_PRIO12_OFFSET); + addr_hit[ 25] = (reg_addr == RV_PLIC_PRIO13_OFFSET); + addr_hit[ 26] = (reg_addr == RV_PLIC_PRIO14_OFFSET); + addr_hit[ 27] = (reg_addr == RV_PLIC_PRIO15_OFFSET); + addr_hit[ 28] = (reg_addr == RV_PLIC_PRIO16_OFFSET); + addr_hit[ 29] = (reg_addr == RV_PLIC_PRIO17_OFFSET); + addr_hit[ 30] = (reg_addr == RV_PLIC_PRIO18_OFFSET); + addr_hit[ 31] = (reg_addr == RV_PLIC_PRIO19_OFFSET); + addr_hit[ 32] = (reg_addr == RV_PLIC_PRIO20_OFFSET); + addr_hit[ 33] = (reg_addr == RV_PLIC_PRIO21_OFFSET); + addr_hit[ 34] = (reg_addr == RV_PLIC_PRIO22_OFFSET); + addr_hit[ 35] = (reg_addr == RV_PLIC_PRIO23_OFFSET); + addr_hit[ 36] = (reg_addr == RV_PLIC_PRIO24_OFFSET); + addr_hit[ 37] = (reg_addr == RV_PLIC_PRIO25_OFFSET); + addr_hit[ 38] = (reg_addr == RV_PLIC_PRIO26_OFFSET); + addr_hit[ 39] = (reg_addr == RV_PLIC_PRIO27_OFFSET); + addr_hit[ 40] = (reg_addr == RV_PLIC_PRIO28_OFFSET); + addr_hit[ 41] = (reg_addr == RV_PLIC_PRIO29_OFFSET); + addr_hit[ 42] = (reg_addr == RV_PLIC_PRIO30_OFFSET); + addr_hit[ 43] = (reg_addr == RV_PLIC_PRIO31_OFFSET); + addr_hit[ 44] = (reg_addr == RV_PLIC_PRIO32_OFFSET); + addr_hit[ 45] = (reg_addr == RV_PLIC_PRIO33_OFFSET); + addr_hit[ 46] = (reg_addr == RV_PLIC_PRIO34_OFFSET); + addr_hit[ 47] = (reg_addr == RV_PLIC_PRIO35_OFFSET); + addr_hit[ 48] = (reg_addr == RV_PLIC_PRIO36_OFFSET); + addr_hit[ 49] = (reg_addr == RV_PLIC_PRIO37_OFFSET); + addr_hit[ 50] = (reg_addr == RV_PLIC_PRIO38_OFFSET); + addr_hit[ 51] = (reg_addr == RV_PLIC_PRIO39_OFFSET); + addr_hit[ 52] = (reg_addr == RV_PLIC_PRIO40_OFFSET); + addr_hit[ 53] = (reg_addr == RV_PLIC_PRIO41_OFFSET); + addr_hit[ 54] = (reg_addr == RV_PLIC_PRIO42_OFFSET); + addr_hit[ 55] = (reg_addr == RV_PLIC_PRIO43_OFFSET); + addr_hit[ 56] = (reg_addr == RV_PLIC_PRIO44_OFFSET); + addr_hit[ 57] = (reg_addr == RV_PLIC_PRIO45_OFFSET); + addr_hit[ 58] = (reg_addr == RV_PLIC_PRIO46_OFFSET); + addr_hit[ 59] = (reg_addr == RV_PLIC_PRIO47_OFFSET); + addr_hit[ 60] = (reg_addr == RV_PLIC_PRIO48_OFFSET); + addr_hit[ 61] = (reg_addr == RV_PLIC_PRIO49_OFFSET); + addr_hit[ 62] = (reg_addr == RV_PLIC_PRIO50_OFFSET); + addr_hit[ 63] = (reg_addr == RV_PLIC_PRIO51_OFFSET); + addr_hit[ 64] = (reg_addr == RV_PLIC_PRIO52_OFFSET); + addr_hit[ 65] = (reg_addr == RV_PLIC_PRIO53_OFFSET); + addr_hit[ 66] = (reg_addr == RV_PLIC_PRIO54_OFFSET); + addr_hit[ 67] = (reg_addr == RV_PLIC_PRIO55_OFFSET); + addr_hit[ 68] = (reg_addr == RV_PLIC_PRIO56_OFFSET); + addr_hit[ 69] = (reg_addr == RV_PLIC_PRIO57_OFFSET); + addr_hit[ 70] = (reg_addr == RV_PLIC_PRIO58_OFFSET); + addr_hit[ 71] = (reg_addr == RV_PLIC_PRIO59_OFFSET); + addr_hit[ 72] = (reg_addr == RV_PLIC_PRIO60_OFFSET); + addr_hit[ 73] = (reg_addr == RV_PLIC_PRIO61_OFFSET); + addr_hit[ 74] = (reg_addr == RV_PLIC_PRIO62_OFFSET); + addr_hit[ 75] = (reg_addr == RV_PLIC_PRIO63_OFFSET); + addr_hit[ 76] = (reg_addr == RV_PLIC_PRIO64_OFFSET); + addr_hit[ 77] = (reg_addr == RV_PLIC_PRIO65_OFFSET); + addr_hit[ 78] = (reg_addr == RV_PLIC_PRIO66_OFFSET); + addr_hit[ 79] = (reg_addr == RV_PLIC_PRIO67_OFFSET); + addr_hit[ 80] = (reg_addr == RV_PLIC_PRIO68_OFFSET); + addr_hit[ 81] = (reg_addr == RV_PLIC_PRIO69_OFFSET); + addr_hit[ 82] = (reg_addr == RV_PLIC_PRIO70_OFFSET); + addr_hit[ 83] = (reg_addr == RV_PLIC_PRIO71_OFFSET); + addr_hit[ 84] = (reg_addr == RV_PLIC_PRIO72_OFFSET); + addr_hit[ 85] = (reg_addr == RV_PLIC_PRIO73_OFFSET); + addr_hit[ 86] = (reg_addr == RV_PLIC_PRIO74_OFFSET); + addr_hit[ 87] = (reg_addr == RV_PLIC_PRIO75_OFFSET); + addr_hit[ 88] = (reg_addr == RV_PLIC_PRIO76_OFFSET); + addr_hit[ 89] = (reg_addr == RV_PLIC_PRIO77_OFFSET); + addr_hit[ 90] = (reg_addr == RV_PLIC_PRIO78_OFFSET); + addr_hit[ 91] = (reg_addr == RV_PLIC_PRIO79_OFFSET); + addr_hit[ 92] = (reg_addr == RV_PLIC_PRIO80_OFFSET); + addr_hit[ 93] = (reg_addr == RV_PLIC_PRIO81_OFFSET); + addr_hit[ 94] = (reg_addr == RV_PLIC_PRIO82_OFFSET); + addr_hit[ 95] = (reg_addr == RV_PLIC_PRIO83_OFFSET); + addr_hit[ 96] = (reg_addr == RV_PLIC_PRIO84_OFFSET); + addr_hit[ 97] = (reg_addr == RV_PLIC_PRIO85_OFFSET); + addr_hit[ 98] = (reg_addr == RV_PLIC_PRIO86_OFFSET); + addr_hit[ 99] = (reg_addr == RV_PLIC_PRIO87_OFFSET); + addr_hit[100] = (reg_addr == RV_PLIC_PRIO88_OFFSET); + addr_hit[101] = (reg_addr == RV_PLIC_PRIO89_OFFSET); + addr_hit[102] = (reg_addr == RV_PLIC_PRIO90_OFFSET); + addr_hit[103] = (reg_addr == RV_PLIC_PRIO91_OFFSET); + addr_hit[104] = (reg_addr == RV_PLIC_PRIO92_OFFSET); + addr_hit[105] = (reg_addr == RV_PLIC_PRIO93_OFFSET); + addr_hit[106] = (reg_addr == RV_PLIC_PRIO94_OFFSET); + addr_hit[107] = (reg_addr == RV_PLIC_PRIO95_OFFSET); + addr_hit[108] = (reg_addr == RV_PLIC_PRIO96_OFFSET); + addr_hit[109] = (reg_addr == RV_PLIC_PRIO97_OFFSET); + addr_hit[110] = (reg_addr == RV_PLIC_PRIO98_OFFSET); + addr_hit[111] = (reg_addr == RV_PLIC_PRIO99_OFFSET); + addr_hit[112] = (reg_addr == RV_PLIC_PRIO100_OFFSET); + addr_hit[113] = (reg_addr == RV_PLIC_PRIO101_OFFSET); + addr_hit[114] = (reg_addr == RV_PLIC_PRIO102_OFFSET); + addr_hit[115] = (reg_addr == RV_PLIC_PRIO103_OFFSET); + addr_hit[116] = (reg_addr == RV_PLIC_PRIO104_OFFSET); + addr_hit[117] = (reg_addr == RV_PLIC_PRIO105_OFFSET); + addr_hit[118] = (reg_addr == RV_PLIC_PRIO106_OFFSET); + addr_hit[119] = (reg_addr == RV_PLIC_PRIO107_OFFSET); + addr_hit[120] = (reg_addr == RV_PLIC_PRIO108_OFFSET); + addr_hit[121] = (reg_addr == RV_PLIC_PRIO109_OFFSET); + addr_hit[122] = (reg_addr == RV_PLIC_PRIO110_OFFSET); + addr_hit[123] = (reg_addr == RV_PLIC_PRIO111_OFFSET); + addr_hit[124] = (reg_addr == RV_PLIC_PRIO112_OFFSET); + addr_hit[125] = (reg_addr == RV_PLIC_PRIO113_OFFSET); + addr_hit[126] = (reg_addr == RV_PLIC_PRIO114_OFFSET); + addr_hit[127] = (reg_addr == RV_PLIC_PRIO115_OFFSET); + addr_hit[128] = (reg_addr == RV_PLIC_PRIO116_OFFSET); + addr_hit[129] = (reg_addr == RV_PLIC_PRIO117_OFFSET); + addr_hit[130] = (reg_addr == RV_PLIC_PRIO118_OFFSET); + addr_hit[131] = (reg_addr == RV_PLIC_PRIO119_OFFSET); + addr_hit[132] = (reg_addr == RV_PLIC_PRIO120_OFFSET); + addr_hit[133] = (reg_addr == RV_PLIC_PRIO121_OFFSET); + addr_hit[134] = (reg_addr == RV_PLIC_PRIO122_OFFSET); + addr_hit[135] = (reg_addr == RV_PLIC_PRIO123_OFFSET); + addr_hit[136] = (reg_addr == RV_PLIC_PRIO124_OFFSET); + addr_hit[137] = (reg_addr == RV_PLIC_PRIO125_OFFSET); + addr_hit[138] = (reg_addr == RV_PLIC_PRIO126_OFFSET); + addr_hit[139] = (reg_addr == RV_PLIC_PRIO127_OFFSET); + addr_hit[140] = (reg_addr == RV_PLIC_PRIO128_OFFSET); + addr_hit[141] = (reg_addr == RV_PLIC_PRIO129_OFFSET); + addr_hit[142] = (reg_addr == RV_PLIC_PRIO130_OFFSET); + addr_hit[143] = (reg_addr == RV_PLIC_PRIO131_OFFSET); + addr_hit[144] = (reg_addr == RV_PLIC_PRIO132_OFFSET); + addr_hit[145] = (reg_addr == RV_PLIC_PRIO133_OFFSET); + addr_hit[146] = (reg_addr == RV_PLIC_PRIO134_OFFSET); + addr_hit[147] = (reg_addr == RV_PLIC_PRIO135_OFFSET); + addr_hit[148] = (reg_addr == RV_PLIC_PRIO136_OFFSET); + addr_hit[149] = (reg_addr == RV_PLIC_PRIO137_OFFSET); + addr_hit[150] = (reg_addr == RV_PLIC_PRIO138_OFFSET); + addr_hit[151] = (reg_addr == RV_PLIC_PRIO139_OFFSET); + addr_hit[152] = (reg_addr == RV_PLIC_PRIO140_OFFSET); + addr_hit[153] = (reg_addr == RV_PLIC_PRIO141_OFFSET); + addr_hit[154] = (reg_addr == RV_PLIC_PRIO142_OFFSET); + addr_hit[155] = (reg_addr == RV_PLIC_PRIO143_OFFSET); + addr_hit[156] = (reg_addr == RV_PLIC_PRIO144_OFFSET); + addr_hit[157] = (reg_addr == RV_PLIC_PRIO145_OFFSET); + addr_hit[158] = (reg_addr == RV_PLIC_PRIO146_OFFSET); + addr_hit[159] = (reg_addr == RV_PLIC_PRIO147_OFFSET); + addr_hit[160] = (reg_addr == RV_PLIC_PRIO148_OFFSET); + addr_hit[161] = (reg_addr == RV_PLIC_PRIO149_OFFSET); + addr_hit[162] = (reg_addr == RV_PLIC_PRIO150_OFFSET); + addr_hit[163] = (reg_addr == RV_PLIC_PRIO151_OFFSET); + addr_hit[164] = (reg_addr == RV_PLIC_PRIO152_OFFSET); + addr_hit[165] = (reg_addr == RV_PLIC_PRIO153_OFFSET); + addr_hit[166] = (reg_addr == RV_PLIC_PRIO154_OFFSET); + addr_hit[167] = (reg_addr == RV_PLIC_PRIO155_OFFSET); + addr_hit[168] = (reg_addr == RV_PLIC_PRIO156_OFFSET); + addr_hit[169] = (reg_addr == RV_PLIC_PRIO157_OFFSET); + addr_hit[170] = (reg_addr == RV_PLIC_PRIO158_OFFSET); + addr_hit[171] = (reg_addr == RV_PLIC_PRIO159_OFFSET); + addr_hit[172] = (reg_addr == RV_PLIC_PRIO160_OFFSET); + addr_hit[173] = (reg_addr == RV_PLIC_PRIO161_OFFSET); + addr_hit[174] = (reg_addr == RV_PLIC_PRIO162_OFFSET); + addr_hit[175] = (reg_addr == RV_PLIC_PRIO163_OFFSET); + addr_hit[176] = (reg_addr == RV_PLIC_PRIO164_OFFSET); + addr_hit[177] = (reg_addr == RV_PLIC_PRIO165_OFFSET); + addr_hit[178] = (reg_addr == RV_PLIC_PRIO166_OFFSET); + addr_hit[179] = (reg_addr == RV_PLIC_PRIO167_OFFSET); + addr_hit[180] = (reg_addr == RV_PLIC_PRIO168_OFFSET); + addr_hit[181] = (reg_addr == RV_PLIC_PRIO169_OFFSET); + addr_hit[182] = (reg_addr == RV_PLIC_PRIO170_OFFSET); + addr_hit[183] = (reg_addr == RV_PLIC_PRIO171_OFFSET); + addr_hit[184] = (reg_addr == RV_PLIC_IE0_0_OFFSET); + addr_hit[185] = (reg_addr == RV_PLIC_IE0_1_OFFSET); + addr_hit[186] = (reg_addr == RV_PLIC_IE0_2_OFFSET); + addr_hit[187] = (reg_addr == RV_PLIC_IE0_3_OFFSET); + addr_hit[188] = (reg_addr == RV_PLIC_IE0_4_OFFSET); + addr_hit[189] = (reg_addr == RV_PLIC_IE0_5_OFFSET); + addr_hit[190] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET); + addr_hit[191] = (reg_addr == RV_PLIC_CC0_OFFSET); + addr_hit[192] = (reg_addr == RV_PLIC_MSIP0_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -14389,6 +20163,62 @@ if (addr_hit[134] && reg_we && (RV_PLIC_PERMIT[134] != (RV_PLIC_PERMIT[134] & reg_be))) wr_err = 1'b1 ; if (addr_hit[135] && reg_we && (RV_PLIC_PERMIT[135] != (RV_PLIC_PERMIT[135] & reg_be))) wr_err = 1'b1 ; if (addr_hit[136] && reg_we && (RV_PLIC_PERMIT[136] != (RV_PLIC_PERMIT[136] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[137] && reg_we && (RV_PLIC_PERMIT[137] != (RV_PLIC_PERMIT[137] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[138] && reg_we && (RV_PLIC_PERMIT[138] != (RV_PLIC_PERMIT[138] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[139] && reg_we && (RV_PLIC_PERMIT[139] != (RV_PLIC_PERMIT[139] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[140] && reg_we && (RV_PLIC_PERMIT[140] != (RV_PLIC_PERMIT[140] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[141] && reg_we && (RV_PLIC_PERMIT[141] != (RV_PLIC_PERMIT[141] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[142] && reg_we && (RV_PLIC_PERMIT[142] != (RV_PLIC_PERMIT[142] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[143] && reg_we && (RV_PLIC_PERMIT[143] != (RV_PLIC_PERMIT[143] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[144] && reg_we && (RV_PLIC_PERMIT[144] != (RV_PLIC_PERMIT[144] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[145] && reg_we && (RV_PLIC_PERMIT[145] != (RV_PLIC_PERMIT[145] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[146] && reg_we && (RV_PLIC_PERMIT[146] != (RV_PLIC_PERMIT[146] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[147] && reg_we && (RV_PLIC_PERMIT[147] != (RV_PLIC_PERMIT[147] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[148] && reg_we && (RV_PLIC_PERMIT[148] != (RV_PLIC_PERMIT[148] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[149] && reg_we && (RV_PLIC_PERMIT[149] != (RV_PLIC_PERMIT[149] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[150] && reg_we && (RV_PLIC_PERMIT[150] != (RV_PLIC_PERMIT[150] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[151] && reg_we && (RV_PLIC_PERMIT[151] != (RV_PLIC_PERMIT[151] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[152] && reg_we && (RV_PLIC_PERMIT[152] != (RV_PLIC_PERMIT[152] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[153] && reg_we && (RV_PLIC_PERMIT[153] != (RV_PLIC_PERMIT[153] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[154] && reg_we && (RV_PLIC_PERMIT[154] != (RV_PLIC_PERMIT[154] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[155] && reg_we && (RV_PLIC_PERMIT[155] != (RV_PLIC_PERMIT[155] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[156] && reg_we && (RV_PLIC_PERMIT[156] != (RV_PLIC_PERMIT[156] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[157] && reg_we && (RV_PLIC_PERMIT[157] != (RV_PLIC_PERMIT[157] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[158] && reg_we && (RV_PLIC_PERMIT[158] != (RV_PLIC_PERMIT[158] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[159] && reg_we && (RV_PLIC_PERMIT[159] != (RV_PLIC_PERMIT[159] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[160] && reg_we && (RV_PLIC_PERMIT[160] != (RV_PLIC_PERMIT[160] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[161] && reg_we && (RV_PLIC_PERMIT[161] != (RV_PLIC_PERMIT[161] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[162] && reg_we && (RV_PLIC_PERMIT[162] != (RV_PLIC_PERMIT[162] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[163] && reg_we && (RV_PLIC_PERMIT[163] != (RV_PLIC_PERMIT[163] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[164] && reg_we && (RV_PLIC_PERMIT[164] != (RV_PLIC_PERMIT[164] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[165] && reg_we && (RV_PLIC_PERMIT[165] != (RV_PLIC_PERMIT[165] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[166] && reg_we && (RV_PLIC_PERMIT[166] != (RV_PLIC_PERMIT[166] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[167] && reg_we && (RV_PLIC_PERMIT[167] != (RV_PLIC_PERMIT[167] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[168] && reg_we && (RV_PLIC_PERMIT[168] != (RV_PLIC_PERMIT[168] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[169] && reg_we && (RV_PLIC_PERMIT[169] != (RV_PLIC_PERMIT[169] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[170] && reg_we && (RV_PLIC_PERMIT[170] != (RV_PLIC_PERMIT[170] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[171] && reg_we && (RV_PLIC_PERMIT[171] != (RV_PLIC_PERMIT[171] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[172] && reg_we && (RV_PLIC_PERMIT[172] != (RV_PLIC_PERMIT[172] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[173] && reg_we && (RV_PLIC_PERMIT[173] != (RV_PLIC_PERMIT[173] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[174] && reg_we && (RV_PLIC_PERMIT[174] != (RV_PLIC_PERMIT[174] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[175] && reg_we && (RV_PLIC_PERMIT[175] != (RV_PLIC_PERMIT[175] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[176] && reg_we && (RV_PLIC_PERMIT[176] != (RV_PLIC_PERMIT[176] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[177] && reg_we && (RV_PLIC_PERMIT[177] != (RV_PLIC_PERMIT[177] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[178] && reg_we && (RV_PLIC_PERMIT[178] != (RV_PLIC_PERMIT[178] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[179] && reg_we && (RV_PLIC_PERMIT[179] != (RV_PLIC_PERMIT[179] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[180] && reg_we && (RV_PLIC_PERMIT[180] != (RV_PLIC_PERMIT[180] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[181] && reg_we && (RV_PLIC_PERMIT[181] != (RV_PLIC_PERMIT[181] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[182] && reg_we && (RV_PLIC_PERMIT[182] != (RV_PLIC_PERMIT[182] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[183] && reg_we && (RV_PLIC_PERMIT[183] != (RV_PLIC_PERMIT[183] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[184] && reg_we && (RV_PLIC_PERMIT[184] != (RV_PLIC_PERMIT[184] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[185] && reg_we && (RV_PLIC_PERMIT[185] != (RV_PLIC_PERMIT[185] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[186] && reg_we && (RV_PLIC_PERMIT[186] != (RV_PLIC_PERMIT[186] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[187] && reg_we && (RV_PLIC_PERMIT[187] != (RV_PLIC_PERMIT[187] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[188] && reg_we && (RV_PLIC_PERMIT[188] != (RV_PLIC_PERMIT[188] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[189] && reg_we && (RV_PLIC_PERMIT[189] != (RV_PLIC_PERMIT[189] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[190] && reg_we && (RV_PLIC_PERMIT[190] != (RV_PLIC_PERMIT[190] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[191] && reg_we && (RV_PLIC_PERMIT[191] != (RV_PLIC_PERMIT[191] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[192] && reg_we && (RV_PLIC_PERMIT[192] != (RV_PLIC_PERMIT[192] & reg_be))) wr_err = 1'b1 ; end @@ -14513,1112 +20343,1612 @@ - assign le_0_le_0_we = addr_hit[4] & reg_we & ~wr_err; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + assign le_0_le_0_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_0_wd = reg_wdata[0]; - assign le_0_le_1_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_1_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_1_wd = reg_wdata[1]; - assign le_0_le_2_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_2_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_2_wd = reg_wdata[2]; - assign le_0_le_3_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_3_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_3_wd = reg_wdata[3]; - assign le_0_le_4_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_4_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_4_wd = reg_wdata[4]; - assign le_0_le_5_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_5_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_5_wd = reg_wdata[5]; - assign le_0_le_6_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_6_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_6_wd = reg_wdata[6]; - assign le_0_le_7_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_7_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_7_wd = reg_wdata[7]; - assign le_0_le_8_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_8_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_8_wd = reg_wdata[8]; - assign le_0_le_9_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_9_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_9_wd = reg_wdata[9]; - assign le_0_le_10_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_10_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_10_wd = reg_wdata[10]; - assign le_0_le_11_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_11_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_11_wd = reg_wdata[11]; - assign le_0_le_12_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_12_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_12_wd = reg_wdata[12]; - assign le_0_le_13_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_13_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_13_wd = reg_wdata[13]; - assign le_0_le_14_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_14_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_14_wd = reg_wdata[14]; - assign le_0_le_15_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_15_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_15_wd = reg_wdata[15]; - assign le_0_le_16_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_16_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_16_wd = reg_wdata[16]; - assign le_0_le_17_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_17_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_17_wd = reg_wdata[17]; - assign le_0_le_18_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_18_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_18_wd = reg_wdata[18]; - assign le_0_le_19_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_19_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_19_wd = reg_wdata[19]; - assign le_0_le_20_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_20_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_20_wd = reg_wdata[20]; - assign le_0_le_21_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_21_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_21_wd = reg_wdata[21]; - assign le_0_le_22_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_22_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_22_wd = reg_wdata[22]; - assign le_0_le_23_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_23_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_23_wd = reg_wdata[23]; - assign le_0_le_24_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_24_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_24_wd = reg_wdata[24]; - assign le_0_le_25_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_25_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_25_wd = reg_wdata[25]; - assign le_0_le_26_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_26_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_26_wd = reg_wdata[26]; - assign le_0_le_27_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_27_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_27_wd = reg_wdata[27]; - assign le_0_le_28_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_28_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_28_wd = reg_wdata[28]; - assign le_0_le_29_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_29_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_29_wd = reg_wdata[29]; - assign le_0_le_30_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_30_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_30_wd = reg_wdata[30]; - assign le_0_le_31_we = addr_hit[4] & reg_we & ~wr_err; + assign le_0_le_31_we = addr_hit[6] & reg_we & ~wr_err; assign le_0_le_31_wd = reg_wdata[31]; - assign le_1_le_32_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_32_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_32_wd = reg_wdata[0]; - assign le_1_le_33_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_33_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_33_wd = reg_wdata[1]; - assign le_1_le_34_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_34_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_34_wd = reg_wdata[2]; - assign le_1_le_35_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_35_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_35_wd = reg_wdata[3]; - assign le_1_le_36_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_36_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_36_wd = reg_wdata[4]; - assign le_1_le_37_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_37_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_37_wd = reg_wdata[5]; - assign le_1_le_38_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_38_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_38_wd = reg_wdata[6]; - assign le_1_le_39_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_39_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_39_wd = reg_wdata[7]; - assign le_1_le_40_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_40_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_40_wd = reg_wdata[8]; - assign le_1_le_41_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_41_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_41_wd = reg_wdata[9]; - assign le_1_le_42_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_42_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_42_wd = reg_wdata[10]; - assign le_1_le_43_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_43_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_43_wd = reg_wdata[11]; - assign le_1_le_44_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_44_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_44_wd = reg_wdata[12]; - assign le_1_le_45_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_45_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_45_wd = reg_wdata[13]; - assign le_1_le_46_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_46_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_46_wd = reg_wdata[14]; - assign le_1_le_47_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_47_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_47_wd = reg_wdata[15]; - assign le_1_le_48_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_48_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_48_wd = reg_wdata[16]; - assign le_1_le_49_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_49_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_49_wd = reg_wdata[17]; - assign le_1_le_50_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_50_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_50_wd = reg_wdata[18]; - assign le_1_le_51_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_51_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_51_wd = reg_wdata[19]; - assign le_1_le_52_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_52_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_52_wd = reg_wdata[20]; - assign le_1_le_53_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_53_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_53_wd = reg_wdata[21]; - assign le_1_le_54_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_54_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_54_wd = reg_wdata[22]; - assign le_1_le_55_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_55_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_55_wd = reg_wdata[23]; - assign le_1_le_56_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_56_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_56_wd = reg_wdata[24]; - assign le_1_le_57_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_57_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_57_wd = reg_wdata[25]; - assign le_1_le_58_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_58_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_58_wd = reg_wdata[26]; - assign le_1_le_59_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_59_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_59_wd = reg_wdata[27]; - assign le_1_le_60_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_60_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_60_wd = reg_wdata[28]; - assign le_1_le_61_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_61_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_61_wd = reg_wdata[29]; - assign le_1_le_62_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_62_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_62_wd = reg_wdata[30]; - assign le_1_le_63_we = addr_hit[5] & reg_we & ~wr_err; + assign le_1_le_63_we = addr_hit[7] & reg_we & ~wr_err; assign le_1_le_63_wd = reg_wdata[31]; - assign le_2_le_64_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_64_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_64_wd = reg_wdata[0]; - assign le_2_le_65_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_65_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_65_wd = reg_wdata[1]; - assign le_2_le_66_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_66_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_66_wd = reg_wdata[2]; - assign le_2_le_67_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_67_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_67_wd = reg_wdata[3]; - assign le_2_le_68_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_68_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_68_wd = reg_wdata[4]; - assign le_2_le_69_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_69_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_69_wd = reg_wdata[5]; - assign le_2_le_70_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_70_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_70_wd = reg_wdata[6]; - assign le_2_le_71_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_71_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_71_wd = reg_wdata[7]; - assign le_2_le_72_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_72_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_72_wd = reg_wdata[8]; - assign le_2_le_73_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_73_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_73_wd = reg_wdata[9]; - assign le_2_le_74_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_74_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_74_wd = reg_wdata[10]; - assign le_2_le_75_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_75_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_75_wd = reg_wdata[11]; - assign le_2_le_76_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_76_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_76_wd = reg_wdata[12]; - assign le_2_le_77_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_77_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_77_wd = reg_wdata[13]; - assign le_2_le_78_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_78_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_78_wd = reg_wdata[14]; - assign le_2_le_79_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_79_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_79_wd = reg_wdata[15]; - assign le_2_le_80_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_80_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_80_wd = reg_wdata[16]; - assign le_2_le_81_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_81_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_81_wd = reg_wdata[17]; - assign le_2_le_82_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_82_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_82_wd = reg_wdata[18]; - assign le_2_le_83_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_83_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_83_wd = reg_wdata[19]; - assign le_2_le_84_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_84_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_84_wd = reg_wdata[20]; - assign le_2_le_85_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_85_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_85_wd = reg_wdata[21]; - assign le_2_le_86_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_86_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_86_wd = reg_wdata[22]; - assign le_2_le_87_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_87_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_87_wd = reg_wdata[23]; - assign le_2_le_88_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_88_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_88_wd = reg_wdata[24]; - assign le_2_le_89_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_89_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_89_wd = reg_wdata[25]; - assign le_2_le_90_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_90_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_90_wd = reg_wdata[26]; - assign le_2_le_91_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_91_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_91_wd = reg_wdata[27]; - assign le_2_le_92_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_92_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_92_wd = reg_wdata[28]; - assign le_2_le_93_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_93_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_93_wd = reg_wdata[29]; - assign le_2_le_94_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_94_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_94_wd = reg_wdata[30]; - assign le_2_le_95_we = addr_hit[6] & reg_we & ~wr_err; + assign le_2_le_95_we = addr_hit[8] & reg_we & ~wr_err; assign le_2_le_95_wd = reg_wdata[31]; - assign le_3_le_96_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_96_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_96_wd = reg_wdata[0]; - assign le_3_le_97_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_97_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_97_wd = reg_wdata[1]; - assign le_3_le_98_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_98_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_98_wd = reg_wdata[2]; - assign le_3_le_99_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_99_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_99_wd = reg_wdata[3]; - assign le_3_le_100_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_100_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_100_wd = reg_wdata[4]; - assign le_3_le_101_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_101_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_101_wd = reg_wdata[5]; - assign le_3_le_102_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_102_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_102_wd = reg_wdata[6]; - assign le_3_le_103_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_103_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_103_wd = reg_wdata[7]; - assign le_3_le_104_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_104_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_104_wd = reg_wdata[8]; - assign le_3_le_105_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_105_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_105_wd = reg_wdata[9]; - assign le_3_le_106_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_106_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_106_wd = reg_wdata[10]; - assign le_3_le_107_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_107_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_107_wd = reg_wdata[11]; - assign le_3_le_108_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_108_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_108_wd = reg_wdata[12]; - assign le_3_le_109_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_109_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_109_wd = reg_wdata[13]; - assign le_3_le_110_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_110_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_110_wd = reg_wdata[14]; - assign le_3_le_111_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_111_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_111_wd = reg_wdata[15]; - assign le_3_le_112_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_112_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_112_wd = reg_wdata[16]; - assign le_3_le_113_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_113_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_113_wd = reg_wdata[17]; - assign le_3_le_114_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_114_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_114_wd = reg_wdata[18]; - assign le_3_le_115_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_115_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_115_wd = reg_wdata[19]; - assign le_3_le_116_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_116_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_116_wd = reg_wdata[20]; - assign le_3_le_117_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_117_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_117_wd = reg_wdata[21]; - assign le_3_le_118_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_118_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_118_wd = reg_wdata[22]; - assign le_3_le_119_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_119_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_119_wd = reg_wdata[23]; - assign le_3_le_120_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_120_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_120_wd = reg_wdata[24]; - assign le_3_le_121_we = addr_hit[7] & reg_we & ~wr_err; + assign le_3_le_121_we = addr_hit[9] & reg_we & ~wr_err; assign le_3_le_121_wd = reg_wdata[25]; - assign prio0_we = addr_hit[8] & reg_we & ~wr_err; + assign le_3_le_122_we = addr_hit[9] & reg_we & ~wr_err; + assign le_3_le_122_wd = reg_wdata[26]; + + assign le_3_le_123_we = addr_hit[9] & reg_we & ~wr_err; + assign le_3_le_123_wd = reg_wdata[27]; + + assign le_3_le_124_we = addr_hit[9] & reg_we & ~wr_err; + assign le_3_le_124_wd = reg_wdata[28]; + + assign le_3_le_125_we = addr_hit[9] & reg_we & ~wr_err; + assign le_3_le_125_wd = reg_wdata[29]; + + assign le_3_le_126_we = addr_hit[9] & reg_we & ~wr_err; + assign le_3_le_126_wd = reg_wdata[30]; + + assign le_3_le_127_we = addr_hit[9] & reg_we & ~wr_err; + assign le_3_le_127_wd = reg_wdata[31]; + + assign le_4_le_128_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_128_wd = reg_wdata[0]; + + assign le_4_le_129_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_129_wd = reg_wdata[1]; + + assign le_4_le_130_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_130_wd = reg_wdata[2]; + + assign le_4_le_131_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_131_wd = reg_wdata[3]; + + assign le_4_le_132_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_132_wd = reg_wdata[4]; + + assign le_4_le_133_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_133_wd = reg_wdata[5]; + + assign le_4_le_134_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_134_wd = reg_wdata[6]; + + assign le_4_le_135_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_135_wd = reg_wdata[7]; + + assign le_4_le_136_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_136_wd = reg_wdata[8]; + + assign le_4_le_137_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_137_wd = reg_wdata[9]; + + assign le_4_le_138_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_138_wd = reg_wdata[10]; + + assign le_4_le_139_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_139_wd = reg_wdata[11]; + + assign le_4_le_140_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_140_wd = reg_wdata[12]; + + assign le_4_le_141_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_141_wd = reg_wdata[13]; + + assign le_4_le_142_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_142_wd = reg_wdata[14]; + + assign le_4_le_143_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_143_wd = reg_wdata[15]; + + assign le_4_le_144_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_144_wd = reg_wdata[16]; + + assign le_4_le_145_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_145_wd = reg_wdata[17]; + + assign le_4_le_146_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_146_wd = reg_wdata[18]; + + assign le_4_le_147_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_147_wd = reg_wdata[19]; + + assign le_4_le_148_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_148_wd = reg_wdata[20]; + + assign le_4_le_149_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_149_wd = reg_wdata[21]; + + assign le_4_le_150_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_150_wd = reg_wdata[22]; + + assign le_4_le_151_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_151_wd = reg_wdata[23]; + + assign le_4_le_152_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_152_wd = reg_wdata[24]; + + assign le_4_le_153_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_153_wd = reg_wdata[25]; + + assign le_4_le_154_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_154_wd = reg_wdata[26]; + + assign le_4_le_155_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_155_wd = reg_wdata[27]; + + assign le_4_le_156_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_156_wd = reg_wdata[28]; + + assign le_4_le_157_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_157_wd = reg_wdata[29]; + + assign le_4_le_158_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_158_wd = reg_wdata[30]; + + assign le_4_le_159_we = addr_hit[10] & reg_we & ~wr_err; + assign le_4_le_159_wd = reg_wdata[31]; + + assign le_5_le_160_we = addr_hit[11] & reg_we & ~wr_err; + assign le_5_le_160_wd = reg_wdata[0]; + + assign le_5_le_161_we = addr_hit[11] & reg_we & ~wr_err; + assign le_5_le_161_wd = reg_wdata[1]; + + assign le_5_le_162_we = addr_hit[11] & reg_we & ~wr_err; + assign le_5_le_162_wd = reg_wdata[2]; + + assign le_5_le_163_we = addr_hit[11] & reg_we & ~wr_err; + assign le_5_le_163_wd = reg_wdata[3]; + + assign le_5_le_164_we = addr_hit[11] & reg_we & ~wr_err; + assign le_5_le_164_wd = reg_wdata[4]; + + assign le_5_le_165_we = addr_hit[11] & reg_we & ~wr_err; + assign le_5_le_165_wd = reg_wdata[5]; + + assign le_5_le_166_we = addr_hit[11] & reg_we & ~wr_err; + assign le_5_le_166_wd = reg_wdata[6]; + + assign le_5_le_167_we = addr_hit[11] & reg_we & ~wr_err; + assign le_5_le_167_wd = reg_wdata[7]; + + assign le_5_le_168_we = addr_hit[11] & reg_we & ~wr_err; + assign le_5_le_168_wd = reg_wdata[8]; + + assign le_5_le_169_we = addr_hit[11] & reg_we & ~wr_err; + assign le_5_le_169_wd = reg_wdata[9]; + + assign le_5_le_170_we = addr_hit[11] & reg_we & ~wr_err; + assign le_5_le_170_wd = reg_wdata[10]; + + assign le_5_le_171_we = addr_hit[11] & reg_we & ~wr_err; + assign le_5_le_171_wd = reg_wdata[11]; + + assign prio0_we = addr_hit[12] & reg_we & ~wr_err; assign prio0_wd = reg_wdata[1:0]; - assign prio1_we = addr_hit[9] & reg_we & ~wr_err; + assign prio1_we = addr_hit[13] & reg_we & ~wr_err; assign prio1_wd = reg_wdata[1:0]; - assign prio2_we = addr_hit[10] & reg_we & ~wr_err; + assign prio2_we = addr_hit[14] & reg_we & ~wr_err; assign prio2_wd = reg_wdata[1:0]; - assign prio3_we = addr_hit[11] & reg_we & ~wr_err; + assign prio3_we = addr_hit[15] & reg_we & ~wr_err; assign prio3_wd = reg_wdata[1:0]; - assign prio4_we = addr_hit[12] & reg_we & ~wr_err; + assign prio4_we = addr_hit[16] & reg_we & ~wr_err; assign prio4_wd = reg_wdata[1:0]; - assign prio5_we = addr_hit[13] & reg_we & ~wr_err; + assign prio5_we = addr_hit[17] & reg_we & ~wr_err; assign prio5_wd = reg_wdata[1:0]; - assign prio6_we = addr_hit[14] & reg_we & ~wr_err; + assign prio6_we = addr_hit[18] & reg_we & ~wr_err; assign prio6_wd = reg_wdata[1:0]; - assign prio7_we = addr_hit[15] & reg_we & ~wr_err; + assign prio7_we = addr_hit[19] & reg_we & ~wr_err; assign prio7_wd = reg_wdata[1:0]; - assign prio8_we = addr_hit[16] & reg_we & ~wr_err; + assign prio8_we = addr_hit[20] & reg_we & ~wr_err; assign prio8_wd = reg_wdata[1:0]; - assign prio9_we = addr_hit[17] & reg_we & ~wr_err; + assign prio9_we = addr_hit[21] & reg_we & ~wr_err; assign prio9_wd = reg_wdata[1:0]; - assign prio10_we = addr_hit[18] & reg_we & ~wr_err; + assign prio10_we = addr_hit[22] & reg_we & ~wr_err; assign prio10_wd = reg_wdata[1:0]; - assign prio11_we = addr_hit[19] & reg_we & ~wr_err; + assign prio11_we = addr_hit[23] & reg_we & ~wr_err; assign prio11_wd = reg_wdata[1:0]; - assign prio12_we = addr_hit[20] & reg_we & ~wr_err; + assign prio12_we = addr_hit[24] & reg_we & ~wr_err; assign prio12_wd = reg_wdata[1:0]; - assign prio13_we = addr_hit[21] & reg_we & ~wr_err; + assign prio13_we = addr_hit[25] & reg_we & ~wr_err; assign prio13_wd = reg_wdata[1:0]; - assign prio14_we = addr_hit[22] & reg_we & ~wr_err; + assign prio14_we = addr_hit[26] & reg_we & ~wr_err; assign prio14_wd = reg_wdata[1:0]; - assign prio15_we = addr_hit[23] & reg_we & ~wr_err; + assign prio15_we = addr_hit[27] & reg_we & ~wr_err; assign prio15_wd = reg_wdata[1:0]; - assign prio16_we = addr_hit[24] & reg_we & ~wr_err; + assign prio16_we = addr_hit[28] & reg_we & ~wr_err; assign prio16_wd = reg_wdata[1:0]; - assign prio17_we = addr_hit[25] & reg_we & ~wr_err; + assign prio17_we = addr_hit[29] & reg_we & ~wr_err; assign prio17_wd = reg_wdata[1:0]; - assign prio18_we = addr_hit[26] & reg_we & ~wr_err; + assign prio18_we = addr_hit[30] & reg_we & ~wr_err; assign prio18_wd = reg_wdata[1:0]; - assign prio19_we = addr_hit[27] & reg_we & ~wr_err; + assign prio19_we = addr_hit[31] & reg_we & ~wr_err; assign prio19_wd = reg_wdata[1:0]; - assign prio20_we = addr_hit[28] & reg_we & ~wr_err; + assign prio20_we = addr_hit[32] & reg_we & ~wr_err; assign prio20_wd = reg_wdata[1:0]; - assign prio21_we = addr_hit[29] & reg_we & ~wr_err; + assign prio21_we = addr_hit[33] & reg_we & ~wr_err; assign prio21_wd = reg_wdata[1:0]; - assign prio22_we = addr_hit[30] & reg_we & ~wr_err; + assign prio22_we = addr_hit[34] & reg_we & ~wr_err; assign prio22_wd = reg_wdata[1:0]; - assign prio23_we = addr_hit[31] & reg_we & ~wr_err; + assign prio23_we = addr_hit[35] & reg_we & ~wr_err; assign prio23_wd = reg_wdata[1:0]; - assign prio24_we = addr_hit[32] & reg_we & ~wr_err; + assign prio24_we = addr_hit[36] & reg_we & ~wr_err; assign prio24_wd = reg_wdata[1:0]; - assign prio25_we = addr_hit[33] & reg_we & ~wr_err; + assign prio25_we = addr_hit[37] & reg_we & ~wr_err; assign prio25_wd = reg_wdata[1:0]; - assign prio26_we = addr_hit[34] & reg_we & ~wr_err; + assign prio26_we = addr_hit[38] & reg_we & ~wr_err; assign prio26_wd = reg_wdata[1:0]; - assign prio27_we = addr_hit[35] & reg_we & ~wr_err; + assign prio27_we = addr_hit[39] & reg_we & ~wr_err; assign prio27_wd = reg_wdata[1:0]; - assign prio28_we = addr_hit[36] & reg_we & ~wr_err; + assign prio28_we = addr_hit[40] & reg_we & ~wr_err; assign prio28_wd = reg_wdata[1:0]; - assign prio29_we = addr_hit[37] & reg_we & ~wr_err; + assign prio29_we = addr_hit[41] & reg_we & ~wr_err; assign prio29_wd = reg_wdata[1:0]; - assign prio30_we = addr_hit[38] & reg_we & ~wr_err; + assign prio30_we = addr_hit[42] & reg_we & ~wr_err; assign prio30_wd = reg_wdata[1:0]; - assign prio31_we = addr_hit[39] & reg_we & ~wr_err; + assign prio31_we = addr_hit[43] & reg_we & ~wr_err; assign prio31_wd = reg_wdata[1:0]; - assign prio32_we = addr_hit[40] & reg_we & ~wr_err; + assign prio32_we = addr_hit[44] & reg_we & ~wr_err; assign prio32_wd = reg_wdata[1:0]; - assign prio33_we = addr_hit[41] & reg_we & ~wr_err; + assign prio33_we = addr_hit[45] & reg_we & ~wr_err; assign prio33_wd = reg_wdata[1:0]; - assign prio34_we = addr_hit[42] & reg_we & ~wr_err; + assign prio34_we = addr_hit[46] & reg_we & ~wr_err; assign prio34_wd = reg_wdata[1:0]; - assign prio35_we = addr_hit[43] & reg_we & ~wr_err; + assign prio35_we = addr_hit[47] & reg_we & ~wr_err; assign prio35_wd = reg_wdata[1:0]; - assign prio36_we = addr_hit[44] & reg_we & ~wr_err; + assign prio36_we = addr_hit[48] & reg_we & ~wr_err; assign prio36_wd = reg_wdata[1:0]; - assign prio37_we = addr_hit[45] & reg_we & ~wr_err; + assign prio37_we = addr_hit[49] & reg_we & ~wr_err; assign prio37_wd = reg_wdata[1:0]; - assign prio38_we = addr_hit[46] & reg_we & ~wr_err; + assign prio38_we = addr_hit[50] & reg_we & ~wr_err; assign prio38_wd = reg_wdata[1:0]; - assign prio39_we = addr_hit[47] & reg_we & ~wr_err; + assign prio39_we = addr_hit[51] & reg_we & ~wr_err; assign prio39_wd = reg_wdata[1:0]; - assign prio40_we = addr_hit[48] & reg_we & ~wr_err; + assign prio40_we = addr_hit[52] & reg_we & ~wr_err; assign prio40_wd = reg_wdata[1:0]; - assign prio41_we = addr_hit[49] & reg_we & ~wr_err; + assign prio41_we = addr_hit[53] & reg_we & ~wr_err; assign prio41_wd = reg_wdata[1:0]; - assign prio42_we = addr_hit[50] & reg_we & ~wr_err; + assign prio42_we = addr_hit[54] & reg_we & ~wr_err; assign prio42_wd = reg_wdata[1:0]; - assign prio43_we = addr_hit[51] & reg_we & ~wr_err; + assign prio43_we = addr_hit[55] & reg_we & ~wr_err; assign prio43_wd = reg_wdata[1:0]; - assign prio44_we = addr_hit[52] & reg_we & ~wr_err; + assign prio44_we = addr_hit[56] & reg_we & ~wr_err; assign prio44_wd = reg_wdata[1:0]; - assign prio45_we = addr_hit[53] & reg_we & ~wr_err; + assign prio45_we = addr_hit[57] & reg_we & ~wr_err; assign prio45_wd = reg_wdata[1:0]; - assign prio46_we = addr_hit[54] & reg_we & ~wr_err; + assign prio46_we = addr_hit[58] & reg_we & ~wr_err; assign prio46_wd = reg_wdata[1:0]; - assign prio47_we = addr_hit[55] & reg_we & ~wr_err; + assign prio47_we = addr_hit[59] & reg_we & ~wr_err; assign prio47_wd = reg_wdata[1:0]; - assign prio48_we = addr_hit[56] & reg_we & ~wr_err; + assign prio48_we = addr_hit[60] & reg_we & ~wr_err; assign prio48_wd = reg_wdata[1:0]; - assign prio49_we = addr_hit[57] & reg_we & ~wr_err; + assign prio49_we = addr_hit[61] & reg_we & ~wr_err; assign prio49_wd = reg_wdata[1:0]; - assign prio50_we = addr_hit[58] & reg_we & ~wr_err; + assign prio50_we = addr_hit[62] & reg_we & ~wr_err; assign prio50_wd = reg_wdata[1:0]; - assign prio51_we = addr_hit[59] & reg_we & ~wr_err; + assign prio51_we = addr_hit[63] & reg_we & ~wr_err; assign prio51_wd = reg_wdata[1:0]; - assign prio52_we = addr_hit[60] & reg_we & ~wr_err; + assign prio52_we = addr_hit[64] & reg_we & ~wr_err; assign prio52_wd = reg_wdata[1:0]; - assign prio53_we = addr_hit[61] & reg_we & ~wr_err; + assign prio53_we = addr_hit[65] & reg_we & ~wr_err; assign prio53_wd = reg_wdata[1:0]; - assign prio54_we = addr_hit[62] & reg_we & ~wr_err; + assign prio54_we = addr_hit[66] & reg_we & ~wr_err; assign prio54_wd = reg_wdata[1:0]; - assign prio55_we = addr_hit[63] & reg_we & ~wr_err; + assign prio55_we = addr_hit[67] & reg_we & ~wr_err; assign prio55_wd = reg_wdata[1:0]; - assign prio56_we = addr_hit[64] & reg_we & ~wr_err; + assign prio56_we = addr_hit[68] & reg_we & ~wr_err; assign prio56_wd = reg_wdata[1:0]; - assign prio57_we = addr_hit[65] & reg_we & ~wr_err; + assign prio57_we = addr_hit[69] & reg_we & ~wr_err; assign prio57_wd = reg_wdata[1:0]; - assign prio58_we = addr_hit[66] & reg_we & ~wr_err; + assign prio58_we = addr_hit[70] & reg_we & ~wr_err; assign prio58_wd = reg_wdata[1:0]; - assign prio59_we = addr_hit[67] & reg_we & ~wr_err; + assign prio59_we = addr_hit[71] & reg_we & ~wr_err; assign prio59_wd = reg_wdata[1:0]; - assign prio60_we = addr_hit[68] & reg_we & ~wr_err; + assign prio60_we = addr_hit[72] & reg_we & ~wr_err; assign prio60_wd = reg_wdata[1:0]; - assign prio61_we = addr_hit[69] & reg_we & ~wr_err; + assign prio61_we = addr_hit[73] & reg_we & ~wr_err; assign prio61_wd = reg_wdata[1:0]; - assign prio62_we = addr_hit[70] & reg_we & ~wr_err; + assign prio62_we = addr_hit[74] & reg_we & ~wr_err; assign prio62_wd = reg_wdata[1:0]; - assign prio63_we = addr_hit[71] & reg_we & ~wr_err; + assign prio63_we = addr_hit[75] & reg_we & ~wr_err; assign prio63_wd = reg_wdata[1:0]; - assign prio64_we = addr_hit[72] & reg_we & ~wr_err; + assign prio64_we = addr_hit[76] & reg_we & ~wr_err; assign prio64_wd = reg_wdata[1:0]; - assign prio65_we = addr_hit[73] & reg_we & ~wr_err; + assign prio65_we = addr_hit[77] & reg_we & ~wr_err; assign prio65_wd = reg_wdata[1:0]; - assign prio66_we = addr_hit[74] & reg_we & ~wr_err; + assign prio66_we = addr_hit[78] & reg_we & ~wr_err; assign prio66_wd = reg_wdata[1:0]; - assign prio67_we = addr_hit[75] & reg_we & ~wr_err; + assign prio67_we = addr_hit[79] & reg_we & ~wr_err; assign prio67_wd = reg_wdata[1:0]; - assign prio68_we = addr_hit[76] & reg_we & ~wr_err; + assign prio68_we = addr_hit[80] & reg_we & ~wr_err; assign prio68_wd = reg_wdata[1:0]; - assign prio69_we = addr_hit[77] & reg_we & ~wr_err; + assign prio69_we = addr_hit[81] & reg_we & ~wr_err; assign prio69_wd = reg_wdata[1:0]; - assign prio70_we = addr_hit[78] & reg_we & ~wr_err; + assign prio70_we = addr_hit[82] & reg_we & ~wr_err; assign prio70_wd = reg_wdata[1:0]; - assign prio71_we = addr_hit[79] & reg_we & ~wr_err; + assign prio71_we = addr_hit[83] & reg_we & ~wr_err; assign prio71_wd = reg_wdata[1:0]; - assign prio72_we = addr_hit[80] & reg_we & ~wr_err; + assign prio72_we = addr_hit[84] & reg_we & ~wr_err; assign prio72_wd = reg_wdata[1:0]; - assign prio73_we = addr_hit[81] & reg_we & ~wr_err; + assign prio73_we = addr_hit[85] & reg_we & ~wr_err; assign prio73_wd = reg_wdata[1:0]; - assign prio74_we = addr_hit[82] & reg_we & ~wr_err; + assign prio74_we = addr_hit[86] & reg_we & ~wr_err; assign prio74_wd = reg_wdata[1:0]; - assign prio75_we = addr_hit[83] & reg_we & ~wr_err; + assign prio75_we = addr_hit[87] & reg_we & ~wr_err; assign prio75_wd = reg_wdata[1:0]; - assign prio76_we = addr_hit[84] & reg_we & ~wr_err; + assign prio76_we = addr_hit[88] & reg_we & ~wr_err; assign prio76_wd = reg_wdata[1:0]; - assign prio77_we = addr_hit[85] & reg_we & ~wr_err; + assign prio77_we = addr_hit[89] & reg_we & ~wr_err; assign prio77_wd = reg_wdata[1:0]; - assign prio78_we = addr_hit[86] & reg_we & ~wr_err; + assign prio78_we = addr_hit[90] & reg_we & ~wr_err; assign prio78_wd = reg_wdata[1:0]; - assign prio79_we = addr_hit[87] & reg_we & ~wr_err; + assign prio79_we = addr_hit[91] & reg_we & ~wr_err; assign prio79_wd = reg_wdata[1:0]; - assign prio80_we = addr_hit[88] & reg_we & ~wr_err; + assign prio80_we = addr_hit[92] & reg_we & ~wr_err; assign prio80_wd = reg_wdata[1:0]; - assign prio81_we = addr_hit[89] & reg_we & ~wr_err; + assign prio81_we = addr_hit[93] & reg_we & ~wr_err; assign prio81_wd = reg_wdata[1:0]; - assign prio82_we = addr_hit[90] & reg_we & ~wr_err; + assign prio82_we = addr_hit[94] & reg_we & ~wr_err; assign prio82_wd = reg_wdata[1:0]; - assign prio83_we = addr_hit[91] & reg_we & ~wr_err; + assign prio83_we = addr_hit[95] & reg_we & ~wr_err; assign prio83_wd = reg_wdata[1:0]; - assign prio84_we = addr_hit[92] & reg_we & ~wr_err; + assign prio84_we = addr_hit[96] & reg_we & ~wr_err; assign prio84_wd = reg_wdata[1:0]; - assign prio85_we = addr_hit[93] & reg_we & ~wr_err; + assign prio85_we = addr_hit[97] & reg_we & ~wr_err; assign prio85_wd = reg_wdata[1:0]; - assign prio86_we = addr_hit[94] & reg_we & ~wr_err; + assign prio86_we = addr_hit[98] & reg_we & ~wr_err; assign prio86_wd = reg_wdata[1:0]; - assign prio87_we = addr_hit[95] & reg_we & ~wr_err; + assign prio87_we = addr_hit[99] & reg_we & ~wr_err; assign prio87_wd = reg_wdata[1:0]; - assign prio88_we = addr_hit[96] & reg_we & ~wr_err; + assign prio88_we = addr_hit[100] & reg_we & ~wr_err; assign prio88_wd = reg_wdata[1:0]; - assign prio89_we = addr_hit[97] & reg_we & ~wr_err; + assign prio89_we = addr_hit[101] & reg_we & ~wr_err; assign prio89_wd = reg_wdata[1:0]; - assign prio90_we = addr_hit[98] & reg_we & ~wr_err; + assign prio90_we = addr_hit[102] & reg_we & ~wr_err; assign prio90_wd = reg_wdata[1:0]; - assign prio91_we = addr_hit[99] & reg_we & ~wr_err; + assign prio91_we = addr_hit[103] & reg_we & ~wr_err; assign prio91_wd = reg_wdata[1:0]; - assign prio92_we = addr_hit[100] & reg_we & ~wr_err; + assign prio92_we = addr_hit[104] & reg_we & ~wr_err; assign prio92_wd = reg_wdata[1:0]; - assign prio93_we = addr_hit[101] & reg_we & ~wr_err; + assign prio93_we = addr_hit[105] & reg_we & ~wr_err; assign prio93_wd = reg_wdata[1:0]; - assign prio94_we = addr_hit[102] & reg_we & ~wr_err; + assign prio94_we = addr_hit[106] & reg_we & ~wr_err; assign prio94_wd = reg_wdata[1:0]; - assign prio95_we = addr_hit[103] & reg_we & ~wr_err; + assign prio95_we = addr_hit[107] & reg_we & ~wr_err; assign prio95_wd = reg_wdata[1:0]; - assign prio96_we = addr_hit[104] & reg_we & ~wr_err; + assign prio96_we = addr_hit[108] & reg_we & ~wr_err; assign prio96_wd = reg_wdata[1:0]; - assign prio97_we = addr_hit[105] & reg_we & ~wr_err; + assign prio97_we = addr_hit[109] & reg_we & ~wr_err; assign prio97_wd = reg_wdata[1:0]; - assign prio98_we = addr_hit[106] & reg_we & ~wr_err; + assign prio98_we = addr_hit[110] & reg_we & ~wr_err; assign prio98_wd = reg_wdata[1:0]; - assign prio99_we = addr_hit[107] & reg_we & ~wr_err; + assign prio99_we = addr_hit[111] & reg_we & ~wr_err; assign prio99_wd = reg_wdata[1:0]; - assign prio100_we = addr_hit[108] & reg_we & ~wr_err; + assign prio100_we = addr_hit[112] & reg_we & ~wr_err; assign prio100_wd = reg_wdata[1:0]; - assign prio101_we = addr_hit[109] & reg_we & ~wr_err; + assign prio101_we = addr_hit[113] & reg_we & ~wr_err; assign prio101_wd = reg_wdata[1:0]; - assign prio102_we = addr_hit[110] & reg_we & ~wr_err; + assign prio102_we = addr_hit[114] & reg_we & ~wr_err; assign prio102_wd = reg_wdata[1:0]; - assign prio103_we = addr_hit[111] & reg_we & ~wr_err; + assign prio103_we = addr_hit[115] & reg_we & ~wr_err; assign prio103_wd = reg_wdata[1:0]; - assign prio104_we = addr_hit[112] & reg_we & ~wr_err; + assign prio104_we = addr_hit[116] & reg_we & ~wr_err; assign prio104_wd = reg_wdata[1:0]; - assign prio105_we = addr_hit[113] & reg_we & ~wr_err; + assign prio105_we = addr_hit[117] & reg_we & ~wr_err; assign prio105_wd = reg_wdata[1:0]; - assign prio106_we = addr_hit[114] & reg_we & ~wr_err; + assign prio106_we = addr_hit[118] & reg_we & ~wr_err; assign prio106_wd = reg_wdata[1:0]; - assign prio107_we = addr_hit[115] & reg_we & ~wr_err; + assign prio107_we = addr_hit[119] & reg_we & ~wr_err; assign prio107_wd = reg_wdata[1:0]; - assign prio108_we = addr_hit[116] & reg_we & ~wr_err; + assign prio108_we = addr_hit[120] & reg_we & ~wr_err; assign prio108_wd = reg_wdata[1:0]; - assign prio109_we = addr_hit[117] & reg_we & ~wr_err; + assign prio109_we = addr_hit[121] & reg_we & ~wr_err; assign prio109_wd = reg_wdata[1:0]; - assign prio110_we = addr_hit[118] & reg_we & ~wr_err; + assign prio110_we = addr_hit[122] & reg_we & ~wr_err; assign prio110_wd = reg_wdata[1:0]; - assign prio111_we = addr_hit[119] & reg_we & ~wr_err; + assign prio111_we = addr_hit[123] & reg_we & ~wr_err; assign prio111_wd = reg_wdata[1:0]; - assign prio112_we = addr_hit[120] & reg_we & ~wr_err; + assign prio112_we = addr_hit[124] & reg_we & ~wr_err; assign prio112_wd = reg_wdata[1:0]; - assign prio113_we = addr_hit[121] & reg_we & ~wr_err; + assign prio113_we = addr_hit[125] & reg_we & ~wr_err; assign prio113_wd = reg_wdata[1:0]; - assign prio114_we = addr_hit[122] & reg_we & ~wr_err; + assign prio114_we = addr_hit[126] & reg_we & ~wr_err; assign prio114_wd = reg_wdata[1:0]; - assign prio115_we = addr_hit[123] & reg_we & ~wr_err; + assign prio115_we = addr_hit[127] & reg_we & ~wr_err; assign prio115_wd = reg_wdata[1:0]; - assign prio116_we = addr_hit[124] & reg_we & ~wr_err; + assign prio116_we = addr_hit[128] & reg_we & ~wr_err; assign prio116_wd = reg_wdata[1:0]; - assign prio117_we = addr_hit[125] & reg_we & ~wr_err; + assign prio117_we = addr_hit[129] & reg_we & ~wr_err; assign prio117_wd = reg_wdata[1:0]; - assign prio118_we = addr_hit[126] & reg_we & ~wr_err; + assign prio118_we = addr_hit[130] & reg_we & ~wr_err; assign prio118_wd = reg_wdata[1:0]; - assign prio119_we = addr_hit[127] & reg_we & ~wr_err; + assign prio119_we = addr_hit[131] & reg_we & ~wr_err; assign prio119_wd = reg_wdata[1:0]; - assign prio120_we = addr_hit[128] & reg_we & ~wr_err; + assign prio120_we = addr_hit[132] & reg_we & ~wr_err; assign prio120_wd = reg_wdata[1:0]; - assign prio121_we = addr_hit[129] & reg_we & ~wr_err; + assign prio121_we = addr_hit[133] & reg_we & ~wr_err; assign prio121_wd = reg_wdata[1:0]; - assign ie0_0_e_0_we = addr_hit[130] & reg_we & ~wr_err; + assign prio122_we = addr_hit[134] & reg_we & ~wr_err; + assign prio122_wd = reg_wdata[1:0]; + + assign prio123_we = addr_hit[135] & reg_we & ~wr_err; + assign prio123_wd = reg_wdata[1:0]; + + assign prio124_we = addr_hit[136] & reg_we & ~wr_err; + assign prio124_wd = reg_wdata[1:0]; + + assign prio125_we = addr_hit[137] & reg_we & ~wr_err; + assign prio125_wd = reg_wdata[1:0]; + + assign prio126_we = addr_hit[138] & reg_we & ~wr_err; + assign prio126_wd = reg_wdata[1:0]; + + assign prio127_we = addr_hit[139] & reg_we & ~wr_err; + assign prio127_wd = reg_wdata[1:0]; + + assign prio128_we = addr_hit[140] & reg_we & ~wr_err; + assign prio128_wd = reg_wdata[1:0]; + + assign prio129_we = addr_hit[141] & reg_we & ~wr_err; + assign prio129_wd = reg_wdata[1:0]; + + assign prio130_we = addr_hit[142] & reg_we & ~wr_err; + assign prio130_wd = reg_wdata[1:0]; + + assign prio131_we = addr_hit[143] & reg_we & ~wr_err; + assign prio131_wd = reg_wdata[1:0]; + + assign prio132_we = addr_hit[144] & reg_we & ~wr_err; + assign prio132_wd = reg_wdata[1:0]; + + assign prio133_we = addr_hit[145] & reg_we & ~wr_err; + assign prio133_wd = reg_wdata[1:0]; + + assign prio134_we = addr_hit[146] & reg_we & ~wr_err; + assign prio134_wd = reg_wdata[1:0]; + + assign prio135_we = addr_hit[147] & reg_we & ~wr_err; + assign prio135_wd = reg_wdata[1:0]; + + assign prio136_we = addr_hit[148] & reg_we & ~wr_err; + assign prio136_wd = reg_wdata[1:0]; + + assign prio137_we = addr_hit[149] & reg_we & ~wr_err; + assign prio137_wd = reg_wdata[1:0]; + + assign prio138_we = addr_hit[150] & reg_we & ~wr_err; + assign prio138_wd = reg_wdata[1:0]; + + assign prio139_we = addr_hit[151] & reg_we & ~wr_err; + assign prio139_wd = reg_wdata[1:0]; + + assign prio140_we = addr_hit[152] & reg_we & ~wr_err; + assign prio140_wd = reg_wdata[1:0]; + + assign prio141_we = addr_hit[153] & reg_we & ~wr_err; + assign prio141_wd = reg_wdata[1:0]; + + assign prio142_we = addr_hit[154] & reg_we & ~wr_err; + assign prio142_wd = reg_wdata[1:0]; + + assign prio143_we = addr_hit[155] & reg_we & ~wr_err; + assign prio143_wd = reg_wdata[1:0]; + + assign prio144_we = addr_hit[156] & reg_we & ~wr_err; + assign prio144_wd = reg_wdata[1:0]; + + assign prio145_we = addr_hit[157] & reg_we & ~wr_err; + assign prio145_wd = reg_wdata[1:0]; + + assign prio146_we = addr_hit[158] & reg_we & ~wr_err; + assign prio146_wd = reg_wdata[1:0]; + + assign prio147_we = addr_hit[159] & reg_we & ~wr_err; + assign prio147_wd = reg_wdata[1:0]; + + assign prio148_we = addr_hit[160] & reg_we & ~wr_err; + assign prio148_wd = reg_wdata[1:0]; + + assign prio149_we = addr_hit[161] & reg_we & ~wr_err; + assign prio149_wd = reg_wdata[1:0]; + + assign prio150_we = addr_hit[162] & reg_we & ~wr_err; + assign prio150_wd = reg_wdata[1:0]; + + assign prio151_we = addr_hit[163] & reg_we & ~wr_err; + assign prio151_wd = reg_wdata[1:0]; + + assign prio152_we = addr_hit[164] & reg_we & ~wr_err; + assign prio152_wd = reg_wdata[1:0]; + + assign prio153_we = addr_hit[165] & reg_we & ~wr_err; + assign prio153_wd = reg_wdata[1:0]; + + assign prio154_we = addr_hit[166] & reg_we & ~wr_err; + assign prio154_wd = reg_wdata[1:0]; + + assign prio155_we = addr_hit[167] & reg_we & ~wr_err; + assign prio155_wd = reg_wdata[1:0]; + + assign prio156_we = addr_hit[168] & reg_we & ~wr_err; + assign prio156_wd = reg_wdata[1:0]; + + assign prio157_we = addr_hit[169] & reg_we & ~wr_err; + assign prio157_wd = reg_wdata[1:0]; + + assign prio158_we = addr_hit[170] & reg_we & ~wr_err; + assign prio158_wd = reg_wdata[1:0]; + + assign prio159_we = addr_hit[171] & reg_we & ~wr_err; + assign prio159_wd = reg_wdata[1:0]; + + assign prio160_we = addr_hit[172] & reg_we & ~wr_err; + assign prio160_wd = reg_wdata[1:0]; + + assign prio161_we = addr_hit[173] & reg_we & ~wr_err; + assign prio161_wd = reg_wdata[1:0]; + + assign prio162_we = addr_hit[174] & reg_we & ~wr_err; + assign prio162_wd = reg_wdata[1:0]; + + assign prio163_we = addr_hit[175] & reg_we & ~wr_err; + assign prio163_wd = reg_wdata[1:0]; + + assign prio164_we = addr_hit[176] & reg_we & ~wr_err; + assign prio164_wd = reg_wdata[1:0]; + + assign prio165_we = addr_hit[177] & reg_we & ~wr_err; + assign prio165_wd = reg_wdata[1:0]; + + assign prio166_we = addr_hit[178] & reg_we & ~wr_err; + assign prio166_wd = reg_wdata[1:0]; + + assign prio167_we = addr_hit[179] & reg_we & ~wr_err; + assign prio167_wd = reg_wdata[1:0]; + + assign prio168_we = addr_hit[180] & reg_we & ~wr_err; + assign prio168_wd = reg_wdata[1:0]; + + assign prio169_we = addr_hit[181] & reg_we & ~wr_err; + assign prio169_wd = reg_wdata[1:0]; + + assign prio170_we = addr_hit[182] & reg_we & ~wr_err; + assign prio170_wd = reg_wdata[1:0]; + + assign prio171_we = addr_hit[183] & reg_we & ~wr_err; + assign prio171_wd = reg_wdata[1:0]; + + assign ie0_0_e_0_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_0_wd = reg_wdata[0]; - assign ie0_0_e_1_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_1_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_1_wd = reg_wdata[1]; - assign ie0_0_e_2_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_2_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_2_wd = reg_wdata[2]; - assign ie0_0_e_3_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_3_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_3_wd = reg_wdata[3]; - assign ie0_0_e_4_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_4_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_4_wd = reg_wdata[4]; - assign ie0_0_e_5_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_5_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_5_wd = reg_wdata[5]; - assign ie0_0_e_6_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_6_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_6_wd = reg_wdata[6]; - assign ie0_0_e_7_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_7_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_7_wd = reg_wdata[7]; - assign ie0_0_e_8_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_8_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_8_wd = reg_wdata[8]; - assign ie0_0_e_9_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_9_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_9_wd = reg_wdata[9]; - assign ie0_0_e_10_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_10_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_10_wd = reg_wdata[10]; - assign ie0_0_e_11_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_11_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_11_wd = reg_wdata[11]; - assign ie0_0_e_12_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_12_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_12_wd = reg_wdata[12]; - assign ie0_0_e_13_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_13_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_13_wd = reg_wdata[13]; - assign ie0_0_e_14_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_14_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_14_wd = reg_wdata[14]; - assign ie0_0_e_15_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_15_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_15_wd = reg_wdata[15]; - assign ie0_0_e_16_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_16_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_16_wd = reg_wdata[16]; - assign ie0_0_e_17_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_17_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_17_wd = reg_wdata[17]; - assign ie0_0_e_18_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_18_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_18_wd = reg_wdata[18]; - assign ie0_0_e_19_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_19_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_19_wd = reg_wdata[19]; - assign ie0_0_e_20_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_20_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_20_wd = reg_wdata[20]; - assign ie0_0_e_21_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_21_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_21_wd = reg_wdata[21]; - assign ie0_0_e_22_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_22_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_22_wd = reg_wdata[22]; - assign ie0_0_e_23_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_23_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_23_wd = reg_wdata[23]; - assign ie0_0_e_24_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_24_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_24_wd = reg_wdata[24]; - assign ie0_0_e_25_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_25_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_25_wd = reg_wdata[25]; - assign ie0_0_e_26_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_26_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_26_wd = reg_wdata[26]; - assign ie0_0_e_27_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_27_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_27_wd = reg_wdata[27]; - assign ie0_0_e_28_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_28_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_28_wd = reg_wdata[28]; - assign ie0_0_e_29_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_29_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_29_wd = reg_wdata[29]; - assign ie0_0_e_30_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_30_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_30_wd = reg_wdata[30]; - assign ie0_0_e_31_we = addr_hit[130] & reg_we & ~wr_err; + assign ie0_0_e_31_we = addr_hit[184] & reg_we & ~wr_err; assign ie0_0_e_31_wd = reg_wdata[31]; - assign ie0_1_e_32_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_32_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_32_wd = reg_wdata[0]; - assign ie0_1_e_33_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_33_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_33_wd = reg_wdata[1]; - assign ie0_1_e_34_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_34_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_34_wd = reg_wdata[2]; - assign ie0_1_e_35_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_35_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_35_wd = reg_wdata[3]; - assign ie0_1_e_36_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_36_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_36_wd = reg_wdata[4]; - assign ie0_1_e_37_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_37_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_37_wd = reg_wdata[5]; - assign ie0_1_e_38_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_38_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_38_wd = reg_wdata[6]; - assign ie0_1_e_39_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_39_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_39_wd = reg_wdata[7]; - assign ie0_1_e_40_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_40_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_40_wd = reg_wdata[8]; - assign ie0_1_e_41_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_41_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_41_wd = reg_wdata[9]; - assign ie0_1_e_42_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_42_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_42_wd = reg_wdata[10]; - assign ie0_1_e_43_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_43_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_43_wd = reg_wdata[11]; - assign ie0_1_e_44_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_44_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_44_wd = reg_wdata[12]; - assign ie0_1_e_45_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_45_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_45_wd = reg_wdata[13]; - assign ie0_1_e_46_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_46_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_46_wd = reg_wdata[14]; - assign ie0_1_e_47_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_47_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_47_wd = reg_wdata[15]; - assign ie0_1_e_48_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_48_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_48_wd = reg_wdata[16]; - assign ie0_1_e_49_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_49_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_49_wd = reg_wdata[17]; - assign ie0_1_e_50_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_50_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_50_wd = reg_wdata[18]; - assign ie0_1_e_51_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_51_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_51_wd = reg_wdata[19]; - assign ie0_1_e_52_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_52_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_52_wd = reg_wdata[20]; - assign ie0_1_e_53_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_53_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_53_wd = reg_wdata[21]; - assign ie0_1_e_54_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_54_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_54_wd = reg_wdata[22]; - assign ie0_1_e_55_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_55_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_55_wd = reg_wdata[23]; - assign ie0_1_e_56_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_56_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_56_wd = reg_wdata[24]; - assign ie0_1_e_57_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_57_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_57_wd = reg_wdata[25]; - assign ie0_1_e_58_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_58_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_58_wd = reg_wdata[26]; - assign ie0_1_e_59_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_59_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_59_wd = reg_wdata[27]; - assign ie0_1_e_60_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_60_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_60_wd = reg_wdata[28]; - assign ie0_1_e_61_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_61_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_61_wd = reg_wdata[29]; - assign ie0_1_e_62_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_62_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_62_wd = reg_wdata[30]; - assign ie0_1_e_63_we = addr_hit[131] & reg_we & ~wr_err; + assign ie0_1_e_63_we = addr_hit[185] & reg_we & ~wr_err; assign ie0_1_e_63_wd = reg_wdata[31]; - assign ie0_2_e_64_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_64_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_64_wd = reg_wdata[0]; - assign ie0_2_e_65_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_65_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_65_wd = reg_wdata[1]; - assign ie0_2_e_66_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_66_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_66_wd = reg_wdata[2]; - assign ie0_2_e_67_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_67_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_67_wd = reg_wdata[3]; - assign ie0_2_e_68_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_68_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_68_wd = reg_wdata[4]; - assign ie0_2_e_69_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_69_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_69_wd = reg_wdata[5]; - assign ie0_2_e_70_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_70_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_70_wd = reg_wdata[6]; - assign ie0_2_e_71_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_71_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_71_wd = reg_wdata[7]; - assign ie0_2_e_72_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_72_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_72_wd = reg_wdata[8]; - assign ie0_2_e_73_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_73_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_73_wd = reg_wdata[9]; - assign ie0_2_e_74_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_74_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_74_wd = reg_wdata[10]; - assign ie0_2_e_75_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_75_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_75_wd = reg_wdata[11]; - assign ie0_2_e_76_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_76_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_76_wd = reg_wdata[12]; - assign ie0_2_e_77_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_77_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_77_wd = reg_wdata[13]; - assign ie0_2_e_78_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_78_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_78_wd = reg_wdata[14]; - assign ie0_2_e_79_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_79_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_79_wd = reg_wdata[15]; - assign ie0_2_e_80_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_80_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_80_wd = reg_wdata[16]; - assign ie0_2_e_81_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_81_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_81_wd = reg_wdata[17]; - assign ie0_2_e_82_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_82_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_82_wd = reg_wdata[18]; - assign ie0_2_e_83_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_83_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_83_wd = reg_wdata[19]; - assign ie0_2_e_84_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_84_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_84_wd = reg_wdata[20]; - assign ie0_2_e_85_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_85_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_85_wd = reg_wdata[21]; - assign ie0_2_e_86_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_86_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_86_wd = reg_wdata[22]; - assign ie0_2_e_87_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_87_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_87_wd = reg_wdata[23]; - assign ie0_2_e_88_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_88_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_88_wd = reg_wdata[24]; - assign ie0_2_e_89_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_89_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_89_wd = reg_wdata[25]; - assign ie0_2_e_90_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_90_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_90_wd = reg_wdata[26]; - assign ie0_2_e_91_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_91_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_91_wd = reg_wdata[27]; - assign ie0_2_e_92_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_92_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_92_wd = reg_wdata[28]; - assign ie0_2_e_93_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_93_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_93_wd = reg_wdata[29]; - assign ie0_2_e_94_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_94_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_94_wd = reg_wdata[30]; - assign ie0_2_e_95_we = addr_hit[132] & reg_we & ~wr_err; + assign ie0_2_e_95_we = addr_hit[186] & reg_we & ~wr_err; assign ie0_2_e_95_wd = reg_wdata[31]; - assign ie0_3_e_96_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_96_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_96_wd = reg_wdata[0]; - assign ie0_3_e_97_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_97_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_97_wd = reg_wdata[1]; - assign ie0_3_e_98_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_98_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_98_wd = reg_wdata[2]; - assign ie0_3_e_99_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_99_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_99_wd = reg_wdata[3]; - assign ie0_3_e_100_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_100_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_100_wd = reg_wdata[4]; - assign ie0_3_e_101_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_101_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_101_wd = reg_wdata[5]; - assign ie0_3_e_102_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_102_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_102_wd = reg_wdata[6]; - assign ie0_3_e_103_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_103_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_103_wd = reg_wdata[7]; - assign ie0_3_e_104_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_104_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_104_wd = reg_wdata[8]; - assign ie0_3_e_105_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_105_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_105_wd = reg_wdata[9]; - assign ie0_3_e_106_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_106_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_106_wd = reg_wdata[10]; - assign ie0_3_e_107_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_107_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_107_wd = reg_wdata[11]; - assign ie0_3_e_108_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_108_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_108_wd = reg_wdata[12]; - assign ie0_3_e_109_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_109_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_109_wd = reg_wdata[13]; - assign ie0_3_e_110_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_110_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_110_wd = reg_wdata[14]; - assign ie0_3_e_111_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_111_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_111_wd = reg_wdata[15]; - assign ie0_3_e_112_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_112_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_112_wd = reg_wdata[16]; - assign ie0_3_e_113_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_113_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_113_wd = reg_wdata[17]; - assign ie0_3_e_114_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_114_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_114_wd = reg_wdata[18]; - assign ie0_3_e_115_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_115_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_115_wd = reg_wdata[19]; - assign ie0_3_e_116_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_116_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_116_wd = reg_wdata[20]; - assign ie0_3_e_117_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_117_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_117_wd = reg_wdata[21]; - assign ie0_3_e_118_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_118_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_118_wd = reg_wdata[22]; - assign ie0_3_e_119_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_119_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_119_wd = reg_wdata[23]; - assign ie0_3_e_120_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_120_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_120_wd = reg_wdata[24]; - assign ie0_3_e_121_we = addr_hit[133] & reg_we & ~wr_err; + assign ie0_3_e_121_we = addr_hit[187] & reg_we & ~wr_err; assign ie0_3_e_121_wd = reg_wdata[25]; - assign threshold0_we = addr_hit[134] & reg_we & ~wr_err; + assign ie0_3_e_122_we = addr_hit[187] & reg_we & ~wr_err; + assign ie0_3_e_122_wd = reg_wdata[26]; + + assign ie0_3_e_123_we = addr_hit[187] & reg_we & ~wr_err; + assign ie0_3_e_123_wd = reg_wdata[27]; + + assign ie0_3_e_124_we = addr_hit[187] & reg_we & ~wr_err; + assign ie0_3_e_124_wd = reg_wdata[28]; + + assign ie0_3_e_125_we = addr_hit[187] & reg_we & ~wr_err; + assign ie0_3_e_125_wd = reg_wdata[29]; + + assign ie0_3_e_126_we = addr_hit[187] & reg_we & ~wr_err; + assign ie0_3_e_126_wd = reg_wdata[30]; + + assign ie0_3_e_127_we = addr_hit[187] & reg_we & ~wr_err; + assign ie0_3_e_127_wd = reg_wdata[31]; + + assign ie0_4_e_128_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_128_wd = reg_wdata[0]; + + assign ie0_4_e_129_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_129_wd = reg_wdata[1]; + + assign ie0_4_e_130_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_130_wd = reg_wdata[2]; + + assign ie0_4_e_131_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_131_wd = reg_wdata[3]; + + assign ie0_4_e_132_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_132_wd = reg_wdata[4]; + + assign ie0_4_e_133_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_133_wd = reg_wdata[5]; + + assign ie0_4_e_134_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_134_wd = reg_wdata[6]; + + assign ie0_4_e_135_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_135_wd = reg_wdata[7]; + + assign ie0_4_e_136_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_136_wd = reg_wdata[8]; + + assign ie0_4_e_137_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_137_wd = reg_wdata[9]; + + assign ie0_4_e_138_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_138_wd = reg_wdata[10]; + + assign ie0_4_e_139_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_139_wd = reg_wdata[11]; + + assign ie0_4_e_140_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_140_wd = reg_wdata[12]; + + assign ie0_4_e_141_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_141_wd = reg_wdata[13]; + + assign ie0_4_e_142_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_142_wd = reg_wdata[14]; + + assign ie0_4_e_143_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_143_wd = reg_wdata[15]; + + assign ie0_4_e_144_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_144_wd = reg_wdata[16]; + + assign ie0_4_e_145_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_145_wd = reg_wdata[17]; + + assign ie0_4_e_146_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_146_wd = reg_wdata[18]; + + assign ie0_4_e_147_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_147_wd = reg_wdata[19]; + + assign ie0_4_e_148_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_148_wd = reg_wdata[20]; + + assign ie0_4_e_149_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_149_wd = reg_wdata[21]; + + assign ie0_4_e_150_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_150_wd = reg_wdata[22]; + + assign ie0_4_e_151_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_151_wd = reg_wdata[23]; + + assign ie0_4_e_152_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_152_wd = reg_wdata[24]; + + assign ie0_4_e_153_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_153_wd = reg_wdata[25]; + + assign ie0_4_e_154_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_154_wd = reg_wdata[26]; + + assign ie0_4_e_155_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_155_wd = reg_wdata[27]; + + assign ie0_4_e_156_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_156_wd = reg_wdata[28]; + + assign ie0_4_e_157_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_157_wd = reg_wdata[29]; + + assign ie0_4_e_158_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_158_wd = reg_wdata[30]; + + assign ie0_4_e_159_we = addr_hit[188] & reg_we & ~wr_err; + assign ie0_4_e_159_wd = reg_wdata[31]; + + assign ie0_5_e_160_we = addr_hit[189] & reg_we & ~wr_err; + assign ie0_5_e_160_wd = reg_wdata[0]; + + assign ie0_5_e_161_we = addr_hit[189] & reg_we & ~wr_err; + assign ie0_5_e_161_wd = reg_wdata[1]; + + assign ie0_5_e_162_we = addr_hit[189] & reg_we & ~wr_err; + assign ie0_5_e_162_wd = reg_wdata[2]; + + assign ie0_5_e_163_we = addr_hit[189] & reg_we & ~wr_err; + assign ie0_5_e_163_wd = reg_wdata[3]; + + assign ie0_5_e_164_we = addr_hit[189] & reg_we & ~wr_err; + assign ie0_5_e_164_wd = reg_wdata[4]; + + assign ie0_5_e_165_we = addr_hit[189] & reg_we & ~wr_err; + assign ie0_5_e_165_wd = reg_wdata[5]; + + assign ie0_5_e_166_we = addr_hit[189] & reg_we & ~wr_err; + assign ie0_5_e_166_wd = reg_wdata[6]; + + assign ie0_5_e_167_we = addr_hit[189] & reg_we & ~wr_err; + assign ie0_5_e_167_wd = reg_wdata[7]; + + assign ie0_5_e_168_we = addr_hit[189] & reg_we & ~wr_err; + assign ie0_5_e_168_wd = reg_wdata[8]; + + assign ie0_5_e_169_we = addr_hit[189] & reg_we & ~wr_err; + assign ie0_5_e_169_wd = reg_wdata[9]; + + assign ie0_5_e_170_we = addr_hit[189] & reg_we & ~wr_err; + assign ie0_5_e_170_wd = reg_wdata[10]; + + assign ie0_5_e_171_we = addr_hit[189] & reg_we & ~wr_err; + assign ie0_5_e_171_wd = reg_wdata[11]; + + assign threshold0_we = addr_hit[190] & reg_we & ~wr_err; assign threshold0_wd = reg_wdata[1:0]; - assign cc0_we = addr_hit[135] & reg_we & ~wr_err; - assign cc0_wd = reg_wdata[6:0]; - assign cc0_re = addr_hit[135] && reg_re; + assign cc0_we = addr_hit[191] & reg_we & ~wr_err; + assign cc0_wd = reg_wdata[7:0]; + assign cc0_re = addr_hit[191] && reg_re; - assign msip0_we = addr_hit[136] & reg_we & ~wr_err; + assign msip0_we = addr_hit[192] & reg_we & ~wr_err; assign msip0_wd = reg_wdata[0]; // Read data return @@ -15757,9 +22087,65 @@ reg_rdata_next[23] = ip_3_p_119_qs; reg_rdata_next[24] = ip_3_p_120_qs; reg_rdata_next[25] = ip_3_p_121_qs; + reg_rdata_next[26] = ip_3_p_122_qs; + reg_rdata_next[27] = ip_3_p_123_qs; + reg_rdata_next[28] = ip_3_p_124_qs; + reg_rdata_next[29] = ip_3_p_125_qs; + reg_rdata_next[30] = ip_3_p_126_qs; + reg_rdata_next[31] = ip_3_p_127_qs; end addr_hit[4]: begin + reg_rdata_next[0] = ip_4_p_128_qs; + reg_rdata_next[1] = ip_4_p_129_qs; + reg_rdata_next[2] = ip_4_p_130_qs; + reg_rdata_next[3] = ip_4_p_131_qs; + reg_rdata_next[4] = ip_4_p_132_qs; + reg_rdata_next[5] = ip_4_p_133_qs; + reg_rdata_next[6] = ip_4_p_134_qs; + reg_rdata_next[7] = ip_4_p_135_qs; + reg_rdata_next[8] = ip_4_p_136_qs; + reg_rdata_next[9] = ip_4_p_137_qs; + reg_rdata_next[10] = ip_4_p_138_qs; + reg_rdata_next[11] = ip_4_p_139_qs; + reg_rdata_next[12] = ip_4_p_140_qs; + reg_rdata_next[13] = ip_4_p_141_qs; + reg_rdata_next[14] = ip_4_p_142_qs; + reg_rdata_next[15] = ip_4_p_143_qs; + reg_rdata_next[16] = ip_4_p_144_qs; + reg_rdata_next[17] = ip_4_p_145_qs; + reg_rdata_next[18] = ip_4_p_146_qs; + reg_rdata_next[19] = ip_4_p_147_qs; + reg_rdata_next[20] = ip_4_p_148_qs; + reg_rdata_next[21] = ip_4_p_149_qs; + reg_rdata_next[22] = ip_4_p_150_qs; + reg_rdata_next[23] = ip_4_p_151_qs; + reg_rdata_next[24] = ip_4_p_152_qs; + reg_rdata_next[25] = ip_4_p_153_qs; + reg_rdata_next[26] = ip_4_p_154_qs; + reg_rdata_next[27] = ip_4_p_155_qs; + reg_rdata_next[28] = ip_4_p_156_qs; + reg_rdata_next[29] = ip_4_p_157_qs; + reg_rdata_next[30] = ip_4_p_158_qs; + reg_rdata_next[31] = ip_4_p_159_qs; + end + + addr_hit[5]: begin + reg_rdata_next[0] = ip_5_p_160_qs; + reg_rdata_next[1] = ip_5_p_161_qs; + reg_rdata_next[2] = ip_5_p_162_qs; + reg_rdata_next[3] = ip_5_p_163_qs; + reg_rdata_next[4] = ip_5_p_164_qs; + reg_rdata_next[5] = ip_5_p_165_qs; + reg_rdata_next[6] = ip_5_p_166_qs; + reg_rdata_next[7] = ip_5_p_167_qs; + reg_rdata_next[8] = ip_5_p_168_qs; + reg_rdata_next[9] = ip_5_p_169_qs; + reg_rdata_next[10] = ip_5_p_170_qs; + reg_rdata_next[11] = ip_5_p_171_qs; + end + + addr_hit[6]: begin reg_rdata_next[0] = le_0_le_0_qs; reg_rdata_next[1] = le_0_le_1_qs; reg_rdata_next[2] = le_0_le_2_qs; @@ -15794,7 +22180,7 @@ reg_rdata_next[31] = le_0_le_31_qs; end - addr_hit[5]: begin + addr_hit[7]: begin reg_rdata_next[0] = le_1_le_32_qs; reg_rdata_next[1] = le_1_le_33_qs; reg_rdata_next[2] = le_1_le_34_qs; @@ -15829,7 +22215,7 @@ reg_rdata_next[31] = le_1_le_63_qs; end - addr_hit[6]: begin + addr_hit[8]: begin reg_rdata_next[0] = le_2_le_64_qs; reg_rdata_next[1] = le_2_le_65_qs; reg_rdata_next[2] = le_2_le_66_qs; @@ -15864,7 +22250,7 @@ reg_rdata_next[31] = le_2_le_95_qs; end - addr_hit[7]: begin + addr_hit[9]: begin reg_rdata_next[0] = le_3_le_96_qs; reg_rdata_next[1] = le_3_le_97_qs; reg_rdata_next[2] = le_3_le_98_qs; @@ -15891,497 +22277,753 @@ reg_rdata_next[23] = le_3_le_119_qs; reg_rdata_next[24] = le_3_le_120_qs; reg_rdata_next[25] = le_3_le_121_qs; - end - - addr_hit[8]: begin - reg_rdata_next[1:0] = prio0_qs; - end - - addr_hit[9]: begin - reg_rdata_next[1:0] = prio1_qs; + reg_rdata_next[26] = le_3_le_122_qs; + reg_rdata_next[27] = le_3_le_123_qs; + reg_rdata_next[28] = le_3_le_124_qs; + reg_rdata_next[29] = le_3_le_125_qs; + reg_rdata_next[30] = le_3_le_126_qs; + reg_rdata_next[31] = le_3_le_127_qs; end addr_hit[10]: begin - reg_rdata_next[1:0] = prio2_qs; + reg_rdata_next[0] = le_4_le_128_qs; + reg_rdata_next[1] = le_4_le_129_qs; + reg_rdata_next[2] = le_4_le_130_qs; + reg_rdata_next[3] = le_4_le_131_qs; + reg_rdata_next[4] = le_4_le_132_qs; + reg_rdata_next[5] = le_4_le_133_qs; + reg_rdata_next[6] = le_4_le_134_qs; + reg_rdata_next[7] = le_4_le_135_qs; + reg_rdata_next[8] = le_4_le_136_qs; + reg_rdata_next[9] = le_4_le_137_qs; + reg_rdata_next[10] = le_4_le_138_qs; + reg_rdata_next[11] = le_4_le_139_qs; + reg_rdata_next[12] = le_4_le_140_qs; + reg_rdata_next[13] = le_4_le_141_qs; + reg_rdata_next[14] = le_4_le_142_qs; + reg_rdata_next[15] = le_4_le_143_qs; + reg_rdata_next[16] = le_4_le_144_qs; + reg_rdata_next[17] = le_4_le_145_qs; + reg_rdata_next[18] = le_4_le_146_qs; + reg_rdata_next[19] = le_4_le_147_qs; + reg_rdata_next[20] = le_4_le_148_qs; + reg_rdata_next[21] = le_4_le_149_qs; + reg_rdata_next[22] = le_4_le_150_qs; + reg_rdata_next[23] = le_4_le_151_qs; + reg_rdata_next[24] = le_4_le_152_qs; + reg_rdata_next[25] = le_4_le_153_qs; + reg_rdata_next[26] = le_4_le_154_qs; + reg_rdata_next[27] = le_4_le_155_qs; + reg_rdata_next[28] = le_4_le_156_qs; + reg_rdata_next[29] = le_4_le_157_qs; + reg_rdata_next[30] = le_4_le_158_qs; + reg_rdata_next[31] = le_4_le_159_qs; end addr_hit[11]: begin - reg_rdata_next[1:0] = prio3_qs; + reg_rdata_next[0] = le_5_le_160_qs; + reg_rdata_next[1] = le_5_le_161_qs; + reg_rdata_next[2] = le_5_le_162_qs; + reg_rdata_next[3] = le_5_le_163_qs; + reg_rdata_next[4] = le_5_le_164_qs; + reg_rdata_next[5] = le_5_le_165_qs; + reg_rdata_next[6] = le_5_le_166_qs; + reg_rdata_next[7] = le_5_le_167_qs; + reg_rdata_next[8] = le_5_le_168_qs; + reg_rdata_next[9] = le_5_le_169_qs; + reg_rdata_next[10] = le_5_le_170_qs; + reg_rdata_next[11] = le_5_le_171_qs; end addr_hit[12]: begin - reg_rdata_next[1:0] = prio4_qs; + reg_rdata_next[1:0] = prio0_qs; end addr_hit[13]: begin - reg_rdata_next[1:0] = prio5_qs; + reg_rdata_next[1:0] = prio1_qs; end addr_hit[14]: begin - reg_rdata_next[1:0] = prio6_qs; + reg_rdata_next[1:0] = prio2_qs; end addr_hit[15]: begin - reg_rdata_next[1:0] = prio7_qs; + reg_rdata_next[1:0] = prio3_qs; end addr_hit[16]: begin - reg_rdata_next[1:0] = prio8_qs; + reg_rdata_next[1:0] = prio4_qs; end addr_hit[17]: begin - reg_rdata_next[1:0] = prio9_qs; + reg_rdata_next[1:0] = prio5_qs; end addr_hit[18]: begin - reg_rdata_next[1:0] = prio10_qs; + reg_rdata_next[1:0] = prio6_qs; end addr_hit[19]: begin - reg_rdata_next[1:0] = prio11_qs; + reg_rdata_next[1:0] = prio7_qs; end addr_hit[20]: begin - reg_rdata_next[1:0] = prio12_qs; + reg_rdata_next[1:0] = prio8_qs; end addr_hit[21]: begin - reg_rdata_next[1:0] = prio13_qs; + reg_rdata_next[1:0] = prio9_qs; end addr_hit[22]: begin - reg_rdata_next[1:0] = prio14_qs; + reg_rdata_next[1:0] = prio10_qs; end addr_hit[23]: begin - reg_rdata_next[1:0] = prio15_qs; + reg_rdata_next[1:0] = prio11_qs; end addr_hit[24]: begin - reg_rdata_next[1:0] = prio16_qs; + reg_rdata_next[1:0] = prio12_qs; end addr_hit[25]: begin - reg_rdata_next[1:0] = prio17_qs; + reg_rdata_next[1:0] = prio13_qs; end addr_hit[26]: begin - reg_rdata_next[1:0] = prio18_qs; + reg_rdata_next[1:0] = prio14_qs; end addr_hit[27]: begin - reg_rdata_next[1:0] = prio19_qs; + reg_rdata_next[1:0] = prio15_qs; end addr_hit[28]: begin - reg_rdata_next[1:0] = prio20_qs; + reg_rdata_next[1:0] = prio16_qs; end addr_hit[29]: begin - reg_rdata_next[1:0] = prio21_qs; + reg_rdata_next[1:0] = prio17_qs; end addr_hit[30]: begin - reg_rdata_next[1:0] = prio22_qs; + reg_rdata_next[1:0] = prio18_qs; end addr_hit[31]: begin - reg_rdata_next[1:0] = prio23_qs; + reg_rdata_next[1:0] = prio19_qs; end addr_hit[32]: begin - reg_rdata_next[1:0] = prio24_qs; + reg_rdata_next[1:0] = prio20_qs; end addr_hit[33]: begin - reg_rdata_next[1:0] = prio25_qs; + reg_rdata_next[1:0] = prio21_qs; end addr_hit[34]: begin - reg_rdata_next[1:0] = prio26_qs; + reg_rdata_next[1:0] = prio22_qs; end addr_hit[35]: begin - reg_rdata_next[1:0] = prio27_qs; + reg_rdata_next[1:0] = prio23_qs; end addr_hit[36]: begin - reg_rdata_next[1:0] = prio28_qs; + reg_rdata_next[1:0] = prio24_qs; end addr_hit[37]: begin - reg_rdata_next[1:0] = prio29_qs; + reg_rdata_next[1:0] = prio25_qs; end addr_hit[38]: begin - reg_rdata_next[1:0] = prio30_qs; + reg_rdata_next[1:0] = prio26_qs; end addr_hit[39]: begin - reg_rdata_next[1:0] = prio31_qs; + reg_rdata_next[1:0] = prio27_qs; end addr_hit[40]: begin - reg_rdata_next[1:0] = prio32_qs; + reg_rdata_next[1:0] = prio28_qs; end addr_hit[41]: begin - reg_rdata_next[1:0] = prio33_qs; + reg_rdata_next[1:0] = prio29_qs; end addr_hit[42]: begin - reg_rdata_next[1:0] = prio34_qs; + reg_rdata_next[1:0] = prio30_qs; end addr_hit[43]: begin - reg_rdata_next[1:0] = prio35_qs; + reg_rdata_next[1:0] = prio31_qs; end addr_hit[44]: begin - reg_rdata_next[1:0] = prio36_qs; + reg_rdata_next[1:0] = prio32_qs; end addr_hit[45]: begin - reg_rdata_next[1:0] = prio37_qs; + reg_rdata_next[1:0] = prio33_qs; end addr_hit[46]: begin - reg_rdata_next[1:0] = prio38_qs; + reg_rdata_next[1:0] = prio34_qs; end addr_hit[47]: begin - reg_rdata_next[1:0] = prio39_qs; + reg_rdata_next[1:0] = prio35_qs; end addr_hit[48]: begin - reg_rdata_next[1:0] = prio40_qs; + reg_rdata_next[1:0] = prio36_qs; end addr_hit[49]: begin - reg_rdata_next[1:0] = prio41_qs; + reg_rdata_next[1:0] = prio37_qs; end addr_hit[50]: begin - reg_rdata_next[1:0] = prio42_qs; + reg_rdata_next[1:0] = prio38_qs; end addr_hit[51]: begin - reg_rdata_next[1:0] = prio43_qs; + reg_rdata_next[1:0] = prio39_qs; end addr_hit[52]: begin - reg_rdata_next[1:0] = prio44_qs; + reg_rdata_next[1:0] = prio40_qs; end addr_hit[53]: begin - reg_rdata_next[1:0] = prio45_qs; + reg_rdata_next[1:0] = prio41_qs; end addr_hit[54]: begin - reg_rdata_next[1:0] = prio46_qs; + reg_rdata_next[1:0] = prio42_qs; end addr_hit[55]: begin - reg_rdata_next[1:0] = prio47_qs; + reg_rdata_next[1:0] = prio43_qs; end addr_hit[56]: begin - reg_rdata_next[1:0] = prio48_qs; + reg_rdata_next[1:0] = prio44_qs; end addr_hit[57]: begin - reg_rdata_next[1:0] = prio49_qs; + reg_rdata_next[1:0] = prio45_qs; end addr_hit[58]: begin - reg_rdata_next[1:0] = prio50_qs; + reg_rdata_next[1:0] = prio46_qs; end addr_hit[59]: begin - reg_rdata_next[1:0] = prio51_qs; + reg_rdata_next[1:0] = prio47_qs; end addr_hit[60]: begin - reg_rdata_next[1:0] = prio52_qs; + reg_rdata_next[1:0] = prio48_qs; end addr_hit[61]: begin - reg_rdata_next[1:0] = prio53_qs; + reg_rdata_next[1:0] = prio49_qs; end addr_hit[62]: begin - reg_rdata_next[1:0] = prio54_qs; + reg_rdata_next[1:0] = prio50_qs; end addr_hit[63]: begin - reg_rdata_next[1:0] = prio55_qs; + reg_rdata_next[1:0] = prio51_qs; end addr_hit[64]: begin - reg_rdata_next[1:0] = prio56_qs; + reg_rdata_next[1:0] = prio52_qs; end addr_hit[65]: begin - reg_rdata_next[1:0] = prio57_qs; + reg_rdata_next[1:0] = prio53_qs; end addr_hit[66]: begin - reg_rdata_next[1:0] = prio58_qs; + reg_rdata_next[1:0] = prio54_qs; end addr_hit[67]: begin - reg_rdata_next[1:0] = prio59_qs; + reg_rdata_next[1:0] = prio55_qs; end addr_hit[68]: begin - reg_rdata_next[1:0] = prio60_qs; + reg_rdata_next[1:0] = prio56_qs; end addr_hit[69]: begin - reg_rdata_next[1:0] = prio61_qs; + reg_rdata_next[1:0] = prio57_qs; end addr_hit[70]: begin - reg_rdata_next[1:0] = prio62_qs; + reg_rdata_next[1:0] = prio58_qs; end addr_hit[71]: begin - reg_rdata_next[1:0] = prio63_qs; + reg_rdata_next[1:0] = prio59_qs; end addr_hit[72]: begin - reg_rdata_next[1:0] = prio64_qs; + reg_rdata_next[1:0] = prio60_qs; end addr_hit[73]: begin - reg_rdata_next[1:0] = prio65_qs; + reg_rdata_next[1:0] = prio61_qs; end addr_hit[74]: begin - reg_rdata_next[1:0] = prio66_qs; + reg_rdata_next[1:0] = prio62_qs; end addr_hit[75]: begin - reg_rdata_next[1:0] = prio67_qs; + reg_rdata_next[1:0] = prio63_qs; end addr_hit[76]: begin - reg_rdata_next[1:0] = prio68_qs; + reg_rdata_next[1:0] = prio64_qs; end addr_hit[77]: begin - reg_rdata_next[1:0] = prio69_qs; + reg_rdata_next[1:0] = prio65_qs; end addr_hit[78]: begin - reg_rdata_next[1:0] = prio70_qs; + reg_rdata_next[1:0] = prio66_qs; end addr_hit[79]: begin - reg_rdata_next[1:0] = prio71_qs; + reg_rdata_next[1:0] = prio67_qs; end addr_hit[80]: begin - reg_rdata_next[1:0] = prio72_qs; + reg_rdata_next[1:0] = prio68_qs; end addr_hit[81]: begin - reg_rdata_next[1:0] = prio73_qs; + reg_rdata_next[1:0] = prio69_qs; end addr_hit[82]: begin - reg_rdata_next[1:0] = prio74_qs; + reg_rdata_next[1:0] = prio70_qs; end addr_hit[83]: begin - reg_rdata_next[1:0] = prio75_qs; + reg_rdata_next[1:0] = prio71_qs; end addr_hit[84]: begin - reg_rdata_next[1:0] = prio76_qs; + reg_rdata_next[1:0] = prio72_qs; end addr_hit[85]: begin - reg_rdata_next[1:0] = prio77_qs; + reg_rdata_next[1:0] = prio73_qs; end addr_hit[86]: begin - reg_rdata_next[1:0] = prio78_qs; + reg_rdata_next[1:0] = prio74_qs; end addr_hit[87]: begin - reg_rdata_next[1:0] = prio79_qs; + reg_rdata_next[1:0] = prio75_qs; end addr_hit[88]: begin - reg_rdata_next[1:0] = prio80_qs; + reg_rdata_next[1:0] = prio76_qs; end addr_hit[89]: begin - reg_rdata_next[1:0] = prio81_qs; + reg_rdata_next[1:0] = prio77_qs; end addr_hit[90]: begin - reg_rdata_next[1:0] = prio82_qs; + reg_rdata_next[1:0] = prio78_qs; end addr_hit[91]: begin - reg_rdata_next[1:0] = prio83_qs; + reg_rdata_next[1:0] = prio79_qs; end addr_hit[92]: begin - reg_rdata_next[1:0] = prio84_qs; + reg_rdata_next[1:0] = prio80_qs; end addr_hit[93]: begin - reg_rdata_next[1:0] = prio85_qs; + reg_rdata_next[1:0] = prio81_qs; end addr_hit[94]: begin - reg_rdata_next[1:0] = prio86_qs; + reg_rdata_next[1:0] = prio82_qs; end addr_hit[95]: begin - reg_rdata_next[1:0] = prio87_qs; + reg_rdata_next[1:0] = prio83_qs; end addr_hit[96]: begin - reg_rdata_next[1:0] = prio88_qs; + reg_rdata_next[1:0] = prio84_qs; end addr_hit[97]: begin - reg_rdata_next[1:0] = prio89_qs; + reg_rdata_next[1:0] = prio85_qs; end addr_hit[98]: begin - reg_rdata_next[1:0] = prio90_qs; + reg_rdata_next[1:0] = prio86_qs; end addr_hit[99]: begin - reg_rdata_next[1:0] = prio91_qs; + reg_rdata_next[1:0] = prio87_qs; end addr_hit[100]: begin - reg_rdata_next[1:0] = prio92_qs; + reg_rdata_next[1:0] = prio88_qs; end addr_hit[101]: begin - reg_rdata_next[1:0] = prio93_qs; + reg_rdata_next[1:0] = prio89_qs; end addr_hit[102]: begin - reg_rdata_next[1:0] = prio94_qs; + reg_rdata_next[1:0] = prio90_qs; end addr_hit[103]: begin - reg_rdata_next[1:0] = prio95_qs; + reg_rdata_next[1:0] = prio91_qs; end addr_hit[104]: begin - reg_rdata_next[1:0] = prio96_qs; + reg_rdata_next[1:0] = prio92_qs; end addr_hit[105]: begin - reg_rdata_next[1:0] = prio97_qs; + reg_rdata_next[1:0] = prio93_qs; end addr_hit[106]: begin - reg_rdata_next[1:0] = prio98_qs; + reg_rdata_next[1:0] = prio94_qs; end addr_hit[107]: begin - reg_rdata_next[1:0] = prio99_qs; + reg_rdata_next[1:0] = prio95_qs; end addr_hit[108]: begin - reg_rdata_next[1:0] = prio100_qs; + reg_rdata_next[1:0] = prio96_qs; end addr_hit[109]: begin - reg_rdata_next[1:0] = prio101_qs; + reg_rdata_next[1:0] = prio97_qs; end addr_hit[110]: begin - reg_rdata_next[1:0] = prio102_qs; + reg_rdata_next[1:0] = prio98_qs; end addr_hit[111]: begin - reg_rdata_next[1:0] = prio103_qs; + reg_rdata_next[1:0] = prio99_qs; end addr_hit[112]: begin - reg_rdata_next[1:0] = prio104_qs; + reg_rdata_next[1:0] = prio100_qs; end addr_hit[113]: begin - reg_rdata_next[1:0] = prio105_qs; + reg_rdata_next[1:0] = prio101_qs; end addr_hit[114]: begin - reg_rdata_next[1:0] = prio106_qs; + reg_rdata_next[1:0] = prio102_qs; end addr_hit[115]: begin - reg_rdata_next[1:0] = prio107_qs; + reg_rdata_next[1:0] = prio103_qs; end addr_hit[116]: begin - reg_rdata_next[1:0] = prio108_qs; + reg_rdata_next[1:0] = prio104_qs; end addr_hit[117]: begin - reg_rdata_next[1:0] = prio109_qs; + reg_rdata_next[1:0] = prio105_qs; end addr_hit[118]: begin - reg_rdata_next[1:0] = prio110_qs; + reg_rdata_next[1:0] = prio106_qs; end addr_hit[119]: begin - reg_rdata_next[1:0] = prio111_qs; + reg_rdata_next[1:0] = prio107_qs; end addr_hit[120]: begin - reg_rdata_next[1:0] = prio112_qs; + reg_rdata_next[1:0] = prio108_qs; end addr_hit[121]: begin - reg_rdata_next[1:0] = prio113_qs; + reg_rdata_next[1:0] = prio109_qs; end addr_hit[122]: begin - reg_rdata_next[1:0] = prio114_qs; + reg_rdata_next[1:0] = prio110_qs; end addr_hit[123]: begin - reg_rdata_next[1:0] = prio115_qs; + reg_rdata_next[1:0] = prio111_qs; end addr_hit[124]: begin - reg_rdata_next[1:0] = prio116_qs; + reg_rdata_next[1:0] = prio112_qs; end addr_hit[125]: begin - reg_rdata_next[1:0] = prio117_qs; + reg_rdata_next[1:0] = prio113_qs; end addr_hit[126]: begin - reg_rdata_next[1:0] = prio118_qs; + reg_rdata_next[1:0] = prio114_qs; end addr_hit[127]: begin - reg_rdata_next[1:0] = prio119_qs; + reg_rdata_next[1:0] = prio115_qs; end addr_hit[128]: begin - reg_rdata_next[1:0] = prio120_qs; + reg_rdata_next[1:0] = prio116_qs; end addr_hit[129]: begin - reg_rdata_next[1:0] = prio121_qs; + reg_rdata_next[1:0] = prio117_qs; end addr_hit[130]: begin + reg_rdata_next[1:0] = prio118_qs; + end + + addr_hit[131]: begin + reg_rdata_next[1:0] = prio119_qs; + end + + addr_hit[132]: begin + reg_rdata_next[1:0] = prio120_qs; + end + + addr_hit[133]: begin + reg_rdata_next[1:0] = prio121_qs; + end + + addr_hit[134]: begin + reg_rdata_next[1:0] = prio122_qs; + end + + addr_hit[135]: begin + reg_rdata_next[1:0] = prio123_qs; + end + + addr_hit[136]: begin + reg_rdata_next[1:0] = prio124_qs; + end + + addr_hit[137]: begin + reg_rdata_next[1:0] = prio125_qs; + end + + addr_hit[138]: begin + reg_rdata_next[1:0] = prio126_qs; + end + + addr_hit[139]: begin + reg_rdata_next[1:0] = prio127_qs; + end + + addr_hit[140]: begin + reg_rdata_next[1:0] = prio128_qs; + end + + addr_hit[141]: begin + reg_rdata_next[1:0] = prio129_qs; + end + + addr_hit[142]: begin + reg_rdata_next[1:0] = prio130_qs; + end + + addr_hit[143]: begin + reg_rdata_next[1:0] = prio131_qs; + end + + addr_hit[144]: begin + reg_rdata_next[1:0] = prio132_qs; + end + + addr_hit[145]: begin + reg_rdata_next[1:0] = prio133_qs; + end + + addr_hit[146]: begin + reg_rdata_next[1:0] = prio134_qs; + end + + addr_hit[147]: begin + reg_rdata_next[1:0] = prio135_qs; + end + + addr_hit[148]: begin + reg_rdata_next[1:0] = prio136_qs; + end + + addr_hit[149]: begin + reg_rdata_next[1:0] = prio137_qs; + end + + addr_hit[150]: begin + reg_rdata_next[1:0] = prio138_qs; + end + + addr_hit[151]: begin + reg_rdata_next[1:0] = prio139_qs; + end + + addr_hit[152]: begin + reg_rdata_next[1:0] = prio140_qs; + end + + addr_hit[153]: begin + reg_rdata_next[1:0] = prio141_qs; + end + + addr_hit[154]: begin + reg_rdata_next[1:0] = prio142_qs; + end + + addr_hit[155]: begin + reg_rdata_next[1:0] = prio143_qs; + end + + addr_hit[156]: begin + reg_rdata_next[1:0] = prio144_qs; + end + + addr_hit[157]: begin + reg_rdata_next[1:0] = prio145_qs; + end + + addr_hit[158]: begin + reg_rdata_next[1:0] = prio146_qs; + end + + addr_hit[159]: begin + reg_rdata_next[1:0] = prio147_qs; + end + + addr_hit[160]: begin + reg_rdata_next[1:0] = prio148_qs; + end + + addr_hit[161]: begin + reg_rdata_next[1:0] = prio149_qs; + end + + addr_hit[162]: begin + reg_rdata_next[1:0] = prio150_qs; + end + + addr_hit[163]: begin + reg_rdata_next[1:0] = prio151_qs; + end + + addr_hit[164]: begin + reg_rdata_next[1:0] = prio152_qs; + end + + addr_hit[165]: begin + reg_rdata_next[1:0] = prio153_qs; + end + + addr_hit[166]: begin + reg_rdata_next[1:0] = prio154_qs; + end + + addr_hit[167]: begin + reg_rdata_next[1:0] = prio155_qs; + end + + addr_hit[168]: begin + reg_rdata_next[1:0] = prio156_qs; + end + + addr_hit[169]: begin + reg_rdata_next[1:0] = prio157_qs; + end + + addr_hit[170]: begin + reg_rdata_next[1:0] = prio158_qs; + end + + addr_hit[171]: begin + reg_rdata_next[1:0] = prio159_qs; + end + + addr_hit[172]: begin + reg_rdata_next[1:0] = prio160_qs; + end + + addr_hit[173]: begin + reg_rdata_next[1:0] = prio161_qs; + end + + addr_hit[174]: begin + reg_rdata_next[1:0] = prio162_qs; + end + + addr_hit[175]: begin + reg_rdata_next[1:0] = prio163_qs; + end + + addr_hit[176]: begin + reg_rdata_next[1:0] = prio164_qs; + end + + addr_hit[177]: begin + reg_rdata_next[1:0] = prio165_qs; + end + + addr_hit[178]: begin + reg_rdata_next[1:0] = prio166_qs; + end + + addr_hit[179]: begin + reg_rdata_next[1:0] = prio167_qs; + end + + addr_hit[180]: begin + reg_rdata_next[1:0] = prio168_qs; + end + + addr_hit[181]: begin + reg_rdata_next[1:0] = prio169_qs; + end + + addr_hit[182]: begin + reg_rdata_next[1:0] = prio170_qs; + end + + addr_hit[183]: begin + reg_rdata_next[1:0] = prio171_qs; + end + + addr_hit[184]: begin reg_rdata_next[0] = ie0_0_e_0_qs; reg_rdata_next[1] = ie0_0_e_1_qs; reg_rdata_next[2] = ie0_0_e_2_qs; @@ -16416,7 +23058,7 @@ reg_rdata_next[31] = ie0_0_e_31_qs; end - addr_hit[131]: begin + addr_hit[185]: begin reg_rdata_next[0] = ie0_1_e_32_qs; reg_rdata_next[1] = ie0_1_e_33_qs; reg_rdata_next[2] = ie0_1_e_34_qs; @@ -16451,7 +23093,7 @@ reg_rdata_next[31] = ie0_1_e_63_qs; end - addr_hit[132]: begin + addr_hit[186]: begin reg_rdata_next[0] = ie0_2_e_64_qs; reg_rdata_next[1] = ie0_2_e_65_qs; reg_rdata_next[2] = ie0_2_e_66_qs; @@ -16486,7 +23128,7 @@ reg_rdata_next[31] = ie0_2_e_95_qs; end - addr_hit[133]: begin + addr_hit[187]: begin reg_rdata_next[0] = ie0_3_e_96_qs; reg_rdata_next[1] = ie0_3_e_97_qs; reg_rdata_next[2] = ie0_3_e_98_qs; @@ -16513,17 +23155,73 @@ reg_rdata_next[23] = ie0_3_e_119_qs; reg_rdata_next[24] = ie0_3_e_120_qs; reg_rdata_next[25] = ie0_3_e_121_qs; + reg_rdata_next[26] = ie0_3_e_122_qs; + reg_rdata_next[27] = ie0_3_e_123_qs; + reg_rdata_next[28] = ie0_3_e_124_qs; + reg_rdata_next[29] = ie0_3_e_125_qs; + reg_rdata_next[30] = ie0_3_e_126_qs; + reg_rdata_next[31] = ie0_3_e_127_qs; end - addr_hit[134]: begin + addr_hit[188]: begin + reg_rdata_next[0] = ie0_4_e_128_qs; + reg_rdata_next[1] = ie0_4_e_129_qs; + reg_rdata_next[2] = ie0_4_e_130_qs; + reg_rdata_next[3] = ie0_4_e_131_qs; + reg_rdata_next[4] = ie0_4_e_132_qs; + reg_rdata_next[5] = ie0_4_e_133_qs; + reg_rdata_next[6] = ie0_4_e_134_qs; + reg_rdata_next[7] = ie0_4_e_135_qs; + reg_rdata_next[8] = ie0_4_e_136_qs; + reg_rdata_next[9] = ie0_4_e_137_qs; + reg_rdata_next[10] = ie0_4_e_138_qs; + reg_rdata_next[11] = ie0_4_e_139_qs; + reg_rdata_next[12] = ie0_4_e_140_qs; + reg_rdata_next[13] = ie0_4_e_141_qs; + reg_rdata_next[14] = ie0_4_e_142_qs; + reg_rdata_next[15] = ie0_4_e_143_qs; + reg_rdata_next[16] = ie0_4_e_144_qs; + reg_rdata_next[17] = ie0_4_e_145_qs; + reg_rdata_next[18] = ie0_4_e_146_qs; + reg_rdata_next[19] = ie0_4_e_147_qs; + reg_rdata_next[20] = ie0_4_e_148_qs; + reg_rdata_next[21] = ie0_4_e_149_qs; + reg_rdata_next[22] = ie0_4_e_150_qs; + reg_rdata_next[23] = ie0_4_e_151_qs; + reg_rdata_next[24] = ie0_4_e_152_qs; + reg_rdata_next[25] = ie0_4_e_153_qs; + reg_rdata_next[26] = ie0_4_e_154_qs; + reg_rdata_next[27] = ie0_4_e_155_qs; + reg_rdata_next[28] = ie0_4_e_156_qs; + reg_rdata_next[29] = ie0_4_e_157_qs; + reg_rdata_next[30] = ie0_4_e_158_qs; + reg_rdata_next[31] = ie0_4_e_159_qs; + end + + addr_hit[189]: begin + reg_rdata_next[0] = ie0_5_e_160_qs; + reg_rdata_next[1] = ie0_5_e_161_qs; + reg_rdata_next[2] = ie0_5_e_162_qs; + reg_rdata_next[3] = ie0_5_e_163_qs; + reg_rdata_next[4] = ie0_5_e_164_qs; + reg_rdata_next[5] = ie0_5_e_165_qs; + reg_rdata_next[6] = ie0_5_e_166_qs; + reg_rdata_next[7] = ie0_5_e_167_qs; + reg_rdata_next[8] = ie0_5_e_168_qs; + reg_rdata_next[9] = ie0_5_e_169_qs; + reg_rdata_next[10] = ie0_5_e_170_qs; + reg_rdata_next[11] = ie0_5_e_171_qs; + end + + addr_hit[190]: begin reg_rdata_next[1:0] = threshold0_qs; end - addr_hit[135]: begin - reg_rdata_next[6:0] = cc0_qs; + addr_hit[191]: begin + reg_rdata_next[7:0] = cc0_qs; end - addr_hit[136]: begin + addr_hit[192]: begin reg_rdata_next[0] = msip0_qs; end
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson index 4fabea0..ec2845d 100644 --- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson +++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
@@ -31,6 +31,10 @@ uart1 uart2 uart3 + i2c0 + i2c1 + i2c2 + pattgen gpio spi_device rv_timer @@ -134,6 +138,78 @@ pipeline_byp: "true" } { + name: i2c0 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: "false" + inst_type: i2c + addr_range: + [ + { + base_addr: 0x40080000 + size_byte: 0x1000 + } + ] + xbar: false + stub: false + pipeline_byp: "true" + } + { + name: i2c1 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: "false" + inst_type: i2c + addr_range: + [ + { + base_addr: 0x40090000 + size_byte: 0x1000 + } + ] + xbar: false + stub: false + pipeline_byp: "true" + } + { + name: i2c2 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: "false" + inst_type: i2c + addr_range: + [ + { + base_addr: 0x400A0000 + size_byte: 0x1000 + } + ] + xbar: false + stub: false + pipeline_byp: "true" + } + { + name: pattgen + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: "false" + inst_type: pattgen + addr_range: + [ + { + base_addr: 0x400E0000 + size_byte: 0x1000 + } + ] + xbar: false + stub: false + pipeline_byp: "true" + } + { name: gpio type: device clock: clk_peri_i
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson index 1ada605..55a3129 100644 --- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson +++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
@@ -45,6 +45,30 @@ } { struct: "tl" type: "req_rsp" + name: "tl_i2c0" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_i2c1" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_i2c2" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_pattgen" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" name: "tl_gpio" act: "req" package: "tlul_pkg"
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv index ee1c37b..db1fe10 100644 --- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
@@ -21,6 +21,10 @@ `CONNECT_TL_DEVICE_IF(uart1, dut, clk_peri_i, rst_n) `CONNECT_TL_DEVICE_IF(uart2, dut, clk_peri_i, rst_n) `CONNECT_TL_DEVICE_IF(uart3, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(i2c0, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(i2c1, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(i2c2, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(pattgen, dut, clk_peri_i, rst_n) `CONNECT_TL_DEVICE_IF(gpio, dut, clk_peri_i, rst_n) `CONNECT_TL_DEVICE_IF(spi_device, dut, clk_peri_i, rst_n) `CONNECT_TL_DEVICE_IF(rv_timer, dut, clk_peri_i, rst_n)
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg index 52057b9..a8657e2 100644 --- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg +++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg
@@ -27,6 +27,20 @@ -node tb.dut tl_uart3_o.a_address[15:12] -node tb.dut tl_uart3_o.a_address[29:18] -node tb.dut tl_uart3_o.a_address[31:31] +-node tb.dut tl_i2c0_o.a_address[18:12] +-node tb.dut tl_i2c0_o.a_address[29:20] +-node tb.dut tl_i2c0_o.a_address[31:31] +-node tb.dut tl_i2c1_o.a_address[15:12] +-node tb.dut tl_i2c1_o.a_address[18:17] +-node tb.dut tl_i2c1_o.a_address[29:20] +-node tb.dut tl_i2c1_o.a_address[31:31] +-node tb.dut tl_i2c2_o.a_address[16:12] +-node tb.dut tl_i2c2_o.a_address[18:18] +-node tb.dut tl_i2c2_o.a_address[29:20] +-node tb.dut tl_i2c2_o.a_address[31:31] +-node tb.dut tl_pattgen_o.a_address[16:12] +-node tb.dut tl_pattgen_o.a_address[29:20] +-node tb.dut tl_pattgen_o.a_address[31:31] -node tb.dut tl_gpio_o.a_address[17:12] -node tb.dut tl_gpio_o.a_address[29:19] -node tb.dut tl_gpio_o.a_address[31:31]
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv index f32a436..69bde58 100644 --- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
@@ -19,6 +19,18 @@ '{"uart3", '{ '{32'h40030000, 32'h40030fff} }}, + '{"i2c0", '{ + '{32'h40080000, 32'h40080fff} + }}, + '{"i2c1", '{ + '{32'h40090000, 32'h40090fff} + }}, + '{"i2c2", '{ + '{32'h400a0000, 32'h400a0fff} + }}, + '{"pattgen", '{ + '{32'h400e0000, 32'h400e0fff} + }}, '{"gpio", '{ '{32'h40040000, 32'h40040fff} }}, @@ -72,6 +84,10 @@ "uart1", "uart2", "uart3", + "i2c0", + "i2c1", + "i2c2", + "pattgen", "gpio", "spi_device", "rv_timer",
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv index 75fa8d9..3945cf9 100644 --- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv +++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
@@ -38,6 +38,30 @@ .h2d (tl_uart3_o), .d2h (tl_uart3_i) ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_i2c0 ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_i2c0_o), + .d2h (tl_i2c0_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_i2c1 ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_i2c1_o), + .d2h (tl_i2c1_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_i2c2 ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_i2c2_o), + .d2h (tl_i2c2_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_pattgen ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_pattgen_o), + .d2h (tl_pattgen_i) + ); bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_gpio ( .clk_i (clk_peri_i), .rst_ni (rst_peri_ni),
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv index c7610f0..74639fc 100644 --- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv +++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
@@ -10,6 +10,10 @@ localparam logic [31:0] ADDR_SPACE_UART1 = 32'h 40010000; localparam logic [31:0] ADDR_SPACE_UART2 = 32'h 40020000; localparam logic [31:0] ADDR_SPACE_UART3 = 32'h 40030000; + localparam logic [31:0] ADDR_SPACE_I2C0 = 32'h 40080000; + localparam logic [31:0] ADDR_SPACE_I2C1 = 32'h 40090000; + localparam logic [31:0] ADDR_SPACE_I2C2 = 32'h 400a0000; + localparam logic [31:0] ADDR_SPACE_PATTGEN = 32'h 400e0000; localparam logic [31:0] ADDR_SPACE_GPIO = 32'h 40040000; localparam logic [31:0] ADDR_SPACE_SPI_DEVICE = 32'h 40050000; localparam logic [31:0] ADDR_SPACE_RV_TIMER = 32'h 40100000; @@ -30,6 +34,10 @@ localparam logic [31:0] ADDR_MASK_UART1 = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_UART2 = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_UART3 = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_I2C0 = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_I2C1 = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_I2C2 = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_PATTGEN = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_GPIO = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_SPI_DEVICE = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_RV_TIMER = 32'h 00000fff; @@ -47,28 +55,32 @@ localparam logic [31:0] ADDR_MASK_AST_WRAPPER = 32'h 00000fff; localparam int N_HOST = 1; - localparam int N_DEVICE = 19; + localparam int N_DEVICE = 23; typedef enum int { TlUart0 = 0, TlUart1 = 1, TlUart2 = 2, TlUart3 = 3, - TlGpio = 4, - TlSpiDevice = 5, - TlRvTimer = 6, - TlUsbdev = 7, - TlPwrmgr = 8, - TlRstmgr = 9, - TlClkmgr = 10, - TlRamRet = 11, - TlOtpCtrl = 12, - TlLcCtrl = 13, - TlSensorCtrl = 14, - TlAlertHandler = 15, - TlSramCtrlRet = 16, - TlNmiGen = 17, - TlAstWrapper = 18 + TlI2C0 = 4, + TlI2C1 = 5, + TlI2C2 = 6, + TlPattgen = 7, + TlGpio = 8, + TlSpiDevice = 9, + TlRvTimer = 10, + TlUsbdev = 11, + TlPwrmgr = 12, + TlRstmgr = 13, + TlClkmgr = 14, + TlRamRet = 15, + TlOtpCtrl = 16, + TlLcCtrl = 17, + TlSensorCtrl = 18, + TlAlertHandler = 19, + TlSramCtrlRet = 20, + TlNmiGen = 21, + TlAstWrapper = 22 } tl_device_e; typedef enum int {
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv index 379fc84..c6cfcbd 100644 --- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv +++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
@@ -7,11 +7,15 @@ // // Interconnect // main -// -> s1n_20 +// -> s1n_24 // -> uart0 // -> uart1 // -> uart2 // -> uart3 +// -> i2c0 +// -> i2c1 +// -> i2c2 +// -> pattgen // -> gpio // -> spi_device // -> rv_timer @@ -45,6 +49,14 @@ input tlul_pkg::tl_d2h_t tl_uart2_i, output tlul_pkg::tl_h2d_t tl_uart3_o, input tlul_pkg::tl_d2h_t tl_uart3_i, + output tlul_pkg::tl_h2d_t tl_i2c0_o, + input tlul_pkg::tl_d2h_t tl_i2c0_i, + output tlul_pkg::tl_h2d_t tl_i2c1_o, + input tlul_pkg::tl_d2h_t tl_i2c1_i, + output tlul_pkg::tl_h2d_t tl_i2c2_o, + input tlul_pkg::tl_d2h_t tl_i2c2_i, + output tlul_pkg::tl_h2d_t tl_pattgen_o, + input tlul_pkg::tl_d2h_t tl_pattgen_i, output tlul_pkg::tl_h2d_t tl_gpio_o, input tlul_pkg::tl_d2h_t tl_gpio_i, output tlul_pkg::tl_h2d_t tl_spi_device_o, @@ -87,137 +99,161 @@ logic unused_scanmode; assign unused_scanmode = scanmode_i; - tl_h2d_t tl_s1n_20_us_h2d ; - tl_d2h_t tl_s1n_20_us_d2h ; + tl_h2d_t tl_s1n_24_us_h2d ; + tl_d2h_t tl_s1n_24_us_d2h ; - tl_h2d_t tl_s1n_20_ds_h2d [19]; - tl_d2h_t tl_s1n_20_ds_d2h [19]; + tl_h2d_t tl_s1n_24_ds_h2d [23]; + tl_d2h_t tl_s1n_24_ds_d2h [23]; // Create steering signal - logic [4:0] dev_sel_s1n_20; + logic [4:0] dev_sel_s1n_24; - assign tl_uart0_o = tl_s1n_20_ds_h2d[0]; - assign tl_s1n_20_ds_d2h[0] = tl_uart0_i; + assign tl_uart0_o = tl_s1n_24_ds_h2d[0]; + assign tl_s1n_24_ds_d2h[0] = tl_uart0_i; - assign tl_uart1_o = tl_s1n_20_ds_h2d[1]; - assign tl_s1n_20_ds_d2h[1] = tl_uart1_i; + assign tl_uart1_o = tl_s1n_24_ds_h2d[1]; + assign tl_s1n_24_ds_d2h[1] = tl_uart1_i; - assign tl_uart2_o = tl_s1n_20_ds_h2d[2]; - assign tl_s1n_20_ds_d2h[2] = tl_uart2_i; + assign tl_uart2_o = tl_s1n_24_ds_h2d[2]; + assign tl_s1n_24_ds_d2h[2] = tl_uart2_i; - assign tl_uart3_o = tl_s1n_20_ds_h2d[3]; - assign tl_s1n_20_ds_d2h[3] = tl_uart3_i; + assign tl_uart3_o = tl_s1n_24_ds_h2d[3]; + assign tl_s1n_24_ds_d2h[3] = tl_uart3_i; - assign tl_gpio_o = tl_s1n_20_ds_h2d[4]; - assign tl_s1n_20_ds_d2h[4] = tl_gpio_i; + assign tl_i2c0_o = tl_s1n_24_ds_h2d[4]; + assign tl_s1n_24_ds_d2h[4] = tl_i2c0_i; - assign tl_spi_device_o = tl_s1n_20_ds_h2d[5]; - assign tl_s1n_20_ds_d2h[5] = tl_spi_device_i; + assign tl_i2c1_o = tl_s1n_24_ds_h2d[5]; + assign tl_s1n_24_ds_d2h[5] = tl_i2c1_i; - assign tl_rv_timer_o = tl_s1n_20_ds_h2d[6]; - assign tl_s1n_20_ds_d2h[6] = tl_rv_timer_i; + assign tl_i2c2_o = tl_s1n_24_ds_h2d[6]; + assign tl_s1n_24_ds_d2h[6] = tl_i2c2_i; - assign tl_usbdev_o = tl_s1n_20_ds_h2d[7]; - assign tl_s1n_20_ds_d2h[7] = tl_usbdev_i; + assign tl_pattgen_o = tl_s1n_24_ds_h2d[7]; + assign tl_s1n_24_ds_d2h[7] = tl_pattgen_i; - assign tl_pwrmgr_o = tl_s1n_20_ds_h2d[8]; - assign tl_s1n_20_ds_d2h[8] = tl_pwrmgr_i; + assign tl_gpio_o = tl_s1n_24_ds_h2d[8]; + assign tl_s1n_24_ds_d2h[8] = tl_gpio_i; - assign tl_rstmgr_o = tl_s1n_20_ds_h2d[9]; - assign tl_s1n_20_ds_d2h[9] = tl_rstmgr_i; + assign tl_spi_device_o = tl_s1n_24_ds_h2d[9]; + assign tl_s1n_24_ds_d2h[9] = tl_spi_device_i; - assign tl_clkmgr_o = tl_s1n_20_ds_h2d[10]; - assign tl_s1n_20_ds_d2h[10] = tl_clkmgr_i; + assign tl_rv_timer_o = tl_s1n_24_ds_h2d[10]; + assign tl_s1n_24_ds_d2h[10] = tl_rv_timer_i; - assign tl_ram_ret_o = tl_s1n_20_ds_h2d[11]; - assign tl_s1n_20_ds_d2h[11] = tl_ram_ret_i; + assign tl_usbdev_o = tl_s1n_24_ds_h2d[11]; + assign tl_s1n_24_ds_d2h[11] = tl_usbdev_i; - assign tl_otp_ctrl_o = tl_s1n_20_ds_h2d[12]; - assign tl_s1n_20_ds_d2h[12] = tl_otp_ctrl_i; + assign tl_pwrmgr_o = tl_s1n_24_ds_h2d[12]; + assign tl_s1n_24_ds_d2h[12] = tl_pwrmgr_i; - assign tl_lc_ctrl_o = tl_s1n_20_ds_h2d[13]; - assign tl_s1n_20_ds_d2h[13] = tl_lc_ctrl_i; + assign tl_rstmgr_o = tl_s1n_24_ds_h2d[13]; + assign tl_s1n_24_ds_d2h[13] = tl_rstmgr_i; - assign tl_sensor_ctrl_o = tl_s1n_20_ds_h2d[14]; - assign tl_s1n_20_ds_d2h[14] = tl_sensor_ctrl_i; + assign tl_clkmgr_o = tl_s1n_24_ds_h2d[14]; + assign tl_s1n_24_ds_d2h[14] = tl_clkmgr_i; - assign tl_alert_handler_o = tl_s1n_20_ds_h2d[15]; - assign tl_s1n_20_ds_d2h[15] = tl_alert_handler_i; + assign tl_ram_ret_o = tl_s1n_24_ds_h2d[15]; + assign tl_s1n_24_ds_d2h[15] = tl_ram_ret_i; - assign tl_nmi_gen_o = tl_s1n_20_ds_h2d[16]; - assign tl_s1n_20_ds_d2h[16] = tl_nmi_gen_i; + assign tl_otp_ctrl_o = tl_s1n_24_ds_h2d[16]; + assign tl_s1n_24_ds_d2h[16] = tl_otp_ctrl_i; - assign tl_ast_wrapper_o = tl_s1n_20_ds_h2d[17]; - assign tl_s1n_20_ds_d2h[17] = tl_ast_wrapper_i; + assign tl_lc_ctrl_o = tl_s1n_24_ds_h2d[17]; + assign tl_s1n_24_ds_d2h[17] = tl_lc_ctrl_i; - assign tl_sram_ctrl_ret_o = tl_s1n_20_ds_h2d[18]; - assign tl_s1n_20_ds_d2h[18] = tl_sram_ctrl_ret_i; + assign tl_sensor_ctrl_o = tl_s1n_24_ds_h2d[18]; + assign tl_s1n_24_ds_d2h[18] = tl_sensor_ctrl_i; - assign tl_s1n_20_us_h2d = tl_main_i; - assign tl_main_o = tl_s1n_20_us_d2h; + assign tl_alert_handler_o = tl_s1n_24_ds_h2d[19]; + assign tl_s1n_24_ds_d2h[19] = tl_alert_handler_i; + + assign tl_nmi_gen_o = tl_s1n_24_ds_h2d[20]; + assign tl_s1n_24_ds_d2h[20] = tl_nmi_gen_i; + + assign tl_ast_wrapper_o = tl_s1n_24_ds_h2d[21]; + assign tl_s1n_24_ds_d2h[21] = tl_ast_wrapper_i; + + assign tl_sram_ctrl_ret_o = tl_s1n_24_ds_h2d[22]; + assign tl_s1n_24_ds_d2h[22] = tl_sram_ctrl_ret_i; + + assign tl_s1n_24_us_h2d = tl_main_i; + assign tl_main_o = tl_s1n_24_us_d2h; always_comb begin // default steering to generate error response if address is not within the range - dev_sel_s1n_20 = 5'd19; - if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin - dev_sel_s1n_20 = 5'd0; + dev_sel_s1n_24 = 5'd23; + if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin + dev_sel_s1n_24 = 5'd0; - end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_UART1)) == ADDR_SPACE_UART1) begin - dev_sel_s1n_20 = 5'd1; + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_UART1)) == ADDR_SPACE_UART1) begin + dev_sel_s1n_24 = 5'd1; - end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_UART2)) == ADDR_SPACE_UART2) begin - dev_sel_s1n_20 = 5'd2; + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_UART2)) == ADDR_SPACE_UART2) begin + dev_sel_s1n_24 = 5'd2; - end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_UART3)) == ADDR_SPACE_UART3) begin - dev_sel_s1n_20 = 5'd3; + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_UART3)) == ADDR_SPACE_UART3) begin + dev_sel_s1n_24 = 5'd3; - end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin - dev_sel_s1n_20 = 5'd4; + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_I2C0)) == ADDR_SPACE_I2C0) begin + dev_sel_s1n_24 = 5'd4; - end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin - dev_sel_s1n_20 = 5'd5; + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_I2C1)) == ADDR_SPACE_I2C1) begin + dev_sel_s1n_24 = 5'd5; - end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin - dev_sel_s1n_20 = 5'd6; + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_I2C2)) == ADDR_SPACE_I2C2) begin + dev_sel_s1n_24 = 5'd6; - end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin - dev_sel_s1n_20 = 5'd7; + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_PATTGEN)) == ADDR_SPACE_PATTGEN) begin + dev_sel_s1n_24 = 5'd7; - end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_PWRMGR)) == ADDR_SPACE_PWRMGR) begin - dev_sel_s1n_20 = 5'd8; + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin + dev_sel_s1n_24 = 5'd8; - end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_RSTMGR)) == ADDR_SPACE_RSTMGR) begin - dev_sel_s1n_20 = 5'd9; + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin + dev_sel_s1n_24 = 5'd9; - end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_CLKMGR)) == ADDR_SPACE_CLKMGR) begin - dev_sel_s1n_20 = 5'd10; + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin + dev_sel_s1n_24 = 5'd10; - end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_RAM_RET)) == ADDR_SPACE_RAM_RET) begin - dev_sel_s1n_20 = 5'd11; + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin + dev_sel_s1n_24 = 5'd11; - end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_OTP_CTRL)) == ADDR_SPACE_OTP_CTRL) begin - dev_sel_s1n_20 = 5'd12; + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_PWRMGR)) == ADDR_SPACE_PWRMGR) begin + dev_sel_s1n_24 = 5'd12; - end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_LC_CTRL)) == ADDR_SPACE_LC_CTRL) begin - dev_sel_s1n_20 = 5'd13; + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_RSTMGR)) == ADDR_SPACE_RSTMGR) begin + dev_sel_s1n_24 = 5'd13; - end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_SENSOR_CTRL)) == ADDR_SPACE_SENSOR_CTRL) begin - dev_sel_s1n_20 = 5'd14; + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_CLKMGR)) == ADDR_SPACE_CLKMGR) begin + dev_sel_s1n_24 = 5'd14; - end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin - dev_sel_s1n_20 = 5'd15; + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_RAM_RET)) == ADDR_SPACE_RAM_RET) begin + dev_sel_s1n_24 = 5'd15; - end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin - dev_sel_s1n_20 = 5'd16; + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_OTP_CTRL)) == ADDR_SPACE_OTP_CTRL) begin + dev_sel_s1n_24 = 5'd16; - end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_AST_WRAPPER)) == ADDR_SPACE_AST_WRAPPER) begin - dev_sel_s1n_20 = 5'd17; + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_LC_CTRL)) == ADDR_SPACE_LC_CTRL) begin + dev_sel_s1n_24 = 5'd17; - end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_RET)) == ADDR_SPACE_SRAM_CTRL_RET) begin - dev_sel_s1n_20 = 5'd18; + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_SENSOR_CTRL)) == ADDR_SPACE_SENSOR_CTRL) begin + dev_sel_s1n_24 = 5'd18; + + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin + dev_sel_s1n_24 = 5'd19; + + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin + dev_sel_s1n_24 = 5'd20; + + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_AST_WRAPPER)) == ADDR_SPACE_AST_WRAPPER) begin + dev_sel_s1n_24 = 5'd21; + + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_RET)) == ADDR_SPACE_SRAM_CTRL_RET) begin + dev_sel_s1n_24 = 5'd22; end end @@ -226,17 +262,17 @@ tlul_socket_1n #( .HReqDepth (4'h0), .HRspDepth (4'h0), - .DReqDepth (76'h0), - .DRspDepth (76'h0), - .N (19) - ) u_s1n_20 ( + .DReqDepth (92'h0), + .DRspDepth (92'h0), + .N (23) + ) u_s1n_24 ( .clk_i (clk_peri_i), .rst_ni (rst_peri_ni), - .tl_h_i (tl_s1n_20_us_h2d), - .tl_h_o (tl_s1n_20_us_d2h), - .tl_d_o (tl_s1n_20_ds_h2d), - .tl_d_i (tl_s1n_20_ds_d2h), - .dev_select_i (dev_sel_s1n_20) + .tl_h_i (tl_s1n_24_us_h2d), + .tl_h_o (tl_s1n_24_us_d2h), + .tl_d_o (tl_s1n_24_ds_h2d), + .tl_d_i (tl_s1n_24_ds_d2h), + .dev_select_i (dev_sel_s1n_24) ); endmodule
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index c15fb62..953c7a1 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -100,9 +100,9 @@ import top_earlgrey_rnd_cnst_pkg::*; // Signals - logic [34:0] mio_p2d; - logic [34:0] mio_d2p; - logic [34:0] mio_d2p_en; + logic [40:0] mio_p2d; + logic [44:0] mio_d2p; + logic [44:0] mio_d2p_en; logic [14:0] dio_p2d; logic [14:0] dio_d2p; logic [14:0] dio_d2p_en; @@ -132,6 +132,36 @@ logic cio_spi_device_sdi_p2d; logic cio_spi_device_sdo_d2p; logic cio_spi_device_sdo_en_d2p; + // i2c0 + logic cio_i2c0_sda_p2d; + logic cio_i2c0_scl_p2d; + logic cio_i2c0_sda_d2p; + logic cio_i2c0_sda_en_d2p; + logic cio_i2c0_scl_d2p; + logic cio_i2c0_scl_en_d2p; + // i2c1 + logic cio_i2c1_sda_p2d; + logic cio_i2c1_scl_p2d; + logic cio_i2c1_sda_d2p; + logic cio_i2c1_sda_en_d2p; + logic cio_i2c1_scl_d2p; + logic cio_i2c1_scl_en_d2p; + // i2c2 + logic cio_i2c2_sda_p2d; + logic cio_i2c2_scl_p2d; + logic cio_i2c2_sda_d2p; + logic cio_i2c2_sda_en_d2p; + logic cio_i2c2_scl_d2p; + logic cio_i2c2_scl_en_d2p; + // pattgen + logic cio_pattgen_pda0_tx_d2p; + logic cio_pattgen_pda0_tx_en_d2p; + logic cio_pattgen_pcl0_tx_d2p; + logic cio_pattgen_pcl0_tx_en_d2p; + logic cio_pattgen_pda1_tx_d2p; + logic cio_pattgen_pda1_tx_en_d2p; + logic cio_pattgen_pcl1_tx_d2p; + logic cio_pattgen_pcl1_tx_en_d2p; // rv_timer // sensor_ctrl // otp_ctrl @@ -179,7 +209,7 @@ // otbn - logic [121:0] intr_vector; + logic [171:0] intr_vector; // Interrupt source list logic intr_uart0_tx_watermark; logic intr_uart0_rx_watermark; @@ -220,6 +250,56 @@ logic intr_spi_device_rxerr; logic intr_spi_device_rxoverflow; logic intr_spi_device_txunderflow; + logic intr_i2c0_fmt_watermark; + logic intr_i2c0_rx_watermark; + logic intr_i2c0_fmt_overflow; + logic intr_i2c0_rx_overflow; + logic intr_i2c0_nak; + logic intr_i2c0_scl_interference; + logic intr_i2c0_sda_interference; + logic intr_i2c0_stretch_timeout; + logic intr_i2c0_sda_unstable; + logic intr_i2c0_trans_complete; + logic intr_i2c0_tx_empty; + logic intr_i2c0_tx_nonempty; + logic intr_i2c0_tx_overflow; + logic intr_i2c0_acq_overflow; + logic intr_i2c0_ack_stop; + logic intr_i2c0_host_timeout; + logic intr_i2c1_fmt_watermark; + logic intr_i2c1_rx_watermark; + logic intr_i2c1_fmt_overflow; + logic intr_i2c1_rx_overflow; + logic intr_i2c1_nak; + logic intr_i2c1_scl_interference; + logic intr_i2c1_sda_interference; + logic intr_i2c1_stretch_timeout; + logic intr_i2c1_sda_unstable; + logic intr_i2c1_trans_complete; + logic intr_i2c1_tx_empty; + logic intr_i2c1_tx_nonempty; + logic intr_i2c1_tx_overflow; + logic intr_i2c1_acq_overflow; + logic intr_i2c1_ack_stop; + logic intr_i2c1_host_timeout; + logic intr_i2c2_fmt_watermark; + logic intr_i2c2_rx_watermark; + logic intr_i2c2_fmt_overflow; + logic intr_i2c2_rx_overflow; + logic intr_i2c2_nak; + logic intr_i2c2_scl_interference; + logic intr_i2c2_sda_interference; + logic intr_i2c2_stretch_timeout; + logic intr_i2c2_sda_unstable; + logic intr_i2c2_trans_complete; + logic intr_i2c2_tx_empty; + logic intr_i2c2_tx_nonempty; + logic intr_i2c2_tx_overflow; + logic intr_i2c2_acq_overflow; + logic intr_i2c2_ack_stop; + logic intr_i2c2_host_timeout; + logic intr_pattgen_done_ch0; + logic intr_pattgen_done_ch1; logic intr_rv_timer_timer_expired_0_0; logic intr_otp_ctrl_otp_operation_done; logic intr_otp_ctrl_otp_error; @@ -277,8 +357,8 @@ logic [0:0] irq_plic; logic [0:0] msip; - logic [6:0] irq_id[1]; - logic [6:0] unused_irq_id[1]; + logic [7:0] irq_id[1]; + logic [7:0] unused_irq_id[1]; // this avoids lint errors assign unused_irq_id = irq_id; @@ -397,6 +477,14 @@ tlul_pkg::tl_d2h_t uart2_tl_rsp; tlul_pkg::tl_h2d_t uart3_tl_req; tlul_pkg::tl_d2h_t uart3_tl_rsp; + tlul_pkg::tl_h2d_t i2c0_tl_req; + tlul_pkg::tl_d2h_t i2c0_tl_rsp; + tlul_pkg::tl_h2d_t i2c1_tl_req; + tlul_pkg::tl_d2h_t i2c1_tl_rsp; + tlul_pkg::tl_h2d_t i2c2_tl_req; + tlul_pkg::tl_d2h_t i2c2_tl_rsp; + tlul_pkg::tl_h2d_t pattgen_tl_req; + tlul_pkg::tl_d2h_t pattgen_tl_rsp; tlul_pkg::tl_h2d_t gpio_tl_req; tlul_pkg::tl_d2h_t gpio_tl_rsp; tlul_pkg::tl_h2d_t spi_device_tl_req; @@ -450,6 +538,9 @@ logic unused_daon_rst_lc_io_div4; logic unused_daon_rst_spi_device; logic unused_daon_rst_usb; + logic unused_daon_rst_i2c0; + logic unused_daon_rst_i2c1; + logic unused_daon_rst_i2c2; assign unused_d0_rst_por_aon = rstmgr_resets.rst_por_aon_n[rstmgr_pkg::Domain0Sel]; assign unused_d0_rst_por = rstmgr_resets.rst_por_n[rstmgr_pkg::Domain0Sel]; assign unused_d0_rst_por_io = rstmgr_resets.rst_por_io_n[rstmgr_pkg::Domain0Sel]; @@ -460,6 +551,9 @@ assign unused_daon_rst_lc_io_div4 = rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]; assign unused_daon_rst_spi_device = rstmgr_resets.rst_spi_device_n[rstmgr_pkg::DomainAonSel]; assign unused_daon_rst_usb = rstmgr_resets.rst_usb_n[rstmgr_pkg::DomainAonSel]; + assign unused_daon_rst_i2c0 = rstmgr_resets.rst_i2c0_n[rstmgr_pkg::DomainAonSel]; + assign unused_daon_rst_i2c1 = rstmgr_resets.rst_i2c1_n[rstmgr_pkg::DomainAonSel]; + assign unused_daon_rst_i2c2 = rstmgr_resets.rst_i2c2_n[rstmgr_pkg::DomainAonSel]; // Non-debug module reset == reset for everything except for the debug module logic ndmreset_req; @@ -804,6 +898,8 @@ // Inter-module signals .tl_i(uart0_tl_req), .tl_o(uart0_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_io_div4_secure), .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]) ); @@ -830,6 +926,8 @@ // Inter-module signals .tl_i(uart1_tl_req), .tl_o(uart1_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_io_div4_secure), .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]) ); @@ -856,6 +954,8 @@ // Inter-module signals .tl_i(uart2_tl_req), .tl_o(uart2_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_io_div4_secure), .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]) ); @@ -882,6 +982,8 @@ // Inter-module signals .tl_i(uart3_tl_req), .tl_o(uart3_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_io_div4_secure), .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]) ); @@ -901,6 +1003,8 @@ // Inter-module signals .tl_i(gpio_tl_req), .tl_o(gpio_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_io_div4_peri), .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]) ); @@ -928,10 +1032,154 @@ .tl_i(spi_device_tl_req), .tl_o(spi_device_tl_rsp), .scanmode_i (scanmode_i), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_io_div4_peri), .rst_ni (rstmgr_resets.rst_spi_device_n[rstmgr_pkg::Domain0Sel]) ); + i2c u_i2c0 ( + + // Input + .cio_sda_i (cio_i2c0_sda_p2d), + .cio_scl_i (cio_i2c0_scl_p2d), + + // Output + .cio_sda_o (cio_i2c0_sda_d2p), + .cio_sda_en_o (cio_i2c0_sda_en_d2p), + .cio_scl_o (cio_i2c0_scl_d2p), + .cio_scl_en_o (cio_i2c0_scl_en_d2p), + + // Interrupt + .intr_fmt_watermark_o (intr_i2c0_fmt_watermark), + .intr_rx_watermark_o (intr_i2c0_rx_watermark), + .intr_fmt_overflow_o (intr_i2c0_fmt_overflow), + .intr_rx_overflow_o (intr_i2c0_rx_overflow), + .intr_nak_o (intr_i2c0_nak), + .intr_scl_interference_o (intr_i2c0_scl_interference), + .intr_sda_interference_o (intr_i2c0_sda_interference), + .intr_stretch_timeout_o (intr_i2c0_stretch_timeout), + .intr_sda_unstable_o (intr_i2c0_sda_unstable), + .intr_trans_complete_o (intr_i2c0_trans_complete), + .intr_tx_empty_o (intr_i2c0_tx_empty), + .intr_tx_nonempty_o (intr_i2c0_tx_nonempty), + .intr_tx_overflow_o (intr_i2c0_tx_overflow), + .intr_acq_overflow_o (intr_i2c0_acq_overflow), + .intr_ack_stop_o (intr_i2c0_ack_stop), + .intr_host_timeout_o (intr_i2c0_host_timeout), + + // Inter-module signals + .tl_i(i2c0_tl_req), + .tl_o(i2c0_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_clocks.clk_io_div4_peri), + .rst_ni (rstmgr_resets.rst_i2c0_n[rstmgr_pkg::Domain0Sel]) + ); + + i2c u_i2c1 ( + + // Input + .cio_sda_i (cio_i2c1_sda_p2d), + .cio_scl_i (cio_i2c1_scl_p2d), + + // Output + .cio_sda_o (cio_i2c1_sda_d2p), + .cio_sda_en_o (cio_i2c1_sda_en_d2p), + .cio_scl_o (cio_i2c1_scl_d2p), + .cio_scl_en_o (cio_i2c1_scl_en_d2p), + + // Interrupt + .intr_fmt_watermark_o (intr_i2c1_fmt_watermark), + .intr_rx_watermark_o (intr_i2c1_rx_watermark), + .intr_fmt_overflow_o (intr_i2c1_fmt_overflow), + .intr_rx_overflow_o (intr_i2c1_rx_overflow), + .intr_nak_o (intr_i2c1_nak), + .intr_scl_interference_o (intr_i2c1_scl_interference), + .intr_sda_interference_o (intr_i2c1_sda_interference), + .intr_stretch_timeout_o (intr_i2c1_stretch_timeout), + .intr_sda_unstable_o (intr_i2c1_sda_unstable), + .intr_trans_complete_o (intr_i2c1_trans_complete), + .intr_tx_empty_o (intr_i2c1_tx_empty), + .intr_tx_nonempty_o (intr_i2c1_tx_nonempty), + .intr_tx_overflow_o (intr_i2c1_tx_overflow), + .intr_acq_overflow_o (intr_i2c1_acq_overflow), + .intr_ack_stop_o (intr_i2c1_ack_stop), + .intr_host_timeout_o (intr_i2c1_host_timeout), + + // Inter-module signals + .tl_i(i2c1_tl_req), + .tl_o(i2c1_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_clocks.clk_io_div4_peri), + .rst_ni (rstmgr_resets.rst_i2c1_n[rstmgr_pkg::Domain0Sel]) + ); + + i2c u_i2c2 ( + + // Input + .cio_sda_i (cio_i2c2_sda_p2d), + .cio_scl_i (cio_i2c2_scl_p2d), + + // Output + .cio_sda_o (cio_i2c2_sda_d2p), + .cio_sda_en_o (cio_i2c2_sda_en_d2p), + .cio_scl_o (cio_i2c2_scl_d2p), + .cio_scl_en_o (cio_i2c2_scl_en_d2p), + + // Interrupt + .intr_fmt_watermark_o (intr_i2c2_fmt_watermark), + .intr_rx_watermark_o (intr_i2c2_rx_watermark), + .intr_fmt_overflow_o (intr_i2c2_fmt_overflow), + .intr_rx_overflow_o (intr_i2c2_rx_overflow), + .intr_nak_o (intr_i2c2_nak), + .intr_scl_interference_o (intr_i2c2_scl_interference), + .intr_sda_interference_o (intr_i2c2_sda_interference), + .intr_stretch_timeout_o (intr_i2c2_stretch_timeout), + .intr_sda_unstable_o (intr_i2c2_sda_unstable), + .intr_trans_complete_o (intr_i2c2_trans_complete), + .intr_tx_empty_o (intr_i2c2_tx_empty), + .intr_tx_nonempty_o (intr_i2c2_tx_nonempty), + .intr_tx_overflow_o (intr_i2c2_tx_overflow), + .intr_acq_overflow_o (intr_i2c2_acq_overflow), + .intr_ack_stop_o (intr_i2c2_ack_stop), + .intr_host_timeout_o (intr_i2c2_host_timeout), + + // Inter-module signals + .tl_i(i2c2_tl_req), + .tl_o(i2c2_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_clocks.clk_io_div4_peri), + .rst_ni (rstmgr_resets.rst_i2c2_n[rstmgr_pkg::Domain0Sel]) + ); + + pattgen u_pattgen ( + + // Output + .cio_pda0_tx_o (cio_pattgen_pda0_tx_d2p), + .cio_pda0_tx_en_o (cio_pattgen_pda0_tx_en_d2p), + .cio_pcl0_tx_o (cio_pattgen_pcl0_tx_d2p), + .cio_pcl0_tx_en_o (cio_pattgen_pcl0_tx_en_d2p), + .cio_pda1_tx_o (cio_pattgen_pda1_tx_d2p), + .cio_pda1_tx_en_o (cio_pattgen_pda1_tx_en_d2p), + .cio_pcl1_tx_o (cio_pattgen_pcl1_tx_d2p), + .cio_pcl1_tx_en_o (cio_pattgen_pcl1_tx_en_d2p), + + // Interrupt + .intr_done_ch0_o (intr_pattgen_done_ch0), + .intr_done_ch1_o (intr_pattgen_done_ch1), + + // Inter-module signals + .tl_i(pattgen_tl_req), + .tl_o(pattgen_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_clocks.clk_io_div4_peri), + .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]) + ); + rv_timer u_rv_timer ( // Interrupt @@ -940,6 +1188,8 @@ // Inter-module signals .tl_i(rv_timer_tl_req), .tl_o(rv_timer_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_io_div4_timers), .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]) ); @@ -962,6 +1212,8 @@ .ast_status_i(sensor_ctrl_ast_status_i), .tl_i(sensor_ctrl_tl_req), .tl_o(sensor_ctrl_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_io_div4_secure), .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]) ); @@ -1007,6 +1259,8 @@ .otp_hw_cfg_o(otp_ctrl_otp_hw_cfg), .tl_i(otp_ctrl_tl_req), .tl_o(otp_ctrl_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_io_div4_timers), .clk_edn_i (clkmgr_clocks.clk_main_timers), .rst_ni (rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), @@ -1060,6 +1314,8 @@ .tl_i(lc_ctrl_tl_req), .tl_o(lc_ctrl_tl_rsp), .scanmode_i (scanmode_i), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_io_div4_timers), .rst_ni (rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) ); @@ -1085,6 +1341,8 @@ // alert signals .alert_rx_o ( alert_rx ), .alert_tx_i ( alert_tx ), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_io_div4_timers), .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]) ); @@ -1102,6 +1360,8 @@ .esc_rx_o(), .tl_i(nmi_gen_tl_req), .tl_o(nmi_gen_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_io_div4_timers), .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]) ); @@ -1131,6 +1391,8 @@ .rstreqs_i(pwrmgr_rstreqs), .tl_i(pwrmgr_tl_req), .tl_o(pwrmgr_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_io_div4_powerup), .clk_slow_i (clkmgr_clocks.clk_aon_powerup), .rst_ni (rstmgr_resets.rst_por_n[rstmgr_pkg::DomainAonSel]), @@ -1152,6 +1414,8 @@ .tl_o(rstmgr_tl_rsp), .scanmode_i (scanmode_i), .scan_rst_ni (scan_rst_ni), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_io_div4_powerup), .clk_aon_i (clkmgr_clocks.clk_aon_powerup), .clk_main_i (clkmgr_clocks.clk_main_powerup), @@ -1179,6 +1443,8 @@ .tl_i(clkmgr_tl_req), .tl_o(clkmgr_tl_rsp), .scanmode_i (scanmode_i), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_io_div4_powerup), .rst_ni (rstmgr_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]), .rst_main_ni (rstmgr_resets.rst_por_n[rstmgr_pkg::DomainAonSel]), @@ -1221,6 +1487,8 @@ .dio_out_o, .dio_oe_o, .dio_in_i, + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_main_secure), .clk_aon_i (clkmgr_clocks.clk_aon_secure), .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::DomainAonSel]), @@ -1235,6 +1503,8 @@ .mio_attr_o, .dio_attr_o, + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_main_secure), .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::DomainAonSel]) ); @@ -1294,6 +1564,8 @@ .usb_state_debug_i(pinmux_usb_state_debug), .tl_i(usbdev_tl_req), .tl_o(usbdev_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_io_div4_peri), .clk_aon_i (clkmgr_clocks.clk_aon_peri), .clk_usb_48mhz_i (clkmgr_clocks.clk_usb_peri), @@ -1319,6 +1591,8 @@ .lc_escalate_en_i(lc_ctrl_lc_escalate_en), .tl_i(sram_ctrl_ret_tl_req), .tl_o(sram_ctrl_ret_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_io_div4_peri), .clk_otp_i (clkmgr_clocks.clk_io_div4_peri), .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]), @@ -1363,6 +1637,8 @@ .keymgr_o(flash_ctrl_keymgr), .tl_i(flash_ctrl_tl_req), .tl_o(flash_ctrl_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_main_infra), .clk_otp_i (clkmgr_clocks.clk_io_div4_infra), .rst_ni (rstmgr_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), @@ -1379,6 +1655,8 @@ .irq_o (irq_plic), .irq_id_o (irq_id), .msip_o (msip), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_main_secure), .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]) ); @@ -1405,6 +1683,8 @@ .idle_o(clkmgr_idle[0]), .tl_i(aes_tl_req), .tl_o(aes_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_main_aes), .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]) ); @@ -1420,6 +1700,8 @@ .idle_o(clkmgr_idle[1]), .tl_i(hmac_tl_req), .tl_o(hmac_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_main_hmac), .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]) ); @@ -1443,6 +1725,8 @@ .idle_o(clkmgr_idle[2]), .tl_i(kmac_tl_req), .tl_o(kmac_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_main_kmac), .clk_edn_i (clkmgr_clocks.clk_main_kmac), .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]), @@ -1488,6 +1772,8 @@ .lc_keymgr_div_i(lc_ctrl_lc_keymgr_div), .tl_i(keymgr_tl_req), .tl_o(keymgr_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_main_secure), .clk_edn_i (clkmgr_clocks.clk_main_secure), .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]), @@ -1513,6 +1799,8 @@ .lc_hw_debug_en_i(lc_ctrl_pkg::Off), .tl_i(csrng_tl_req), .tl_o(csrng_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_main_secure), .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]) ); @@ -1538,6 +1826,8 @@ .efuse_es_sw_reg_en_i('0), .tl_i(entropy_src_tl_req), .tl_o(entropy_src_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_main_secure), .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]) ); @@ -1555,6 +1845,8 @@ .edn_o(), .tl_i(edn0_tl_req), .tl_o(edn0_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_main_secure), .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]) ); @@ -1572,6 +1864,8 @@ .edn_o(), .tl_i(edn1_tl_req), .tl_o(edn1_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_main_secure), .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]) ); @@ -1593,6 +1887,8 @@ .lc_escalate_en_i(lc_ctrl_lc_escalate_en), .tl_i(sram_ctrl_main_tl_req), .tl_o(sram_ctrl_main_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_main_secure), .clk_otp_i (clkmgr_clocks.clk_io_div4_secure), .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]), @@ -1615,6 +1911,8 @@ .idle_o(clkmgr_idle[3]), .tl_i(otbn_tl_req), .tl_o(otbn_tl_rsp), + + // Clock and reset connections .clk_i (clkmgr_clocks.clk_main_otbn), .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]) ); @@ -1672,6 +1970,56 @@ intr_flash_ctrl_rd_full, intr_flash_ctrl_prog_lvl, intr_flash_ctrl_prog_empty, + intr_pattgen_done_ch1, + intr_pattgen_done_ch0, + intr_i2c2_host_timeout, + intr_i2c2_ack_stop, + intr_i2c2_acq_overflow, + intr_i2c2_tx_overflow, + intr_i2c2_tx_nonempty, + intr_i2c2_tx_empty, + intr_i2c2_trans_complete, + intr_i2c2_sda_unstable, + intr_i2c2_stretch_timeout, + intr_i2c2_sda_interference, + intr_i2c2_scl_interference, + intr_i2c2_nak, + intr_i2c2_rx_overflow, + intr_i2c2_fmt_overflow, + intr_i2c2_rx_watermark, + intr_i2c2_fmt_watermark, + intr_i2c1_host_timeout, + intr_i2c1_ack_stop, + intr_i2c1_acq_overflow, + intr_i2c1_tx_overflow, + intr_i2c1_tx_nonempty, + intr_i2c1_tx_empty, + intr_i2c1_trans_complete, + intr_i2c1_sda_unstable, + intr_i2c1_stretch_timeout, + intr_i2c1_sda_interference, + intr_i2c1_scl_interference, + intr_i2c1_nak, + intr_i2c1_rx_overflow, + intr_i2c1_fmt_overflow, + intr_i2c1_rx_watermark, + intr_i2c1_fmt_watermark, + intr_i2c0_host_timeout, + intr_i2c0_ack_stop, + intr_i2c0_acq_overflow, + intr_i2c0_tx_overflow, + intr_i2c0_tx_nonempty, + intr_i2c0_tx_empty, + intr_i2c0_trans_complete, + intr_i2c0_sda_unstable, + intr_i2c0_stretch_timeout, + intr_i2c0_sda_interference, + intr_i2c0_scl_interference, + intr_i2c0_nak, + intr_i2c0_rx_overflow, + intr_i2c0_fmt_overflow, + intr_i2c0_rx_watermark, + intr_i2c0_fmt_watermark, intr_spi_device_txunderflow, intr_spi_device_rxoverflow, intr_spi_device_rxerr, @@ -1836,6 +2184,22 @@ .tl_uart3_o(uart3_tl_req), .tl_uart3_i(uart3_tl_rsp), + // port: tl_i2c0 + .tl_i2c0_o(i2c0_tl_req), + .tl_i2c0_i(i2c0_tl_rsp), + + // port: tl_i2c1 + .tl_i2c1_o(i2c1_tl_req), + .tl_i2c1_i(i2c1_tl_rsp), + + // port: tl_i2c2 + .tl_i2c2_o(i2c2_tl_req), + .tl_i2c2_i(i2c2_tl_rsp), + + // port: tl_pattgen + .tl_pattgen_o(pattgen_tl_req), + .tl_pattgen_i(pattgen_tl_rsp), + // port: tl_gpio .tl_gpio_o(gpio_tl_req), .tl_gpio_i(gpio_tl_rsp), @@ -1902,21 +2266,47 @@ // Pinmux connections assign mio_d2p = { + cio_pattgen_pcl1_tx_d2p, + cio_pattgen_pda1_tx_d2p, + cio_pattgen_pcl0_tx_d2p, + cio_pattgen_pda0_tx_d2p, cio_uart3_tx_d2p, cio_uart2_tx_d2p, cio_uart1_tx_d2p, + cio_i2c2_scl_d2p, + cio_i2c2_sda_d2p, + cio_i2c1_scl_d2p, + cio_i2c1_sda_d2p, + cio_i2c0_scl_d2p, + cio_i2c0_sda_d2p, cio_gpio_gpio_d2p }; assign mio_d2p_en = { + cio_pattgen_pcl1_tx_en_d2p, + cio_pattgen_pda1_tx_en_d2p, + cio_pattgen_pcl0_tx_en_d2p, + cio_pattgen_pda0_tx_en_d2p, cio_uart3_tx_en_d2p, cio_uart2_tx_en_d2p, cio_uart1_tx_en_d2p, + cio_i2c2_scl_en_d2p, + cio_i2c2_sda_en_d2p, + cio_i2c1_scl_en_d2p, + cio_i2c1_sda_en_d2p, + cio_i2c0_scl_en_d2p, + cio_i2c0_sda_en_d2p, cio_gpio_gpio_en_d2p }; assign { cio_uart3_rx_p2d, cio_uart2_rx_p2d, cio_uart1_rx_p2d, + cio_i2c2_scl_p2d, + cio_i2c2_sda_p2d, + cio_i2c1_scl_p2d, + cio_i2c1_sda_p2d, + cio_i2c0_scl_p2d, + cio_i2c0_sda_p2d, cio_gpio_gpio_p2d } = mio_p2d;
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv index b7e8956..8d872c3 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
@@ -72,6 +72,46 @@ parameter int unsigned TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES = 32'h1000; /** + * Peripheral base address for i2c0 in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_I2C0_BASE_ADDR = 32'h40080000; + + /** + * Peripheral size in bytes for i2c0 in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_I2C0_SIZE_BYTES = 32'h1000; + + /** + * Peripheral base address for i2c1 in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_I2C1_BASE_ADDR = 32'h40090000; + + /** + * Peripheral size in bytes for i2c1 in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_I2C1_SIZE_BYTES = 32'h1000; + + /** + * Peripheral base address for i2c2 in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_I2C2_BASE_ADDR = 32'h400A0000; + + /** + * Peripheral size in bytes for i2c2 in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_I2C2_SIZE_BYTES = 32'h1000; + + /** + * Peripheral base address for pattgen in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_PATTGEN_BASE_ADDR = 32'h400E0000; + + /** + * Peripheral size in bytes for pattgen in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_PATTGEN_SIZE_BYTES = 32'h1000; + + /** * Peripheral base address for rv_timer in top earlgrey. */ parameter int unsigned TOP_EARLGREY_RV_TIMER_BASE_ADDR = 32'h40100000;
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c index 5b3957c..bb96cdf 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -11,7 +11,7 @@ * `top_earlgrey_plic_peripheral_t`. */ const top_earlgrey_plic_peripheral_t - top_earlgrey_plic_interrupt_for_peripheral[122] = { + top_earlgrey_plic_interrupt_for_peripheral[172] = { [kTopEarlgreyPlicIrqIdNone] = kTopEarlgreyPlicPeripheralUnknown, [kTopEarlgreyPlicIrqIdUart0TxWatermark] = kTopEarlgreyPlicPeripheralUart0, [kTopEarlgreyPlicIrqIdUart0RxWatermark] = kTopEarlgreyPlicPeripheralUart0, @@ -83,6 +83,56 @@ [kTopEarlgreyPlicIrqIdSpiDeviceRxerr] = kTopEarlgreyPlicPeripheralSpiDevice, [kTopEarlgreyPlicIrqIdSpiDeviceRxoverflow] = kTopEarlgreyPlicPeripheralSpiDevice, [kTopEarlgreyPlicIrqIdSpiDeviceTxunderflow] = kTopEarlgreyPlicPeripheralSpiDevice, + [kTopEarlgreyPlicIrqIdI2c0FmtWatermark] = kTopEarlgreyPlicPeripheralI2c0, + [kTopEarlgreyPlicIrqIdI2c0RxWatermark] = kTopEarlgreyPlicPeripheralI2c0, + [kTopEarlgreyPlicIrqIdI2c0FmtOverflow] = kTopEarlgreyPlicPeripheralI2c0, + [kTopEarlgreyPlicIrqIdI2c0RxOverflow] = kTopEarlgreyPlicPeripheralI2c0, + [kTopEarlgreyPlicIrqIdI2c0Nak] = kTopEarlgreyPlicPeripheralI2c0, + [kTopEarlgreyPlicIrqIdI2c0SclInterference] = kTopEarlgreyPlicPeripheralI2c0, + [kTopEarlgreyPlicIrqIdI2c0SdaInterference] = kTopEarlgreyPlicPeripheralI2c0, + [kTopEarlgreyPlicIrqIdI2c0StretchTimeout] = kTopEarlgreyPlicPeripheralI2c0, + [kTopEarlgreyPlicIrqIdI2c0SdaUnstable] = kTopEarlgreyPlicPeripheralI2c0, + [kTopEarlgreyPlicIrqIdI2c0TransComplete] = kTopEarlgreyPlicPeripheralI2c0, + [kTopEarlgreyPlicIrqIdI2c0TxEmpty] = kTopEarlgreyPlicPeripheralI2c0, + [kTopEarlgreyPlicIrqIdI2c0TxNonempty] = kTopEarlgreyPlicPeripheralI2c0, + [kTopEarlgreyPlicIrqIdI2c0TxOverflow] = kTopEarlgreyPlicPeripheralI2c0, + [kTopEarlgreyPlicIrqIdI2c0AcqOverflow] = kTopEarlgreyPlicPeripheralI2c0, + [kTopEarlgreyPlicIrqIdI2c0AckStop] = kTopEarlgreyPlicPeripheralI2c0, + [kTopEarlgreyPlicIrqIdI2c0HostTimeout] = kTopEarlgreyPlicPeripheralI2c0, + [kTopEarlgreyPlicIrqIdI2c1FmtWatermark] = kTopEarlgreyPlicPeripheralI2c1, + [kTopEarlgreyPlicIrqIdI2c1RxWatermark] = kTopEarlgreyPlicPeripheralI2c1, + [kTopEarlgreyPlicIrqIdI2c1FmtOverflow] = kTopEarlgreyPlicPeripheralI2c1, + [kTopEarlgreyPlicIrqIdI2c1RxOverflow] = kTopEarlgreyPlicPeripheralI2c1, + [kTopEarlgreyPlicIrqIdI2c1Nak] = kTopEarlgreyPlicPeripheralI2c1, + [kTopEarlgreyPlicIrqIdI2c1SclInterference] = kTopEarlgreyPlicPeripheralI2c1, + [kTopEarlgreyPlicIrqIdI2c1SdaInterference] = kTopEarlgreyPlicPeripheralI2c1, + [kTopEarlgreyPlicIrqIdI2c1StretchTimeout] = kTopEarlgreyPlicPeripheralI2c1, + [kTopEarlgreyPlicIrqIdI2c1SdaUnstable] = kTopEarlgreyPlicPeripheralI2c1, + [kTopEarlgreyPlicIrqIdI2c1TransComplete] = kTopEarlgreyPlicPeripheralI2c1, + [kTopEarlgreyPlicIrqIdI2c1TxEmpty] = kTopEarlgreyPlicPeripheralI2c1, + [kTopEarlgreyPlicIrqIdI2c1TxNonempty] = kTopEarlgreyPlicPeripheralI2c1, + [kTopEarlgreyPlicIrqIdI2c1TxOverflow] = kTopEarlgreyPlicPeripheralI2c1, + [kTopEarlgreyPlicIrqIdI2c1AcqOverflow] = kTopEarlgreyPlicPeripheralI2c1, + [kTopEarlgreyPlicIrqIdI2c1AckStop] = kTopEarlgreyPlicPeripheralI2c1, + [kTopEarlgreyPlicIrqIdI2c1HostTimeout] = kTopEarlgreyPlicPeripheralI2c1, + [kTopEarlgreyPlicIrqIdI2c2FmtWatermark] = kTopEarlgreyPlicPeripheralI2c2, + [kTopEarlgreyPlicIrqIdI2c2RxWatermark] = kTopEarlgreyPlicPeripheralI2c2, + [kTopEarlgreyPlicIrqIdI2c2FmtOverflow] = kTopEarlgreyPlicPeripheralI2c2, + [kTopEarlgreyPlicIrqIdI2c2RxOverflow] = kTopEarlgreyPlicPeripheralI2c2, + [kTopEarlgreyPlicIrqIdI2c2Nak] = kTopEarlgreyPlicPeripheralI2c2, + [kTopEarlgreyPlicIrqIdI2c2SclInterference] = kTopEarlgreyPlicPeripheralI2c2, + [kTopEarlgreyPlicIrqIdI2c2SdaInterference] = kTopEarlgreyPlicPeripheralI2c2, + [kTopEarlgreyPlicIrqIdI2c2StretchTimeout] = kTopEarlgreyPlicPeripheralI2c2, + [kTopEarlgreyPlicIrqIdI2c2SdaUnstable] = kTopEarlgreyPlicPeripheralI2c2, + [kTopEarlgreyPlicIrqIdI2c2TransComplete] = kTopEarlgreyPlicPeripheralI2c2, + [kTopEarlgreyPlicIrqIdI2c2TxEmpty] = kTopEarlgreyPlicPeripheralI2c2, + [kTopEarlgreyPlicIrqIdI2c2TxNonempty] = kTopEarlgreyPlicPeripheralI2c2, + [kTopEarlgreyPlicIrqIdI2c2TxOverflow] = kTopEarlgreyPlicPeripheralI2c2, + [kTopEarlgreyPlicIrqIdI2c2AcqOverflow] = kTopEarlgreyPlicPeripheralI2c2, + [kTopEarlgreyPlicIrqIdI2c2AckStop] = kTopEarlgreyPlicPeripheralI2c2, + [kTopEarlgreyPlicIrqIdI2c2HostTimeout] = kTopEarlgreyPlicPeripheralI2c2, + [kTopEarlgreyPlicIrqIdPattgenDoneCh0] = kTopEarlgreyPlicPeripheralPattgen, + [kTopEarlgreyPlicIrqIdPattgenDoneCh1] = kTopEarlgreyPlicPeripheralPattgen, [kTopEarlgreyPlicIrqIdFlashCtrlProgEmpty] = kTopEarlgreyPlicPeripheralFlashCtrl, [kTopEarlgreyPlicIrqIdFlashCtrlProgLvl] = kTopEarlgreyPlicPeripheralFlashCtrl, [kTopEarlgreyPlicIrqIdFlashCtrlRdFull] = kTopEarlgreyPlicPeripheralFlashCtrl,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h index b307013..9bd5250 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -134,6 +134,78 @@ #define TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES 0x1000u /** + * Peripheral base address for i2c0 in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_I2C0_BASE_ADDR 0x40080000u + +/** + * Peripheral size for i2c0 in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_I2C0_BASE_ADDR and + * `TOP_EARLGREY_I2C0_BASE_ADDR + TOP_EARLGREY_I2C0_SIZE_BYTES`. + */ +#define TOP_EARLGREY_I2C0_SIZE_BYTES 0x1000u + +/** + * Peripheral base address for i2c1 in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_I2C1_BASE_ADDR 0x40090000u + +/** + * Peripheral size for i2c1 in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_I2C1_BASE_ADDR and + * `TOP_EARLGREY_I2C1_BASE_ADDR + TOP_EARLGREY_I2C1_SIZE_BYTES`. + */ +#define TOP_EARLGREY_I2C1_SIZE_BYTES 0x1000u + +/** + * Peripheral base address for i2c2 in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_I2C2_BASE_ADDR 0x400A0000u + +/** + * Peripheral size for i2c2 in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_I2C2_BASE_ADDR and + * `TOP_EARLGREY_I2C2_BASE_ADDR + TOP_EARLGREY_I2C2_SIZE_BYTES`. + */ +#define TOP_EARLGREY_I2C2_SIZE_BYTES 0x1000u + +/** + * Peripheral base address for pattgen in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_PATTGEN_BASE_ADDR 0x400E0000u + +/** + * Peripheral size for pattgen in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_PATTGEN_BASE_ADDR and + * `TOP_EARLGREY_PATTGEN_BASE_ADDR + TOP_EARLGREY_PATTGEN_SIZE_BYTES`. + */ +#define TOP_EARLGREY_PATTGEN_SIZE_BYTES 0x1000u + +/** * Peripheral base address for rv_timer in top earlgrey. * * This should be used with #mmio_region_from_addr to access the memory-mapped @@ -639,21 +711,25 @@ kTopEarlgreyPlicPeripheralUart3 = 4, /**< uart3 */ kTopEarlgreyPlicPeripheralGpio = 5, /**< gpio */ kTopEarlgreyPlicPeripheralSpiDevice = 6, /**< spi_device */ - kTopEarlgreyPlicPeripheralFlashCtrl = 7, /**< flash_ctrl */ - kTopEarlgreyPlicPeripheralHmac = 8, /**< hmac */ - kTopEarlgreyPlicPeripheralAlertHandler = 9, /**< alert_handler */ - kTopEarlgreyPlicPeripheralNmiGen = 10, /**< nmi_gen */ - kTopEarlgreyPlicPeripheralUsbdev = 11, /**< usbdev */ - kTopEarlgreyPlicPeripheralPwrmgr = 12, /**< pwrmgr */ - kTopEarlgreyPlicPeripheralOtbn = 13, /**< otbn */ - kTopEarlgreyPlicPeripheralKeymgr = 14, /**< keymgr */ - kTopEarlgreyPlicPeripheralKmac = 15, /**< kmac */ - kTopEarlgreyPlicPeripheralOtpCtrl = 16, /**< otp_ctrl */ - kTopEarlgreyPlicPeripheralCsrng = 17, /**< csrng */ - kTopEarlgreyPlicPeripheralEdn0 = 18, /**< edn0 */ - kTopEarlgreyPlicPeripheralEdn1 = 19, /**< edn1 */ - kTopEarlgreyPlicPeripheralEntropySrc = 20, /**< entropy_src */ - kTopEarlgreyPlicPeripheralLast = 20, /**< \internal Final PLIC peripheral */ + kTopEarlgreyPlicPeripheralI2c0 = 7, /**< i2c0 */ + kTopEarlgreyPlicPeripheralI2c1 = 8, /**< i2c1 */ + kTopEarlgreyPlicPeripheralI2c2 = 9, /**< i2c2 */ + kTopEarlgreyPlicPeripheralPattgen = 10, /**< pattgen */ + kTopEarlgreyPlicPeripheralFlashCtrl = 11, /**< flash_ctrl */ + kTopEarlgreyPlicPeripheralHmac = 12, /**< hmac */ + kTopEarlgreyPlicPeripheralAlertHandler = 13, /**< alert_handler */ + kTopEarlgreyPlicPeripheralNmiGen = 14, /**< nmi_gen */ + kTopEarlgreyPlicPeripheralUsbdev = 15, /**< usbdev */ + kTopEarlgreyPlicPeripheralPwrmgr = 16, /**< pwrmgr */ + kTopEarlgreyPlicPeripheralOtbn = 17, /**< otbn */ + kTopEarlgreyPlicPeripheralKeymgr = 18, /**< keymgr */ + kTopEarlgreyPlicPeripheralKmac = 19, /**< kmac */ + kTopEarlgreyPlicPeripheralOtpCtrl = 20, /**< otp_ctrl */ + kTopEarlgreyPlicPeripheralCsrng = 21, /**< csrng */ + kTopEarlgreyPlicPeripheralEdn0 = 22, /**< edn0 */ + kTopEarlgreyPlicPeripheralEdn1 = 23, /**< edn1 */ + kTopEarlgreyPlicPeripheralEntropySrc = 24, /**< entropy_src */ + kTopEarlgreyPlicPeripheralLast = 24, /**< \internal Final PLIC peripheral */ } top_earlgrey_plic_peripheral_t; /** @@ -734,58 +810,108 @@ kTopEarlgreyPlicIrqIdSpiDeviceRxerr = 68, /**< spi_device_rxerr */ kTopEarlgreyPlicIrqIdSpiDeviceRxoverflow = 69, /**< spi_device_rxoverflow */ kTopEarlgreyPlicIrqIdSpiDeviceTxunderflow = 70, /**< spi_device_txunderflow */ - kTopEarlgreyPlicIrqIdFlashCtrlProgEmpty = 71, /**< flash_ctrl_prog_empty */ - kTopEarlgreyPlicIrqIdFlashCtrlProgLvl = 72, /**< flash_ctrl_prog_lvl */ - kTopEarlgreyPlicIrqIdFlashCtrlRdFull = 73, /**< flash_ctrl_rd_full */ - kTopEarlgreyPlicIrqIdFlashCtrlRdLvl = 74, /**< flash_ctrl_rd_lvl */ - kTopEarlgreyPlicIrqIdFlashCtrlOpDone = 75, /**< flash_ctrl_op_done */ - kTopEarlgreyPlicIrqIdHmacHmacDone = 76, /**< hmac_hmac_done */ - kTopEarlgreyPlicIrqIdHmacFifoEmpty = 77, /**< hmac_fifo_empty */ - kTopEarlgreyPlicIrqIdHmacHmacErr = 78, /**< hmac_hmac_err */ - kTopEarlgreyPlicIrqIdAlertHandlerClassa = 79, /**< alert_handler_classa */ - kTopEarlgreyPlicIrqIdAlertHandlerClassb = 80, /**< alert_handler_classb */ - kTopEarlgreyPlicIrqIdAlertHandlerClassc = 81, /**< alert_handler_classc */ - kTopEarlgreyPlicIrqIdAlertHandlerClassd = 82, /**< alert_handler_classd */ - kTopEarlgreyPlicIrqIdNmiGenEsc0 = 83, /**< nmi_gen_esc0 */ - kTopEarlgreyPlicIrqIdNmiGenEsc1 = 84, /**< nmi_gen_esc1 */ - kTopEarlgreyPlicIrqIdNmiGenEsc2 = 85, /**< nmi_gen_esc2 */ - kTopEarlgreyPlicIrqIdUsbdevPktReceived = 86, /**< usbdev_pkt_received */ - kTopEarlgreyPlicIrqIdUsbdevPktSent = 87, /**< usbdev_pkt_sent */ - kTopEarlgreyPlicIrqIdUsbdevDisconnected = 88, /**< usbdev_disconnected */ - kTopEarlgreyPlicIrqIdUsbdevHostLost = 89, /**< usbdev_host_lost */ - kTopEarlgreyPlicIrqIdUsbdevLinkReset = 90, /**< usbdev_link_reset */ - kTopEarlgreyPlicIrqIdUsbdevLinkSuspend = 91, /**< usbdev_link_suspend */ - kTopEarlgreyPlicIrqIdUsbdevLinkResume = 92, /**< usbdev_link_resume */ - kTopEarlgreyPlicIrqIdUsbdevAvEmpty = 93, /**< usbdev_av_empty */ - kTopEarlgreyPlicIrqIdUsbdevRxFull = 94, /**< usbdev_rx_full */ - kTopEarlgreyPlicIrqIdUsbdevAvOverflow = 95, /**< usbdev_av_overflow */ - kTopEarlgreyPlicIrqIdUsbdevLinkInErr = 96, /**< usbdev_link_in_err */ - kTopEarlgreyPlicIrqIdUsbdevRxCrcErr = 97, /**< usbdev_rx_crc_err */ - kTopEarlgreyPlicIrqIdUsbdevRxPidErr = 98, /**< usbdev_rx_pid_err */ - kTopEarlgreyPlicIrqIdUsbdevRxBitstuffErr = 99, /**< usbdev_rx_bitstuff_err */ - kTopEarlgreyPlicIrqIdUsbdevFrame = 100, /**< usbdev_frame */ - kTopEarlgreyPlicIrqIdUsbdevConnected = 101, /**< usbdev_connected */ - kTopEarlgreyPlicIrqIdUsbdevLinkOutErr = 102, /**< usbdev_link_out_err */ - kTopEarlgreyPlicIrqIdPwrmgrWakeup = 103, /**< pwrmgr_wakeup */ - kTopEarlgreyPlicIrqIdOtbnDone = 104, /**< otbn_done */ - kTopEarlgreyPlicIrqIdKeymgrOpDone = 105, /**< keymgr_op_done */ - kTopEarlgreyPlicIrqIdKmacKmacDone = 106, /**< kmac_kmac_done */ - kTopEarlgreyPlicIrqIdKmacFifoEmpty = 107, /**< kmac_fifo_empty */ - kTopEarlgreyPlicIrqIdKmacKmacErr = 108, /**< kmac_kmac_err */ - kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone = 109, /**< otp_ctrl_otp_operation_done */ - kTopEarlgreyPlicIrqIdOtpCtrlOtpError = 110, /**< otp_ctrl_otp_error */ - kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 111, /**< csrng_cs_cmd_req_done */ - kTopEarlgreyPlicIrqIdCsrngCsEntropyReq = 112, /**< csrng_cs_entropy_req */ - kTopEarlgreyPlicIrqIdCsrngCsHwInstExc = 113, /**< csrng_cs_hw_inst_exc */ - kTopEarlgreyPlicIrqIdCsrngCsFifoErr = 114, /**< csrng_cs_fifo_err */ - kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 115, /**< edn0_edn_cmd_req_done */ - kTopEarlgreyPlicIrqIdEdn0EdnFifoErr = 116, /**< edn0_edn_fifo_err */ - kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 117, /**< edn1_edn_cmd_req_done */ - kTopEarlgreyPlicIrqIdEdn1EdnFifoErr = 118, /**< edn1_edn_fifo_err */ - kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 119, /**< entropy_src_es_entropy_valid */ - kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 120, /**< entropy_src_es_health_test_failed */ - kTopEarlgreyPlicIrqIdEntropySrcEsFifoErr = 121, /**< entropy_src_es_fifo_err */ - kTopEarlgreyPlicIrqIdLast = 121, /**< \internal The Last Valid Interrupt ID. */ + kTopEarlgreyPlicIrqIdI2c0FmtWatermark = 71, /**< i2c0_fmt_watermark */ + kTopEarlgreyPlicIrqIdI2c0RxWatermark = 72, /**< i2c0_rx_watermark */ + kTopEarlgreyPlicIrqIdI2c0FmtOverflow = 73, /**< i2c0_fmt_overflow */ + kTopEarlgreyPlicIrqIdI2c0RxOverflow = 74, /**< i2c0_rx_overflow */ + kTopEarlgreyPlicIrqIdI2c0Nak = 75, /**< i2c0_nak */ + kTopEarlgreyPlicIrqIdI2c0SclInterference = 76, /**< i2c0_scl_interference */ + kTopEarlgreyPlicIrqIdI2c0SdaInterference = 77, /**< i2c0_sda_interference */ + kTopEarlgreyPlicIrqIdI2c0StretchTimeout = 78, /**< i2c0_stretch_timeout */ + kTopEarlgreyPlicIrqIdI2c0SdaUnstable = 79, /**< i2c0_sda_unstable */ + kTopEarlgreyPlicIrqIdI2c0TransComplete = 80, /**< i2c0_trans_complete */ + kTopEarlgreyPlicIrqIdI2c0TxEmpty = 81, /**< i2c0_tx_empty */ + kTopEarlgreyPlicIrqIdI2c0TxNonempty = 82, /**< i2c0_tx_nonempty */ + kTopEarlgreyPlicIrqIdI2c0TxOverflow = 83, /**< i2c0_tx_overflow */ + kTopEarlgreyPlicIrqIdI2c0AcqOverflow = 84, /**< i2c0_acq_overflow */ + kTopEarlgreyPlicIrqIdI2c0AckStop = 85, /**< i2c0_ack_stop */ + kTopEarlgreyPlicIrqIdI2c0HostTimeout = 86, /**< i2c0_host_timeout */ + kTopEarlgreyPlicIrqIdI2c1FmtWatermark = 87, /**< i2c1_fmt_watermark */ + kTopEarlgreyPlicIrqIdI2c1RxWatermark = 88, /**< i2c1_rx_watermark */ + kTopEarlgreyPlicIrqIdI2c1FmtOverflow = 89, /**< i2c1_fmt_overflow */ + kTopEarlgreyPlicIrqIdI2c1RxOverflow = 90, /**< i2c1_rx_overflow */ + kTopEarlgreyPlicIrqIdI2c1Nak = 91, /**< i2c1_nak */ + kTopEarlgreyPlicIrqIdI2c1SclInterference = 92, /**< i2c1_scl_interference */ + kTopEarlgreyPlicIrqIdI2c1SdaInterference = 93, /**< i2c1_sda_interference */ + kTopEarlgreyPlicIrqIdI2c1StretchTimeout = 94, /**< i2c1_stretch_timeout */ + kTopEarlgreyPlicIrqIdI2c1SdaUnstable = 95, /**< i2c1_sda_unstable */ + kTopEarlgreyPlicIrqIdI2c1TransComplete = 96, /**< i2c1_trans_complete */ + kTopEarlgreyPlicIrqIdI2c1TxEmpty = 97, /**< i2c1_tx_empty */ + kTopEarlgreyPlicIrqIdI2c1TxNonempty = 98, /**< i2c1_tx_nonempty */ + kTopEarlgreyPlicIrqIdI2c1TxOverflow = 99, /**< i2c1_tx_overflow */ + kTopEarlgreyPlicIrqIdI2c1AcqOverflow = 100, /**< i2c1_acq_overflow */ + kTopEarlgreyPlicIrqIdI2c1AckStop = 101, /**< i2c1_ack_stop */ + kTopEarlgreyPlicIrqIdI2c1HostTimeout = 102, /**< i2c1_host_timeout */ + kTopEarlgreyPlicIrqIdI2c2FmtWatermark = 103, /**< i2c2_fmt_watermark */ + kTopEarlgreyPlicIrqIdI2c2RxWatermark = 104, /**< i2c2_rx_watermark */ + kTopEarlgreyPlicIrqIdI2c2FmtOverflow = 105, /**< i2c2_fmt_overflow */ + kTopEarlgreyPlicIrqIdI2c2RxOverflow = 106, /**< i2c2_rx_overflow */ + kTopEarlgreyPlicIrqIdI2c2Nak = 107, /**< i2c2_nak */ + kTopEarlgreyPlicIrqIdI2c2SclInterference = 108, /**< i2c2_scl_interference */ + kTopEarlgreyPlicIrqIdI2c2SdaInterference = 109, /**< i2c2_sda_interference */ + kTopEarlgreyPlicIrqIdI2c2StretchTimeout = 110, /**< i2c2_stretch_timeout */ + kTopEarlgreyPlicIrqIdI2c2SdaUnstable = 111, /**< i2c2_sda_unstable */ + kTopEarlgreyPlicIrqIdI2c2TransComplete = 112, /**< i2c2_trans_complete */ + kTopEarlgreyPlicIrqIdI2c2TxEmpty = 113, /**< i2c2_tx_empty */ + kTopEarlgreyPlicIrqIdI2c2TxNonempty = 114, /**< i2c2_tx_nonempty */ + kTopEarlgreyPlicIrqIdI2c2TxOverflow = 115, /**< i2c2_tx_overflow */ + kTopEarlgreyPlicIrqIdI2c2AcqOverflow = 116, /**< i2c2_acq_overflow */ + kTopEarlgreyPlicIrqIdI2c2AckStop = 117, /**< i2c2_ack_stop */ + kTopEarlgreyPlicIrqIdI2c2HostTimeout = 118, /**< i2c2_host_timeout */ + kTopEarlgreyPlicIrqIdPattgenDoneCh0 = 119, /**< pattgen_done_ch0 */ + kTopEarlgreyPlicIrqIdPattgenDoneCh1 = 120, /**< pattgen_done_ch1 */ + kTopEarlgreyPlicIrqIdFlashCtrlProgEmpty = 121, /**< flash_ctrl_prog_empty */ + kTopEarlgreyPlicIrqIdFlashCtrlProgLvl = 122, /**< flash_ctrl_prog_lvl */ + kTopEarlgreyPlicIrqIdFlashCtrlRdFull = 123, /**< flash_ctrl_rd_full */ + kTopEarlgreyPlicIrqIdFlashCtrlRdLvl = 124, /**< flash_ctrl_rd_lvl */ + kTopEarlgreyPlicIrqIdFlashCtrlOpDone = 125, /**< flash_ctrl_op_done */ + kTopEarlgreyPlicIrqIdHmacHmacDone = 126, /**< hmac_hmac_done */ + kTopEarlgreyPlicIrqIdHmacFifoEmpty = 127, /**< hmac_fifo_empty */ + kTopEarlgreyPlicIrqIdHmacHmacErr = 128, /**< hmac_hmac_err */ + kTopEarlgreyPlicIrqIdAlertHandlerClassa = 129, /**< alert_handler_classa */ + kTopEarlgreyPlicIrqIdAlertHandlerClassb = 130, /**< alert_handler_classb */ + kTopEarlgreyPlicIrqIdAlertHandlerClassc = 131, /**< alert_handler_classc */ + kTopEarlgreyPlicIrqIdAlertHandlerClassd = 132, /**< alert_handler_classd */ + kTopEarlgreyPlicIrqIdNmiGenEsc0 = 133, /**< nmi_gen_esc0 */ + kTopEarlgreyPlicIrqIdNmiGenEsc1 = 134, /**< nmi_gen_esc1 */ + kTopEarlgreyPlicIrqIdNmiGenEsc2 = 135, /**< nmi_gen_esc2 */ + kTopEarlgreyPlicIrqIdUsbdevPktReceived = 136, /**< usbdev_pkt_received */ + kTopEarlgreyPlicIrqIdUsbdevPktSent = 137, /**< usbdev_pkt_sent */ + kTopEarlgreyPlicIrqIdUsbdevDisconnected = 138, /**< usbdev_disconnected */ + kTopEarlgreyPlicIrqIdUsbdevHostLost = 139, /**< usbdev_host_lost */ + kTopEarlgreyPlicIrqIdUsbdevLinkReset = 140, /**< usbdev_link_reset */ + kTopEarlgreyPlicIrqIdUsbdevLinkSuspend = 141, /**< usbdev_link_suspend */ + kTopEarlgreyPlicIrqIdUsbdevLinkResume = 142, /**< usbdev_link_resume */ + kTopEarlgreyPlicIrqIdUsbdevAvEmpty = 143, /**< usbdev_av_empty */ + kTopEarlgreyPlicIrqIdUsbdevRxFull = 144, /**< usbdev_rx_full */ + kTopEarlgreyPlicIrqIdUsbdevAvOverflow = 145, /**< usbdev_av_overflow */ + kTopEarlgreyPlicIrqIdUsbdevLinkInErr = 146, /**< usbdev_link_in_err */ + kTopEarlgreyPlicIrqIdUsbdevRxCrcErr = 147, /**< usbdev_rx_crc_err */ + kTopEarlgreyPlicIrqIdUsbdevRxPidErr = 148, /**< usbdev_rx_pid_err */ + kTopEarlgreyPlicIrqIdUsbdevRxBitstuffErr = 149, /**< usbdev_rx_bitstuff_err */ + kTopEarlgreyPlicIrqIdUsbdevFrame = 150, /**< usbdev_frame */ + kTopEarlgreyPlicIrqIdUsbdevConnected = 151, /**< usbdev_connected */ + kTopEarlgreyPlicIrqIdUsbdevLinkOutErr = 152, /**< usbdev_link_out_err */ + kTopEarlgreyPlicIrqIdPwrmgrWakeup = 153, /**< pwrmgr_wakeup */ + kTopEarlgreyPlicIrqIdOtbnDone = 154, /**< otbn_done */ + kTopEarlgreyPlicIrqIdKeymgrOpDone = 155, /**< keymgr_op_done */ + kTopEarlgreyPlicIrqIdKmacKmacDone = 156, /**< kmac_kmac_done */ + kTopEarlgreyPlicIrqIdKmacFifoEmpty = 157, /**< kmac_fifo_empty */ + kTopEarlgreyPlicIrqIdKmacKmacErr = 158, /**< kmac_kmac_err */ + kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone = 159, /**< otp_ctrl_otp_operation_done */ + kTopEarlgreyPlicIrqIdOtpCtrlOtpError = 160, /**< otp_ctrl_otp_error */ + kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 161, /**< csrng_cs_cmd_req_done */ + kTopEarlgreyPlicIrqIdCsrngCsEntropyReq = 162, /**< csrng_cs_entropy_req */ + kTopEarlgreyPlicIrqIdCsrngCsHwInstExc = 163, /**< csrng_cs_hw_inst_exc */ + kTopEarlgreyPlicIrqIdCsrngCsFifoErr = 164, /**< csrng_cs_fifo_err */ + kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 165, /**< edn0_edn_cmd_req_done */ + kTopEarlgreyPlicIrqIdEdn0EdnFifoErr = 166, /**< edn0_edn_fifo_err */ + kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 167, /**< edn1_edn_cmd_req_done */ + kTopEarlgreyPlicIrqIdEdn1EdnFifoErr = 168, /**< edn1_edn_fifo_err */ + kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 169, /**< entropy_src_es_entropy_valid */ + kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 170, /**< entropy_src_es_health_test_failed */ + kTopEarlgreyPlicIrqIdEntropySrcEsFifoErr = 171, /**< entropy_src_es_fifo_err */ + kTopEarlgreyPlicIrqIdLast = 171, /**< \internal The Last Valid Interrupt ID. */ } top_earlgrey_plic_irq_id_t; /** @@ -795,7 +921,7 @@ * `top_earlgrey_plic_peripheral_t`. */ extern const top_earlgrey_plic_peripheral_t - top_earlgrey_plic_interrupt_for_peripheral[122]; + top_earlgrey_plic_interrupt_for_peripheral[172]; /** * PLIC Interrupt Target. @@ -915,10 +1041,16 @@ kTopEarlgreyPinmuxPeripheralInGpioGpio29 = 29, /**< gpio_gpio 29 */ kTopEarlgreyPinmuxPeripheralInGpioGpio30 = 30, /**< gpio_gpio 30 */ kTopEarlgreyPinmuxPeripheralInGpioGpio31 = 31, /**< gpio_gpio 31 */ - kTopEarlgreyPinmuxPeripheralInUart1Rx = 32, /**< uart1_rx */ - kTopEarlgreyPinmuxPeripheralInUart2Rx = 33, /**< uart2_rx */ - kTopEarlgreyPinmuxPeripheralInUart3Rx = 34, /**< uart3_rx */ - kTopEarlgreyPinmuxPeripheralInLast = 34, /**< \internal Last valid peripheral input */ + kTopEarlgreyPinmuxPeripheralInI2c0Sda = 32, /**< i2c0_sda */ + kTopEarlgreyPinmuxPeripheralInI2c0Scl = 33, /**< i2c0_scl */ + kTopEarlgreyPinmuxPeripheralInI2c1Sda = 34, /**< i2c1_sda */ + kTopEarlgreyPinmuxPeripheralInI2c1Scl = 35, /**< i2c1_scl */ + kTopEarlgreyPinmuxPeripheralInI2c2Sda = 36, /**< i2c2_sda */ + kTopEarlgreyPinmuxPeripheralInI2c2Scl = 37, /**< i2c2_scl */ + kTopEarlgreyPinmuxPeripheralInUart1Rx = 38, /**< uart1_rx */ + kTopEarlgreyPinmuxPeripheralInUart2Rx = 39, /**< uart2_rx */ + kTopEarlgreyPinmuxPeripheralInUart3Rx = 40, /**< uart3_rx */ + kTopEarlgreyPinmuxPeripheralInLast = 40, /**< \internal Last valid peripheral input */ } top_earlgrey_pinmux_peripheral_in_t; /** @@ -1040,10 +1172,20 @@ kTopEarlgreyPinmuxOutselGpioGpio29 = 32, /**< gpio_gpio 29 */ kTopEarlgreyPinmuxOutselGpioGpio30 = 33, /**< gpio_gpio 30 */ kTopEarlgreyPinmuxOutselGpioGpio31 = 34, /**< gpio_gpio 31 */ - kTopEarlgreyPinmuxOutselUart1Tx = 35, /**< uart1_tx */ - kTopEarlgreyPinmuxOutselUart2Tx = 36, /**< uart2_tx */ - kTopEarlgreyPinmuxOutselUart3Tx = 37, /**< uart3_tx */ - kTopEarlgreyPinmuxOutselLast = 37, /**< \internal Last valid outsel value */ + kTopEarlgreyPinmuxOutselI2c0Sda = 35, /**< i2c0_sda */ + kTopEarlgreyPinmuxOutselI2c0Scl = 36, /**< i2c0_scl */ + kTopEarlgreyPinmuxOutselI2c1Sda = 37, /**< i2c1_sda */ + kTopEarlgreyPinmuxOutselI2c1Scl = 38, /**< i2c1_scl */ + kTopEarlgreyPinmuxOutselI2c2Sda = 39, /**< i2c2_sda */ + kTopEarlgreyPinmuxOutselI2c2Scl = 40, /**< i2c2_scl */ + kTopEarlgreyPinmuxOutselUart1Tx = 41, /**< uart1_tx */ + kTopEarlgreyPinmuxOutselUart2Tx = 42, /**< uart2_tx */ + kTopEarlgreyPinmuxOutselUart3Tx = 43, /**< uart3_tx */ + kTopEarlgreyPinmuxOutselPattgenPda0Tx = 44, /**< pattgen_pda0_tx */ + kTopEarlgreyPinmuxOutselPattgenPcl0Tx = 45, /**< pattgen_pcl0_tx */ + kTopEarlgreyPinmuxOutselPattgenPda1Tx = 46, /**< pattgen_pda1_tx */ + kTopEarlgreyPinmuxOutselPattgenPcl1Tx = 47, /**< pattgen_pcl1_tx */ + kTopEarlgreyPinmuxOutselLast = 47, /**< \internal Last valid outsel value */ } top_earlgrey_pinmux_outsel_t; /** @@ -1060,7 +1202,10 @@ typedef enum top_earlgrey_reset_manager_sw_resets { kTopEarlgreyResetManagerSwResetsSpiDevice = 0, /**< */ kTopEarlgreyResetManagerSwResetsUsb = 1, /**< */ - kTopEarlgreyResetManagerSwResetsLast = 1, /**< \internal Last valid rstmgr software reset request */ + kTopEarlgreyResetManagerSwResetsI2c0 = 2, /**< */ + kTopEarlgreyResetManagerSwResetsI2c1 = 3, /**< */ + kTopEarlgreyResetManagerSwResetsI2c2 = 4, /**< */ + kTopEarlgreyResetManagerSwResetsLast = 4, /**< \internal Last valid rstmgr software reset request */ } top_earlgrey_reset_manager_sw_resets_t; /**