| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| // ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// |
| // PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: |
| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| |
| # CLKMGR register template |
| # |
| { |
| name: "CLKMGR", |
| scan: "true", |
| clocking: [ |
| {clock: "clk_i", reset: "rst_ni", primary: true}, |
| {clock: "clk_main_i", reset: "rst_main_ni"}, |
| {clock: "clk_io_i", reset: "rst_io_ni"}, |
| {clock: "clk_usb_i", reset: "rst_usb_ni"}, |
| {clock: "clk_aon_i", reset: "rst_aon_ni"}, |
| {clock: "clk_io_div2_i", reset: "rst_io_div2_ni", internal: true}, |
| {clock: "clk_io_div4_i", reset: "rst_io_div4_ni", internal: true}, |
| ] |
| bus_interfaces: [ |
| { protocol: "tlul", direction: "device" } |
| ], |
| alert_list: [ |
| { name: "recov_fault", |
| desc: ''' |
| This recoverable alert is triggered when there are measurement errors. |
| ''' |
| } |
| { name: "fatal_fault", |
| desc: ''' |
| This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. |
| ''' |
| } |
| ], |
| regwidth: "32", |
| param_list: [ |
| { name: "NumGroups", |
| desc: "Number of clock groups", |
| type: "int", |
| default: "7", |
| local: "true" |
| }, |
| { name: "NumSwGateableClocks", |
| desc: "Number of SW gateable clocks", |
| type: "int", |
| default: "4", |
| local: "true" |
| }, |
| { name: "NumHintableClocks", |
| desc: "Number of hintable clocks", |
| type: "int", |
| default: "5", |
| local: "true" |
| }, |
| ], |
| |
| inter_signal_list: [ |
| { struct: "clkmgr_out", |
| type: "uni", |
| name: "clocks", |
| act: "req", |
| package: "clkmgr_pkg", |
| }, |
| |
| { struct: "clkmgr_cg_en", |
| type: "uni", |
| name: "cg_en", |
| act: "req", |
| package: "clkmgr_pkg", |
| }, |
| |
| { struct: "lc_tx", |
| type: "uni", |
| name: "lc_dft_en", |
| act: "rcv", |
| package: "lc_ctrl_pkg", |
| }, |
| |
| { struct: "lc_tx", |
| type: "uni", |
| name: "ast_clk_byp_req", |
| act: "req", |
| package: "lc_ctrl_pkg", |
| }, |
| |
| { struct: "lc_tx", |
| type: "uni", |
| name: "ast_clk_byp_ack", |
| act: "rcv", |
| package: "lc_ctrl_pkg", |
| }, |
| |
| { struct: "lc_tx", |
| type: "uni", |
| name: "lc_clk_byp_req", |
| act: "rcv", |
| package: "lc_ctrl_pkg", |
| }, |
| |
| { struct: "lc_tx", |
| type: "uni", |
| name: "lc_clk_byp_ack", |
| act: "req", |
| package: "lc_ctrl_pkg", |
| }, |
| |
| { struct: "logic", |
| type: "uni", |
| name: "jitter_en", |
| act: "req", |
| package: "" |
| }, |
| |
| // Exported clocks |
| |
| { struct: "pwr_clk", |
| type: "req_rsp", |
| name: "pwr", |
| act: "rsp", |
| }, |
| |
| { struct: "logic", |
| type: "uni", |
| name: "idle", |
| act: "rcv", |
| package: "", |
| width: "5" |
| }, |
| ], |
| |
| |
| registers: [ |
| { name: "EXTCLK_CTRL_REGWEN", |
| desc: "External clock control write enable", |
| swaccess: "rw0c", |
| hwaccess: "none", |
| fields: [ |
| { bits: "0", |
| name: "EN", |
| resval: "1" |
| desc: ''' |
| When 1, the value of !!EXTCLK_CTRL can be set. When 0, writes to !!EXTCLK_CTRL have no |
| effect. |
| ''' |
| }, |
| ] |
| }, |
| |
| { name: "EXTCLK_CTRL", |
| desc: ''' |
| Select external clock |
| ''', |
| regwen: "EXTCLK_CTRL_REGWEN", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { |
| bits: "3:0", |
| name: "SEL", |
| desc: ''' |
| A value of b1010 selects external clock as clock for the system. |
| While this register can always be programmed, it only takes effect when the system is in |
| life cycle TEST or RMA states when DFT is enabled. |
| |
| All other values are invalid and keep clocks on internal sources. |
| ''' |
| resval: "0x5" |
| }, |
| { |
| bits: "7:4", |
| name: "STEP_DOWN", |
| desc: ''' |
| A value of b1010 steps down the clock dividers by a factor of 2 if the !!EXTCLK_CTRL.SEL |
| field is also set to b1010. |
| |
| All other values have no effect. |
| ''' |
| resval: "0x5" |
| } |
| ] |
| }, |
| |
| { name: "JITTER_ENABLE", |
| desc: ''' |
| Enable jittery clock |
| ''', |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { |
| bits: "0", |
| name: "VAL", |
| desc: "Enable jittery clock" |
| resval: "0" |
| } |
| ] |
| }, |
| |
| { name: "CLK_ENABLES", |
| desc: ''' |
| Clock enable for software gateable clocks. |
| These clocks are directly controlled by software. |
| ''', |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { |
| bits: "0", |
| name: "CLK_IO_DIV4_PERI_EN", |
| resval: 1, |
| desc: ''' |
| 0 CLK_IO_DIV4_PERI is disabled. |
| 1 CLK_IO_DIV4_PERI is enabled. |
| ''' |
| } |
| { |
| bits: "1", |
| name: "CLK_IO_DIV2_PERI_EN", |
| resval: 1, |
| desc: ''' |
| 0 CLK_IO_DIV2_PERI is disabled. |
| 1 CLK_IO_DIV2_PERI is enabled. |
| ''' |
| } |
| { |
| bits: "2", |
| name: "CLK_IO_PERI_EN", |
| resval: 1, |
| desc: ''' |
| 0 CLK_IO_PERI is disabled. |
| 1 CLK_IO_PERI is enabled. |
| ''' |
| } |
| { |
| bits: "3", |
| name: "CLK_USB_PERI_EN", |
| resval: 1, |
| desc: ''' |
| 0 CLK_USB_PERI is disabled. |
| 1 CLK_USB_PERI is enabled. |
| ''' |
| } |
| ] |
| // the CLK_ENABLE register cannot be written, otherwise there is the potential clocks could be |
| // disabled and the system will hang |
| tags: ["excl:CsrAllTests:CsrExclAll"] |
| }, |
| |
| { name: "CLK_HINTS", |
| desc: ''' |
| Clock hint for software gateable transactional clocks during active mode. |
| During low power mode, all clocks are gated off regardless of the software hint. |
| |
| Transactional clocks are not fully controlled by software. Instead software provides only a disable hint. |
| |
| When software provides a disable hint, the clock manager checks to see if the associated hardware block is idle. |
| If the hardware block is idle, then the clock is disabled. |
| If the hardware block is not idle, the clock is kept on. |
| |
| For the enable case, the software hint is immediately honored and the clock turned on. Hardware does not provide any |
| feedback in this case. |
| ''', |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { |
| bits: "0", |
| name: "CLK_MAIN_AES_HINT", |
| resval: 1, |
| desc: ''' |
| 0 CLK_MAIN_AES can be disabled. |
| 1 CLK_MAIN_AES is enabled. |
| ''' |
| } |
| { |
| bits: "1", |
| name: "CLK_MAIN_HMAC_HINT", |
| resval: 1, |
| desc: ''' |
| 0 CLK_MAIN_HMAC can be disabled. |
| 1 CLK_MAIN_HMAC is enabled. |
| ''' |
| } |
| { |
| bits: "2", |
| name: "CLK_MAIN_KMAC_HINT", |
| resval: 1, |
| desc: ''' |
| 0 CLK_MAIN_KMAC can be disabled. |
| 1 CLK_MAIN_KMAC is enabled. |
| ''' |
| } |
| { |
| bits: "3", |
| name: "CLK_IO_DIV4_OTBN_HINT", |
| resval: 1, |
| desc: ''' |
| 0 CLK_IO_DIV4_OTBN can be disabled. |
| 1 CLK_IO_DIV4_OTBN is enabled. |
| ''' |
| } |
| { |
| bits: "4", |
| name: "CLK_MAIN_OTBN_HINT", |
| resval: 1, |
| desc: ''' |
| 0 CLK_MAIN_OTBN can be disabled. |
| 1 CLK_MAIN_OTBN is enabled. |
| ''' |
| } |
| ] |
| // the CLK_HINT register cannot be written, otherwise there is the potential clocks could be |
| // disabled and the system will hang |
| tags: ["excl:CsrAllTests:CsrExclAll"] |
| }, |
| |
| { name: "CLK_HINTS_STATUS", |
| desc: ''' |
| Since the final state of !!CLK_HINTS is not always determined by software, |
| this register provides read feedback for the current clock state. |
| |
| ''', |
| swaccess: "ro", |
| hwaccess: "hwo", |
| fields: [ |
| { |
| bits: "0", |
| name: "CLK_MAIN_AES_VAL", |
| resval: 1, |
| desc: ''' |
| 0 CLK_MAIN_AES is disabled. |
| 1 CLK_MAIN_AES is enabled. |
| ''' |
| } |
| { |
| bits: "1", |
| name: "CLK_MAIN_HMAC_VAL", |
| resval: 1, |
| desc: ''' |
| 0 CLK_MAIN_HMAC is disabled. |
| 1 CLK_MAIN_HMAC is enabled. |
| ''' |
| } |
| { |
| bits: "2", |
| name: "CLK_MAIN_KMAC_VAL", |
| resval: 1, |
| desc: ''' |
| 0 CLK_MAIN_KMAC is disabled. |
| 1 CLK_MAIN_KMAC is enabled. |
| ''' |
| } |
| { |
| bits: "3", |
| name: "CLK_IO_DIV4_OTBN_VAL", |
| resval: 1, |
| desc: ''' |
| 0 CLK_IO_DIV4_OTBN is disabled. |
| 1 CLK_IO_DIV4_OTBN is enabled. |
| ''' |
| } |
| { |
| bits: "4", |
| name: "CLK_MAIN_OTBN_VAL", |
| resval: 1, |
| desc: ''' |
| 0 CLK_MAIN_OTBN is disabled. |
| 1 CLK_MAIN_OTBN is enabled. |
| ''' |
| } |
| ] |
| }, |
| |
| { name: "MEASURE_CTRL_REGWEN", |
| desc: "Measurement control write enable", |
| swaccess: "rw0c", |
| hwaccess: "none", |
| fields: [ |
| { bits: "0", |
| name: "EN", |
| resval: "1" |
| desc: ''' |
| When 1, the value of the measurement control can be set. When 0, writes have no |
| effect. |
| ''' |
| }, |
| ] |
| }, |
| |
| { name: "IO_MEASURE_CTRL", |
| desc: ''' |
| Configuration controls for io measurement. |
| |
| The threshold fields are made wider than required (by 1 bit) to ensure |
| there is room to adjust for measurement inaccuracies. |
| ''', |
| regwen: "MEASURE_CTRL_REGWEN", |
| swaccess: "rw", |
| hwaccess: "hro", |
| async: "clk_io_i", |
| fields: [ |
| { |
| bits: "0", |
| name: "EN", |
| desc: "Enable measurement for io", |
| resval: "0", |
| // Measurements can cause recoverable errors depending on the |
| // thresholds which the CSR tests will not predict correctly. |
| // To provide better CSR coverage we allow writing the threshold |
| // fields, but not enabling the counters. |
| tags: ["excl:CsrNonInitTests:CsrExclWrite"] |
| }, |
| |
| { |
| bits: "13:4", |
| name: "MAX_THRESH", |
| desc: "Max threshold for io measurement", |
| resval: "490" |
| }, |
| |
| { |
| bits: "23:14", |
| name: "MIN_THRESH", |
| desc: "Min threshold for io measurement", |
| resval: "470" |
| }, |
| ] |
| }, |
| { name: "IO_DIV2_MEASURE_CTRL", |
| desc: ''' |
| Configuration controls for io_div2 measurement. |
| |
| The threshold fields are made wider than required (by 1 bit) to ensure |
| there is room to adjust for measurement inaccuracies. |
| ''', |
| regwen: "MEASURE_CTRL_REGWEN", |
| swaccess: "rw", |
| hwaccess: "hro", |
| async: "clk_io_div2_i", |
| fields: [ |
| { |
| bits: "0", |
| name: "EN", |
| desc: "Enable measurement for io_div2", |
| resval: "0", |
| // Measurements can cause recoverable errors depending on the |
| // thresholds which the CSR tests will not predict correctly. |
| // To provide better CSR coverage we allow writing the threshold |
| // fields, but not enabling the counters. |
| tags: ["excl:CsrNonInitTests:CsrExclWrite"] |
| }, |
| |
| { |
| bits: "12:4", |
| name: "MAX_THRESH", |
| desc: "Max threshold for io_div2 measurement", |
| resval: "250" |
| }, |
| |
| { |
| bits: "21:13", |
| name: "MIN_THRESH", |
| desc: "Min threshold for io_div2 measurement", |
| resval: "230" |
| }, |
| ] |
| }, |
| { name: "IO_DIV4_MEASURE_CTRL", |
| desc: ''' |
| Configuration controls for io_div4 measurement. |
| |
| The threshold fields are made wider than required (by 1 bit) to ensure |
| there is room to adjust for measurement inaccuracies. |
| ''', |
| regwen: "MEASURE_CTRL_REGWEN", |
| swaccess: "rw", |
| hwaccess: "hro", |
| async: "clk_io_div4_i", |
| fields: [ |
| { |
| bits: "0", |
| name: "EN", |
| desc: "Enable measurement for io_div4", |
| resval: "0", |
| // Measurements can cause recoverable errors depending on the |
| // thresholds which the CSR tests will not predict correctly. |
| // To provide better CSR coverage we allow writing the threshold |
| // fields, but not enabling the counters. |
| tags: ["excl:CsrNonInitTests:CsrExclWrite"] |
| }, |
| |
| { |
| bits: "11:4", |
| name: "MAX_THRESH", |
| desc: "Max threshold for io_div4 measurement", |
| resval: "130" |
| }, |
| |
| { |
| bits: "19:12", |
| name: "MIN_THRESH", |
| desc: "Min threshold for io_div4 measurement", |
| resval: "110" |
| }, |
| ] |
| }, |
| { name: "MAIN_MEASURE_CTRL", |
| desc: ''' |
| Configuration controls for main measurement. |
| |
| The threshold fields are made wider than required (by 1 bit) to ensure |
| there is room to adjust for measurement inaccuracies. |
| ''', |
| regwen: "MEASURE_CTRL_REGWEN", |
| swaccess: "rw", |
| hwaccess: "hro", |
| async: "clk_main_i", |
| fields: [ |
| { |
| bits: "0", |
| name: "EN", |
| desc: "Enable measurement for main", |
| resval: "0", |
| // Measurements can cause recoverable errors depending on the |
| // thresholds which the CSR tests will not predict correctly. |
| // To provide better CSR coverage we allow writing the threshold |
| // fields, but not enabling the counters. |
| tags: ["excl:CsrNonInitTests:CsrExclWrite"] |
| }, |
| |
| { |
| bits: "13:4", |
| name: "MAX_THRESH", |
| desc: "Max threshold for main measurement", |
| resval: "510" |
| }, |
| |
| { |
| bits: "23:14", |
| name: "MIN_THRESH", |
| desc: "Min threshold for main measurement", |
| resval: "490" |
| }, |
| ] |
| }, |
| { name: "USB_MEASURE_CTRL", |
| desc: ''' |
| Configuration controls for usb measurement. |
| |
| The threshold fields are made wider than required (by 1 bit) to ensure |
| there is room to adjust for measurement inaccuracies. |
| ''', |
| regwen: "MEASURE_CTRL_REGWEN", |
| swaccess: "rw", |
| hwaccess: "hro", |
| async: "clk_usb_i", |
| fields: [ |
| { |
| bits: "0", |
| name: "EN", |
| desc: "Enable measurement for usb", |
| resval: "0", |
| // Measurements can cause recoverable errors depending on the |
| // thresholds which the CSR tests will not predict correctly. |
| // To provide better CSR coverage we allow writing the threshold |
| // fields, but not enabling the counters. |
| tags: ["excl:CsrNonInitTests:CsrExclWrite"] |
| }, |
| |
| { |
| bits: "12:4", |
| name: "MAX_THRESH", |
| desc: "Max threshold for usb measurement", |
| resval: "250" |
| }, |
| |
| { |
| bits: "21:13", |
| name: "MIN_THRESH", |
| desc: "Min threshold for usb measurement", |
| resval: "230" |
| }, |
| ] |
| }, |
| |
| { name: "RECOV_ERR_CODE", |
| desc: "Recoverable Error code ", |
| swaccess: "rw1c", |
| hwaccess: "hwo", |
| fields: [ |
| { |
| bits: "0", |
| name: "IO_MEASURE_ERR", |
| resval: 0, |
| desc: ''' |
| io has encountered a measurement error. |
| ''' |
| } |
| { |
| bits: "1", |
| name: "IO_DIV2_MEASURE_ERR", |
| resval: 0, |
| desc: ''' |
| io_div2 has encountered a measurement error. |
| ''' |
| } |
| { |
| bits: "2", |
| name: "IO_DIV4_MEASURE_ERR", |
| resval: 0, |
| desc: ''' |
| io_div4 has encountered a measurement error. |
| ''' |
| } |
| { |
| bits: "3", |
| name: "MAIN_MEASURE_ERR", |
| resval: 0, |
| desc: ''' |
| main has encountered a measurement error. |
| ''' |
| } |
| { |
| bits: "4", |
| name: "USB_MEASURE_ERR", |
| resval: 0, |
| desc: ''' |
| usb has encountered a measurement error. |
| ''' |
| } |
| ] |
| }, |
| |
| { name: "FATAL_ERR_CODE", |
| desc: "Error code ", |
| swaccess: "ro", |
| hwaccess: "hrw", |
| fields: [ |
| { bits: "0", |
| name: "REG_INTG", |
| resval: 0 |
| desc: ''' |
| Register file has experienced a fatal integrity error. |
| ''' |
| }, |
| ] |
| }, |
| ] |
| } |
