[padctrl] Remove padctrl sources and merge functionality into pinmux Note that hw/ip/padctrl still contains some legacy documentation material and design sources that need to be moved or merged with the pinmux docs. This will be done in a separate PR. Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/doc/rm/comportability_specification/index.md b/doc/rm/comportability_specification/index.md index ccc1b2f..5ae21f3 100644 --- a/doc/rm/comportability_specification/index.md +++ b/doc/rm/comportability_specification/index.md
@@ -203,8 +203,8 @@ That is done at the top level with an Hjson configuration file. See the top level specification for information about that configuration file. -In addition, full pad control is not done by the peripheral logic, but is done by the [`padctrl`]({{< relref "/hw/ip/padctrl/doc" >}}) module. -The `padctrl` module provides software configuration control over pad drive strength, pin mapping, pad type (push/pull, open drain, etc). +In addition, full pad control is not done by the peripheral logic, but is done, by the `pinmux` as well. +The `pinmux` module provides software configuration control over pad drive strength, pin mapping, pad type (push/pull, open drain, etc). ### Interrupts
diff --git a/hw/Makefile b/hw/Makefile index 0362c0c..7331646 100644 --- a/hw/Makefile +++ b/hw/Makefile
@@ -25,7 +25,6 @@ lc_ctrl \ nmi_gen \ otp_ctrl \ - padctrl \ pinmux \ pwrmgr \ rstmgr \
diff --git a/hw/formal/fpv_all b/hw/formal/fpv_all index d5b09fd..967b73a 100755 --- a/hw/formal/fpv_all +++ b/hw/formal/fpv_all
@@ -53,7 +53,6 @@ "prim_secded_hamming_39_32_fpv" "prim_secded_hamming_72_64_fpv" "pinmux_fpv" - "padctrl_fpv" "rv_plic_fpv" "rv_plic_generic_fpv" )
diff --git a/hw/ip/padctrl/data/padctrl.hjson b/hw/ip/padctrl/data/padctrl.hjson deleted file mode 100644 index 6900f46..0000000 --- a/hw/ip/padctrl/data/padctrl.hjson +++ /dev/null
@@ -1,127 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -# PADCTRL register template -# -# Parameter (given by Python tool) -# - n_dio_pads: Number of dedicated IO pads -# - n_mio_pads: Number of muxed IO pads -# - attr_dw: Attribute datawidth -{ - name: "PADCTRL", - clock_primary: "clk_i", - bus_device: "tlul", - regwidth: "32", - param_list: [ - { name: "NDioPads", - desc: "Number of dedicated IO pads", - type: "int", - default: "4", - local: "true" - }, - { name: "NMioPads", - desc: "Number of muxed IO pads", - type: "int", - default: "16", - local: "true" - }, - { name: "AttrDw", - desc: "Pad attribute data width", - type: "int", - default: "10", - local: "true" - }, - ], - registers: [ - { name: "REGWEN", - desc: ''' - Register write enable for all control registers. - ''', - swaccess: "rw0c", - hwaccess: "none", - fields: [ - { - bits: "0", - name: "wen", - desc: ''' When true, all configuration registers can be modified. - When false, they become read-only. Defaults true, write zero to clear. - ''' - resval: 1, - }, - ] - }, -# dedicated pads - { multireg: { name: "DIO_PADS", - desc: '''Dedicated pad attributes. - This register has WARL behavior as some attributes may not be implemented. - ''', - count: "NDioPads", - swaccess: "rw", - hwaccess: "hrw", - hwext: "true", - hwqe: "true", - regwen: "REGWEN", - cname: "ATTR", - fields: [ - { bits: "9:0", - name: "ATTR", - desc: '''Bit 0: input/output inversion, - Bit 1: Virtual open drain enable. - Bit 2: Pull enable. - Bit 3: Pull select (0: pull down, 1: pull up). - Bit 4: Keeper enable. - Bit 5: Schmitt trigger enable. - Bit 6: Slew rate (0: slow, 1: fast). - Bit 7/8: Drive strength (00: weakest, 11: strongest). - Bit 9: Reserved. - ''' - resval: 0 - } - ], - // these CSRs have WARL behavior and may not - // read back the same value that was written to them. - // further, they have hardware side effects since they drive the - // pad attributes, and hence no random data should be written to them. - tags: ["excl:CsrAllTests:CsrExclWrite"] - } - }, -# muxed pads - { multireg: { name: "MIO_PADS", - desc: '''Muxed pad attributes. - This register has WARL behavior as some attributes may not be implemented. - ''', - count: "NMioPads", - swaccess: "rw", - hwaccess: "hrw", - hwext: "true", - hwqe: "true", - regwen: "REGWEN", - cname: "ATTR", - fields: [ - { bits: "9:0", - name: "ATTR", - desc: '''Bit 0: input/output inversion, - Bit 1: Virtual open drain enable. - Bit 2: Pull enable. - Bit 3: Pull select (0: pull down, 1: pull up). - Bit 4: Keeper enable. - Bit 5: Schmitt trigger enable. - Bit 6: Slew rate (0: slow, 1: fast). - Bit 7/8: Drive strength (00: weakest, 11: strongest). - Bit 9: Reserved. - ''' - resval: 0 - } - ], - // these CSRs have WARL behavior and may not - // read back the same value that was written to them. - // further, they have hardware side effects since they drive the - // pad attributes, and hence no random data should be written to them. - tags: ["excl:CsrAllTests:CsrExclWrite"] - } - }, - ], -} - -
diff --git a/hw/ip/padctrl/data/padctrl.hjson.tpl b/hw/ip/padctrl/data/padctrl.hjson.tpl deleted file mode 100644 index afef779..0000000 --- a/hw/ip/padctrl/data/padctrl.hjson.tpl +++ /dev/null
@@ -1,126 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -# PADCTRL register template -# -# Parameter (given by Python tool) -# - n_dio_pads: Number of dedicated IO pads -# - n_mio_pads: Number of muxed IO pads -# - attr_dw: Attribute datawidth -{ - name: "PADCTRL", - clock_primary: "clk_i", - bus_device: "tlul", - regwidth: "32", - param_list: [ - { name: "NDioPads", - desc: "Number of dedicated IO pads", - type: "int", - default: "${n_dio_pads}", - local: "true" - }, - { name: "NMioPads", - desc: "Number of muxed IO pads", - type: "int", - default: "${n_mio_pads}", - local: "true" - }, - { name: "AttrDw", - desc: "Pad attribute data width", - type: "int", - default: "${attr_dw}", - local: "true" - }, - ], - registers: [ - { name: "REGWEN", - desc: ''' - Register write enable for all control registers. - ''', - swaccess: "rw0c", - hwaccess: "none", - fields: [ - { - bits: "0", - name: "wen", - desc: ''' When true, all configuration registers can be modified. - When false, they become read-only. Defaults true, write zero to clear. - ''' - resval: 1, - }, - ] - }, -# dedicated pads - { multireg: { name: "DIO_PADS", - desc: '''Dedicated pad attributes. - This register has WARL behavior as some attributes may not be implemented. - ''', - count: "NDioPads", - swaccess: "rw", - hwaccess: "hrw", - hwext: "true", - hwqe: "true", - regwen: "REGWEN", - cname: "ATTR", - fields: [ - { bits: "9:0", - name: "ATTR", - desc: '''Bit 0: input/output inversion, - Bit 1: Virtual open drain enable. - Bit 2: Pull enable. - Bit 3: Pull select (0: pull down, 1: pull up). - Bit 4: Keeper enable. - Bit 5: Schmitt trigger enable. - Bit 6: Slew rate (0: slow, 1: fast). - Bit 7/8: Drive strength (00: weakest, 11: strongest). - Bit 9: Reserved. - ''' - resval: 0 - } - ], - // these CSRs have WARL behavior and may not - // read back the same value that was written to them. - // further, they have hardware side effects since they drive the - // pad attributes, and hence no random data should be written to them. - tags: ["excl:CsrAllTests:CsrExclWrite"] - } - }, -# muxed pads - { multireg: { name: "MIO_PADS", - desc: '''Muxed pad attributes. - This register has WARL behavior as some attributes may not be implemented. - ''', - count: "NMioPads", - swaccess: "rw", - hwaccess: "hrw", - hwext: "true", - hwqe: "true", - regwen: "REGWEN", - cname: "ATTR", - fields: [ - { bits: "9:0", - name: "ATTR", - desc: '''Bit 0: input/output inversion, - Bit 1: Virtual open drain enable. - Bit 2: Pull enable. - Bit 3: Pull select (0: pull down, 1: pull up). - Bit 4: Keeper enable. - Bit 5: Schmitt trigger enable. - Bit 6: Slew rate (0: slow, 1: fast). - Bit 7/8: Drive strength (00: weakest, 11: strongest). - Bit 9: Reserved. - ''' - resval: 0 - } - ], - // these CSRs have WARL behavior and may not - // read back the same value that was written to them. - // further, they have hardware side effects since they drive the - // pad attributes, and hence no random data should be written to them. - tags: ["excl:CsrAllTests:CsrExclWrite"] - } - }, - ], -} -
diff --git a/hw/ip/padctrl/data/padctrl.prj.hjson b/hw/ip/padctrl/data/padctrl.prj.hjson deleted file mode 100644 index 8314ef8..0000000 --- a/hw/ip/padctrl/data/padctrl.prj.hjson +++ /dev/null
@@ -1,15 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -{ - name: "padctrl", - design_spec: "hw/ip/padctrl/doc", - dv_doc: "hw/ip/padctrl/doc/dv", - hw_checklist: "hw/ip/padctrl/doc/checklist", - version: "0.5", - life_stage: "L1", - design_stage: "D1", - verification_stage: "V0", - notes: "will be verified at top level; formal at block level", -}
diff --git a/hw/ip/padctrl/data/padctrl_fpv_testplan.hjson b/hw/ip/padctrl/data/padctrl_fpv_testplan.hjson deleted file mode 100644 index 3b78cd1..0000000 --- a/hw/ip/padctrl/data/padctrl_fpv_testplan.hjson +++ /dev/null
@@ -1,175 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -{ - name: "padctrl" - import_testplans: ["hw/dv/tools/dvsim/testplans/fpv_csr_testplan.hjson"] - entries: [ - { - name: MioWarl_A - // TODO: need a better way eliminate the differentiation between imp targets - desc: '''In either generic or Xilinx mode, if a muxed IO's pad attribute is written to the - mio_pads registers via the TLUL interface, this assertion checks if the corresponding - mio_attr_o's reserved bits remain 0. This assertion intends to test the - write_any_read_legal access policy for the mio_pads registers.''' - milestone: V2 - tests: ["padctrl_assert"] - } - { - name: MioAttr_A - desc: '''In either generic or Xilinx mode, if a muxed IO's pad attribute is written to the - mio_pads registers via the TLUL interface, this assertion checks if the corresponding - mio_attr_o value is updated correctly.''' - milestone: V2 - tests: ["padctrl_assert"] - } - { - name: MioBackwardCheck_A - desc: '''If the output mio_attr_o has changed, then a valid write to the mio_pads register - must have taken place or the write enable signal must have risen in the previous - cycle.''' - milestone: V2 - tests: ["padctrl_assert"] - } - { - name: DioWarl_A - desc: '''In either generic or Xilinx mode, if a dedicated IO's pad attribute is written to - the dio_pads registers via the TLUL interface, this assertion checks if the - corresponding dio_attr_o's reserved bits remain 0. This assertion intends to test the - write_any_read_legal access policy for the dio_pads registers.''' - milestone: V2 - tests: ["padctrl_assert"] - } - { - name: DioAttr_A - desc: '''In either generic or Xilinx mode, if a dedicated IO's pad attribute is written to - the dio_pads registers via the TLUL interface, this assertion checks if the - corresponding dio_attr_o value is updated correctly.''' - milestone: V2 - tests: ["padctrl_assert"] - } - { - name: DioBackwardCheck_A - desc: '''If the output dio_attr_o has changed, then a valid write to the dio_pads register - must have taken place or the write enable signal must have risen in the previous - cycle.''' - milestone: V2 - tests: ["padctrl_assert"] - } - { - name: ClkConn_A - desc: "This assertion checks that clk_pad_i is correctly connected to clk_o." - milestone: V2 - tests: ["padring_assert"] - } - { - name: RstConn_A - desc: "This assertion checks that rst_pad_ni is correctly connected to rst_no." - milestone: V2 - tests: ["padring_assert"] - } - { - name: MioIn_A - desc: '''This assertion checks the muxed IO output mio_in_o based on mio_pad_io and - mio_attr_i inversion bit.''' - milestone: V2 - tests: ["padring_assert"] - } - { - name: MioInBackwardCheck_A - desc: '''If the muxed IO output mio_in_o has changed, then mio_pad_io or mio_attr_i must be - changed in the same clock cycle.''' - milestone: V2 - tests: ["padring_assert"] - } - { - name: MioOutNormal_A - desc: '''If the selected muxed IO output is enabled and the corresponding attribute is not - open drain, then the mio_pad_io must be the (possibly inverted) muxed IO output - value.''' - milestone: V2 - tests: ["padring_assert"] - } - { - name: MioOutOd0_A - desc: '''If the selected muxed IO output is enabled, the open drain attribute is set, and the - expected mio_output value is 0, then the mio_pad_io must be 0.''' - milestone: V2 - tests: ["padring_assert"] - } - { - name: MioOutOd1_A - desc: '''If the selected muxed IO output is enabled, the open drain attribute is set, and the - expected mio_output value is not 0, then the mio_pad_io must be either 0, 1, x or - high z.''' - milestone: V2 - tests: ["padring_assert"] - } - { - name: MioOutBackwardCheck_A - desc: '''If the muxed IO output mio_pad_io has changed and mio_oe_i is enabled, then - mio_attr_i or mio_output_value must be changed in the same clock cycle.''' - milestone: V2 - tests: ["padring_assert"] - } - { - name: MioOe_A - desc: '''If the selected muxed IO output is not enabled, the mio_pad_io must be either 0, 1, - x or high z.''' - milestone: V2 - tests: ["padring_assert"] - } - { - name: DioIn_A - desc: '''This assertion checks the dedicated IO output dio_in_o based on dio_pad_io and - dio_attr_i inversion bit.''' - milestone: V2 - tests: ["padring_assert"] - } - { - name: DioInBackwardCheck_A - desc: '''If dedicated IO output dio_in_o has changed, then dio_pad_io or dio_attr_i must be - changed in the same clock cycle.''' - milestone: V2 - tests: ["padring_assert"] - } - { - name: DioOutNormal_A - desc: '''If the selected dedicated IO output is enabled and the corresponding attribute is - not open drain, then the dio_pad_io must be the (possibly inverted) dedicated IO output - value.''' - milestone: V2 - tests: ["padring_assert"] - } - { - name: DioOutOd0_A - desc: '''If the selected dedicated IO output is enabled, the open drain attribute is set, and - the expected dio_output value is 0, then the dio_pad_io must be 0.''' - milestone: V2 - tests: ["padring_assert"] - } - { - name: DioOutOd1_A - desc: '''If the selected dedicated IO output is enabled, the open drain attribute is set, and - the expected dio_output value is not 0, then the dio_pad_io must be either 0, 1, x or - high z.''' - milestone: V2 - tests: ["padring_assert"] - } - { - name: DioOutBackwardCheck_A - desc: '''If the dedicated IO output dio_pad_io has changed and dio_oe_i is enabled, then - dio_attr_i or dio_output_value must be changed in the same clock cycle.''' - milestone: V2 - tests: ["padring_assert"] - } - { - name: DioOe_A - desc: '''If the selected dedicated IO output is not enabled, the dio_pad_io must be either 0, - 1, x or high z.''' - milestone: V2 - tests: ["padring_assert"] - } - ] -} -
diff --git a/hw/ip/padctrl/doc/checklist.md b/hw/ip/padctrl/doc/checklist.md deleted file mode 100644 index 156b005..0000000 --- a/hw/ip/padctrl/doc/checklist.md +++ /dev/null
@@ -1,236 +0,0 @@ ---- -title: "Padctrl Checklist" ---- - -This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [Padctrl peripheral.]({{< relref "./" >}}) -All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}}) - -## Design Checklist - -### D1 - -Type | Item | Resolution | Note/Collaterals ---------------|--------------------------------|-------------|------------------ -Documentation | [SPEC_COMPLETE][] | Done | [Padctrl spec]({{< relref "./" >}}) -Documentation | [CSR_DEFINED][] | Done | -RTL | [CLKRST_CONNECTED][] | Done | -RTL | [IP_TOP][] | Done | -RTL | [IP_INSTANTIABLE][] | Done | -RTL | [PHYSICAL_MACROS_DEFINED_80][] | Done | -RTL | [FUNC_IMPLEMENTED][] | Done | -RTL | [ASSERT_KNOWN_ADDED][] | Done | -Code Quality | [LINT_SETUP][] | Done | - - -[SPEC_COMPLETE]: {{<relref "/doc/project/checklist.md#spec_complete" >}} -[CSR_DEFINED]: {{<relref "/doc/project/checklist.md#csr_defined" >}} -[CLKRST_CONNECTED]: {{<relref "/doc/project/checklist.md#clkrst_connected" >}} -[IP_TOP]: {{<relref "/doc/project/checklist.md#ip_top" >}} -[IP_INSTANTIABLE]: {{<relref "/doc/project/checklist.md#ip_instantiable" >}} -[PHYSICAL_MACROS_DEFINED_80]: {{<relref "/doc/project/checklist.md#physical_macros_defined_80" >}} -[FUNC_IMPLEMENTED]: {{<relref "/doc/project/checklist.md#func_implemented" >}} -[ASSERT_KNOWN_ADDED]: {{<relref "/doc/project/checklist.md#assert_known_added" >}} -[LINT_SETUP]: {{<relref "/doc/project/checklist.md#lint_setup" >}} - -### D2 - -Type | Item | Resolution | Note/Collaterals ---------------|-------------------------|-------------|------------------ -Documentation | [NEW_FEATURES][] | Not Started | -Documentation | [BLOCK_DIAGRAM][] | Done | -Documentation | [DOC_INTERFACE][] | Done | -Documentation | [MISSING_FUNC][] | Not Started | -Documentation | [FEATURE_FROZEN][] | Not Started | -RTL | [FEATURE_COMPLETE][] | Not Started | -RTL | [AREA_CHECK][] | Not Started | -RTL | [PORT_FROZEN][] | Not Started | -RTL | [ARCHITECTURE_FROZEN][] | Not Started | -RTL | [REVIEW_TODO][] | Not Started | -RTL | [STYLE_X][] | Not Started | -Code Quality | [LINT_PASS][] | Done | -Code Quality | [CDC_SETUP][] | Done | -Code Quality | [FPGA_TIMING][] | Not Started | -Code Quality | [CDC_SYNCMACRO][] | Done | -Security | [SEC_CM_IMPLEMENTED][] | Not Started | -Security | [SEC_NON_RESET_FLOPS][] | Not Started | -Security | [SEC_SHADOW_REGS][] | Not Started | -Security | [SEC_RND_CNST][] | Not Started | - -[NEW_FEATURES]: {{<relref "/doc/project/checklist.md#new_features" >}} -[BLOCK_DIAGRAM]: {{<relref "/doc/project/checklist.md#block_diagram" >}} -[DOC_INTERFACE]: {{<relref "/doc/project/checklist.md#doc_interface" >}} -[MISSING_FUNC]: {{<relref "/doc/project/checklist.md#missing_func" >}} -[FEATURE_FROZEN]: {{<relref "/doc/project/checklist.md#feature_frozen" >}} -[FEATURE_COMPLETE]: {{<relref "/doc/project/checklist.md#feature_complete" >}} -[AREA_CHECK]: {{<relref "/doc/project/checklist.md#area_check" >}} -[PORT_FROZEN]: {{<relref "/doc/project/checklist.md#port_frozen" >}} -[ARCHITECTURE_FROZEN]: {{<relref "/doc/project/checklist.md#architecture_frozen" >}} -[REVIEW_TODO]: {{<relref "/doc/project/checklist.md#review_todo" >}} -[STYLE_X]: {{<relref "/doc/project/checklist.md#style_x" >}} -[LINT_PASS]: {{<relref "/doc/project/checklist.md#lint_pass" >}} -[CDC_SETUP]: {{<relref "/doc/project/checklist.md#cdc_setup" >}} -[FPGA_TIMING]: {{<relref "/doc/project/checklist.md#fpga_timing" >}} -[CDC_SYNCMACRO]: {{<relref "/doc/project/checklist.md#cdc_syncmacro" >}} -[SEC_CM_IMPLEMENTED]: {{<relref "/doc/project/checklist.md#sec_cm_implemented" >}} -[SEC_NON_RESET_FLOPS]: {{<relref "/doc/project/checklist.md#sec_non_reset_flops" >}} -[SEC_SHADOW_REGS]: {{<relref "/doc/project/checklist.md#sec_shadow_regs" >}} -[SEC_RND_CNST]: {{<relref "/doc/project/checklist.md#sec_rnd_cnst" >}} - -### D3 - - Type | Item | Resolution | Note/Collaterals ---------------|-------------------------|-------------|------------------ -Documentation | [NEW_FEATURES_D3][] | Not Started | -RTL | [TODO_COMPLETE][] | Not Started | -Code Quality | [LINT_COMPLETE][] | Not Started | -Code Quality | [CDC_COMPLETE][] | Not Started | -Review | [REVIEW_RTL][] | Not Started | -Review | [REVIEW_DELETED_FF][] | Not Started | -Review | [REVIEW_SW_CSR][] | Not Started | -Review | [REVIEW_SW_FATAL_ERR][] | Not Started | -Review | [REVIEW_SW_CHANGE][] | Not Started | -Review | [REVIEW_SW_ERRATA][] | Not Started | -Review | Reviewer(s) | Not Started | -Review | Signoff date | Not Started | - -[NEW_FEATURES_D3]: {{<relref "/doc/project/checklist.md#new_features_d3" >}} -[TODO_COMPLETE]: {{<relref "/doc/project/checklist.md#todo_complete" >}} -[LINT_COMPLETE]: {{<relref "/doc/project/checklist.md#lint_complete" >}} -[CDC_COMPLETE]: {{<relref "/doc/project/checklist.md#cdc_complete" >}} -[REVIEW_RTL]: {{<relref "/doc/project/checklist.md#review_rtl" >}} -[REVIEW_DBG]: {{<relref "/doc/project/checklist.md#review_dbg" >}} -[REVIEW_DELETED_FF]: {{<relref "/doc/project/checklist.md#review_deleted_ff" >}} -[REVIEW_SW_CSR]: {{<relref "/doc/project/checklist.md#review_sw_csr" >}} -[REVIEW_SW_FATAL_ERR]: {{<relref "/doc/project/checklist.md#review_sw_fatal_err" >}} -[REVIEW_SW_CHANGE]: {{<relref "/doc/project/checklist.md#review_sw_change" >}} -[REVIEW_SW_ERRATA]: {{<relref "/doc/project/checklist.md#review_sw_errata" >}} - -## Verification Checklist - -### V1 - - Type | Item | Resolution | Note/Collaterals ---------------|---------------------------------------|-------------|------------------ -Documentation | [DV_DOC_DRAFT_COMPLETED][] | In Progress | -Documentation | [DV_PLAN_COMPLETED][] | In Progress | -Testbench | [TB_TOP_CREATED][] | Done | -Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done | -Testbench | [SIM_TB_ENV_CREATED][] | Done | -Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | N/A | This block uses FPV -Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Not Started | -Testbench | [TB_GEN_AUTOMATED][] | Not Started | -Tests | [SIM_SMOKE_TEST_PASSING][] | Done | -Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | In Progress | FPV CSR tests being developed by @cindychip -Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | Not Started | -Tool Setup | [SIM_ALT_TOOL_SETUP][] | N/A | -Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Done | -Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Not Started | -Regression | [FPV_REGRESSION_SETUP][] | Not Started | -Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Not Started | -Code Quality | [TB_LINT_SETUP][] | Done | -Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Not Started | -Review | [DESIGN_SPEC_REVIEWED][] | Not Started | -Review | [DV_PLAN_REVIEWED][] | Not Started | -Review | [STD_TEST_CATEGORIES_PLANNED][] | Not Started | Exception (?) -Review | [V2_CHECKLIST_SCOPED][] | Not Started | - -[DV_DOC_DRAFT_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_doc_draft_completed" >}} -[DV_PLAN_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_plan_completed" >}} -[TB_TOP_CREATED]: {{<relref "/doc/project/checklist.md#tb_top_created" >}} -[PRELIMINARY_ASSERTION_CHECKS_ADDED]: {{<relref "/doc/project/checklist.md#preliminary_assertion_checks_added" >}} -[SIM_TB_ENV_CREATED]: {{<relref "/doc/project/checklist.md#sim_tb_env_created" >}} -[SIM_RAL_MODEL_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#sim_ral_model_gen_automated" >}} -[CSR_CHECK_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#csr_check_gen_automated" >}} -[TB_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#tb_gen_automated" >}} -[SIM_SMOKE_TEST_PASSING]: {{<relref "/doc/project/checklist.md#sim_smoke_test_passing" >}} -[SIM_CSR_MEM_TEST_SUITE_PASSING]: {{<relref "/doc/project/checklist.md#sim_csr_mem_test_suite_passing" >}} -[FPV_MAIN_ASSERTIONS_PROVEN]: {{<relref "/doc/project/checklist.md#fpv_main_assertions_proven" >}} -[SIM_ALT_TOOL_SETUP]: {{<relref "/doc/project/checklist.md#sim_alt_tool_setup" >}} -[SIM_SMOKE_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#sim_smoke_regression_setup" >}} -[SIM_NIGHTLY_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#sim_nightly_regression_setup" >}} -[FPV_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#fpv_regression_setup" >}} -[SIM_COVERAGE_MODEL_ADDED]: {{<relref "/doc/project/checklist.md#sim_coverage_model_added" >}} -[TB_LINT_SETUP]: {{<relref "/doc/project/checklist.md#tb_lint_setup" >}} -[PRE_VERIFIED_SUB_MODULES_V1]: {{<relref "/doc/project/checklist.md#pre_verified_sub_modules_v1" >}} -[DESIGN_SPEC_REVIEWED]: {{<relref "/doc/project/checklist.md#design_spec_reviewed" >}} -[DV_PLAN_REVIEWED]: {{<relref "/doc/project/checklist.md#dv_plan_reviewed" >}} -[STD_TEST_CATEGORIES_PLANNED]: {{<relref "/doc/project/checklist.md#std_test_categories_planned" >}} -[V2_CHECKLIST_SCOPED]: {{<relref "/doc/project/checklist.md#v2_checklist_scoped" >}} - -### V2 - - Type | Item | Resolution | Note/Collaterals ---------------|-----------------------------------------|-------------|------------------ -Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Not Started | -Documentation | [DV_PLAN_COMPLETED][] | Not Started | -Testbench | [ALL_INTERFACES_EXERCISED][] | Not Started | -Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Not Started | -Testbench | [SIM_TB_ENV_COMPLETED][] | Not Started | -Tests | [SIM_ALL_TESTS_PASSING][] | Not Started | -Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | Not Started | -Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | Not Started | -Tests | [SIM_FW_SIMULATED][] | Not Started | -Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Not Started | -Coverage | [SIM_CODE_COVERAGE_V2][] | Not Started | -Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Not Started | -Coverage | [FPV_CODE_COVERAGE_V2][] | Not Started | -Coverage | [FPV_COI_COVERAGE_V2][] | Not Started | -Code Quality | [TB_LINT_PASS][] | Not Started | -Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Not Started | -Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Not Started | -Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Not Started | -Review | [V3_CHECKLIST_SCOPED][] | Not Started | - -[DESIGN_DELTAS_CAPTURED_V2]: {{<relref "/doc/project/checklist.md#design_deltas_captured_v2" >}} -[DV_PLAN_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_doc_completed" >}} -[ALL_INTERFACES_EXERCISED]: {{<relref "/doc/project/checklist.md#all_interfaces_exercised" >}} -[ALL_ASSERTION_CHECKS_ADDED]: {{<relref "/doc/project/checklist.md#all_assertion_checks_added" >}} -[SIM_TB_ENV_COMPLETED]: {{<relref "/doc/project/checklist.md#sim_tb_env_completed" >}} -[SIM_ALL_TESTS_PASSING]: {{<relref "/doc/project/checklist.md#sim_all_tests_passing" >}} -[FPV_ALL_ASSERTIONS_WRITTEN]: {{<relref "/doc/project/checklist.md#fpv_all_assertions_written" >}} -[FPV_ALL_ASSUMPTIONS_REVIEWED]: {{<relref "/doc/project/checklist.md#fpv_all_assumptions_reviewed" >}} -[SIM_FW_SIMULATED]: {{<relref "/doc/project/checklist.md#sim_fw_simulated" >}} -[SIM_NIGHTLY_REGRESSION_V2]: {{<relref "/doc/project/checklist.md#sim_nightly_regression_v2" >}} -[SIM_CODE_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#sim_code_coverage_v2" >}} -[SIM_FUNCTIONAL_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#sim_functional_coverage_v2" >}} -[FPV_CODE_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#fpv_code_coverage_v2" >}} -[FPV_COI_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#fpv_coi_coverage_v2" >}} -[TB_LINT_PASS]: {{<relref "/doc/project/checklist.md#tb_lint_pass" >}} -[NO_HIGH_PRIORITY_ISSUES_PENDING]: {{<relref "/doc/project/checklist.md#no_high_priority_issues_pending" >}} -[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:{{<relref "/doc/project/checklist.md#all_low_priority_issues_root_caused" >}} -[PRE_VERIFIED_SUB_MODULES_V2]: {{<relref "/doc/project/checklist.md#pre_verified_sub_modules_v2" >}} -[V3_CHECKLIST_SCOPED]: {{<relref "/doc/project/checklist.md#v3_checklist_scoped" >}} - -### V3 - - Type | Item | Resolution | Note/Collaterals ---------------|-----------------------------------|-------------|------------------ -Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | -Testbench | [ALL_TODOS_RESOLVED][] | Not Started | -Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started | -Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started | -Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | -Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | -Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | -Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started | -Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started | -Issues | [NO_ISSUES_PENDING][] | Not Started | -Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | -Code Quality | [TB_LINT_COMPLETE][] | Not Started | -Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | -Review | Reviewer(s) | Not Started | -Review | Signoff date | Not Started | - -[DESIGN_DELTAS_CAPTURED_V3]: {{<relref "/doc/project/checklist.md#design_deltas_captured_v3" >}} -[ALL_TODOS_RESOLVED]: {{<relref "/doc/project/checklist.md#all_todos_resolved" >}} -[X_PROP_ANALYSIS_COMPLETED]: {{<relref "/doc/project/checklist.md#x_prop_analysis_completed" >}} -[FPV_ASSERTIONS_PROVEN_AT_V3]: {{<relref "/doc/project/checklist.md#fpv_assertions_proven_at_v3" >}} -[SIM_NIGHTLY_REGRESSION_AT_V3]: {{<relref "/doc/project/checklist.md#sim_nightly_regression_at_v3" >}} -[SIM_CODE_COVERAGE_AT_100]: {{<relref "/doc/project/checklist.md#sim_code_coverage_at_100" >}} -[SIM_FUNCTIONAL_COVERAGE_AT_100]:{{<relref "/doc/project/checklist.md#sim_functional_coverage_at_100" >}} -[FPV_CODE_COVERAGE_AT_100]: {{<relref "/doc/project/checklist.md#fpv_code_coverage_at_100" >}} -[FPV_COI_COVERAGE_AT_100]: {{<relref "/doc/project/checklist.md#fpv_coi_coverage_at_100" >}} -[NO_ISSUES_PENDING]: {{<relref "/doc/project/checklist.md#no_issues_pending" >}} -[NO_TOOL_WARNINGS_THROWN]: {{<relref "/doc/project/checklist.md#no_tool_warnings_thrown" >}} -[TB_LINT_COMPLETE]: {{<relref "/doc/project/checklist.md#tb_lint_complete" >}} -[PRE_VERIFIED_SUB_MODULES_V3]: {{<relref "/doc/project/checklist.md#pre_verified_sub_modules_v3" >}}
diff --git a/hw/ip/padctrl/doc/dv/_index.md b/hw/ip/padctrl/doc/dv/_index.md deleted file mode 100644 index 16c5067..0000000 --- a/hw/ip/padctrl/doc/dv/_index.md +++ /dev/null
@@ -1,46 +0,0 @@ ---- -title: "PADCTRL DV document" ---- - -## Goals -* **DV**: - * PADCTRL is decided to verify in FPV only - -* **FPV**: - * Verify all the PADCTRL outputs by writing assumptions and assertions with a FPV based testbench - * Verify TileLink device protocol compliance with a FPV based testbench - -## Current status -* [Design & verification stage]({{< relref "hw" >}}) - * [HW development stages]({{< relref "doc/project/development_stages.md" >}}) -* FPV dashboard (link TBD) - -## Design features -For detailed information on PADCTRL design features, please see the -[PADCTRL design specification]({{< relref "hw/ip/padctrl/doc" >}}). - -## Testbench architecture -PADCTRL FPV testbench has been constructed based on the [formal architecture]({{< relref "hw/formal/README.md" >}}). -The PADCTRL testbench consists of two RTL modules: padctrl and padring. - -### Block diagram - - -#### TLUL assertions -* The `../fpv/tb/padctrl_bind.sv` binds the `tlul_assert` [assertions]({{< relref "hw/ip/tlul/doc/TlulProtocolChecker.md" >}}) with padctrl to ensure TileLink interface protocol compliance -* TODO: Plan to implement csr assertions under `../fpv/vip/` to assert the TileLink writes and reads correct CSRs - -#### PADCTRL assertions -* The `../fpv/tb/padctrl_bind_fpv.sv` binds module `padctrl_assert_fpv` with the padctrl RTL. -The assertion file ensures padctrl's outputs (`mio_attr_o` and `dio_attr_o`) under the generic or Xilinx implementation are verified. -* The `../fpv/tb/padctrl_bind_fpv.sv` also binds module `padring_assert_fpv` with the padring RTL. -The assertion file ensures all the padring's outputs are verified. - -##### Symbolic variables -Due to there are large number of muxed and dedicated IOs, the symbolic variable is used to reduce the number of repeated assertions code. -In padctrl_assert_fpv and padring_assert_fpv, we declared two symbolic variables `mio_sel` and `dio_sel` to represent the index for muxed IO and dedicated IO. -Detailed explanation is listed in the [Symbolic Variables]({{< relref "hw/formal/README.md#symbolic-variables" >}}) section. - -## DV plan -{{< testplan "hw/ip/padctrl/data/padctrl_fpv_testplan.hjson" >}} -
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diff --git a/hw/ip/padctrl/fpv/padctrl_fpv.core b/hw/ip/padctrl/fpv/padctrl_fpv.core deleted file mode 100644 index 820a2da..0000000 --- a/hw/ip/padctrl/fpv/padctrl_fpv.core +++ /dev/null
@@ -1,45 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:fpv:padctrl_fpv:0.1" -description: "PADCTRL FPV target" -filesets: - files_formal: - depend: - - lowrisc:ip:tlul - # note: this is an example config which may differ - # from a particular top-level config - - lowrisc:ip:padctrl - - lowrisc:prim:prim_pkg - - lowrisc:fpv:csr_assert_gen - files: - - tb/padctrl_fpv.sv - - tb/padctrl_bind_fpv.sv - - vip/padctrl_assert_fpv.sv - - vip/padring_assert_fpv.sv - file_type: systemVerilogSource - -generate: - csr_assert_gen: - generator: csr_assert_gen - parameters: - spec: ../data/padctrl.hjson - depend: lowrisc:ip:padctrl_reg - -targets: - default: &default_target - # note, this setting is just used - # to generate a file list for jg - default_tool: icarus - filesets: - - files_formal - generate: - - csr_assert_gen - toplevel: padctrl_fpv - - formal: - <<: *default_target - - lint: - <<: *default_target
diff --git a/hw/ip/padctrl/fpv/tb/padctrl_bind_fpv.sv b/hw/ip/padctrl/fpv/tb/padctrl_bind_fpv.sv deleted file mode 100644 index e1e1340..0000000 --- a/hw/ip/padctrl/fpv/tb/padctrl_bind_fpv.sv +++ /dev/null
@@ -1,33 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// - -module padctrl_bind_fpv; - - bind padring padring_assert_fpv i_padring_assert_fpv ( - .* - ); - - bind padctrl padctrl_assert_fpv i_padctrl_assert_fpv ( - .* - ); - - bind padctrl tlul_assert #( - .EndpointType("Device") - ) tlul_assert_device ( - .clk_i, - .rst_ni, - .h2d (tl_i), - .d2h (tl_o) - ); - - bind padctrl padctrl_csr_assert_fpv i_padctrl_csr_assert_fpv ( - .clk_i, - .rst_ni, - .h2d (tl_i), - .d2h (tl_o), - .reg2hw (reg2hw), - .hw2reg (hw2reg) - ); -endmodule : padctrl_bind_fpv
diff --git a/hw/ip/padctrl/fpv/tb/padctrl_fpv.sv b/hw/ip/padctrl/fpv/tb/padctrl_fpv.sv deleted file mode 100644 index 901423e..0000000 --- a/hw/ip/padctrl/fpv/tb/padctrl_fpv.sv +++ /dev/null
@@ -1,53 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Testbench module for padctrl. Intended to use with a formal tool. - -module padctrl_fpv ( - input wire clk_i, - input wire rst_ni, - output logic clk_o, - output logic rst_no, - input tlul_pkg::tl_h2d_t tl_i, - output tlul_pkg::tl_d2h_t tl_o, - inout wire [padctrl_reg_pkg::NMioPads-1:0] mio_pad_io, - inout wire [padctrl_reg_pkg::NDioPads-1:0] dio_pad_io, - input [padctrl_reg_pkg::NMioPads-1:0] mio_out_i, - input [padctrl_reg_pkg::NMioPads-1:0] mio_oe_i, - output logic [padctrl_reg_pkg::NMioPads-1:0] mio_in_o, - input [padctrl_reg_pkg::NDioPads-1:0] dio_out_i, - input [padctrl_reg_pkg::NDioPads-1:0] dio_oe_i, - output logic [padctrl_reg_pkg::NDioPads-1:0] dio_in_o -); - - logic [padctrl_reg_pkg::NMioPads-1:0][padctrl_reg_pkg::AttrDw-1:0] mio_attr; - logic [padctrl_reg_pkg::NDioPads-1:0][padctrl_reg_pkg::AttrDw-1:0] dio_attr; - - padctrl i_padctrl ( - .clk_i , - .rst_ni , - .tl_i , - .tl_o , - .mio_attr_o(mio_attr), - .dio_attr_o(dio_attr) - ); - - padring i_padring ( - .clk_pad_i(clk_i), - .rst_pad_ni(rst_ni), - .clk_o , - .rst_no , - .mio_pad_io, - .dio_pad_io, - .mio_out_i , - .mio_oe_i , - .mio_in_o , - .dio_out_i , - .dio_oe_i , - .dio_in_o , - .mio_attr_i(mio_attr), - .dio_attr_i(dio_attr) - ); - -endmodule : padctrl_fpv
diff --git a/hw/ip/padctrl/fpv/vip/padctrl_assert_fpv.sv b/hw/ip/padctrl/fpv/vip/padctrl_assert_fpv.sv deleted file mode 100644 index 2d2f73b..0000000 --- a/hw/ip/padctrl/fpv/vip/padctrl_assert_fpv.sv +++ /dev/null
@@ -1,94 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Assertions for padring. Intended to use with a formal tool. -// Note that only the mandatory pad attributes are tested here. - - -`include "prim_assert.sv" - -module padctrl_assert_fpv ( - input clk_i, - input rst_ni, - // Bus Interface (device) - input tlul_pkg::tl_h2d_t tl_i, - input tlul_pkg::tl_d2h_t tl_o, - // pad attributes to chip level instance - input logic[padctrl_reg_pkg::NMioPads-1:0] - [padctrl_reg_pkg::AttrDw-1:0] mio_attr_o, - input logic[padctrl_reg_pkg::NDioPads-1:0] - [padctrl_reg_pkg::AttrDw-1:0] dio_attr_o -); - - import prim_pkg::*; - - // symbolic vars for FPV - int unsigned mio_sel; - int unsigned dio_sel; - - ///////////////////////// - // Check muxed IO pads // - ///////////////////////// - - logic [padctrl_reg_pkg::NMioPads-1:0][padctrl_reg_pkg::AttrDw-1:0] mio_warl_masks; - for (genvar k = 0; k < padctrl_reg_pkg::NMioPads; k++) begin : gen_mio_attr - prim_generic_pad_wrapper #( - .AttrDw ( padctrl_reg_pkg::AttrDw ), - .WarlOnly ( 1'b1 ) - ) dut ( - .inout_io ( ), - .in_o ( ), - .ie_i ( 1'b0 ), - .out_i ( 1'b0 ), - .oe_i ( 1'b0 ), - .attr_i ( '0 ), - .warl_o ( mio_warl_masks[k] ) - ); - end - - `ASSUME(NMioRange_M, mio_sel < padctrl_reg_pkg::NMioPads, clk_i, !rst_ni) - `ASSUME(NMioStable_M, ##1 $stable(mio_sel), clk_i, !rst_ni) - - `ASSERT(MioWarl_A, padctrl.reg2hw.mio_pads[mio_sel].qe |=> - (~mio_warl_masks[mio_sel] & mio_attr_o[mio_sel]) == '0) - `ASSERT(MioAttr_A, padctrl.reg2hw.mio_pads[mio_sel].qe |=> - mio_attr_o[mio_sel] == - $past(padctrl.reg2hw.mio_pads[mio_sel].q & mio_warl_masks[mio_sel])) - `ASSERT(MioBackwardCheck_A, ##2 !$stable(mio_attr_o[mio_sel]) |-> - !$stable(padctrl.reg2hw.mio_pads[mio_sel] & mio_warl_masks[mio_sel]) || - $rose($past(padctrl.reg2hw.mio_pads[mio_sel].qe))) - - ///////////////////////////// - // Check dedicated IO pads // - ///////////////////////////// - - logic [padctrl_reg_pkg::NDioPads-1:0][padctrl_reg_pkg::AttrDw-1:0] dio_warl_masks; - for (genvar k = 0; k < padctrl_reg_pkg::NDioPads; k++) begin : gen_dio_attr - prim_generic_pad_wrapper #( - .AttrDw ( padctrl_reg_pkg::AttrDw ), - .WarlOnly ( 1'b1 ) - ) i_prim_generic_pad_wrapper ( - .inout_io ( ), - .in_o ( ), - .ie_i ( 1'b0 ), - .out_i ( 1'b0 ), - .oe_i ( 1'b0 ), - .attr_i ( '0 ), - .warl_o ( dio_warl_masks[k] ) - ); - end - - `ASSUME(NDioRange_M, dio_sel < padctrl_reg_pkg::NDioPads, clk_i, !rst_ni) - `ASSUME(NDioStable_M, ##1 $stable(dio_sel), clk_i, !rst_ni) - - `ASSERT(DioWarl_A, padctrl.reg2hw.mio_pads[mio_sel].qe |=> - (~dio_warl_masks[dio_sel] & dio_attr_o[dio_sel]) == '0) - `ASSERT(DioAttr_A, padctrl.reg2hw.dio_pads[dio_sel].qe |=> - dio_attr_o[dio_sel] == - $past(padctrl.reg2hw.dio_pads[dio_sel].q & dio_warl_masks[dio_sel])) - `ASSERT(DioBackwardCheck_A, ##2 !$stable(dio_attr_o[dio_sel]) |-> - !$stable(padctrl.reg2hw.dio_pads[dio_sel] & dio_warl_masks[dio_sel]) || - $rose($past(padctrl.reg2hw.dio_pads[dio_sel].qe))) - -endmodule : padctrl_assert_fpv
diff --git a/hw/ip/padctrl/fpv/vip/padring_assert_fpv.sv b/hw/ip/padctrl/fpv/vip/padring_assert_fpv.sv deleted file mode 100644 index d266e24..0000000 --- a/hw/ip/padctrl/fpv/vip/padring_assert_fpv.sv +++ /dev/null
@@ -1,116 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Assertions for padring. Intended to use with a formal tool. -// Note that only the mandatory pad attributes are tested here. - -`include "prim_assert.sv" - -module padring_assert_fpv ( - input clk_pad_i, - input rst_pad_ni, - input clk_o, - input rst_no, - input [padctrl_reg_pkg::NMioPads-1:0] mio_pad_io, - input [padctrl_reg_pkg::NDioPads-1:0] dio_pad_io, - input [padctrl_reg_pkg::NMioPads-1:0] mio_out_i, - input [padctrl_reg_pkg::NMioPads-1:0] mio_oe_i, - input [padctrl_reg_pkg::NMioPads-1:0] mio_in_o, - input [padctrl_reg_pkg::NDioPads-1:0] dio_out_i, - input [padctrl_reg_pkg::NDioPads-1:0] dio_oe_i, - input [padctrl_reg_pkg::NDioPads-1:0] dio_in_o, - input [padctrl_reg_pkg::NMioPads-1:0] - [padctrl_reg_pkg::AttrDw-1:0] mio_attr_i, - input [padctrl_reg_pkg::NDioPads-1:0] - [padctrl_reg_pkg::AttrDw-1:0] dio_attr_i -); - - // symbolic vars for FPV - int unsigned mio_sel; - int unsigned dio_sel; - - /////////////////////////////////////////////////////// - // Check main connectivity of infrastructure signals // - /////////////////////////////////////////////////////// - - `ASSERT(ClkConn_A, clk_pad_i === clk_o, clk_pad_i, !rst_pad_ni) - `ASSERT(RstConn_A, rst_pad_ni === rst_no, clk_pad_i, !rst_pad_ni) - - ///////////////////////// - // Check muxed IO pads // - ///////////////////////// - - `ASSUME(NMioRange_M, mio_sel < padctrl_reg_pkg::NMioPads, clk_pad_i, !rst_pad_ni) - `ASSUME(NMioStable_M, ##1 $stable(mio_sel), clk_pad_i, !rst_pad_ni) - - // attribute 0 is the input/output inversion bit - logic mio_output_value; - assign mio_output_value = mio_out_i[mio_sel] ^ mio_attr_i[mio_sel][0]; - - `ASSERT(MioIn_A, mio_in_o[mio_sel] == mio_pad_io[mio_sel] ^ mio_attr_i[mio_sel][0], - clk_pad_i, !rst_pad_ni) - - `ASSERT(MioInBackwardCheck_A, ##1 !$stable(mio_in_o[mio_sel]) |-> - !$stable(mio_pad_io[mio_sel]) || !$stable(mio_attr_i[mio_sel][0]), - clk_pad_i, !rst_pad_ni) - - `ASSERT(MioOutNormal_A, mio_oe_i[mio_sel] && !mio_attr_i[mio_sel][1] |-> - mio_output_value == mio_pad_io[mio_sel], clk_pad_i, !rst_pad_ni) - - `ASSERT(MioOutOd0_A, mio_oe_i[mio_sel] && mio_attr_i[mio_sel][1] && !mio_output_value |-> - mio_pad_io[mio_sel] == 1'b0, clk_pad_i, !rst_pad_ni) - - // TODO: find a better way to test high-Z? - `ASSERT(MioOutOd1_A, mio_oe_i[mio_sel] && mio_attr_i[mio_sel][1] && mio_output_value |-> - mio_pad_io[mio_sel] === 1'b0 || - mio_pad_io[mio_sel] === 1'b1 || - mio_pad_io[mio_sel] === 1'bz || - mio_pad_io[mio_sel] === 1'bx, clk_pad_i, !rst_pad_ni) - - // TODO: find a better way to test high-Z? - `ASSERT(MioOe_A, !mio_oe_i[mio_sel] |-> - mio_pad_io[mio_sel] === 1'b0 || - mio_pad_io[mio_sel] === 1'b1 || - mio_pad_io[mio_sel] === 1'bz || - mio_pad_io[mio_sel] === 1'bx, clk_pad_i, !rst_pad_ni) - - ///////////////////////////// - // Check dedicated IO pads // - ///////////////////////////// - - `ASSUME(NDioRange_M, dio_sel < padctrl_reg_pkg::NDioPads, clk_pad_i, !rst_pad_ni) - `ASSUME(NDioStable_M, ##1 $stable(dio_sel), clk_pad_i, !rst_pad_ni) - - // attribute 0 is the input/output inversion bit - logic dio_output_value; - assign dio_output_value = dio_out_i[dio_sel] ^ dio_attr_i[dio_sel][0]; - - `ASSERT(DioIn_A, dio_in_o[dio_sel] == dio_pad_io[dio_sel] ^ dio_attr_i[dio_sel][0], - clk_pad_i, !rst_pad_ni) - - `ASSERT(DioInBackwardCheck_A, ##1 !$stable(dio_in_o[dio_sel]) |-> - !$stable(dio_pad_io[dio_sel]) || !$stable(dio_attr_i[dio_sel][0]), - clk_pad_i, !rst_pad_ni) - - `ASSERT(DioOutNormal_A, dio_oe_i[dio_sel] && !dio_attr_i[dio_sel][1] |-> - dio_output_value == dio_pad_io[dio_sel], clk_pad_i, !rst_pad_ni) - - `ASSERT(DioOutOd0_A, dio_oe_i[dio_sel] && dio_attr_i[dio_sel][1] && !dio_output_value |-> - dio_pad_io[dio_sel] == 1'b0, clk_pad_i, !rst_pad_ni) - - // TODO: find a better way to test high-Z? - `ASSERT(DioOutOd1_A, dio_oe_i[dio_sel] && dio_attr_i[dio_sel][1] && dio_output_value |-> - dio_pad_io[dio_sel] === 1'b0 || - dio_pad_io[dio_sel] === 1'b1 || - dio_pad_io[dio_sel] === 1'bz || - dio_pad_io[dio_sel] === 1'bx, clk_pad_i, !rst_pad_ni) - - // TODO: find a better way to test high-Z? - `ASSERT(DioOe_A, !dio_oe_i[dio_sel] |-> - dio_pad_io[dio_sel] === 1'b0 || - dio_pad_io[dio_sel] === 1'b1 || - dio_pad_io[dio_sel] === 1'bz || - dio_pad_io[dio_sel] === 1'bx, clk_pad_i, !rst_pad_ni) - -endmodule : padring_assert_fpv
diff --git a/hw/ip/padctrl/lint/padctrl.vlt b/hw/ip/padctrl/lint/padctrl.vlt deleted file mode 100644 index 83d794b..0000000 --- a/hw/ip/padctrl/lint/padctrl.vlt +++ /dev/null
@@ -1,6 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// waiver file for padctrl -
diff --git a/hw/ip/padctrl/lint/padctrl.waiver b/hw/ip/padctrl/lint/padctrl.waiver deleted file mode 100644 index 594dd5e..0000000 --- a/hw/ip/padctrl/lint/padctrl.waiver +++ /dev/null
@@ -1,20 +0,0 @@ -# Copyright lowRISC contributors. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -# -# waiver file for padctrl - -waive -rules HIER_NET_NOT_READ -regexp {Connected net 'attr\_i\[.*\]' at prim\_.*\_pad\_wrapper\.sv:.* is not read from in module.*} - -location {padring.sv} - -comment "Some IO attributes may not be implemented." - -waive -rules NOT_READ -regexp {Signal 'reg_wdata.* is not read from} - -location {padctrl_reg_top.sv} - -comment "Some wdata bits may be unconnected." - -waive -rules HIER_NET_NOT_READ -regexp {Net 'reg_wdata.* is not read from} - -location {padctrl_reg_top.sv} - -comment "Some wdata bits may be unconnected." - -waive -rules MULTI_DRIVEN -location {padring.sv} -regexp {('clk'|'rst_n') has 2 drivers, also driven at padring.sv.*} - -comment "This error is a false positive in this case, since OE is set to 0."
diff --git a/hw/ip/padctrl/padctrl.core b/hw/ip/padctrl/padctrl.core deleted file mode 100644 index a78315a..0000000 --- a/hw/ip/padctrl/padctrl.core +++ /dev/null
@@ -1,37 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:padctrl:0.1" -description: "Pad control IP" - -filesets: - files_rtl: - depend: - - lowrisc:ip:padctrl_reg - - lowrisc:ip:padctrl_component - -parameters: - SYNTHESIS: - datatype: bool - paramtype: vlogdefine - - -targets: - default: &default_target - filesets: - - files_rtl - toplevel: padctrl - - lint: - <<: *default_target - default_tool: verilator - parameters: - - SYNTHESIS=true - tools: - verilator: - mode: lint-only - verilator_options: - - "-Wall" - -
diff --git a/hw/ip/padctrl/padctrl_component.core b/hw/ip/padctrl/padctrl_component.core deleted file mode 100644 index 21f2be6..0000000 --- a/hw/ip/padctrl/padctrl_component.core +++ /dev/null
@@ -1,52 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:padctrl_component:0.1" -description: "Pin control component without the CSRs" - -filesets: - files_rtl: - depend: - - lowrisc:ip:tlul - - lowrisc:prim:all - # padring.sv depends on padctrl_reg_pkg.sv - - "fileset_topgen ? (lowrisc:systems:topgen-reg-only)" - files: - - rtl/jtag_mux.sv - - rtl/padring.sv - - rtl/padctrl.sv - file_type: systemVerilogSource - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - lowrisc:lint:comportable - files: - - lint/padctrl.vlt - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - - lowrisc:lint:comportable - files: - - lint/padctrl.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - - lowrisc:lint:comportable - - -targets: - default: &default_target - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - files_rtl
diff --git a/hw/ip/padctrl/padctrl_reg.core b/hw/ip/padctrl/padctrl_reg.core deleted file mode 100644 index 6453c64..0000000 --- a/hw/ip/padctrl/padctrl_reg.core +++ /dev/null
@@ -1,22 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:padctrl_reg:0.1" -description: "Auto-generated padctrl register sources with default parameters." - -filesets: - files_rtl: - depend: - - lowrisc:tlul:headers - - files: - - rtl/padctrl_reg_pkg.sv - - rtl/padctrl_reg_top.sv - file_type: systemVerilogSource - - -targets: - default: &default_target - filesets: - - files_rtl
diff --git a/hw/ip/padctrl/rtl/padctrl.sv b/hw/ip/padctrl/rtl/padctrl.sv deleted file mode 100644 index 5683741..0000000 --- a/hw/ip/padctrl/rtl/padctrl.sv +++ /dev/null
@@ -1,121 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// This it the padctrl portion that has to be placed into the toplevel. -// It basically just wraps the regfile and outputs the configuration bits -// to be consumed on the chiplevel. -// - -`include "prim_assert.sv" - -module padctrl import padctrl_reg_pkg::*; ( - input clk_i, - input rst_ni, - // Bus Interface (device) - input tlul_pkg::tl_h2d_t tl_i, - output tlul_pkg::tl_d2h_t tl_o, - // pad attributes to chip level instance - output logic[NMioPads-1:0][AttrDw-1:0] mio_attr_o, - output logic[NDioPads-1:0][AttrDw-1:0] dio_attr_o -); - - ///////////// - // Regfile // - ///////////// - - padctrl_reg2hw_t reg2hw; - padctrl_hw2reg_t hw2reg; - - padctrl_reg_top u_reg ( - .clk_i , - .rst_ni , - .tl_i , - .tl_o , - .reg2hw , - .hw2reg , - .devmode_i(1'b1) - ); - - //////////////// - // HWEXT Regs // - //////////////// - - logic [NDioPads-1:0][AttrDw-1:0] dio_attr_q; - logic [NMioPads-1:0][AttrDw-1:0] mio_attr_q; - - always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs - if (!rst_ni) begin - dio_attr_q <= '0; - mio_attr_q <= '0; - end else begin - // dedicated pads - for (int kk = 0; kk < NDioPads; kk++) begin - if (reg2hw.dio_pads[kk].qe) begin - dio_attr_q[kk] <= reg2hw.dio_pads[kk].q; - end - end - // muxed pads - for (int kk = 0; kk < NMioPads; kk++) begin - if (reg2hw.mio_pads[kk].qe) begin - mio_attr_q[kk] <= reg2hw.mio_pads[kk].q; - end - end - end - end - - //////////////////////// - // Connect attributes // - //////////////////////// - - // Note that these are not real pad instances. We only query the supported attributes here - for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_attr - logic [AttrDw-1:0] warl_mask; - - prim_generic_pad_wrapper #( - .AttrDw ( AttrDw ), - .WarlOnly ( 1'b1 ) // this prevents instantiation of pad logic - ) i_prim_generic_pad_wrapper ( - .inout_io ( ), - .in_o ( ), - .ie_i ( 1'b0 ), - .out_i ( 1'b0 ), - .oe_i ( 1'b0 ), - .attr_i ( '0 ), - .warl_o ( warl_mask ) - ); - - assign dio_attr_o[k] = dio_attr_q[k] & warl_mask; - assign hw2reg.dio_pads[k].d = dio_attr_q[k] & warl_mask; - end - - for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_attr - logic [AttrDw-1:0] warl_mask; - - prim_generic_pad_wrapper #( - .AttrDw ( AttrDw ), - .WarlOnly ( 1'b1 ) // this prevents instantiation of pad logic - ) i_prim_generic_pad_wrapper ( - .inout_io ( ), - .in_o ( ), - .ie_i ( 1'b0 ), - .out_i ( 1'b0 ), - .oe_i ( 1'b0 ), - .attr_i ( '0 ), - .warl_o ( warl_mask ) - ); - - assign mio_attr_o[k] = mio_attr_q[k] & warl_mask; - assign hw2reg.mio_pads[k].d = mio_attr_q[k] & warl_mask; - end - - //////////////// - // Assertions // - //////////////// - - `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid) - `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready) - `ASSERT_KNOWN(MioKnownO_A, mio_attr_o) - `ASSERT_KNOWN(DioKnownO_A, dio_attr_o) - -endmodule : padctrl
diff --git a/hw/ip/padctrl/rtl/padctrl_reg_pkg.sv b/hw/ip/padctrl/rtl/padctrl_reg_pkg.sv deleted file mode 100644 index 5f8930e..0000000 --- a/hw/ip/padctrl/rtl/padctrl_reg_pkg.sv +++ /dev/null
@@ -1,94 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Package auto-generated by `reggen` containing data structure - -package padctrl_reg_pkg; - - // Param list - parameter int NDioPads = 4; - parameter int NMioPads = 16; - parameter int AttrDw = 10; - - // Address width within the block - parameter int BlockAw = 6; - - //////////////////////////// - // Typedefs for registers // - //////////////////////////// - typedef struct packed { - logic [9:0] q; - logic qe; - } padctrl_reg2hw_dio_pads_mreg_t; - - typedef struct packed { - logic [9:0] q; - logic qe; - } padctrl_reg2hw_mio_pads_mreg_t; - - - typedef struct packed { - logic [9:0] d; - } padctrl_hw2reg_dio_pads_mreg_t; - - typedef struct packed { - logic [9:0] d; - } padctrl_hw2reg_mio_pads_mreg_t; - - - /////////////////////////////////////// - // Register to internal design logic // - /////////////////////////////////////// - typedef struct packed { - padctrl_reg2hw_dio_pads_mreg_t [3:0] dio_pads; // [219:176] - padctrl_reg2hw_mio_pads_mreg_t [15:0] mio_pads; // [175:0] - } padctrl_reg2hw_t; - - /////////////////////////////////////// - // Internal design logic to register // - /////////////////////////////////////// - typedef struct packed { - padctrl_hw2reg_dio_pads_mreg_t [3:0] dio_pads; // [199:160] - padctrl_hw2reg_mio_pads_mreg_t [15:0] mio_pads; // [159:0] - } padctrl_hw2reg_t; - - // Register Address - parameter logic [BlockAw-1:0] PADCTRL_REGWEN_OFFSET = 6'h 0; - parameter logic [BlockAw-1:0] PADCTRL_DIO_PADS_0_OFFSET = 6'h 4; - parameter logic [BlockAw-1:0] PADCTRL_DIO_PADS_1_OFFSET = 6'h 8; - parameter logic [BlockAw-1:0] PADCTRL_MIO_PADS_0_OFFSET = 6'h c; - parameter logic [BlockAw-1:0] PADCTRL_MIO_PADS_1_OFFSET = 6'h 10; - parameter logic [BlockAw-1:0] PADCTRL_MIO_PADS_2_OFFSET = 6'h 14; - parameter logic [BlockAw-1:0] PADCTRL_MIO_PADS_3_OFFSET = 6'h 18; - parameter logic [BlockAw-1:0] PADCTRL_MIO_PADS_4_OFFSET = 6'h 1c; - parameter logic [BlockAw-1:0] PADCTRL_MIO_PADS_5_OFFSET = 6'h 20; - - - // Register Index - typedef enum int { - PADCTRL_REGWEN, - PADCTRL_DIO_PADS_0, - PADCTRL_DIO_PADS_1, - PADCTRL_MIO_PADS_0, - PADCTRL_MIO_PADS_1, - PADCTRL_MIO_PADS_2, - PADCTRL_MIO_PADS_3, - PADCTRL_MIO_PADS_4, - PADCTRL_MIO_PADS_5 - } padctrl_id_e; - - // Register width information to check illegal writes - parameter logic [3:0] PADCTRL_PERMIT [9] = '{ - 4'b 0001, // index[0] PADCTRL_REGWEN - 4'b 1111, // index[1] PADCTRL_DIO_PADS_0 - 4'b 0011, // index[2] PADCTRL_DIO_PADS_1 - 4'b 1111, // index[3] PADCTRL_MIO_PADS_0 - 4'b 1111, // index[4] PADCTRL_MIO_PADS_1 - 4'b 1111, // index[5] PADCTRL_MIO_PADS_2 - 4'b 1111, // index[6] PADCTRL_MIO_PADS_3 - 4'b 1111, // index[7] PADCTRL_MIO_PADS_4 - 4'b 0011 // index[8] PADCTRL_MIO_PADS_5 - }; -endpackage -
diff --git a/hw/ip/padctrl/rtl/padctrl_reg_top.sv b/hw/ip/padctrl/rtl/padctrl_reg_top.sv deleted file mode 100644 index c6918a9..0000000 --- a/hw/ip/padctrl/rtl/padctrl_reg_top.sv +++ /dev/null
@@ -1,715 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Top module auto-generated by `reggen` - -`include "prim_assert.sv" - -module padctrl_reg_top ( - input clk_i, - input rst_ni, - - // Below Regster interface can be changed - input tlul_pkg::tl_h2d_t tl_i, - output tlul_pkg::tl_d2h_t tl_o, - // To HW - output padctrl_reg_pkg::padctrl_reg2hw_t reg2hw, // Write - input padctrl_reg_pkg::padctrl_hw2reg_t hw2reg, // Read - - // Config - input devmode_i // If 1, explicit error return for unmapped register access -); - - import padctrl_reg_pkg::* ; - - localparam int AW = 6; - localparam int DW = 32; - localparam int DBW = DW/8; // Byte Width - - // register signals - logic reg_we; - logic reg_re; - logic [AW-1:0] reg_addr; - logic [DW-1:0] reg_wdata; - logic [DBW-1:0] reg_be; - logic [DW-1:0] reg_rdata; - logic reg_error; - - logic addrmiss, wr_err; - - logic [DW-1:0] reg_rdata_next; - - tlul_pkg::tl_h2d_t tl_reg_h2d; - tlul_pkg::tl_d2h_t tl_reg_d2h; - - assign tl_reg_h2d = tl_i; - assign tl_o = tl_reg_d2h; - - tlul_adapter_reg #( - .RegAw(AW), - .RegDw(DW) - ) u_reg_if ( - .clk_i, - .rst_ni, - - .tl_i (tl_reg_h2d), - .tl_o (tl_reg_d2h), - - .we_o (reg_we), - .re_o (reg_re), - .addr_o (reg_addr), - .wdata_o (reg_wdata), - .be_o (reg_be), - .rdata_i (reg_rdata), - .error_i (reg_error) - ); - - assign reg_rdata = reg_rdata_next ; - assign reg_error = (devmode_i & addrmiss) | wr_err ; - - // Define SW related signals - // Format: <reg>_<field>_{wd|we|qs} - // or <reg>_{wd|we|qs} if field == 1 or 0 - logic regwen_qs; - logic regwen_wd; - logic regwen_we; - logic [9:0] dio_pads_0_attr_0_qs; - logic [9:0] dio_pads_0_attr_0_wd; - logic dio_pads_0_attr_0_we; - logic dio_pads_0_attr_0_re; - logic [9:0] dio_pads_0_attr_1_qs; - logic [9:0] dio_pads_0_attr_1_wd; - logic dio_pads_0_attr_1_we; - logic dio_pads_0_attr_1_re; - logic [9:0] dio_pads_0_attr_2_qs; - logic [9:0] dio_pads_0_attr_2_wd; - logic dio_pads_0_attr_2_we; - logic dio_pads_0_attr_2_re; - logic [9:0] dio_pads_1_qs; - logic [9:0] dio_pads_1_wd; - logic dio_pads_1_we; - logic dio_pads_1_re; - logic [9:0] mio_pads_0_attr_0_qs; - logic [9:0] mio_pads_0_attr_0_wd; - logic mio_pads_0_attr_0_we; - logic mio_pads_0_attr_0_re; - logic [9:0] mio_pads_0_attr_1_qs; - logic [9:0] mio_pads_0_attr_1_wd; - logic mio_pads_0_attr_1_we; - logic mio_pads_0_attr_1_re; - logic [9:0] mio_pads_0_attr_2_qs; - logic [9:0] mio_pads_0_attr_2_wd; - logic mio_pads_0_attr_2_we; - logic mio_pads_0_attr_2_re; - logic [9:0] mio_pads_1_attr_3_qs; - logic [9:0] mio_pads_1_attr_3_wd; - logic mio_pads_1_attr_3_we; - logic mio_pads_1_attr_3_re; - logic [9:0] mio_pads_1_attr_4_qs; - logic [9:0] mio_pads_1_attr_4_wd; - logic mio_pads_1_attr_4_we; - logic mio_pads_1_attr_4_re; - logic [9:0] mio_pads_1_attr_5_qs; - logic [9:0] mio_pads_1_attr_5_wd; - logic mio_pads_1_attr_5_we; - logic mio_pads_1_attr_5_re; - logic [9:0] mio_pads_2_attr_6_qs; - logic [9:0] mio_pads_2_attr_6_wd; - logic mio_pads_2_attr_6_we; - logic mio_pads_2_attr_6_re; - logic [9:0] mio_pads_2_attr_7_qs; - logic [9:0] mio_pads_2_attr_7_wd; - logic mio_pads_2_attr_7_we; - logic mio_pads_2_attr_7_re; - logic [9:0] mio_pads_2_attr_8_qs; - logic [9:0] mio_pads_2_attr_8_wd; - logic mio_pads_2_attr_8_we; - logic mio_pads_2_attr_8_re; - logic [9:0] mio_pads_3_attr_9_qs; - logic [9:0] mio_pads_3_attr_9_wd; - logic mio_pads_3_attr_9_we; - logic mio_pads_3_attr_9_re; - logic [9:0] mio_pads_3_attr_10_qs; - logic [9:0] mio_pads_3_attr_10_wd; - logic mio_pads_3_attr_10_we; - logic mio_pads_3_attr_10_re; - logic [9:0] mio_pads_3_attr_11_qs; - logic [9:0] mio_pads_3_attr_11_wd; - logic mio_pads_3_attr_11_we; - logic mio_pads_3_attr_11_re; - logic [9:0] mio_pads_4_attr_12_qs; - logic [9:0] mio_pads_4_attr_12_wd; - logic mio_pads_4_attr_12_we; - logic mio_pads_4_attr_12_re; - logic [9:0] mio_pads_4_attr_13_qs; - logic [9:0] mio_pads_4_attr_13_wd; - logic mio_pads_4_attr_13_we; - logic mio_pads_4_attr_13_re; - logic [9:0] mio_pads_4_attr_14_qs; - logic [9:0] mio_pads_4_attr_14_wd; - logic mio_pads_4_attr_14_we; - logic mio_pads_4_attr_14_re; - logic [9:0] mio_pads_5_qs; - logic [9:0] mio_pads_5_wd; - logic mio_pads_5_we; - logic mio_pads_5_re; - - // Register instances - // R[regwen]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_regwen ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (regwen_we), - .wd (regwen_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (regwen_qs) - ); - - - - // Subregister 0 of Multireg dio_pads - // R[dio_pads_0]: V(True) - - // F[attr_0]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_dio_pads_0_attr_0 ( - .re (dio_pads_0_attr_0_re), - // qualified with register enable - .we (dio_pads_0_attr_0_we & regwen_qs), - .wd (dio_pads_0_attr_0_wd), - .d (hw2reg.dio_pads[0].d), - .qre (), - .qe (reg2hw.dio_pads[0].qe), - .q (reg2hw.dio_pads[0].q ), - .qs (dio_pads_0_attr_0_qs) - ); - - - // F[attr_1]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_dio_pads_0_attr_1 ( - .re (dio_pads_0_attr_1_re), - // qualified with register enable - .we (dio_pads_0_attr_1_we & regwen_qs), - .wd (dio_pads_0_attr_1_wd), - .d (hw2reg.dio_pads[1].d), - .qre (), - .qe (reg2hw.dio_pads[1].qe), - .q (reg2hw.dio_pads[1].q ), - .qs (dio_pads_0_attr_1_qs) - ); - - - // F[attr_2]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_dio_pads_0_attr_2 ( - .re (dio_pads_0_attr_2_re), - // qualified with register enable - .we (dio_pads_0_attr_2_we & regwen_qs), - .wd (dio_pads_0_attr_2_wd), - .d (hw2reg.dio_pads[2].d), - .qre (), - .qe (reg2hw.dio_pads[2].qe), - .q (reg2hw.dio_pads[2].q ), - .qs (dio_pads_0_attr_2_qs) - ); - - - // Subregister 3 of Multireg dio_pads - // R[dio_pads_1]: V(True) - - prim_subreg_ext #( - .DW (10) - ) u_dio_pads_1 ( - .re (dio_pads_1_re), - // qualified with register enable - .we (dio_pads_1_we & regwen_qs), - .wd (dio_pads_1_wd), - .d (hw2reg.dio_pads[3].d), - .qre (), - .qe (reg2hw.dio_pads[3].qe), - .q (reg2hw.dio_pads[3].q ), - .qs (dio_pads_1_qs) - ); - - - - // Subregister 0 of Multireg mio_pads - // R[mio_pads_0]: V(True) - - // F[attr_0]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_0_attr_0 ( - .re (mio_pads_0_attr_0_re), - // qualified with register enable - .we (mio_pads_0_attr_0_we & regwen_qs), - .wd (mio_pads_0_attr_0_wd), - .d (hw2reg.mio_pads[0].d), - .qre (), - .qe (reg2hw.mio_pads[0].qe), - .q (reg2hw.mio_pads[0].q ), - .qs (mio_pads_0_attr_0_qs) - ); - - - // F[attr_1]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_0_attr_1 ( - .re (mio_pads_0_attr_1_re), - // qualified with register enable - .we (mio_pads_0_attr_1_we & regwen_qs), - .wd (mio_pads_0_attr_1_wd), - .d (hw2reg.mio_pads[1].d), - .qre (), - .qe (reg2hw.mio_pads[1].qe), - .q (reg2hw.mio_pads[1].q ), - .qs (mio_pads_0_attr_1_qs) - ); - - - // F[attr_2]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_0_attr_2 ( - .re (mio_pads_0_attr_2_re), - // qualified with register enable - .we (mio_pads_0_attr_2_we & regwen_qs), - .wd (mio_pads_0_attr_2_wd), - .d (hw2reg.mio_pads[2].d), - .qre (), - .qe (reg2hw.mio_pads[2].qe), - .q (reg2hw.mio_pads[2].q ), - .qs (mio_pads_0_attr_2_qs) - ); - - - // Subregister 3 of Multireg mio_pads - // R[mio_pads_1]: V(True) - - // F[attr_3]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_1_attr_3 ( - .re (mio_pads_1_attr_3_re), - // qualified with register enable - .we (mio_pads_1_attr_3_we & regwen_qs), - .wd (mio_pads_1_attr_3_wd), - .d (hw2reg.mio_pads[3].d), - .qre (), - .qe (reg2hw.mio_pads[3].qe), - .q (reg2hw.mio_pads[3].q ), - .qs (mio_pads_1_attr_3_qs) - ); - - - // F[attr_4]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_1_attr_4 ( - .re (mio_pads_1_attr_4_re), - // qualified with register enable - .we (mio_pads_1_attr_4_we & regwen_qs), - .wd (mio_pads_1_attr_4_wd), - .d (hw2reg.mio_pads[4].d), - .qre (), - .qe (reg2hw.mio_pads[4].qe), - .q (reg2hw.mio_pads[4].q ), - .qs (mio_pads_1_attr_4_qs) - ); - - - // F[attr_5]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_1_attr_5 ( - .re (mio_pads_1_attr_5_re), - // qualified with register enable - .we (mio_pads_1_attr_5_we & regwen_qs), - .wd (mio_pads_1_attr_5_wd), - .d (hw2reg.mio_pads[5].d), - .qre (), - .qe (reg2hw.mio_pads[5].qe), - .q (reg2hw.mio_pads[5].q ), - .qs (mio_pads_1_attr_5_qs) - ); - - - // Subregister 6 of Multireg mio_pads - // R[mio_pads_2]: V(True) - - // F[attr_6]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_2_attr_6 ( - .re (mio_pads_2_attr_6_re), - // qualified with register enable - .we (mio_pads_2_attr_6_we & regwen_qs), - .wd (mio_pads_2_attr_6_wd), - .d (hw2reg.mio_pads[6].d), - .qre (), - .qe (reg2hw.mio_pads[6].qe), - .q (reg2hw.mio_pads[6].q ), - .qs (mio_pads_2_attr_6_qs) - ); - - - // F[attr_7]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_2_attr_7 ( - .re (mio_pads_2_attr_7_re), - // qualified with register enable - .we (mio_pads_2_attr_7_we & regwen_qs), - .wd (mio_pads_2_attr_7_wd), - .d (hw2reg.mio_pads[7].d), - .qre (), - .qe (reg2hw.mio_pads[7].qe), - .q (reg2hw.mio_pads[7].q ), - .qs (mio_pads_2_attr_7_qs) - ); - - - // F[attr_8]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_2_attr_8 ( - .re (mio_pads_2_attr_8_re), - // qualified with register enable - .we (mio_pads_2_attr_8_we & regwen_qs), - .wd (mio_pads_2_attr_8_wd), - .d (hw2reg.mio_pads[8].d), - .qre (), - .qe (reg2hw.mio_pads[8].qe), - .q (reg2hw.mio_pads[8].q ), - .qs (mio_pads_2_attr_8_qs) - ); - - - // Subregister 9 of Multireg mio_pads - // R[mio_pads_3]: V(True) - - // F[attr_9]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_3_attr_9 ( - .re (mio_pads_3_attr_9_re), - // qualified with register enable - .we (mio_pads_3_attr_9_we & regwen_qs), - .wd (mio_pads_3_attr_9_wd), - .d (hw2reg.mio_pads[9].d), - .qre (), - .qe (reg2hw.mio_pads[9].qe), - .q (reg2hw.mio_pads[9].q ), - .qs (mio_pads_3_attr_9_qs) - ); - - - // F[attr_10]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_3_attr_10 ( - .re (mio_pads_3_attr_10_re), - // qualified with register enable - .we (mio_pads_3_attr_10_we & regwen_qs), - .wd (mio_pads_3_attr_10_wd), - .d (hw2reg.mio_pads[10].d), - .qre (), - .qe (reg2hw.mio_pads[10].qe), - .q (reg2hw.mio_pads[10].q ), - .qs (mio_pads_3_attr_10_qs) - ); - - - // F[attr_11]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_3_attr_11 ( - .re (mio_pads_3_attr_11_re), - // qualified with register enable - .we (mio_pads_3_attr_11_we & regwen_qs), - .wd (mio_pads_3_attr_11_wd), - .d (hw2reg.mio_pads[11].d), - .qre (), - .qe (reg2hw.mio_pads[11].qe), - .q (reg2hw.mio_pads[11].q ), - .qs (mio_pads_3_attr_11_qs) - ); - - - // Subregister 12 of Multireg mio_pads - // R[mio_pads_4]: V(True) - - // F[attr_12]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_4_attr_12 ( - .re (mio_pads_4_attr_12_re), - // qualified with register enable - .we (mio_pads_4_attr_12_we & regwen_qs), - .wd (mio_pads_4_attr_12_wd), - .d (hw2reg.mio_pads[12].d), - .qre (), - .qe (reg2hw.mio_pads[12].qe), - .q (reg2hw.mio_pads[12].q ), - .qs (mio_pads_4_attr_12_qs) - ); - - - // F[attr_13]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_4_attr_13 ( - .re (mio_pads_4_attr_13_re), - // qualified with register enable - .we (mio_pads_4_attr_13_we & regwen_qs), - .wd (mio_pads_4_attr_13_wd), - .d (hw2reg.mio_pads[13].d), - .qre (), - .qe (reg2hw.mio_pads[13].qe), - .q (reg2hw.mio_pads[13].q ), - .qs (mio_pads_4_attr_13_qs) - ); - - - // F[attr_14]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_4_attr_14 ( - .re (mio_pads_4_attr_14_re), - // qualified with register enable - .we (mio_pads_4_attr_14_we & regwen_qs), - .wd (mio_pads_4_attr_14_wd), - .d (hw2reg.mio_pads[14].d), - .qre (), - .qe (reg2hw.mio_pads[14].qe), - .q (reg2hw.mio_pads[14].q ), - .qs (mio_pads_4_attr_14_qs) - ); - - - // Subregister 15 of Multireg mio_pads - // R[mio_pads_5]: V(True) - - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_5 ( - .re (mio_pads_5_re), - // qualified with register enable - .we (mio_pads_5_we & regwen_qs), - .wd (mio_pads_5_wd), - .d (hw2reg.mio_pads[15].d), - .qre (), - .qe (reg2hw.mio_pads[15].qe), - .q (reg2hw.mio_pads[15].q ), - .qs (mio_pads_5_qs) - ); - - - - - logic [8:0] addr_hit; - always_comb begin - addr_hit = '0; - addr_hit[0] = (reg_addr == PADCTRL_REGWEN_OFFSET); - addr_hit[1] = (reg_addr == PADCTRL_DIO_PADS_0_OFFSET); - addr_hit[2] = (reg_addr == PADCTRL_DIO_PADS_1_OFFSET); - addr_hit[3] = (reg_addr == PADCTRL_MIO_PADS_0_OFFSET); - addr_hit[4] = (reg_addr == PADCTRL_MIO_PADS_1_OFFSET); - addr_hit[5] = (reg_addr == PADCTRL_MIO_PADS_2_OFFSET); - addr_hit[6] = (reg_addr == PADCTRL_MIO_PADS_3_OFFSET); - addr_hit[7] = (reg_addr == PADCTRL_MIO_PADS_4_OFFSET); - addr_hit[8] = (reg_addr == PADCTRL_MIO_PADS_5_OFFSET); - end - - assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; - - // Check sub-word write is permitted - always_comb begin - wr_err = 1'b0; - if (addr_hit[0] && reg_we && (PADCTRL_PERMIT[0] != (PADCTRL_PERMIT[0] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[1] && reg_we && (PADCTRL_PERMIT[1] != (PADCTRL_PERMIT[1] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[2] && reg_we && (PADCTRL_PERMIT[2] != (PADCTRL_PERMIT[2] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[3] && reg_we && (PADCTRL_PERMIT[3] != (PADCTRL_PERMIT[3] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[4] && reg_we && (PADCTRL_PERMIT[4] != (PADCTRL_PERMIT[4] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[5] && reg_we && (PADCTRL_PERMIT[5] != (PADCTRL_PERMIT[5] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[6] && reg_we && (PADCTRL_PERMIT[6] != (PADCTRL_PERMIT[6] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[7] && reg_we && (PADCTRL_PERMIT[7] != (PADCTRL_PERMIT[7] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[8] && reg_we && (PADCTRL_PERMIT[8] != (PADCTRL_PERMIT[8] & reg_be))) wr_err = 1'b1 ; - end - - assign regwen_we = addr_hit[0] & reg_we & ~wr_err; - assign regwen_wd = reg_wdata[0]; - - assign dio_pads_0_attr_0_we = addr_hit[1] & reg_we & ~wr_err; - assign dio_pads_0_attr_0_wd = reg_wdata[9:0]; - assign dio_pads_0_attr_0_re = addr_hit[1] && reg_re; - - assign dio_pads_0_attr_1_we = addr_hit[1] & reg_we & ~wr_err; - assign dio_pads_0_attr_1_wd = reg_wdata[19:10]; - assign dio_pads_0_attr_1_re = addr_hit[1] && reg_re; - - assign dio_pads_0_attr_2_we = addr_hit[1] & reg_we & ~wr_err; - assign dio_pads_0_attr_2_wd = reg_wdata[29:20]; - assign dio_pads_0_attr_2_re = addr_hit[1] && reg_re; - - assign dio_pads_1_we = addr_hit[2] & reg_we & ~wr_err; - assign dio_pads_1_wd = reg_wdata[9:0]; - assign dio_pads_1_re = addr_hit[2] && reg_re; - - assign mio_pads_0_attr_0_we = addr_hit[3] & reg_we & ~wr_err; - assign mio_pads_0_attr_0_wd = reg_wdata[9:0]; - assign mio_pads_0_attr_0_re = addr_hit[3] && reg_re; - - assign mio_pads_0_attr_1_we = addr_hit[3] & reg_we & ~wr_err; - assign mio_pads_0_attr_1_wd = reg_wdata[19:10]; - assign mio_pads_0_attr_1_re = addr_hit[3] && reg_re; - - assign mio_pads_0_attr_2_we = addr_hit[3] & reg_we & ~wr_err; - assign mio_pads_0_attr_2_wd = reg_wdata[29:20]; - assign mio_pads_0_attr_2_re = addr_hit[3] && reg_re; - - assign mio_pads_1_attr_3_we = addr_hit[4] & reg_we & ~wr_err; - assign mio_pads_1_attr_3_wd = reg_wdata[9:0]; - assign mio_pads_1_attr_3_re = addr_hit[4] && reg_re; - - assign mio_pads_1_attr_4_we = addr_hit[4] & reg_we & ~wr_err; - assign mio_pads_1_attr_4_wd = reg_wdata[19:10]; - assign mio_pads_1_attr_4_re = addr_hit[4] && reg_re; - - assign mio_pads_1_attr_5_we = addr_hit[4] & reg_we & ~wr_err; - assign mio_pads_1_attr_5_wd = reg_wdata[29:20]; - assign mio_pads_1_attr_5_re = addr_hit[4] && reg_re; - - assign mio_pads_2_attr_6_we = addr_hit[5] & reg_we & ~wr_err; - assign mio_pads_2_attr_6_wd = reg_wdata[9:0]; - assign mio_pads_2_attr_6_re = addr_hit[5] && reg_re; - - assign mio_pads_2_attr_7_we = addr_hit[5] & reg_we & ~wr_err; - assign mio_pads_2_attr_7_wd = reg_wdata[19:10]; - assign mio_pads_2_attr_7_re = addr_hit[5] && reg_re; - - assign mio_pads_2_attr_8_we = addr_hit[5] & reg_we & ~wr_err; - assign mio_pads_2_attr_8_wd = reg_wdata[29:20]; - assign mio_pads_2_attr_8_re = addr_hit[5] && reg_re; - - assign mio_pads_3_attr_9_we = addr_hit[6] & reg_we & ~wr_err; - assign mio_pads_3_attr_9_wd = reg_wdata[9:0]; - assign mio_pads_3_attr_9_re = addr_hit[6] && reg_re; - - assign mio_pads_3_attr_10_we = addr_hit[6] & reg_we & ~wr_err; - assign mio_pads_3_attr_10_wd = reg_wdata[19:10]; - assign mio_pads_3_attr_10_re = addr_hit[6] && reg_re; - - assign mio_pads_3_attr_11_we = addr_hit[6] & reg_we & ~wr_err; - assign mio_pads_3_attr_11_wd = reg_wdata[29:20]; - assign mio_pads_3_attr_11_re = addr_hit[6] && reg_re; - - assign mio_pads_4_attr_12_we = addr_hit[7] & reg_we & ~wr_err; - assign mio_pads_4_attr_12_wd = reg_wdata[9:0]; - assign mio_pads_4_attr_12_re = addr_hit[7] && reg_re; - - assign mio_pads_4_attr_13_we = addr_hit[7] & reg_we & ~wr_err; - assign mio_pads_4_attr_13_wd = reg_wdata[19:10]; - assign mio_pads_4_attr_13_re = addr_hit[7] && reg_re; - - assign mio_pads_4_attr_14_we = addr_hit[7] & reg_we & ~wr_err; - assign mio_pads_4_attr_14_wd = reg_wdata[29:20]; - assign mio_pads_4_attr_14_re = addr_hit[7] && reg_re; - - assign mio_pads_5_we = addr_hit[8] & reg_we & ~wr_err; - assign mio_pads_5_wd = reg_wdata[9:0]; - assign mio_pads_5_re = addr_hit[8] && reg_re; - - // Read data return - always_comb begin - reg_rdata_next = '0; - unique case (1'b1) - addr_hit[0]: begin - reg_rdata_next[0] = regwen_qs; - end - - addr_hit[1]: begin - reg_rdata_next[9:0] = dio_pads_0_attr_0_qs; - reg_rdata_next[19:10] = dio_pads_0_attr_1_qs; - reg_rdata_next[29:20] = dio_pads_0_attr_2_qs; - end - - addr_hit[2]: begin - reg_rdata_next[9:0] = dio_pads_1_qs; - end - - addr_hit[3]: begin - reg_rdata_next[9:0] = mio_pads_0_attr_0_qs; - reg_rdata_next[19:10] = mio_pads_0_attr_1_qs; - reg_rdata_next[29:20] = mio_pads_0_attr_2_qs; - end - - addr_hit[4]: begin - reg_rdata_next[9:0] = mio_pads_1_attr_3_qs; - reg_rdata_next[19:10] = mio_pads_1_attr_4_qs; - reg_rdata_next[29:20] = mio_pads_1_attr_5_qs; - end - - addr_hit[5]: begin - reg_rdata_next[9:0] = mio_pads_2_attr_6_qs; - reg_rdata_next[19:10] = mio_pads_2_attr_7_qs; - reg_rdata_next[29:20] = mio_pads_2_attr_8_qs; - end - - addr_hit[6]: begin - reg_rdata_next[9:0] = mio_pads_3_attr_9_qs; - reg_rdata_next[19:10] = mio_pads_3_attr_10_qs; - reg_rdata_next[29:20] = mio_pads_3_attr_11_qs; - end - - addr_hit[7]: begin - reg_rdata_next[9:0] = mio_pads_4_attr_12_qs; - reg_rdata_next[19:10] = mio_pads_4_attr_13_qs; - reg_rdata_next[29:20] = mio_pads_4_attr_14_qs; - end - - addr_hit[8]: begin - reg_rdata_next[9:0] = mio_pads_5_qs; - end - - default: begin - reg_rdata_next = '1; - end - endcase - end - - // Assertions for Register Interface - `ASSERT_PULSE(wePulse, reg_we) - `ASSERT_PULSE(rePulse, reg_re) - - `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid) - - `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) - - // this is formulated as an assumption such that the FPV testbenches do disprove this - // property by mistake - `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0) - -endmodule
diff --git a/hw/ip/padctrl/util/reg_padctrl.py b/hw/ip/padctrl/util/reg_padctrl.py deleted file mode 100755 index c15b520..0000000 --- a/hw/ip/padctrl/util/reg_padctrl.py +++ /dev/null
@@ -1,52 +0,0 @@ -#!/usr/bin/env python3 -# Copyright lowRISC contributors. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -r"""Convert mako template to Hjson register description -""" -import argparse -import sys -from io import StringIO - -from mako.template import Template - - -def main(): - parser = argparse.ArgumentParser(prog="reg_padctrl") - parser.add_argument('input', - nargs='?', - metavar='file', - type=argparse.FileType('r'), - default=sys.stdin, - help='input template file') - parser.add_argument('--n_dio_pads', - type=int, - help='Number of dedicated IO pads', - default = 4) - parser.add_argument('--n_mio_pads', - type=int, - help='Number of muxed IO pads', - default = 16) - parser.add_argument('--attr_dw', - type=int, - help='Pad attribute data width', - default = 10) - - args = parser.parse_args() - - # Determine output: if stdin then stdout if not then ?? - out = StringIO() - - reg_tpl = Template(args.input.read()) - out.write( - reg_tpl.render(n_dio_pads=args.n_dio_pads, - n_mio_pads=args.n_mio_pads, - attr_dw=args.attr_dw)) - - print(out.getvalue()) - - out.close() - - -if __name__ == "__main__": - main()
diff --git a/hw/ip/pinmux/data/pinmux.hjson b/hw/ip/pinmux/data/pinmux.hjson index e1c85e2..334d565 100644 --- a/hw/ip/pinmux/data/pinmux.hjson +++ b/hw/ip/pinmux/data/pinmux.hjson
@@ -2,18 +2,6 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // -# PINMUX register template -# -# Parameter (given by Python tool) -# - n_mio_periph_in: Number of muxed peripheral inputs -# - n_mio_periph_out: Number of muxed peripheral outputs -# - n_mio_pads: Number of muxed IO pads -# - n_dio_periph_in: Number of dedicated peripheral inputs -# - n_dio_periph_out: Number of dedicated peripheral outputs -# - n_dio_pads: Number of dedicated IO pads -# - n_wkup_detect: Number of wakeup condition detectors -# - wkup_cnt_width: Width of wakeup counters -# { name: "PINMUX", clock_primary: "clk_i", @@ -121,6 +109,12 @@ ] param_list: [ + { name: "AttrDw", + desc: "Pad attribute data width", + type: "int", + default: "10", + local: "true" + }, { name: "NMioPeriphIn", desc: "Number of muxed peripheral inputs", type: "int", @@ -196,30 +190,6 @@ // TODO: Enable these once supported by topgen and the C header generation script. // These parameters are currently located in pinmux_pkg.sv - // // If a bit is set to 1 in this vector, this MIO activates low power - // // behavior when going to sleep. - // { name: "MioPeriphHasSleepMode", - // desc: ''' - // Indicates whether a MIO channel activates low power behavior - // when going to sleep. - // ''' - // type: "logic [NMioPeriphOut-1:0]", - // // TODO: need to generate this via topgen - // default: "'1", - // local: "true" - // }, - // // If a bit is set to 1 in this vector, this DIO activates low power - // // behavior when going to sleep. - // { name: "DioPeriphHasSleepMode", - // desc: ''' - // Indicates whether a DIO channel activates low power behavior - // when going to sleep. - // ''', - // type: "logic [NDioPads-1:0]", - // // TODO: need to generate this via topgen - // default: "'1", - // local: "true" - // }, // // If a bit is set to 1 in this vector, wakeup detectors are connected // // to this DIO. // { name: "DioPeriphHasWkup", @@ -231,7 +201,9 @@ // }, ], registers: [ -# inputs +////////////////////////// +// MIO Inputs // +////////////////////////// { multireg: { name: "MIO_PERIPH_INSEL_REGWEN", desc: "Register write enable for MIO peripheral input selects.", count: "NMioPeriphIn", @@ -273,7 +245,10 @@ ] } }, -# outputs + +////////////////////////// +// MIO Outputs // +////////////////////////// { multireg: { name: "MIO_OUTSEL_REGWEN", desc: "Register write enable for MIO output selects.", count: "NMioPads", @@ -318,20 +293,23 @@ tags: ["excl:CsrNonInitTests:CsrExclWrite"] } }, -# sleep behavior of MIO peripheral outputs - { multireg: { name: "MIO_OUT_SLEEP_REGWEN", - desc: "Register write enable for MIO sleep value configuration.", + +////////////////////////// +// MIO PAD attributes // +////////////////////////// + { multireg: { name: "MIO_PAD_ATTR_REGWEN", + desc: "Register write enable for MIO PAD attributes.", count: "NMioPads", compact: "false", swaccess: "rw0c", hwaccess: "none", - cname: "MIO_OUT_SLEEP_VAL", + cname: "MIO_PAD", fields: [ { bits: "0", name: "EN", desc: ''' Register write enable bit. - If this is cleared to 0, the corresponding MIO_OUT_SLEEP_VAL + If this is cleared to 0, the corresponding !!MIO_PAD_ATTR is not writable anymore. ''', resval: "1", @@ -339,66 +317,61 @@ ] } }, -# TODO: add individual sleep disable bits - { multireg: { name: "MIO_OUT_SLEEP_VAL", - desc: '''Defines sleep behavior of muxed output or inout. Note that - the MIO output will only switch into sleep mode if the the corresponding - !!MIO_OUTSEL is either set to 0-2, or if !!MIO_OUTSEL selects a peripheral - output that can go into sleep. If an always on peripheral is selected with - !!MIO_OUTSEL, the !!MIO_OUT_SLEEP_VAL configuration has no effect. - ''' + { multireg: { name: "MIO_PAD_ATTR", + desc: ''' + Muxed pad attributes. + This register has WARL behavior since not each pad type may support + all attributes. + ''', count: "NMioPads", compact: "false", swaccess: "rw", - hwaccess: "hro", - regwen: "MIO_OUT_SLEEP_REGWEN", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + regwen: "MIO_PAD_ATTR_REGWEN", regwen_multi: "true", - cname: "OUT", + cname: "MIO_PAD", fields: [ - { bits: "1:0", - name: "OUT", - resval: 2, - desc:"Value to drive in deep sleep." - enum: [ - { value: "0", - name: "Tie-Low", - desc: "The pin is driven actively to zero in deep sleep mode." - }, - { value: "1", - name: "Tie-High", - desc: "The pin is driven actively to one in deep sleep mode." - }, - { value: "2", - name: "High-Z", - desc: ''' - The pin is left undriven in deep sleep mode. Note that the actual - driving behavior during deep sleep will then depend on the pull-up/-down - configuration of padctrl. - ''' - }, - { value: "3", - name: "Keep", - desc: "Keep last driven value (including high-Z)." - }, - ] + { bits: "9:0", + name: "ATTR", + desc: '''Bit 0: input/output inversion, + Bit 1: Virtual open drain enable. + Bit 2: Pull enable. + Bit 3: Pull select (0: pull down, 1: pull up). + Bit 4: Keeper enable. + Bit 5: Schmitt trigger enable. + Bit 6: Slew rate (0: slow, 1: fast). + Bit 7/8: Drive strength (00: weakest, 11: strongest). + Bit 9: Reserved. + ''' + resval: 0 } - ] + ], + // these CSRs have WARL behavior and may not + // read back the same value that was written to them. + // further, they have hardware side effects since they drive the + // pad attributes, and hence no random data should be written to them. + tags: ["excl:CsrAllTests:CsrExclWrite"] } }, -# sleep behavior of DIO peripheral outputs - { multireg: { name: "DIO_OUT_SLEEP_REGWEN", - desc: "Register write enable for DIO sleep value configuration.", + +////////////////////////// +// DIO PAD attributes // +////////////////////////// + { multireg: { name: "DIO_PAD_ATTR_REGWEN", + desc: "Register write enable for DIO PAD attributes.", count: "NDioPads", compact: "false", swaccess: "rw0c", hwaccess: "none", - cname: "DIO_OUT_SLEEP_VAL", + cname: "DIO_PAD", fields: [ { bits: "0", name: "EN", desc: ''' Register write enable bit. - If this is cleared to 0, the corresponding DIO_OUT_SLEEP_VAL + If this is cleared to 0, the corresponding !!DIO_PAD_ATTR is not writable anymore. ''', resval: "1", @@ -406,43 +379,147 @@ ] } }, -# TODO: add individual sleep disable bits - { multireg: { name: "DIO_OUT_SLEEP_VAL", - desc: '''Defines sleep behavior of dedicated output or inout. Note this - register has WARL behavior since the sleep value settings are - meaningless for always-on and input-only DIOs. For these DIOs, - this register always reads 0. - ''' + { multireg: { name: "DIO_PAD_ATTR", + desc: ''' + Dedicated pad attributes. + This register has WARL behavior since not each pad type may support + all attributes. + ''', count: "NDioPads", compact: "false", swaccess: "rw", hwaccess: "hrw", hwext: "true", hwqe: "true", - regwen: "DIO_OUT_SLEEP_REGWEN", + regwen: "DIO_PAD_ATTR_REGWEN", + regwen_multi: "true", + cname: "DIO_PAD", + fields: [ + { bits: "9:0", + name: "ATTR", + desc: '''Bit 0: input/output inversion, + Bit 1: Virtual open drain enable. + Bit 2: Pull enable. + Bit 3: Pull select (0: pull down, 1: pull up). + Bit 4: Keeper enable. + Bit 5: Schmitt trigger enable. + Bit 6: Slew rate (0: slow, 1: fast). + Bit 7/8: Drive strength (00: weakest, 11: strongest). + Bit 9: Reserved. + ''' + resval: 0 + } + ], + // these CSRs have WARL behavior and may not + // read back the same value that was written to them. + // further, they have hardware side effects since they drive the + // pad attributes, and hence no random data should be written to them. + tags: ["excl:CsrAllTests:CsrExclWrite"] + } + }, + +////////////////////////// +// MIO PAD sleep mode // +////////////////////////// + { multireg: { name: "MIO_PAD_SLEEP_STATUS", + desc: "Register indicating whether the corresponding pad is in sleep mode.", + count: "NMioPads", + swaccess: "rw0c", + hwaccess: "hrw", + cname: "MIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + This register is set to 1 if the deep sleep mode of the corresponding + pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. + The sleep mode of the corresponding pad will remain active until SW + clears this bit. + ''', + resval: "0", + } + ] + } + }, + { multireg: { name: "MIO_PAD_SLEEP_REGWEN", + desc: "Register write enable for MIO sleep value configuration.", + count: "NMioPads", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "MIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding !!MIO_OUT_SLEEP_MODE + is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "MIO_PAD_SLEEP_EN", + desc: '''Enables the sleep mode of the corresponding muxed pad. + ''' + count: "NMioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "MIO_PAD_SLEEP_REGWEN", regwen_multi: "true", cname: "OUT", fields: [ - { bits: "1:0", - name: "OUT", + { bits: "0", + name: "EN", + resval: 0, + desc: ''' + Deep sleep mode enable. + If this bit is set to 1 the corresponding pad will enable the sleep behavior + specified in !!MIO_PAD_SLEEP_MODE upon deep sleep entry, and the corresponding bit + in !!MIO_PAD_SLEEP_STATUS will be set to 1. + The pad remains in deep sleep mode until the corresponding bit in + !!MIO_PAD_SLEEP_STATUS is cleared by SW. + Note that if an always on peripheral is connected to a specific MIO pad, + the corresponding !!MIO_PAD_SLEEP_EN bit should be set to 0. + ''' + } + ] + } + }, + { multireg: { name: "MIO_PAD_SLEEP_MODE", + desc: '''Defines sleep behavior of the corresponding muxed pad. + ''' + count: "NMioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "MIO_PAD_SLEEP_REGWEN", + regwen_multi: "true", + cname: "OUT", + fields: [ + { bits: "1:0", + name: "OUT", resval: 2, - desc:"Value to drive in deep sleep." + desc: "Value to drive in deep sleep." enum: [ { value: "0", name: "Tie-Low", - desc: "The pin is driven actively to zero in deep sleep mode." + desc: "The pad is driven actively to zero in deep sleep mode." }, { value: "1", name: "Tie-High", - desc: "The pin is driven actively to one in deep sleep mode." + desc: "The pad is driven actively to one in deep sleep mode." }, { value: "2", name: "High-Z", desc: ''' - The pin is left undriven in deep sleep mode. Note that the actual - driving behavior during deep sleep will then depend on the pull-up/-down - configuration of padctrl. - ''' + The pad is left undriven in deep sleep mode. Note that the actual + driving behavior during deep sleep will then depend on the pull-up/-down + configuration of in !!MIO_PAD_ATTR. + ''' }, { value: "3", name: "Keep", @@ -451,12 +528,123 @@ ] } ] - // these CSRs have WARL behavior and may not - // read back the same value that was written to them. - tags: ["excl:CsrAllTests:CsrExclWriteCheck"] } }, -# wakeup detector enables +////////////////////////// +// DIO PAD sleep mode // +////////////////////////// + { multireg: { name: "DIO_PAD_SLEEP_STATUS", + desc: "Register indicating whether the corresponding pad is in sleep mode.", + count: "NDioPads", + swaccess: "rw0c", + hwaccess: "hrw", + cname: "DIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + This register is set to 1 if the deep sleep mode of the corresponding + pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. + The sleep mode of the corresponding pad will remain active until SW + clears this bit. + ''', + resval: "0", + } + ] + } + }, + { multireg: { name: "DIO_PAD_SLEEP_REGWEN", + desc: "Register write enable for DIO sleep value configuration.", + count: "NDioPads", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "DIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding !!DIO_PAD_SLEEP_MODE + is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "DIO_PAD_SLEEP_EN", + desc: '''Enables the sleep mode of the corresponding dedicated pad. + ''' + count: "NDioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "DIO_PAD_SLEEP_REGWEN", + regwen_multi: "true", + cname: "OUT", + fields: [ + { bits: "0", + name: "EN", + resval: 0, + desc: ''' + Deep sleep mode enable. + If this bit is set to 1 the corresponding pad will enable the sleep behavior + specified in !!DIO_PAD_SLEEP_MODE upon deep sleep entry, and the corresponding bit + in !!DIO_PAD_SLEEP_STATUS will be set to 1. + The pad remains in deep sleep mode until the corresponding bit in + !!DIO_PAD_SLEEP_STATUS is cleared by SW. + Note that if an always on peripheral is connected to a specific DIO pad, + the corresponding !!DIO_PAD_SLEEP_EN bit should be set to 0. + ''' + } + ] + } + }, + { multireg: { name: "DIO_PAD_SLEEP_MODE", + desc: '''Defines sleep behavior of the corresponding dedicated pad. + ''' + count: "NDioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "DIO_PAD_SLEEP_REGWEN", + regwen_multi: "true", + cname: "OUT", + fields: [ + { bits: "1:0", + name: "OUT", + resval: 2, + desc: "Value to drive in deep sleep." + enum: [ + { value: "0", + name: "Tie-Low", + desc: "The pad is driven actively to zero in deep sleep mode." + }, + { value: "1", + name: "Tie-High", + desc: "The pad is driven actively to one in deep sleep mode." + }, + { value: "2", + name: "High-Z", + desc: ''' + The pad is left undriven in deep sleep mode. Note that the actual + driving behavior during deep sleep will then depend on the pull-up/-down + configuration of in !!DIO_PAD_ATTR. + ''' + }, + { value: "3", + name: "Keep", + desc: "Keep last driven value (including high-Z)." + }, + ] + } + ] + } + }, +//////////////////////// +// Wakeup detectors // +//////////////////////// { multireg: { name: "WKUP_DETECTOR_REGWEN", desc: "Register write enable for wakeup detectors.", count: "NWkupDetect", @@ -500,7 +688,7 @@ } }, -# wakeup detector config + # wakeup detector config { multireg: { name: "WKUP_DETECTOR", desc: "Configuration of wakeup condition detectors." count: "NWkupDetect", @@ -567,7 +755,6 @@ } }, -# wakeup detector count thresholds { multireg: { name: "WKUP_DETECTOR_CNT_TH", desc: "Counter thresholds for wakeup condition detectors." count: "NWkupDetect", @@ -589,7 +776,6 @@ } }, -# wakeup detector pad selectors { multireg: { name: "WKUP_DETECTOR_PADSEL", desc: "Pad selects for pad wakeup condition detectors." count: "NWkupDetect", @@ -613,7 +799,6 @@ } }, -# wakeup detector cause regs { multireg: { name: "WKUP_CAUSE", desc: "Cause registers for wakeup detectors." count: "NWkupDetect",
diff --git a/hw/ip/pinmux/data/pinmux.hjson.tpl b/hw/ip/pinmux/data/pinmux.hjson.tpl index 2d9186f..56252d5 100644 --- a/hw/ip/pinmux/data/pinmux.hjson.tpl +++ b/hw/ip/pinmux/data/pinmux.hjson.tpl
@@ -13,6 +13,7 @@ ## - n_dio_pads: Number of dedicated IO pads ## - n_wkup_detect: Number of wakeup condition detectors ## - wkup_cnt_width: Width of wakeup counters +## - attr_dw: Width of wakeup counters { name: "PINMUX", clock_primary: "clk_i", @@ -120,6 +121,12 @@ ] param_list: [ + { name: "AttrDw", + desc: "Pad attribute data width", + type: "int", + default: "${attr_dw}", + local: "true" + }, { name: "NMioPeriphIn", desc: "Number of muxed peripheral inputs", type: "int", @@ -300,6 +307,130 @@ }, ////////////////////////// +// MIO PAD attributes // +////////////////////////// + { multireg: { name: "MIO_PAD_ATTR_REGWEN", + desc: "Register write enable for MIO PAD attributes.", + count: "NMioPads", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "MIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding !!MIO_PAD_ATTR + is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "MIO_PAD_ATTR", + desc: ''' + Muxed pad attributes. + This register has WARL behavior since not each pad type may support + all attributes. + ''', + count: "NMioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + regwen: "MIO_PAD_ATTR_REGWEN", + regwen_multi: "true", + cname: "MIO_PAD", + fields: [ + { bits: "9:0", + name: "ATTR", + desc: '''Bit 0: input/output inversion, + Bit 1: Virtual open drain enable. + Bit 2: Pull enable. + Bit 3: Pull select (0: pull down, 1: pull up). + Bit 4: Keeper enable. + Bit 5: Schmitt trigger enable. + Bit 6: Slew rate (0: slow, 1: fast). + Bit 7/8: Drive strength (00: weakest, 11: strongest). + Bit 9: Reserved. + ''' + resval: 0 + } + ], + // these CSRs have WARL behavior and may not + // read back the same value that was written to them. + // further, they have hardware side effects since they drive the + // pad attributes, and hence no random data should be written to them. + tags: ["excl:CsrAllTests:CsrExclWrite"] + } + }, + +////////////////////////// +// DIO PAD attributes // +////////////////////////// + { multireg: { name: "DIO_PAD_ATTR_REGWEN", + desc: "Register write enable for DIO PAD attributes.", + count: "NDioPads", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "DIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding !!DIO_PAD_ATTR + is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "DIO_PAD_ATTR", + desc: ''' + Dedicated pad attributes. + This register has WARL behavior since not each pad type may support + all attributes. + ''', + count: "NDioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + regwen: "DIO_PAD_ATTR_REGWEN", + regwen_multi: "true", + cname: "DIO_PAD", + fields: [ + { bits: "9:0", + name: "ATTR", + desc: '''Bit 0: input/output inversion, + Bit 1: Virtual open drain enable. + Bit 2: Pull enable. + Bit 3: Pull select (0: pull down, 1: pull up). + Bit 4: Keeper enable. + Bit 5: Schmitt trigger enable. + Bit 6: Slew rate (0: slow, 1: fast). + Bit 7/8: Drive strength (00: weakest, 11: strongest). + Bit 9: Reserved. + ''' + resval: 0 + } + ], + // these CSRs have WARL behavior and may not + // read back the same value that was written to them. + // further, they have hardware side effects since they drive the + // pad attributes, and hence no random data should be written to them. + tags: ["excl:CsrAllTests:CsrExclWrite"] + } + }, + +////////////////////////// // MIO PAD sleep mode // ////////////////////////// { multireg: { name: "MIO_PAD_SLEEP_STATUS",
diff --git a/hw/ip/pinmux/doc/_index.md b/hw/ip/pinmux/doc/_index.md index efd05ed..6955348 100644 --- a/hw/ip/pinmux/doc/_index.md +++ b/hw/ip/pinmux/doc/_index.md
@@ -10,7 +10,7 @@ See that document for integration overview within the broader OpenTitan top level system. The module provides a mechanism to reconfigure the peripheral-to-pin mapping at runtime, which greatly enhances the system flexibility. This IP is closely related to the `padctrl` instance which provides additional control of pad attributes (pull-up, pull-down, open drain, drive strength, keeper and inversion). -See [that spec]({{< relref "hw/ip/padctrl/doc" >}}) for more information. +See (**TODO**) for more information. @@ -29,7 +29,7 @@ The pinmux peripheral is a programmable module designed to wire arbitrary peripheral inputs and outputs to arbitrary multiplexable chip bidirectional pins. It gives much flexibility at the top level of the device, allowing most data pins to be flexibly wired and controlled by many peripherals. It is assumed that all available pins that the pinmux connects to are bidirectional, controlled by logic within this module. -This document does not define how these are connected to pads at the toplevel, since that is governed by the `padctrl` IP [that spec]({{< relref "hw/ip/padctrl/doc" >}}). +This document does not define how these are connected to pads at the toplevel, since that is governed by the `padctrl` IP (**TODO**). However, some discussion is shared in a later section. The number of available peripheral IOs and muxed IOs is configurable, in other words modifiable at design time.
diff --git a/hw/ip/padctrl/doc/generic_pad_wrapper.svg b/hw/ip/pinmux/doc/generic_pad_wrapper.svg similarity index 100% rename from hw/ip/padctrl/doc/generic_pad_wrapper.svg rename to hw/ip/pinmux/doc/generic_pad_wrapper.svg
diff --git a/hw/ip/padctrl/doc/_index.md b/hw/ip/pinmux/doc/padctrl.md similarity index 98% rename from hw/ip/padctrl/doc/_index.md rename to hw/ip/pinmux/doc/padctrl.md index 4be2abf..21a1c9a 100644 --- a/hw/ip/padctrl/doc/_index.md +++ b/hw/ip/pinmux/doc/padctrl.md
@@ -51,7 +51,6 @@ ## Hardware Interfaces -{{< hwcfg "hw/ip/padctrl/data/padctrl.hjson" >}} ### Parameters @@ -173,5 +172,3 @@ ## Register Table - -{{< registers "hw/ip/padctrl/data/padctrl.hjson" >}}
diff --git a/hw/ip/padctrl/doc/padctrl_block_diagram.svg b/hw/ip/pinmux/doc/padctrl_block_diagram.svg similarity index 100% rename from hw/ip/padctrl/doc/padctrl_block_diagram.svg rename to hw/ip/pinmux/doc/padctrl_block_diagram.svg
diff --git a/hw/ip/pinmux/pinmux_component.core b/hw/ip/pinmux/pinmux_component.core index 9c7bfcc..82a29e8 100644 --- a/hw/ip/pinmux/pinmux_component.core +++ b/hw/ip/pinmux/pinmux_component.core
@@ -14,6 +14,8 @@ # pinmux_wkup.sv depends on pinmux_reg_pkg.sv - "fileset_topgen ? (lowrisc:systems:topgen-reg-only)" files: + - rtl/jtag_mux.sv + - rtl/padring.sv - rtl/pinmux_pkg.sv - rtl/pinmux_wkup.sv - rtl/pinmux.sv
diff --git a/hw/ip/padctrl/rtl/jtag_mux.sv b/hw/ip/pinmux/rtl/jtag_mux.sv similarity index 100% rename from hw/ip/padctrl/rtl/jtag_mux.sv rename to hw/ip/pinmux/rtl/jtag_mux.sv
diff --git a/hw/ip/padctrl/rtl/padring.sv b/hw/ip/pinmux/rtl/padring.sv similarity index 97% rename from hw/ip/padctrl/rtl/padring.sv rename to hw/ip/pinmux/rtl/padring.sv index fc8b3d1..282df17 100644 --- a/hw/ip/padctrl/rtl/padring.sv +++ b/hw/ip/pinmux/rtl/padring.sv
@@ -2,14 +2,14 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // -// This it the padctrl portion that has to be instantiated on the chip level. +// This is the pinmux portion that has to be instantiated on the chip level. // The module instantiates the technology dependent pads, and connects them -// to the MIOs/DIOs and pad attributes coming from the padctrl block. +// to the MIOs/DIOs and pad attributes coming from the pinmux block. // `include "prim_assert.sv" -module padring import padctrl_reg_pkg::*; #( +module padring import pinmux_reg_pkg::*; #( // This allows to selectively connect Pad instances. // unconnected inputs are tied to 0, unconnected outputs are high-z. parameter logic [NMioPads-1:0] ConnectMioIn = '1,
diff --git a/hw/ip/pinmux/rtl/pinmux.sv b/hw/ip/pinmux/rtl/pinmux.sv index d1ddb09..cc21b4e 100644 --- a/hw/ip/pinmux/rtl/pinmux.sv +++ b/hw/ip/pinmux/rtl/pinmux.sv
@@ -46,13 +46,15 @@ output logic [NDioPads-1:0] dio_to_periph_o, // Pad side // MIOs - output logic [NMioPads-1:0] mio_out_o, - output logic [NMioPads-1:0] mio_oe_o, - input [NMioPads-1:0] mio_in_i, + output logic [NMioPads-1:0][AttrDw-1:0] mio_attr_o, + output logic [NMioPads-1:0] mio_out_o, + output logic [NMioPads-1:0] mio_oe_o, + input [NMioPads-1:0] mio_in_i, // DIOs - output logic [NDioPads-1:0] dio_out_o, - output logic [NDioPads-1:0] dio_oe_o, - input [NDioPads-1:0] dio_in_i + output logic [NDioPads-1:0][AttrDw-1:0] dio_attr_o, + output logic [NDioPads-1:0] dio_out_o, + output logic [NDioPads-1:0] dio_oe_o, + input [NDioPads-1:0] dio_in_i ); //////////////////////////// @@ -83,6 +85,53 @@ .devmode_i(1'b1) ); + ///////////////////////////// + // Pad attribute registers // + ///////////////////////////// + + logic [NDioPads-1:0][AttrDw-1:0] dio_pad_attr_q; + logic [NMioPads-1:0][AttrDw-1:0] mio_pad_attr_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + dio_pad_attr_q <= '0; + mio_pad_attr_q <= '0; + end else begin + // dedicated pads + for (int kk = 0; kk < NDioPads; kk++) begin + if (reg2hw.dio_pad_attr[kk].qe) begin + dio_pad_attr_q[kk] <= reg2hw.dio_pad_attr[kk].q; + end + end + // muxed pads + for (int kk = 0; kk < NMioPads; kk++) begin + if (reg2hw.mio_pad_attr[kk].qe) begin + mio_pad_attr_q[kk] <= reg2hw.mio_pad_attr[kk].q; + end + end + end + end + + //////////////////////// + // Connect attributes // + //////////////////////// + + // TODO: rework the WARL behavior + for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_attr + logic [AttrDw-1:0] warl_mask; + assign warl_mask = '0; + assign dio_attr_o[k] = dio_pad_attr_q[k] & warl_mask; + assign hw2reg.dio_pad_attr[k].d = dio_pad_attr_q[k] & warl_mask; + end + + for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_attr + logic [AttrDw-1:0] warl_mask; + assign warl_mask = '0; + assign mio_attr_o[k] = mio_pad_attr_q[k] & warl_mask; + assign hw2reg.mio_pad_attr[k].d = mio_pad_attr_q[k] & warl_mask; + end + + /////////////////////////////////////// // USB wake detect module connection // /////////////////////////////////////// @@ -357,6 +406,9 @@ // `ASSERT_KNOWN_IF(DioOutKnownO_A, dio_out_o[k], dio_oe_o[k]) // end + `ASSERT_KNOWN(MioKnownO_A, mio_attr_o) + `ASSERT_KNOWN(DioKnownO_A, dio_attr_o) + // running on slow AON clock `ASSERT_KNOWN(AonWkupReqKnownO_A, aon_wkup_req_o, clk_aon_i, !rst_aon_ni)
diff --git a/hw/ip/pinmux/rtl/pinmux_reg_pkg.sv b/hw/ip/pinmux/rtl/pinmux_reg_pkg.sv index 2329e5c..c3f2396 100644 --- a/hw/ip/pinmux/rtl/pinmux_reg_pkg.sv +++ b/hw/ip/pinmux/rtl/pinmux_reg_pkg.sv
@@ -7,6 +7,7 @@ package pinmux_reg_pkg; // Param list + parameter int AttrDw = 10; parameter int NMioPeriphIn = 33; parameter int NMioPeriphOut = 32; parameter int NMioPads = 32; @@ -35,13 +36,38 @@ } pinmux_reg2hw_mio_outsel_mreg_t; typedef struct packed { - logic [1:0] q; - } pinmux_reg2hw_mio_out_sleep_val_mreg_t; + logic [9:0] q; + logic qe; + } pinmux_reg2hw_mio_pad_attr_mreg_t; + + typedef struct packed { + logic [9:0] q; + logic qe; + } pinmux_reg2hw_dio_pad_attr_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_mio_pad_sleep_status_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_mio_pad_sleep_en_mreg_t; typedef struct packed { logic [1:0] q; - logic qe; - } pinmux_reg2hw_dio_out_sleep_val_mreg_t; + } pinmux_reg2hw_mio_pad_sleep_mode_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_dio_pad_sleep_status_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_dio_pad_sleep_en_mreg_t; + + typedef struct packed { + logic [1:0] q; + } pinmux_reg2hw_dio_pad_sleep_mode_mreg_t; typedef struct packed { logic q; @@ -74,8 +100,22 @@ typedef struct packed { - logic [1:0] d; - } pinmux_hw2reg_dio_out_sleep_val_mreg_t; + logic [9:0] d; + } pinmux_hw2reg_mio_pad_attr_mreg_t; + + typedef struct packed { + logic [9:0] d; + } pinmux_hw2reg_dio_pad_attr_mreg_t; + + typedef struct packed { + logic d; + logic de; + } pinmux_hw2reg_mio_pad_sleep_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } pinmux_hw2reg_dio_pad_sleep_status_mreg_t; typedef struct packed { logic d; @@ -86,10 +126,16 @@ // Register to internal design logic // /////////////////////////////////////// typedef struct packed { - pinmux_reg2hw_mio_periph_insel_mreg_t [32:0] mio_periph_insel; // [677:480] - pinmux_reg2hw_mio_outsel_mreg_t [31:0] mio_outsel; // [479:288] - pinmux_reg2hw_mio_out_sleep_val_mreg_t [31:0] mio_out_sleep_val; // [287:224] - pinmux_reg2hw_dio_out_sleep_val_mreg_t [15:0] dio_out_sleep_val; // [223:176] + pinmux_reg2hw_mio_periph_insel_mreg_t [32:0] mio_periph_insel; // [1285:1088] + pinmux_reg2hw_mio_outsel_mreg_t [31:0] mio_outsel; // [1087:896] + pinmux_reg2hw_mio_pad_attr_mreg_t [31:0] mio_pad_attr; // [895:544] + pinmux_reg2hw_dio_pad_attr_mreg_t [15:0] dio_pad_attr; // [543:368] + pinmux_reg2hw_mio_pad_sleep_status_mreg_t [31:0] mio_pad_sleep_status; // [367:336] + pinmux_reg2hw_mio_pad_sleep_en_mreg_t [31:0] mio_pad_sleep_en; // [335:304] + pinmux_reg2hw_mio_pad_sleep_mode_mreg_t [31:0] mio_pad_sleep_mode; // [303:240] + pinmux_reg2hw_dio_pad_sleep_status_mreg_t [15:0] dio_pad_sleep_status; // [239:224] + pinmux_reg2hw_dio_pad_sleep_en_mreg_t [15:0] dio_pad_sleep_en; // [223:208] + pinmux_reg2hw_dio_pad_sleep_mode_mreg_t [15:0] dio_pad_sleep_mode; // [207:176] pinmux_reg2hw_wkup_detector_en_mreg_t [7:0] wkup_detector_en; // [175:168] pinmux_reg2hw_wkup_detector_mreg_t [7:0] wkup_detector; // [167:128] pinmux_reg2hw_wkup_detector_cnt_th_mreg_t [7:0] wkup_detector_cnt_th; // [127:64] @@ -101,7 +147,10 @@ // Internal design logic to register // /////////////////////////////////////// typedef struct packed { - pinmux_hw2reg_dio_out_sleep_val_mreg_t [15:0] dio_out_sleep_val; // [39:8] + pinmux_hw2reg_mio_pad_attr_mreg_t [31:0] mio_pad_attr; // [583:264] + pinmux_hw2reg_dio_pad_attr_mreg_t [15:0] dio_pad_attr; // [263:104] + pinmux_hw2reg_mio_pad_sleep_status_mreg_t [31:0] mio_pad_sleep_status; // [103:40] + pinmux_hw2reg_dio_pad_sleep_status_mreg_t [15:0] dio_pad_sleep_status; // [39:8] pinmux_hw2reg_wkup_cause_mreg_t [7:0] wkup_cause; // [7:0] } pinmux_hw2reg_t; @@ -236,143 +285,289 @@ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 11'h 1fc; parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 11'h 200; parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 11'h 204; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_0_OFFSET = 11'h 208; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_1_OFFSET = 11'h 20c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_2_OFFSET = 11'h 210; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_3_OFFSET = 11'h 214; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_4_OFFSET = 11'h 218; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_5_OFFSET = 11'h 21c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_6_OFFSET = 11'h 220; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_7_OFFSET = 11'h 224; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_8_OFFSET = 11'h 228; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_9_OFFSET = 11'h 22c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_10_OFFSET = 11'h 230; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_11_OFFSET = 11'h 234; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_12_OFFSET = 11'h 238; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_13_OFFSET = 11'h 23c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_14_OFFSET = 11'h 240; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_15_OFFSET = 11'h 244; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_16_OFFSET = 11'h 248; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_17_OFFSET = 11'h 24c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_18_OFFSET = 11'h 250; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_19_OFFSET = 11'h 254; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_20_OFFSET = 11'h 258; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_21_OFFSET = 11'h 25c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_22_OFFSET = 11'h 260; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_23_OFFSET = 11'h 264; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_24_OFFSET = 11'h 268; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_25_OFFSET = 11'h 26c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_26_OFFSET = 11'h 270; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_27_OFFSET = 11'h 274; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_28_OFFSET = 11'h 278; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_29_OFFSET = 11'h 27c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_30_OFFSET = 11'h 280; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_31_OFFSET = 11'h 284; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_0_OFFSET = 11'h 288; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_1_OFFSET = 11'h 28c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_2_OFFSET = 11'h 290; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_3_OFFSET = 11'h 294; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_4_OFFSET = 11'h 298; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_5_OFFSET = 11'h 29c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_6_OFFSET = 11'h 2a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_7_OFFSET = 11'h 2a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_8_OFFSET = 11'h 2a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_9_OFFSET = 11'h 2ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_10_OFFSET = 11'h 2b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_11_OFFSET = 11'h 2b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_12_OFFSET = 11'h 2b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_13_OFFSET = 11'h 2bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_14_OFFSET = 11'h 2c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_15_OFFSET = 11'h 2c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_16_OFFSET = 11'h 2c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_17_OFFSET = 11'h 2cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_18_OFFSET = 11'h 2d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_19_OFFSET = 11'h 2d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_20_OFFSET = 11'h 2d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_21_OFFSET = 11'h 2dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_22_OFFSET = 11'h 2e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_23_OFFSET = 11'h 2e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_24_OFFSET = 11'h 2e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_25_OFFSET = 11'h 2ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_26_OFFSET = 11'h 2f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_27_OFFSET = 11'h 2f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_28_OFFSET = 11'h 2f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_29_OFFSET = 11'h 2fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_30_OFFSET = 11'h 300; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_31_OFFSET = 11'h 304; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_0_OFFSET = 11'h 308; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_1_OFFSET = 11'h 30c; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_2_OFFSET = 11'h 310; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_3_OFFSET = 11'h 314; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_4_OFFSET = 11'h 318; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_5_OFFSET = 11'h 31c; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_6_OFFSET = 11'h 320; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_7_OFFSET = 11'h 324; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_8_OFFSET = 11'h 328; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_9_OFFSET = 11'h 32c; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_10_OFFSET = 11'h 330; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_11_OFFSET = 11'h 334; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_12_OFFSET = 11'h 338; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_13_OFFSET = 11'h 33c; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_14_OFFSET = 11'h 340; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_15_OFFSET = 11'h 344; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_0_OFFSET = 11'h 348; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_1_OFFSET = 11'h 34c; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_2_OFFSET = 11'h 350; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_3_OFFSET = 11'h 354; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_4_OFFSET = 11'h 358; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_5_OFFSET = 11'h 35c; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_6_OFFSET = 11'h 360; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_7_OFFSET = 11'h 364; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_8_OFFSET = 11'h 368; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_9_OFFSET = 11'h 36c; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_10_OFFSET = 11'h 370; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_11_OFFSET = 11'h 374; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_12_OFFSET = 11'h 378; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_13_OFFSET = 11'h 37c; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_14_OFFSET = 11'h 380; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_15_OFFSET = 11'h 384; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 11'h 388; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 11'h 38c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 11'h 390; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 11'h 394; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 11'h 398; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 11'h 39c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 11'h 3a0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 11'h 3a4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 11'h 3a8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 11'h 3ac; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 11'h 3b0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 11'h 3b4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 11'h 3b8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 11'h 3bc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 11'h 3c0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 11'h 3c4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 11'h 3c8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 11'h 3cc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 11'h 3d0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 11'h 3d4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 11'h 3d8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 11'h 3dc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 11'h 3e0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 11'h 3e4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 11'h 3e8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 11'h 3ec; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 11'h 3f0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 11'h 3f4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 11'h 3f8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 11'h 3fc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 11'h 400; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 11'h 404; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 11'h 408; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 11'h 40c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 11'h 410; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 11'h 414; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 11'h 418; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 11'h 41c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 11'h 420; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 11'h 424; - parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 11'h 428; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 11'h 208; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 11'h 20c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 11'h 210; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 11'h 214; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 11'h 218; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 11'h 21c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 11'h 220; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 11'h 224; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 11'h 228; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 11'h 22c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 11'h 230; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 11'h 234; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 11'h 238; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 11'h 23c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 11'h 240; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 11'h 244; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 11'h 248; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 11'h 24c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 11'h 250; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 11'h 254; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 11'h 258; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 11'h 25c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 11'h 260; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 11'h 264; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 11'h 268; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 11'h 26c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 11'h 270; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 11'h 274; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 11'h 278; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 11'h 27c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 11'h 280; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 11'h 284; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 11'h 288; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 11'h 28c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 11'h 290; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 11'h 294; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 11'h 298; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 11'h 29c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 11'h 2a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 11'h 2a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 11'h 2a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 11'h 2ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 11'h 2b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 11'h 2b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 11'h 2b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 11'h 2bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 11'h 2c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 11'h 2c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 11'h 2c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 11'h 2cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 11'h 2d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 11'h 2d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 11'h 2d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 11'h 2dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 11'h 2e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 11'h 2e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 11'h 2e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 11'h 2ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 11'h 2f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 11'h 2f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 11'h 2f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 11'h 2fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 11'h 300; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 11'h 304; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 11'h 308; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 11'h 30c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 11'h 310; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 11'h 314; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 11'h 318; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 11'h 31c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 11'h 320; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 11'h 324; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 11'h 328; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 11'h 32c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 11'h 330; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 11'h 334; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 11'h 338; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 11'h 33c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 11'h 340; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET = 11'h 344; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 11'h 348; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 11'h 34c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 11'h 350; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 11'h 354; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 11'h 358; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 11'h 35c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 11'h 360; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 11'h 364; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 11'h 368; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 11'h 36c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 11'h 370; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 11'h 374; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 11'h 378; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 11'h 37c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 11'h 380; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_15_OFFSET = 11'h 384; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_OFFSET = 11'h 388; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 11'h 38c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 11'h 390; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 11'h 394; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 11'h 398; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 11'h 39c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 11'h 3a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 11'h 3a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 11'h 3a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 11'h 3ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 11'h 3b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 11'h 3b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 11'h 3b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 11'h 3bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 11'h 3c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 11'h 3c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 11'h 3c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 11'h 3cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 11'h 3d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 11'h 3d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 11'h 3d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 11'h 3dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 11'h 3e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 11'h 3e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 11'h 3e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 11'h 3ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 11'h 3f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 11'h 3f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 11'h 3f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 11'h 3fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 11'h 400; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 11'h 404; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 11'h 408; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 11'h 40c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 11'h 410; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 11'h 414; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 11'h 418; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 11'h 41c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 11'h 420; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 11'h 424; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 11'h 428; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 11'h 42c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 11'h 430; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 11'h 434; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 11'h 438; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 11'h 43c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 11'h 440; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 11'h 444; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 11'h 448; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 11'h 44c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 11'h 450; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 11'h 454; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 11'h 458; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 11'h 45c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 11'h 460; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 11'h 464; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 11'h 468; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 11'h 46c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 11'h 470; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 11'h 474; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 11'h 478; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 11'h 47c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 11'h 480; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 11'h 484; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 11'h 488; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 11'h 48c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 11'h 490; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 11'h 494; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 11'h 498; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 11'h 49c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 11'h 4a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 11'h 4a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 11'h 4a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 11'h 4ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 11'h 4b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 11'h 4b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 11'h 4b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 11'h 4bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 11'h 4c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 11'h 4c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 11'h 4c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 11'h 4cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 11'h 4d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 11'h 4d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 11'h 4d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 11'h 4dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 11'h 4e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 11'h 4e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 11'h 4e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 11'h 4ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 11'h 4f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 11'h 4f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 11'h 4f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 11'h 4fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 11'h 500; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 11'h 504; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 11'h 508; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET = 11'h 50c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 11'h 510; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 11'h 514; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 11'h 518; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 11'h 51c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 11'h 520; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 11'h 524; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 11'h 528; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 11'h 52c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 11'h 530; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 11'h 534; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 11'h 538; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 11'h 53c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 11'h 540; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 11'h 544; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 11'h 548; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET = 11'h 54c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 11'h 550; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 11'h 554; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 11'h 558; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 11'h 55c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 11'h 560; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 11'h 564; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 11'h 568; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 11'h 56c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 11'h 570; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 11'h 574; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 11'h 578; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 11'h 57c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 11'h 580; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 11'h 584; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 11'h 588; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET = 11'h 58c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 11'h 590; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 11'h 594; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 11'h 598; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 11'h 59c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 11'h 5a0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 11'h 5a4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 11'h 5a8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 11'h 5ac; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 11'h 5b0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 11'h 5b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 11'h 5b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 11'h 5bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 11'h 5c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 11'h 5c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 11'h 5c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET = 11'h 5cc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 11'h 5d0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 11'h 5d4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 11'h 5d8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 11'h 5dc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 11'h 5e0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 11'h 5e4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 11'h 5e8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 11'h 5ec; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 11'h 5f0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 11'h 5f4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 11'h 5f8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 11'h 5fc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 11'h 600; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 11'h 604; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 11'h 608; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 11'h 60c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 11'h 610; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 11'h 614; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 11'h 618; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 11'h 61c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 11'h 620; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 11'h 624; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 11'h 628; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 11'h 62c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 11'h 630; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 11'h 634; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 11'h 638; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 11'h 63c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 11'h 640; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 11'h 644; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 11'h 648; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 11'h 64c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 11'h 650; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 11'h 654; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 11'h 658; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 11'h 65c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 11'h 660; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 11'h 664; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 11'h 668; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 11'h 66c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 11'h 670; // Register Index @@ -507,102 +702,248 @@ PINMUX_MIO_OUTSEL_29, PINMUX_MIO_OUTSEL_30, PINMUX_MIO_OUTSEL_31, - PINMUX_MIO_OUT_SLEEP_REGWEN_0, - PINMUX_MIO_OUT_SLEEP_REGWEN_1, - PINMUX_MIO_OUT_SLEEP_REGWEN_2, - PINMUX_MIO_OUT_SLEEP_REGWEN_3, - PINMUX_MIO_OUT_SLEEP_REGWEN_4, - PINMUX_MIO_OUT_SLEEP_REGWEN_5, - PINMUX_MIO_OUT_SLEEP_REGWEN_6, - PINMUX_MIO_OUT_SLEEP_REGWEN_7, - PINMUX_MIO_OUT_SLEEP_REGWEN_8, - PINMUX_MIO_OUT_SLEEP_REGWEN_9, - PINMUX_MIO_OUT_SLEEP_REGWEN_10, - PINMUX_MIO_OUT_SLEEP_REGWEN_11, - PINMUX_MIO_OUT_SLEEP_REGWEN_12, - PINMUX_MIO_OUT_SLEEP_REGWEN_13, - PINMUX_MIO_OUT_SLEEP_REGWEN_14, - PINMUX_MIO_OUT_SLEEP_REGWEN_15, - PINMUX_MIO_OUT_SLEEP_REGWEN_16, - PINMUX_MIO_OUT_SLEEP_REGWEN_17, - PINMUX_MIO_OUT_SLEEP_REGWEN_18, - PINMUX_MIO_OUT_SLEEP_REGWEN_19, - PINMUX_MIO_OUT_SLEEP_REGWEN_20, - PINMUX_MIO_OUT_SLEEP_REGWEN_21, - PINMUX_MIO_OUT_SLEEP_REGWEN_22, - PINMUX_MIO_OUT_SLEEP_REGWEN_23, - PINMUX_MIO_OUT_SLEEP_REGWEN_24, - PINMUX_MIO_OUT_SLEEP_REGWEN_25, - PINMUX_MIO_OUT_SLEEP_REGWEN_26, - PINMUX_MIO_OUT_SLEEP_REGWEN_27, - PINMUX_MIO_OUT_SLEEP_REGWEN_28, - PINMUX_MIO_OUT_SLEEP_REGWEN_29, - PINMUX_MIO_OUT_SLEEP_REGWEN_30, - PINMUX_MIO_OUT_SLEEP_REGWEN_31, - PINMUX_MIO_OUT_SLEEP_VAL_0, - PINMUX_MIO_OUT_SLEEP_VAL_1, - PINMUX_MIO_OUT_SLEEP_VAL_2, - PINMUX_MIO_OUT_SLEEP_VAL_3, - PINMUX_MIO_OUT_SLEEP_VAL_4, - PINMUX_MIO_OUT_SLEEP_VAL_5, - PINMUX_MIO_OUT_SLEEP_VAL_6, - PINMUX_MIO_OUT_SLEEP_VAL_7, - PINMUX_MIO_OUT_SLEEP_VAL_8, - PINMUX_MIO_OUT_SLEEP_VAL_9, - PINMUX_MIO_OUT_SLEEP_VAL_10, - PINMUX_MIO_OUT_SLEEP_VAL_11, - PINMUX_MIO_OUT_SLEEP_VAL_12, - PINMUX_MIO_OUT_SLEEP_VAL_13, - PINMUX_MIO_OUT_SLEEP_VAL_14, - PINMUX_MIO_OUT_SLEEP_VAL_15, - PINMUX_MIO_OUT_SLEEP_VAL_16, - PINMUX_MIO_OUT_SLEEP_VAL_17, - PINMUX_MIO_OUT_SLEEP_VAL_18, - PINMUX_MIO_OUT_SLEEP_VAL_19, - PINMUX_MIO_OUT_SLEEP_VAL_20, - PINMUX_MIO_OUT_SLEEP_VAL_21, - PINMUX_MIO_OUT_SLEEP_VAL_22, - PINMUX_MIO_OUT_SLEEP_VAL_23, - PINMUX_MIO_OUT_SLEEP_VAL_24, - PINMUX_MIO_OUT_SLEEP_VAL_25, - PINMUX_MIO_OUT_SLEEP_VAL_26, - PINMUX_MIO_OUT_SLEEP_VAL_27, - PINMUX_MIO_OUT_SLEEP_VAL_28, - PINMUX_MIO_OUT_SLEEP_VAL_29, - PINMUX_MIO_OUT_SLEEP_VAL_30, - PINMUX_MIO_OUT_SLEEP_VAL_31, - PINMUX_DIO_OUT_SLEEP_REGWEN_0, - PINMUX_DIO_OUT_SLEEP_REGWEN_1, - PINMUX_DIO_OUT_SLEEP_REGWEN_2, - PINMUX_DIO_OUT_SLEEP_REGWEN_3, - PINMUX_DIO_OUT_SLEEP_REGWEN_4, - PINMUX_DIO_OUT_SLEEP_REGWEN_5, - PINMUX_DIO_OUT_SLEEP_REGWEN_6, - PINMUX_DIO_OUT_SLEEP_REGWEN_7, - PINMUX_DIO_OUT_SLEEP_REGWEN_8, - PINMUX_DIO_OUT_SLEEP_REGWEN_9, - PINMUX_DIO_OUT_SLEEP_REGWEN_10, - PINMUX_DIO_OUT_SLEEP_REGWEN_11, - PINMUX_DIO_OUT_SLEEP_REGWEN_12, - PINMUX_DIO_OUT_SLEEP_REGWEN_13, - PINMUX_DIO_OUT_SLEEP_REGWEN_14, - PINMUX_DIO_OUT_SLEEP_REGWEN_15, - PINMUX_DIO_OUT_SLEEP_VAL_0, - PINMUX_DIO_OUT_SLEEP_VAL_1, - PINMUX_DIO_OUT_SLEEP_VAL_2, - PINMUX_DIO_OUT_SLEEP_VAL_3, - PINMUX_DIO_OUT_SLEEP_VAL_4, - PINMUX_DIO_OUT_SLEEP_VAL_5, - PINMUX_DIO_OUT_SLEEP_VAL_6, - PINMUX_DIO_OUT_SLEEP_VAL_7, - PINMUX_DIO_OUT_SLEEP_VAL_8, - PINMUX_DIO_OUT_SLEEP_VAL_9, - PINMUX_DIO_OUT_SLEEP_VAL_10, - PINMUX_DIO_OUT_SLEEP_VAL_11, - PINMUX_DIO_OUT_SLEEP_VAL_12, - PINMUX_DIO_OUT_SLEEP_VAL_13, - PINMUX_DIO_OUT_SLEEP_VAL_14, - PINMUX_DIO_OUT_SLEEP_VAL_15, + PINMUX_MIO_PAD_ATTR_REGWEN_0, + PINMUX_MIO_PAD_ATTR_REGWEN_1, + PINMUX_MIO_PAD_ATTR_REGWEN_2, + PINMUX_MIO_PAD_ATTR_REGWEN_3, + PINMUX_MIO_PAD_ATTR_REGWEN_4, + PINMUX_MIO_PAD_ATTR_REGWEN_5, + PINMUX_MIO_PAD_ATTR_REGWEN_6, + PINMUX_MIO_PAD_ATTR_REGWEN_7, + PINMUX_MIO_PAD_ATTR_REGWEN_8, + PINMUX_MIO_PAD_ATTR_REGWEN_9, + PINMUX_MIO_PAD_ATTR_REGWEN_10, + PINMUX_MIO_PAD_ATTR_REGWEN_11, + PINMUX_MIO_PAD_ATTR_REGWEN_12, + PINMUX_MIO_PAD_ATTR_REGWEN_13, + PINMUX_MIO_PAD_ATTR_REGWEN_14, + PINMUX_MIO_PAD_ATTR_REGWEN_15, + PINMUX_MIO_PAD_ATTR_REGWEN_16, + PINMUX_MIO_PAD_ATTR_REGWEN_17, + PINMUX_MIO_PAD_ATTR_REGWEN_18, + PINMUX_MIO_PAD_ATTR_REGWEN_19, + PINMUX_MIO_PAD_ATTR_REGWEN_20, + PINMUX_MIO_PAD_ATTR_REGWEN_21, + PINMUX_MIO_PAD_ATTR_REGWEN_22, + PINMUX_MIO_PAD_ATTR_REGWEN_23, + PINMUX_MIO_PAD_ATTR_REGWEN_24, + PINMUX_MIO_PAD_ATTR_REGWEN_25, + PINMUX_MIO_PAD_ATTR_REGWEN_26, + PINMUX_MIO_PAD_ATTR_REGWEN_27, + PINMUX_MIO_PAD_ATTR_REGWEN_28, + PINMUX_MIO_PAD_ATTR_REGWEN_29, + PINMUX_MIO_PAD_ATTR_REGWEN_30, + PINMUX_MIO_PAD_ATTR_REGWEN_31, + PINMUX_MIO_PAD_ATTR_0, + PINMUX_MIO_PAD_ATTR_1, + PINMUX_MIO_PAD_ATTR_2, + PINMUX_MIO_PAD_ATTR_3, + PINMUX_MIO_PAD_ATTR_4, + PINMUX_MIO_PAD_ATTR_5, + PINMUX_MIO_PAD_ATTR_6, + PINMUX_MIO_PAD_ATTR_7, + PINMUX_MIO_PAD_ATTR_8, + PINMUX_MIO_PAD_ATTR_9, + PINMUX_MIO_PAD_ATTR_10, + PINMUX_MIO_PAD_ATTR_11, + PINMUX_MIO_PAD_ATTR_12, + PINMUX_MIO_PAD_ATTR_13, + PINMUX_MIO_PAD_ATTR_14, + PINMUX_MIO_PAD_ATTR_15, + PINMUX_MIO_PAD_ATTR_16, + PINMUX_MIO_PAD_ATTR_17, + PINMUX_MIO_PAD_ATTR_18, + PINMUX_MIO_PAD_ATTR_19, + PINMUX_MIO_PAD_ATTR_20, + PINMUX_MIO_PAD_ATTR_21, + PINMUX_MIO_PAD_ATTR_22, + PINMUX_MIO_PAD_ATTR_23, + PINMUX_MIO_PAD_ATTR_24, + PINMUX_MIO_PAD_ATTR_25, + PINMUX_MIO_PAD_ATTR_26, + PINMUX_MIO_PAD_ATTR_27, + PINMUX_MIO_PAD_ATTR_28, + PINMUX_MIO_PAD_ATTR_29, + PINMUX_MIO_PAD_ATTR_30, + PINMUX_MIO_PAD_ATTR_31, + PINMUX_DIO_PAD_ATTR_REGWEN_0, + PINMUX_DIO_PAD_ATTR_REGWEN_1, + PINMUX_DIO_PAD_ATTR_REGWEN_2, + PINMUX_DIO_PAD_ATTR_REGWEN_3, + PINMUX_DIO_PAD_ATTR_REGWEN_4, + PINMUX_DIO_PAD_ATTR_REGWEN_5, + PINMUX_DIO_PAD_ATTR_REGWEN_6, + PINMUX_DIO_PAD_ATTR_REGWEN_7, + PINMUX_DIO_PAD_ATTR_REGWEN_8, + PINMUX_DIO_PAD_ATTR_REGWEN_9, + PINMUX_DIO_PAD_ATTR_REGWEN_10, + PINMUX_DIO_PAD_ATTR_REGWEN_11, + PINMUX_DIO_PAD_ATTR_REGWEN_12, + PINMUX_DIO_PAD_ATTR_REGWEN_13, + PINMUX_DIO_PAD_ATTR_REGWEN_14, + PINMUX_DIO_PAD_ATTR_REGWEN_15, + PINMUX_DIO_PAD_ATTR_0, + PINMUX_DIO_PAD_ATTR_1, + PINMUX_DIO_PAD_ATTR_2, + PINMUX_DIO_PAD_ATTR_3, + PINMUX_DIO_PAD_ATTR_4, + PINMUX_DIO_PAD_ATTR_5, + PINMUX_DIO_PAD_ATTR_6, + PINMUX_DIO_PAD_ATTR_7, + PINMUX_DIO_PAD_ATTR_8, + PINMUX_DIO_PAD_ATTR_9, + PINMUX_DIO_PAD_ATTR_10, + PINMUX_DIO_PAD_ATTR_11, + PINMUX_DIO_PAD_ATTR_12, + PINMUX_DIO_PAD_ATTR_13, + PINMUX_DIO_PAD_ATTR_14, + PINMUX_DIO_PAD_ATTR_15, + PINMUX_MIO_PAD_SLEEP_STATUS, + PINMUX_MIO_PAD_SLEEP_REGWEN_0, + PINMUX_MIO_PAD_SLEEP_REGWEN_1, + PINMUX_MIO_PAD_SLEEP_REGWEN_2, + PINMUX_MIO_PAD_SLEEP_REGWEN_3, + PINMUX_MIO_PAD_SLEEP_REGWEN_4, + PINMUX_MIO_PAD_SLEEP_REGWEN_5, + PINMUX_MIO_PAD_SLEEP_REGWEN_6, + PINMUX_MIO_PAD_SLEEP_REGWEN_7, + PINMUX_MIO_PAD_SLEEP_REGWEN_8, + PINMUX_MIO_PAD_SLEEP_REGWEN_9, + PINMUX_MIO_PAD_SLEEP_REGWEN_10, + PINMUX_MIO_PAD_SLEEP_REGWEN_11, + PINMUX_MIO_PAD_SLEEP_REGWEN_12, + PINMUX_MIO_PAD_SLEEP_REGWEN_13, + PINMUX_MIO_PAD_SLEEP_REGWEN_14, + PINMUX_MIO_PAD_SLEEP_REGWEN_15, + PINMUX_MIO_PAD_SLEEP_REGWEN_16, + PINMUX_MIO_PAD_SLEEP_REGWEN_17, + PINMUX_MIO_PAD_SLEEP_REGWEN_18, + PINMUX_MIO_PAD_SLEEP_REGWEN_19, + PINMUX_MIO_PAD_SLEEP_REGWEN_20, + PINMUX_MIO_PAD_SLEEP_REGWEN_21, + PINMUX_MIO_PAD_SLEEP_REGWEN_22, + PINMUX_MIO_PAD_SLEEP_REGWEN_23, + PINMUX_MIO_PAD_SLEEP_REGWEN_24, + PINMUX_MIO_PAD_SLEEP_REGWEN_25, + PINMUX_MIO_PAD_SLEEP_REGWEN_26, + PINMUX_MIO_PAD_SLEEP_REGWEN_27, + PINMUX_MIO_PAD_SLEEP_REGWEN_28, + PINMUX_MIO_PAD_SLEEP_REGWEN_29, + PINMUX_MIO_PAD_SLEEP_REGWEN_30, + PINMUX_MIO_PAD_SLEEP_REGWEN_31, + PINMUX_MIO_PAD_SLEEP_EN_0, + PINMUX_MIO_PAD_SLEEP_EN_1, + PINMUX_MIO_PAD_SLEEP_EN_2, + PINMUX_MIO_PAD_SLEEP_EN_3, + PINMUX_MIO_PAD_SLEEP_EN_4, + PINMUX_MIO_PAD_SLEEP_EN_5, + PINMUX_MIO_PAD_SLEEP_EN_6, + PINMUX_MIO_PAD_SLEEP_EN_7, + PINMUX_MIO_PAD_SLEEP_EN_8, + PINMUX_MIO_PAD_SLEEP_EN_9, + PINMUX_MIO_PAD_SLEEP_EN_10, + PINMUX_MIO_PAD_SLEEP_EN_11, + PINMUX_MIO_PAD_SLEEP_EN_12, + PINMUX_MIO_PAD_SLEEP_EN_13, + PINMUX_MIO_PAD_SLEEP_EN_14, + PINMUX_MIO_PAD_SLEEP_EN_15, + PINMUX_MIO_PAD_SLEEP_EN_16, + PINMUX_MIO_PAD_SLEEP_EN_17, + PINMUX_MIO_PAD_SLEEP_EN_18, + PINMUX_MIO_PAD_SLEEP_EN_19, + PINMUX_MIO_PAD_SLEEP_EN_20, + PINMUX_MIO_PAD_SLEEP_EN_21, + PINMUX_MIO_PAD_SLEEP_EN_22, + PINMUX_MIO_PAD_SLEEP_EN_23, + PINMUX_MIO_PAD_SLEEP_EN_24, + PINMUX_MIO_PAD_SLEEP_EN_25, + PINMUX_MIO_PAD_SLEEP_EN_26, + PINMUX_MIO_PAD_SLEEP_EN_27, + PINMUX_MIO_PAD_SLEEP_EN_28, + PINMUX_MIO_PAD_SLEEP_EN_29, + PINMUX_MIO_PAD_SLEEP_EN_30, + PINMUX_MIO_PAD_SLEEP_EN_31, + PINMUX_MIO_PAD_SLEEP_MODE_0, + PINMUX_MIO_PAD_SLEEP_MODE_1, + PINMUX_MIO_PAD_SLEEP_MODE_2, + PINMUX_MIO_PAD_SLEEP_MODE_3, + PINMUX_MIO_PAD_SLEEP_MODE_4, + PINMUX_MIO_PAD_SLEEP_MODE_5, + PINMUX_MIO_PAD_SLEEP_MODE_6, + PINMUX_MIO_PAD_SLEEP_MODE_7, + PINMUX_MIO_PAD_SLEEP_MODE_8, + PINMUX_MIO_PAD_SLEEP_MODE_9, + PINMUX_MIO_PAD_SLEEP_MODE_10, + PINMUX_MIO_PAD_SLEEP_MODE_11, + PINMUX_MIO_PAD_SLEEP_MODE_12, + PINMUX_MIO_PAD_SLEEP_MODE_13, + PINMUX_MIO_PAD_SLEEP_MODE_14, + PINMUX_MIO_PAD_SLEEP_MODE_15, + PINMUX_MIO_PAD_SLEEP_MODE_16, + PINMUX_MIO_PAD_SLEEP_MODE_17, + PINMUX_MIO_PAD_SLEEP_MODE_18, + PINMUX_MIO_PAD_SLEEP_MODE_19, + PINMUX_MIO_PAD_SLEEP_MODE_20, + PINMUX_MIO_PAD_SLEEP_MODE_21, + PINMUX_MIO_PAD_SLEEP_MODE_22, + PINMUX_MIO_PAD_SLEEP_MODE_23, + PINMUX_MIO_PAD_SLEEP_MODE_24, + PINMUX_MIO_PAD_SLEEP_MODE_25, + PINMUX_MIO_PAD_SLEEP_MODE_26, + PINMUX_MIO_PAD_SLEEP_MODE_27, + PINMUX_MIO_PAD_SLEEP_MODE_28, + PINMUX_MIO_PAD_SLEEP_MODE_29, + PINMUX_MIO_PAD_SLEEP_MODE_30, + PINMUX_MIO_PAD_SLEEP_MODE_31, + PINMUX_DIO_PAD_SLEEP_STATUS, + PINMUX_DIO_PAD_SLEEP_REGWEN_0, + PINMUX_DIO_PAD_SLEEP_REGWEN_1, + PINMUX_DIO_PAD_SLEEP_REGWEN_2, + PINMUX_DIO_PAD_SLEEP_REGWEN_3, + PINMUX_DIO_PAD_SLEEP_REGWEN_4, + PINMUX_DIO_PAD_SLEEP_REGWEN_5, + PINMUX_DIO_PAD_SLEEP_REGWEN_6, + PINMUX_DIO_PAD_SLEEP_REGWEN_7, + PINMUX_DIO_PAD_SLEEP_REGWEN_8, + PINMUX_DIO_PAD_SLEEP_REGWEN_9, + PINMUX_DIO_PAD_SLEEP_REGWEN_10, + PINMUX_DIO_PAD_SLEEP_REGWEN_11, + PINMUX_DIO_PAD_SLEEP_REGWEN_12, + PINMUX_DIO_PAD_SLEEP_REGWEN_13, + PINMUX_DIO_PAD_SLEEP_REGWEN_14, + PINMUX_DIO_PAD_SLEEP_REGWEN_15, + PINMUX_DIO_PAD_SLEEP_EN_0, + PINMUX_DIO_PAD_SLEEP_EN_1, + PINMUX_DIO_PAD_SLEEP_EN_2, + PINMUX_DIO_PAD_SLEEP_EN_3, + PINMUX_DIO_PAD_SLEEP_EN_4, + PINMUX_DIO_PAD_SLEEP_EN_5, + PINMUX_DIO_PAD_SLEEP_EN_6, + PINMUX_DIO_PAD_SLEEP_EN_7, + PINMUX_DIO_PAD_SLEEP_EN_8, + PINMUX_DIO_PAD_SLEEP_EN_9, + PINMUX_DIO_PAD_SLEEP_EN_10, + PINMUX_DIO_PAD_SLEEP_EN_11, + PINMUX_DIO_PAD_SLEEP_EN_12, + PINMUX_DIO_PAD_SLEEP_EN_13, + PINMUX_DIO_PAD_SLEEP_EN_14, + PINMUX_DIO_PAD_SLEEP_EN_15, + PINMUX_DIO_PAD_SLEEP_MODE_0, + PINMUX_DIO_PAD_SLEEP_MODE_1, + PINMUX_DIO_PAD_SLEEP_MODE_2, + PINMUX_DIO_PAD_SLEEP_MODE_3, + PINMUX_DIO_PAD_SLEEP_MODE_4, + PINMUX_DIO_PAD_SLEEP_MODE_5, + PINMUX_DIO_PAD_SLEEP_MODE_6, + PINMUX_DIO_PAD_SLEEP_MODE_7, + PINMUX_DIO_PAD_SLEEP_MODE_8, + PINMUX_DIO_PAD_SLEEP_MODE_9, + PINMUX_DIO_PAD_SLEEP_MODE_10, + PINMUX_DIO_PAD_SLEEP_MODE_11, + PINMUX_DIO_PAD_SLEEP_MODE_12, + PINMUX_DIO_PAD_SLEEP_MODE_13, + PINMUX_DIO_PAD_SLEEP_MODE_14, + PINMUX_DIO_PAD_SLEEP_MODE_15, PINMUX_WKUP_DETECTOR_REGWEN_0, PINMUX_WKUP_DETECTOR_REGWEN_1, PINMUX_WKUP_DETECTOR_REGWEN_2, @@ -647,7 +988,7 @@ } pinmux_id_e; // Register width information to check illegal writes - parameter logic [3:0] PINMUX_PERMIT [267] = '{ + parameter logic [3:0] PINMUX_PERMIT [413] = '{ 4'b 0001, // index[ 0] PINMUX_MIO_PERIPH_INSEL_REGWEN_0 4'b 0001, // index[ 1] PINMUX_MIO_PERIPH_INSEL_REGWEN_1 4'b 0001, // index[ 2] PINMUX_MIO_PERIPH_INSEL_REGWEN_2 @@ -778,143 +1119,289 @@ 4'b 0001, // index[127] PINMUX_MIO_OUTSEL_29 4'b 0001, // index[128] PINMUX_MIO_OUTSEL_30 4'b 0001, // index[129] PINMUX_MIO_OUTSEL_31 - 4'b 0001, // index[130] PINMUX_MIO_OUT_SLEEP_REGWEN_0 - 4'b 0001, // index[131] PINMUX_MIO_OUT_SLEEP_REGWEN_1 - 4'b 0001, // index[132] PINMUX_MIO_OUT_SLEEP_REGWEN_2 - 4'b 0001, // index[133] PINMUX_MIO_OUT_SLEEP_REGWEN_3 - 4'b 0001, // index[134] PINMUX_MIO_OUT_SLEEP_REGWEN_4 - 4'b 0001, // index[135] PINMUX_MIO_OUT_SLEEP_REGWEN_5 - 4'b 0001, // index[136] PINMUX_MIO_OUT_SLEEP_REGWEN_6 - 4'b 0001, // index[137] PINMUX_MIO_OUT_SLEEP_REGWEN_7 - 4'b 0001, // index[138] PINMUX_MIO_OUT_SLEEP_REGWEN_8 - 4'b 0001, // index[139] PINMUX_MIO_OUT_SLEEP_REGWEN_9 - 4'b 0001, // index[140] PINMUX_MIO_OUT_SLEEP_REGWEN_10 - 4'b 0001, // index[141] PINMUX_MIO_OUT_SLEEP_REGWEN_11 - 4'b 0001, // index[142] PINMUX_MIO_OUT_SLEEP_REGWEN_12 - 4'b 0001, // index[143] PINMUX_MIO_OUT_SLEEP_REGWEN_13 - 4'b 0001, // index[144] PINMUX_MIO_OUT_SLEEP_REGWEN_14 - 4'b 0001, // index[145] PINMUX_MIO_OUT_SLEEP_REGWEN_15 - 4'b 0001, // index[146] PINMUX_MIO_OUT_SLEEP_REGWEN_16 - 4'b 0001, // index[147] PINMUX_MIO_OUT_SLEEP_REGWEN_17 - 4'b 0001, // index[148] PINMUX_MIO_OUT_SLEEP_REGWEN_18 - 4'b 0001, // index[149] PINMUX_MIO_OUT_SLEEP_REGWEN_19 - 4'b 0001, // index[150] PINMUX_MIO_OUT_SLEEP_REGWEN_20 - 4'b 0001, // index[151] PINMUX_MIO_OUT_SLEEP_REGWEN_21 - 4'b 0001, // index[152] PINMUX_MIO_OUT_SLEEP_REGWEN_22 - 4'b 0001, // index[153] PINMUX_MIO_OUT_SLEEP_REGWEN_23 - 4'b 0001, // index[154] PINMUX_MIO_OUT_SLEEP_REGWEN_24 - 4'b 0001, // index[155] PINMUX_MIO_OUT_SLEEP_REGWEN_25 - 4'b 0001, // index[156] PINMUX_MIO_OUT_SLEEP_REGWEN_26 - 4'b 0001, // index[157] PINMUX_MIO_OUT_SLEEP_REGWEN_27 - 4'b 0001, // index[158] PINMUX_MIO_OUT_SLEEP_REGWEN_28 - 4'b 0001, // index[159] PINMUX_MIO_OUT_SLEEP_REGWEN_29 - 4'b 0001, // index[160] PINMUX_MIO_OUT_SLEEP_REGWEN_30 - 4'b 0001, // index[161] PINMUX_MIO_OUT_SLEEP_REGWEN_31 - 4'b 0001, // index[162] PINMUX_MIO_OUT_SLEEP_VAL_0 - 4'b 0001, // index[163] PINMUX_MIO_OUT_SLEEP_VAL_1 - 4'b 0001, // index[164] PINMUX_MIO_OUT_SLEEP_VAL_2 - 4'b 0001, // index[165] PINMUX_MIO_OUT_SLEEP_VAL_3 - 4'b 0001, // index[166] PINMUX_MIO_OUT_SLEEP_VAL_4 - 4'b 0001, // index[167] PINMUX_MIO_OUT_SLEEP_VAL_5 - 4'b 0001, // index[168] PINMUX_MIO_OUT_SLEEP_VAL_6 - 4'b 0001, // index[169] PINMUX_MIO_OUT_SLEEP_VAL_7 - 4'b 0001, // index[170] PINMUX_MIO_OUT_SLEEP_VAL_8 - 4'b 0001, // index[171] PINMUX_MIO_OUT_SLEEP_VAL_9 - 4'b 0001, // index[172] PINMUX_MIO_OUT_SLEEP_VAL_10 - 4'b 0001, // index[173] PINMUX_MIO_OUT_SLEEP_VAL_11 - 4'b 0001, // index[174] PINMUX_MIO_OUT_SLEEP_VAL_12 - 4'b 0001, // index[175] PINMUX_MIO_OUT_SLEEP_VAL_13 - 4'b 0001, // index[176] PINMUX_MIO_OUT_SLEEP_VAL_14 - 4'b 0001, // index[177] PINMUX_MIO_OUT_SLEEP_VAL_15 - 4'b 0001, // index[178] PINMUX_MIO_OUT_SLEEP_VAL_16 - 4'b 0001, // index[179] PINMUX_MIO_OUT_SLEEP_VAL_17 - 4'b 0001, // index[180] PINMUX_MIO_OUT_SLEEP_VAL_18 - 4'b 0001, // index[181] PINMUX_MIO_OUT_SLEEP_VAL_19 - 4'b 0001, // index[182] PINMUX_MIO_OUT_SLEEP_VAL_20 - 4'b 0001, // index[183] PINMUX_MIO_OUT_SLEEP_VAL_21 - 4'b 0001, // index[184] PINMUX_MIO_OUT_SLEEP_VAL_22 - 4'b 0001, // index[185] PINMUX_MIO_OUT_SLEEP_VAL_23 - 4'b 0001, // index[186] PINMUX_MIO_OUT_SLEEP_VAL_24 - 4'b 0001, // index[187] PINMUX_MIO_OUT_SLEEP_VAL_25 - 4'b 0001, // index[188] PINMUX_MIO_OUT_SLEEP_VAL_26 - 4'b 0001, // index[189] PINMUX_MIO_OUT_SLEEP_VAL_27 - 4'b 0001, // index[190] PINMUX_MIO_OUT_SLEEP_VAL_28 - 4'b 0001, // index[191] PINMUX_MIO_OUT_SLEEP_VAL_29 - 4'b 0001, // index[192] PINMUX_MIO_OUT_SLEEP_VAL_30 - 4'b 0001, // index[193] PINMUX_MIO_OUT_SLEEP_VAL_31 - 4'b 0001, // index[194] PINMUX_DIO_OUT_SLEEP_REGWEN_0 - 4'b 0001, // index[195] PINMUX_DIO_OUT_SLEEP_REGWEN_1 - 4'b 0001, // index[196] PINMUX_DIO_OUT_SLEEP_REGWEN_2 - 4'b 0001, // index[197] PINMUX_DIO_OUT_SLEEP_REGWEN_3 - 4'b 0001, // index[198] PINMUX_DIO_OUT_SLEEP_REGWEN_4 - 4'b 0001, // index[199] PINMUX_DIO_OUT_SLEEP_REGWEN_5 - 4'b 0001, // index[200] PINMUX_DIO_OUT_SLEEP_REGWEN_6 - 4'b 0001, // index[201] PINMUX_DIO_OUT_SLEEP_REGWEN_7 - 4'b 0001, // index[202] PINMUX_DIO_OUT_SLEEP_REGWEN_8 - 4'b 0001, // index[203] PINMUX_DIO_OUT_SLEEP_REGWEN_9 - 4'b 0001, // index[204] PINMUX_DIO_OUT_SLEEP_REGWEN_10 - 4'b 0001, // index[205] PINMUX_DIO_OUT_SLEEP_REGWEN_11 - 4'b 0001, // index[206] PINMUX_DIO_OUT_SLEEP_REGWEN_12 - 4'b 0001, // index[207] PINMUX_DIO_OUT_SLEEP_REGWEN_13 - 4'b 0001, // index[208] PINMUX_DIO_OUT_SLEEP_REGWEN_14 - 4'b 0001, // index[209] PINMUX_DIO_OUT_SLEEP_REGWEN_15 - 4'b 0001, // index[210] PINMUX_DIO_OUT_SLEEP_VAL_0 - 4'b 0001, // index[211] PINMUX_DIO_OUT_SLEEP_VAL_1 - 4'b 0001, // index[212] PINMUX_DIO_OUT_SLEEP_VAL_2 - 4'b 0001, // index[213] PINMUX_DIO_OUT_SLEEP_VAL_3 - 4'b 0001, // index[214] PINMUX_DIO_OUT_SLEEP_VAL_4 - 4'b 0001, // index[215] PINMUX_DIO_OUT_SLEEP_VAL_5 - 4'b 0001, // index[216] PINMUX_DIO_OUT_SLEEP_VAL_6 - 4'b 0001, // index[217] PINMUX_DIO_OUT_SLEEP_VAL_7 - 4'b 0001, // index[218] PINMUX_DIO_OUT_SLEEP_VAL_8 - 4'b 0001, // index[219] PINMUX_DIO_OUT_SLEEP_VAL_9 - 4'b 0001, // index[220] PINMUX_DIO_OUT_SLEEP_VAL_10 - 4'b 0001, // index[221] PINMUX_DIO_OUT_SLEEP_VAL_11 - 4'b 0001, // index[222] PINMUX_DIO_OUT_SLEEP_VAL_12 - 4'b 0001, // index[223] PINMUX_DIO_OUT_SLEEP_VAL_13 - 4'b 0001, // index[224] PINMUX_DIO_OUT_SLEEP_VAL_14 - 4'b 0001, // index[225] PINMUX_DIO_OUT_SLEEP_VAL_15 - 4'b 0001, // index[226] PINMUX_WKUP_DETECTOR_REGWEN_0 - 4'b 0001, // index[227] PINMUX_WKUP_DETECTOR_REGWEN_1 - 4'b 0001, // index[228] PINMUX_WKUP_DETECTOR_REGWEN_2 - 4'b 0001, // index[229] PINMUX_WKUP_DETECTOR_REGWEN_3 - 4'b 0001, // index[230] PINMUX_WKUP_DETECTOR_REGWEN_4 - 4'b 0001, // index[231] PINMUX_WKUP_DETECTOR_REGWEN_5 - 4'b 0001, // index[232] PINMUX_WKUP_DETECTOR_REGWEN_6 - 4'b 0001, // index[233] PINMUX_WKUP_DETECTOR_REGWEN_7 - 4'b 0001, // index[234] PINMUX_WKUP_DETECTOR_EN_0 - 4'b 0001, // index[235] PINMUX_WKUP_DETECTOR_EN_1 - 4'b 0001, // index[236] PINMUX_WKUP_DETECTOR_EN_2 - 4'b 0001, // index[237] PINMUX_WKUP_DETECTOR_EN_3 - 4'b 0001, // index[238] PINMUX_WKUP_DETECTOR_EN_4 - 4'b 0001, // index[239] PINMUX_WKUP_DETECTOR_EN_5 - 4'b 0001, // index[240] PINMUX_WKUP_DETECTOR_EN_6 - 4'b 0001, // index[241] PINMUX_WKUP_DETECTOR_EN_7 - 4'b 0001, // index[242] PINMUX_WKUP_DETECTOR_0 - 4'b 0001, // index[243] PINMUX_WKUP_DETECTOR_1 - 4'b 0001, // index[244] PINMUX_WKUP_DETECTOR_2 - 4'b 0001, // index[245] PINMUX_WKUP_DETECTOR_3 - 4'b 0001, // index[246] PINMUX_WKUP_DETECTOR_4 - 4'b 0001, // index[247] PINMUX_WKUP_DETECTOR_5 - 4'b 0001, // index[248] PINMUX_WKUP_DETECTOR_6 - 4'b 0001, // index[249] PINMUX_WKUP_DETECTOR_7 - 4'b 0001, // index[250] PINMUX_WKUP_DETECTOR_CNT_TH_0 - 4'b 0001, // index[251] PINMUX_WKUP_DETECTOR_CNT_TH_1 - 4'b 0001, // index[252] PINMUX_WKUP_DETECTOR_CNT_TH_2 - 4'b 0001, // index[253] PINMUX_WKUP_DETECTOR_CNT_TH_3 - 4'b 0001, // index[254] PINMUX_WKUP_DETECTOR_CNT_TH_4 - 4'b 0001, // index[255] PINMUX_WKUP_DETECTOR_CNT_TH_5 - 4'b 0001, // index[256] PINMUX_WKUP_DETECTOR_CNT_TH_6 - 4'b 0001, // index[257] PINMUX_WKUP_DETECTOR_CNT_TH_7 - 4'b 0001, // index[258] PINMUX_WKUP_DETECTOR_PADSEL_0 - 4'b 0001, // index[259] PINMUX_WKUP_DETECTOR_PADSEL_1 - 4'b 0001, // index[260] PINMUX_WKUP_DETECTOR_PADSEL_2 - 4'b 0001, // index[261] PINMUX_WKUP_DETECTOR_PADSEL_3 - 4'b 0001, // index[262] PINMUX_WKUP_DETECTOR_PADSEL_4 - 4'b 0001, // index[263] PINMUX_WKUP_DETECTOR_PADSEL_5 - 4'b 0001, // index[264] PINMUX_WKUP_DETECTOR_PADSEL_6 - 4'b 0001, // index[265] PINMUX_WKUP_DETECTOR_PADSEL_7 - 4'b 0001 // index[266] PINMUX_WKUP_CAUSE + 4'b 0001, // index[130] PINMUX_MIO_PAD_ATTR_REGWEN_0 + 4'b 0001, // index[131] PINMUX_MIO_PAD_ATTR_REGWEN_1 + 4'b 0001, // index[132] PINMUX_MIO_PAD_ATTR_REGWEN_2 + 4'b 0001, // index[133] PINMUX_MIO_PAD_ATTR_REGWEN_3 + 4'b 0001, // index[134] PINMUX_MIO_PAD_ATTR_REGWEN_4 + 4'b 0001, // index[135] PINMUX_MIO_PAD_ATTR_REGWEN_5 + 4'b 0001, // index[136] PINMUX_MIO_PAD_ATTR_REGWEN_6 + 4'b 0001, // index[137] PINMUX_MIO_PAD_ATTR_REGWEN_7 + 4'b 0001, // index[138] PINMUX_MIO_PAD_ATTR_REGWEN_8 + 4'b 0001, // index[139] PINMUX_MIO_PAD_ATTR_REGWEN_9 + 4'b 0001, // index[140] PINMUX_MIO_PAD_ATTR_REGWEN_10 + 4'b 0001, // index[141] PINMUX_MIO_PAD_ATTR_REGWEN_11 + 4'b 0001, // index[142] PINMUX_MIO_PAD_ATTR_REGWEN_12 + 4'b 0001, // index[143] PINMUX_MIO_PAD_ATTR_REGWEN_13 + 4'b 0001, // index[144] PINMUX_MIO_PAD_ATTR_REGWEN_14 + 4'b 0001, // index[145] PINMUX_MIO_PAD_ATTR_REGWEN_15 + 4'b 0001, // index[146] PINMUX_MIO_PAD_ATTR_REGWEN_16 + 4'b 0001, // index[147] PINMUX_MIO_PAD_ATTR_REGWEN_17 + 4'b 0001, // index[148] PINMUX_MIO_PAD_ATTR_REGWEN_18 + 4'b 0001, // index[149] PINMUX_MIO_PAD_ATTR_REGWEN_19 + 4'b 0001, // index[150] PINMUX_MIO_PAD_ATTR_REGWEN_20 + 4'b 0001, // index[151] PINMUX_MIO_PAD_ATTR_REGWEN_21 + 4'b 0001, // index[152] PINMUX_MIO_PAD_ATTR_REGWEN_22 + 4'b 0001, // index[153] PINMUX_MIO_PAD_ATTR_REGWEN_23 + 4'b 0001, // index[154] PINMUX_MIO_PAD_ATTR_REGWEN_24 + 4'b 0001, // index[155] PINMUX_MIO_PAD_ATTR_REGWEN_25 + 4'b 0001, // index[156] PINMUX_MIO_PAD_ATTR_REGWEN_26 + 4'b 0001, // index[157] PINMUX_MIO_PAD_ATTR_REGWEN_27 + 4'b 0001, // index[158] PINMUX_MIO_PAD_ATTR_REGWEN_28 + 4'b 0001, // index[159] PINMUX_MIO_PAD_ATTR_REGWEN_29 + 4'b 0001, // index[160] PINMUX_MIO_PAD_ATTR_REGWEN_30 + 4'b 0001, // index[161] PINMUX_MIO_PAD_ATTR_REGWEN_31 + 4'b 0011, // index[162] PINMUX_MIO_PAD_ATTR_0 + 4'b 0011, // index[163] PINMUX_MIO_PAD_ATTR_1 + 4'b 0011, // index[164] PINMUX_MIO_PAD_ATTR_2 + 4'b 0011, // index[165] PINMUX_MIO_PAD_ATTR_3 + 4'b 0011, // index[166] PINMUX_MIO_PAD_ATTR_4 + 4'b 0011, // index[167] PINMUX_MIO_PAD_ATTR_5 + 4'b 0011, // index[168] PINMUX_MIO_PAD_ATTR_6 + 4'b 0011, // index[169] PINMUX_MIO_PAD_ATTR_7 + 4'b 0011, // index[170] PINMUX_MIO_PAD_ATTR_8 + 4'b 0011, // index[171] PINMUX_MIO_PAD_ATTR_9 + 4'b 0011, // index[172] PINMUX_MIO_PAD_ATTR_10 + 4'b 0011, // index[173] PINMUX_MIO_PAD_ATTR_11 + 4'b 0011, // index[174] PINMUX_MIO_PAD_ATTR_12 + 4'b 0011, // index[175] PINMUX_MIO_PAD_ATTR_13 + 4'b 0011, // index[176] PINMUX_MIO_PAD_ATTR_14 + 4'b 0011, // index[177] PINMUX_MIO_PAD_ATTR_15 + 4'b 0011, // index[178] PINMUX_MIO_PAD_ATTR_16 + 4'b 0011, // index[179] PINMUX_MIO_PAD_ATTR_17 + 4'b 0011, // index[180] PINMUX_MIO_PAD_ATTR_18 + 4'b 0011, // index[181] PINMUX_MIO_PAD_ATTR_19 + 4'b 0011, // index[182] PINMUX_MIO_PAD_ATTR_20 + 4'b 0011, // index[183] PINMUX_MIO_PAD_ATTR_21 + 4'b 0011, // index[184] PINMUX_MIO_PAD_ATTR_22 + 4'b 0011, // index[185] PINMUX_MIO_PAD_ATTR_23 + 4'b 0011, // index[186] PINMUX_MIO_PAD_ATTR_24 + 4'b 0011, // index[187] PINMUX_MIO_PAD_ATTR_25 + 4'b 0011, // index[188] PINMUX_MIO_PAD_ATTR_26 + 4'b 0011, // index[189] PINMUX_MIO_PAD_ATTR_27 + 4'b 0011, // index[190] PINMUX_MIO_PAD_ATTR_28 + 4'b 0011, // index[191] PINMUX_MIO_PAD_ATTR_29 + 4'b 0011, // index[192] PINMUX_MIO_PAD_ATTR_30 + 4'b 0011, // index[193] PINMUX_MIO_PAD_ATTR_31 + 4'b 0001, // index[194] PINMUX_DIO_PAD_ATTR_REGWEN_0 + 4'b 0001, // index[195] PINMUX_DIO_PAD_ATTR_REGWEN_1 + 4'b 0001, // index[196] PINMUX_DIO_PAD_ATTR_REGWEN_2 + 4'b 0001, // index[197] PINMUX_DIO_PAD_ATTR_REGWEN_3 + 4'b 0001, // index[198] PINMUX_DIO_PAD_ATTR_REGWEN_4 + 4'b 0001, // index[199] PINMUX_DIO_PAD_ATTR_REGWEN_5 + 4'b 0001, // index[200] PINMUX_DIO_PAD_ATTR_REGWEN_6 + 4'b 0001, // index[201] PINMUX_DIO_PAD_ATTR_REGWEN_7 + 4'b 0001, // index[202] PINMUX_DIO_PAD_ATTR_REGWEN_8 + 4'b 0001, // index[203] PINMUX_DIO_PAD_ATTR_REGWEN_9 + 4'b 0001, // index[204] PINMUX_DIO_PAD_ATTR_REGWEN_10 + 4'b 0001, // index[205] PINMUX_DIO_PAD_ATTR_REGWEN_11 + 4'b 0001, // index[206] PINMUX_DIO_PAD_ATTR_REGWEN_12 + 4'b 0001, // index[207] PINMUX_DIO_PAD_ATTR_REGWEN_13 + 4'b 0001, // index[208] PINMUX_DIO_PAD_ATTR_REGWEN_14 + 4'b 0001, // index[209] PINMUX_DIO_PAD_ATTR_REGWEN_15 + 4'b 0011, // index[210] PINMUX_DIO_PAD_ATTR_0 + 4'b 0011, // index[211] PINMUX_DIO_PAD_ATTR_1 + 4'b 0011, // index[212] PINMUX_DIO_PAD_ATTR_2 + 4'b 0011, // index[213] PINMUX_DIO_PAD_ATTR_3 + 4'b 0011, // index[214] PINMUX_DIO_PAD_ATTR_4 + 4'b 0011, // index[215] PINMUX_DIO_PAD_ATTR_5 + 4'b 0011, // index[216] PINMUX_DIO_PAD_ATTR_6 + 4'b 0011, // index[217] PINMUX_DIO_PAD_ATTR_7 + 4'b 0011, // index[218] PINMUX_DIO_PAD_ATTR_8 + 4'b 0011, // index[219] PINMUX_DIO_PAD_ATTR_9 + 4'b 0011, // index[220] PINMUX_DIO_PAD_ATTR_10 + 4'b 0011, // index[221] PINMUX_DIO_PAD_ATTR_11 + 4'b 0011, // index[222] PINMUX_DIO_PAD_ATTR_12 + 4'b 0011, // index[223] PINMUX_DIO_PAD_ATTR_13 + 4'b 0011, // index[224] PINMUX_DIO_PAD_ATTR_14 + 4'b 0011, // index[225] PINMUX_DIO_PAD_ATTR_15 + 4'b 1111, // index[226] PINMUX_MIO_PAD_SLEEP_STATUS + 4'b 0001, // index[227] PINMUX_MIO_PAD_SLEEP_REGWEN_0 + 4'b 0001, // index[228] PINMUX_MIO_PAD_SLEEP_REGWEN_1 + 4'b 0001, // index[229] PINMUX_MIO_PAD_SLEEP_REGWEN_2 + 4'b 0001, // index[230] PINMUX_MIO_PAD_SLEEP_REGWEN_3 + 4'b 0001, // index[231] PINMUX_MIO_PAD_SLEEP_REGWEN_4 + 4'b 0001, // index[232] PINMUX_MIO_PAD_SLEEP_REGWEN_5 + 4'b 0001, // index[233] PINMUX_MIO_PAD_SLEEP_REGWEN_6 + 4'b 0001, // index[234] PINMUX_MIO_PAD_SLEEP_REGWEN_7 + 4'b 0001, // index[235] PINMUX_MIO_PAD_SLEEP_REGWEN_8 + 4'b 0001, // index[236] PINMUX_MIO_PAD_SLEEP_REGWEN_9 + 4'b 0001, // index[237] PINMUX_MIO_PAD_SLEEP_REGWEN_10 + 4'b 0001, // index[238] PINMUX_MIO_PAD_SLEEP_REGWEN_11 + 4'b 0001, // index[239] PINMUX_MIO_PAD_SLEEP_REGWEN_12 + 4'b 0001, // index[240] PINMUX_MIO_PAD_SLEEP_REGWEN_13 + 4'b 0001, // index[241] PINMUX_MIO_PAD_SLEEP_REGWEN_14 + 4'b 0001, // index[242] PINMUX_MIO_PAD_SLEEP_REGWEN_15 + 4'b 0001, // index[243] PINMUX_MIO_PAD_SLEEP_REGWEN_16 + 4'b 0001, // index[244] PINMUX_MIO_PAD_SLEEP_REGWEN_17 + 4'b 0001, // index[245] PINMUX_MIO_PAD_SLEEP_REGWEN_18 + 4'b 0001, // index[246] PINMUX_MIO_PAD_SLEEP_REGWEN_19 + 4'b 0001, // index[247] PINMUX_MIO_PAD_SLEEP_REGWEN_20 + 4'b 0001, // index[248] PINMUX_MIO_PAD_SLEEP_REGWEN_21 + 4'b 0001, // index[249] PINMUX_MIO_PAD_SLEEP_REGWEN_22 + 4'b 0001, // index[250] PINMUX_MIO_PAD_SLEEP_REGWEN_23 + 4'b 0001, // index[251] PINMUX_MIO_PAD_SLEEP_REGWEN_24 + 4'b 0001, // index[252] PINMUX_MIO_PAD_SLEEP_REGWEN_25 + 4'b 0001, // index[253] PINMUX_MIO_PAD_SLEEP_REGWEN_26 + 4'b 0001, // index[254] PINMUX_MIO_PAD_SLEEP_REGWEN_27 + 4'b 0001, // index[255] PINMUX_MIO_PAD_SLEEP_REGWEN_28 + 4'b 0001, // index[256] PINMUX_MIO_PAD_SLEEP_REGWEN_29 + 4'b 0001, // index[257] PINMUX_MIO_PAD_SLEEP_REGWEN_30 + 4'b 0001, // index[258] PINMUX_MIO_PAD_SLEEP_REGWEN_31 + 4'b 0001, // index[259] PINMUX_MIO_PAD_SLEEP_EN_0 + 4'b 0001, // index[260] PINMUX_MIO_PAD_SLEEP_EN_1 + 4'b 0001, // index[261] PINMUX_MIO_PAD_SLEEP_EN_2 + 4'b 0001, // index[262] PINMUX_MIO_PAD_SLEEP_EN_3 + 4'b 0001, // index[263] PINMUX_MIO_PAD_SLEEP_EN_4 + 4'b 0001, // index[264] PINMUX_MIO_PAD_SLEEP_EN_5 + 4'b 0001, // index[265] PINMUX_MIO_PAD_SLEEP_EN_6 + 4'b 0001, // index[266] PINMUX_MIO_PAD_SLEEP_EN_7 + 4'b 0001, // index[267] PINMUX_MIO_PAD_SLEEP_EN_8 + 4'b 0001, // index[268] PINMUX_MIO_PAD_SLEEP_EN_9 + 4'b 0001, // index[269] PINMUX_MIO_PAD_SLEEP_EN_10 + 4'b 0001, // index[270] PINMUX_MIO_PAD_SLEEP_EN_11 + 4'b 0001, // index[271] PINMUX_MIO_PAD_SLEEP_EN_12 + 4'b 0001, // index[272] PINMUX_MIO_PAD_SLEEP_EN_13 + 4'b 0001, // index[273] PINMUX_MIO_PAD_SLEEP_EN_14 + 4'b 0001, // index[274] PINMUX_MIO_PAD_SLEEP_EN_15 + 4'b 0001, // index[275] PINMUX_MIO_PAD_SLEEP_EN_16 + 4'b 0001, // index[276] PINMUX_MIO_PAD_SLEEP_EN_17 + 4'b 0001, // index[277] PINMUX_MIO_PAD_SLEEP_EN_18 + 4'b 0001, // index[278] PINMUX_MIO_PAD_SLEEP_EN_19 + 4'b 0001, // index[279] PINMUX_MIO_PAD_SLEEP_EN_20 + 4'b 0001, // index[280] PINMUX_MIO_PAD_SLEEP_EN_21 + 4'b 0001, // index[281] PINMUX_MIO_PAD_SLEEP_EN_22 + 4'b 0001, // index[282] PINMUX_MIO_PAD_SLEEP_EN_23 + 4'b 0001, // index[283] PINMUX_MIO_PAD_SLEEP_EN_24 + 4'b 0001, // index[284] PINMUX_MIO_PAD_SLEEP_EN_25 + 4'b 0001, // index[285] PINMUX_MIO_PAD_SLEEP_EN_26 + 4'b 0001, // index[286] PINMUX_MIO_PAD_SLEEP_EN_27 + 4'b 0001, // index[287] PINMUX_MIO_PAD_SLEEP_EN_28 + 4'b 0001, // index[288] PINMUX_MIO_PAD_SLEEP_EN_29 + 4'b 0001, // index[289] PINMUX_MIO_PAD_SLEEP_EN_30 + 4'b 0001, // index[290] PINMUX_MIO_PAD_SLEEP_EN_31 + 4'b 0001, // index[291] PINMUX_MIO_PAD_SLEEP_MODE_0 + 4'b 0001, // index[292] PINMUX_MIO_PAD_SLEEP_MODE_1 + 4'b 0001, // index[293] PINMUX_MIO_PAD_SLEEP_MODE_2 + 4'b 0001, // index[294] PINMUX_MIO_PAD_SLEEP_MODE_3 + 4'b 0001, // index[295] PINMUX_MIO_PAD_SLEEP_MODE_4 + 4'b 0001, // index[296] PINMUX_MIO_PAD_SLEEP_MODE_5 + 4'b 0001, // index[297] PINMUX_MIO_PAD_SLEEP_MODE_6 + 4'b 0001, // index[298] PINMUX_MIO_PAD_SLEEP_MODE_7 + 4'b 0001, // index[299] PINMUX_MIO_PAD_SLEEP_MODE_8 + 4'b 0001, // index[300] PINMUX_MIO_PAD_SLEEP_MODE_9 + 4'b 0001, // index[301] PINMUX_MIO_PAD_SLEEP_MODE_10 + 4'b 0001, // index[302] PINMUX_MIO_PAD_SLEEP_MODE_11 + 4'b 0001, // index[303] PINMUX_MIO_PAD_SLEEP_MODE_12 + 4'b 0001, // index[304] PINMUX_MIO_PAD_SLEEP_MODE_13 + 4'b 0001, // index[305] PINMUX_MIO_PAD_SLEEP_MODE_14 + 4'b 0001, // index[306] PINMUX_MIO_PAD_SLEEP_MODE_15 + 4'b 0001, // index[307] PINMUX_MIO_PAD_SLEEP_MODE_16 + 4'b 0001, // index[308] PINMUX_MIO_PAD_SLEEP_MODE_17 + 4'b 0001, // index[309] PINMUX_MIO_PAD_SLEEP_MODE_18 + 4'b 0001, // index[310] PINMUX_MIO_PAD_SLEEP_MODE_19 + 4'b 0001, // index[311] PINMUX_MIO_PAD_SLEEP_MODE_20 + 4'b 0001, // index[312] PINMUX_MIO_PAD_SLEEP_MODE_21 + 4'b 0001, // index[313] PINMUX_MIO_PAD_SLEEP_MODE_22 + 4'b 0001, // index[314] PINMUX_MIO_PAD_SLEEP_MODE_23 + 4'b 0001, // index[315] PINMUX_MIO_PAD_SLEEP_MODE_24 + 4'b 0001, // index[316] PINMUX_MIO_PAD_SLEEP_MODE_25 + 4'b 0001, // index[317] PINMUX_MIO_PAD_SLEEP_MODE_26 + 4'b 0001, // index[318] PINMUX_MIO_PAD_SLEEP_MODE_27 + 4'b 0001, // index[319] PINMUX_MIO_PAD_SLEEP_MODE_28 + 4'b 0001, // index[320] PINMUX_MIO_PAD_SLEEP_MODE_29 + 4'b 0001, // index[321] PINMUX_MIO_PAD_SLEEP_MODE_30 + 4'b 0001, // index[322] PINMUX_MIO_PAD_SLEEP_MODE_31 + 4'b 0011, // index[323] PINMUX_DIO_PAD_SLEEP_STATUS + 4'b 0001, // index[324] PINMUX_DIO_PAD_SLEEP_REGWEN_0 + 4'b 0001, // index[325] PINMUX_DIO_PAD_SLEEP_REGWEN_1 + 4'b 0001, // index[326] PINMUX_DIO_PAD_SLEEP_REGWEN_2 + 4'b 0001, // index[327] PINMUX_DIO_PAD_SLEEP_REGWEN_3 + 4'b 0001, // index[328] PINMUX_DIO_PAD_SLEEP_REGWEN_4 + 4'b 0001, // index[329] PINMUX_DIO_PAD_SLEEP_REGWEN_5 + 4'b 0001, // index[330] PINMUX_DIO_PAD_SLEEP_REGWEN_6 + 4'b 0001, // index[331] PINMUX_DIO_PAD_SLEEP_REGWEN_7 + 4'b 0001, // index[332] PINMUX_DIO_PAD_SLEEP_REGWEN_8 + 4'b 0001, // index[333] PINMUX_DIO_PAD_SLEEP_REGWEN_9 + 4'b 0001, // index[334] PINMUX_DIO_PAD_SLEEP_REGWEN_10 + 4'b 0001, // index[335] PINMUX_DIO_PAD_SLEEP_REGWEN_11 + 4'b 0001, // index[336] PINMUX_DIO_PAD_SLEEP_REGWEN_12 + 4'b 0001, // index[337] PINMUX_DIO_PAD_SLEEP_REGWEN_13 + 4'b 0001, // index[338] PINMUX_DIO_PAD_SLEEP_REGWEN_14 + 4'b 0001, // index[339] PINMUX_DIO_PAD_SLEEP_REGWEN_15 + 4'b 0001, // index[340] PINMUX_DIO_PAD_SLEEP_EN_0 + 4'b 0001, // index[341] PINMUX_DIO_PAD_SLEEP_EN_1 + 4'b 0001, // index[342] PINMUX_DIO_PAD_SLEEP_EN_2 + 4'b 0001, // index[343] PINMUX_DIO_PAD_SLEEP_EN_3 + 4'b 0001, // index[344] PINMUX_DIO_PAD_SLEEP_EN_4 + 4'b 0001, // index[345] PINMUX_DIO_PAD_SLEEP_EN_5 + 4'b 0001, // index[346] PINMUX_DIO_PAD_SLEEP_EN_6 + 4'b 0001, // index[347] PINMUX_DIO_PAD_SLEEP_EN_7 + 4'b 0001, // index[348] PINMUX_DIO_PAD_SLEEP_EN_8 + 4'b 0001, // index[349] PINMUX_DIO_PAD_SLEEP_EN_9 + 4'b 0001, // index[350] PINMUX_DIO_PAD_SLEEP_EN_10 + 4'b 0001, // index[351] PINMUX_DIO_PAD_SLEEP_EN_11 + 4'b 0001, // index[352] PINMUX_DIO_PAD_SLEEP_EN_12 + 4'b 0001, // index[353] PINMUX_DIO_PAD_SLEEP_EN_13 + 4'b 0001, // index[354] PINMUX_DIO_PAD_SLEEP_EN_14 + 4'b 0001, // index[355] PINMUX_DIO_PAD_SLEEP_EN_15 + 4'b 0001, // index[356] PINMUX_DIO_PAD_SLEEP_MODE_0 + 4'b 0001, // index[357] PINMUX_DIO_PAD_SLEEP_MODE_1 + 4'b 0001, // index[358] PINMUX_DIO_PAD_SLEEP_MODE_2 + 4'b 0001, // index[359] PINMUX_DIO_PAD_SLEEP_MODE_3 + 4'b 0001, // index[360] PINMUX_DIO_PAD_SLEEP_MODE_4 + 4'b 0001, // index[361] PINMUX_DIO_PAD_SLEEP_MODE_5 + 4'b 0001, // index[362] PINMUX_DIO_PAD_SLEEP_MODE_6 + 4'b 0001, // index[363] PINMUX_DIO_PAD_SLEEP_MODE_7 + 4'b 0001, // index[364] PINMUX_DIO_PAD_SLEEP_MODE_8 + 4'b 0001, // index[365] PINMUX_DIO_PAD_SLEEP_MODE_9 + 4'b 0001, // index[366] PINMUX_DIO_PAD_SLEEP_MODE_10 + 4'b 0001, // index[367] PINMUX_DIO_PAD_SLEEP_MODE_11 + 4'b 0001, // index[368] PINMUX_DIO_PAD_SLEEP_MODE_12 + 4'b 0001, // index[369] PINMUX_DIO_PAD_SLEEP_MODE_13 + 4'b 0001, // index[370] PINMUX_DIO_PAD_SLEEP_MODE_14 + 4'b 0001, // index[371] PINMUX_DIO_PAD_SLEEP_MODE_15 + 4'b 0001, // index[372] PINMUX_WKUP_DETECTOR_REGWEN_0 + 4'b 0001, // index[373] PINMUX_WKUP_DETECTOR_REGWEN_1 + 4'b 0001, // index[374] PINMUX_WKUP_DETECTOR_REGWEN_2 + 4'b 0001, // index[375] PINMUX_WKUP_DETECTOR_REGWEN_3 + 4'b 0001, // index[376] PINMUX_WKUP_DETECTOR_REGWEN_4 + 4'b 0001, // index[377] PINMUX_WKUP_DETECTOR_REGWEN_5 + 4'b 0001, // index[378] PINMUX_WKUP_DETECTOR_REGWEN_6 + 4'b 0001, // index[379] PINMUX_WKUP_DETECTOR_REGWEN_7 + 4'b 0001, // index[380] PINMUX_WKUP_DETECTOR_EN_0 + 4'b 0001, // index[381] PINMUX_WKUP_DETECTOR_EN_1 + 4'b 0001, // index[382] PINMUX_WKUP_DETECTOR_EN_2 + 4'b 0001, // index[383] PINMUX_WKUP_DETECTOR_EN_3 + 4'b 0001, // index[384] PINMUX_WKUP_DETECTOR_EN_4 + 4'b 0001, // index[385] PINMUX_WKUP_DETECTOR_EN_5 + 4'b 0001, // index[386] PINMUX_WKUP_DETECTOR_EN_6 + 4'b 0001, // index[387] PINMUX_WKUP_DETECTOR_EN_7 + 4'b 0001, // index[388] PINMUX_WKUP_DETECTOR_0 + 4'b 0001, // index[389] PINMUX_WKUP_DETECTOR_1 + 4'b 0001, // index[390] PINMUX_WKUP_DETECTOR_2 + 4'b 0001, // index[391] PINMUX_WKUP_DETECTOR_3 + 4'b 0001, // index[392] PINMUX_WKUP_DETECTOR_4 + 4'b 0001, // index[393] PINMUX_WKUP_DETECTOR_5 + 4'b 0001, // index[394] PINMUX_WKUP_DETECTOR_6 + 4'b 0001, // index[395] PINMUX_WKUP_DETECTOR_7 + 4'b 0001, // index[396] PINMUX_WKUP_DETECTOR_CNT_TH_0 + 4'b 0001, // index[397] PINMUX_WKUP_DETECTOR_CNT_TH_1 + 4'b 0001, // index[398] PINMUX_WKUP_DETECTOR_CNT_TH_2 + 4'b 0001, // index[399] PINMUX_WKUP_DETECTOR_CNT_TH_3 + 4'b 0001, // index[400] PINMUX_WKUP_DETECTOR_CNT_TH_4 + 4'b 0001, // index[401] PINMUX_WKUP_DETECTOR_CNT_TH_5 + 4'b 0001, // index[402] PINMUX_WKUP_DETECTOR_CNT_TH_6 + 4'b 0001, // index[403] PINMUX_WKUP_DETECTOR_CNT_TH_7 + 4'b 0001, // index[404] PINMUX_WKUP_DETECTOR_PADSEL_0 + 4'b 0001, // index[405] PINMUX_WKUP_DETECTOR_PADSEL_1 + 4'b 0001, // index[406] PINMUX_WKUP_DETECTOR_PADSEL_2 + 4'b 0001, // index[407] PINMUX_WKUP_DETECTOR_PADSEL_3 + 4'b 0001, // index[408] PINMUX_WKUP_DETECTOR_PADSEL_4 + 4'b 0001, // index[409] PINMUX_WKUP_DETECTOR_PADSEL_5 + 4'b 0001, // index[410] PINMUX_WKUP_DETECTOR_PADSEL_6 + 4'b 0001, // index[411] PINMUX_WKUP_DETECTOR_PADSEL_7 + 4'b 0001 // index[412] PINMUX_WKUP_CAUSE }; endpackage
diff --git a/hw/ip/pinmux/rtl/pinmux_reg_top.sv b/hw/ip/pinmux/rtl/pinmux_reg_top.sv index cd019a0..6c0bf39 100644 --- a/hw/ip/pinmux/rtl/pinmux_reg_top.sv +++ b/hw/ip/pinmux/rtl/pinmux_reg_top.sv
@@ -461,310 +461,918 @@ logic [5:0] mio_outsel_31_qs; logic [5:0] mio_outsel_31_wd; logic mio_outsel_31_we; - logic mio_out_sleep_regwen_0_qs; - logic mio_out_sleep_regwen_0_wd; - logic mio_out_sleep_regwen_0_we; - logic mio_out_sleep_regwen_1_qs; - logic mio_out_sleep_regwen_1_wd; - logic mio_out_sleep_regwen_1_we; - logic mio_out_sleep_regwen_2_qs; - logic mio_out_sleep_regwen_2_wd; - logic mio_out_sleep_regwen_2_we; - logic mio_out_sleep_regwen_3_qs; - logic mio_out_sleep_regwen_3_wd; - logic mio_out_sleep_regwen_3_we; - logic mio_out_sleep_regwen_4_qs; - logic mio_out_sleep_regwen_4_wd; - logic mio_out_sleep_regwen_4_we; - logic mio_out_sleep_regwen_5_qs; - logic mio_out_sleep_regwen_5_wd; - logic mio_out_sleep_regwen_5_we; - logic mio_out_sleep_regwen_6_qs; - logic mio_out_sleep_regwen_6_wd; - logic mio_out_sleep_regwen_6_we; - logic mio_out_sleep_regwen_7_qs; - logic mio_out_sleep_regwen_7_wd; - logic mio_out_sleep_regwen_7_we; - logic mio_out_sleep_regwen_8_qs; - logic mio_out_sleep_regwen_8_wd; - logic mio_out_sleep_regwen_8_we; - logic mio_out_sleep_regwen_9_qs; - logic mio_out_sleep_regwen_9_wd; - logic mio_out_sleep_regwen_9_we; - logic mio_out_sleep_regwen_10_qs; - logic mio_out_sleep_regwen_10_wd; - logic mio_out_sleep_regwen_10_we; - logic mio_out_sleep_regwen_11_qs; - logic mio_out_sleep_regwen_11_wd; - logic mio_out_sleep_regwen_11_we; - logic mio_out_sleep_regwen_12_qs; - logic mio_out_sleep_regwen_12_wd; - logic mio_out_sleep_regwen_12_we; - logic mio_out_sleep_regwen_13_qs; - logic mio_out_sleep_regwen_13_wd; - logic mio_out_sleep_regwen_13_we; - logic mio_out_sleep_regwen_14_qs; - logic mio_out_sleep_regwen_14_wd; - logic mio_out_sleep_regwen_14_we; - logic mio_out_sleep_regwen_15_qs; - logic mio_out_sleep_regwen_15_wd; - logic mio_out_sleep_regwen_15_we; - logic mio_out_sleep_regwen_16_qs; - logic mio_out_sleep_regwen_16_wd; - logic mio_out_sleep_regwen_16_we; - logic mio_out_sleep_regwen_17_qs; - logic mio_out_sleep_regwen_17_wd; - logic mio_out_sleep_regwen_17_we; - logic mio_out_sleep_regwen_18_qs; - logic mio_out_sleep_regwen_18_wd; - logic mio_out_sleep_regwen_18_we; - logic mio_out_sleep_regwen_19_qs; - logic mio_out_sleep_regwen_19_wd; - logic mio_out_sleep_regwen_19_we; - logic mio_out_sleep_regwen_20_qs; - logic mio_out_sleep_regwen_20_wd; - logic mio_out_sleep_regwen_20_we; - logic mio_out_sleep_regwen_21_qs; - logic mio_out_sleep_regwen_21_wd; - logic mio_out_sleep_regwen_21_we; - logic mio_out_sleep_regwen_22_qs; - logic mio_out_sleep_regwen_22_wd; - logic mio_out_sleep_regwen_22_we; - logic mio_out_sleep_regwen_23_qs; - logic mio_out_sleep_regwen_23_wd; - logic mio_out_sleep_regwen_23_we; - logic mio_out_sleep_regwen_24_qs; - logic mio_out_sleep_regwen_24_wd; - logic mio_out_sleep_regwen_24_we; - logic mio_out_sleep_regwen_25_qs; - logic mio_out_sleep_regwen_25_wd; - logic mio_out_sleep_regwen_25_we; - logic mio_out_sleep_regwen_26_qs; - logic mio_out_sleep_regwen_26_wd; - logic mio_out_sleep_regwen_26_we; - logic mio_out_sleep_regwen_27_qs; - logic mio_out_sleep_regwen_27_wd; - logic mio_out_sleep_regwen_27_we; - logic mio_out_sleep_regwen_28_qs; - logic mio_out_sleep_regwen_28_wd; - logic mio_out_sleep_regwen_28_we; - logic mio_out_sleep_regwen_29_qs; - logic mio_out_sleep_regwen_29_wd; - logic mio_out_sleep_regwen_29_we; - logic mio_out_sleep_regwen_30_qs; - logic mio_out_sleep_regwen_30_wd; - logic mio_out_sleep_regwen_30_we; - logic mio_out_sleep_regwen_31_qs; - logic mio_out_sleep_regwen_31_wd; - logic mio_out_sleep_regwen_31_we; - logic [1:0] mio_out_sleep_val_0_qs; - logic [1:0] mio_out_sleep_val_0_wd; - logic mio_out_sleep_val_0_we; - logic [1:0] mio_out_sleep_val_1_qs; - logic [1:0] mio_out_sleep_val_1_wd; - logic mio_out_sleep_val_1_we; - logic [1:0] mio_out_sleep_val_2_qs; - logic [1:0] mio_out_sleep_val_2_wd; - logic mio_out_sleep_val_2_we; - logic [1:0] mio_out_sleep_val_3_qs; - logic [1:0] mio_out_sleep_val_3_wd; - logic mio_out_sleep_val_3_we; - logic [1:0] mio_out_sleep_val_4_qs; - logic [1:0] mio_out_sleep_val_4_wd; - logic mio_out_sleep_val_4_we; - logic [1:0] mio_out_sleep_val_5_qs; - logic [1:0] mio_out_sleep_val_5_wd; - logic mio_out_sleep_val_5_we; - logic [1:0] mio_out_sleep_val_6_qs; - logic [1:0] mio_out_sleep_val_6_wd; - logic mio_out_sleep_val_6_we; - logic [1:0] mio_out_sleep_val_7_qs; - logic [1:0] mio_out_sleep_val_7_wd; - logic mio_out_sleep_val_7_we; - logic [1:0] mio_out_sleep_val_8_qs; - logic [1:0] mio_out_sleep_val_8_wd; - logic mio_out_sleep_val_8_we; - logic [1:0] mio_out_sleep_val_9_qs; - logic [1:0] mio_out_sleep_val_9_wd; - logic mio_out_sleep_val_9_we; - logic [1:0] mio_out_sleep_val_10_qs; - logic [1:0] mio_out_sleep_val_10_wd; - logic mio_out_sleep_val_10_we; - logic [1:0] mio_out_sleep_val_11_qs; - logic [1:0] mio_out_sleep_val_11_wd; - logic mio_out_sleep_val_11_we; - logic [1:0] mio_out_sleep_val_12_qs; - logic [1:0] mio_out_sleep_val_12_wd; - logic mio_out_sleep_val_12_we; - logic [1:0] mio_out_sleep_val_13_qs; - logic [1:0] mio_out_sleep_val_13_wd; - logic mio_out_sleep_val_13_we; - logic [1:0] mio_out_sleep_val_14_qs; - logic [1:0] mio_out_sleep_val_14_wd; - logic mio_out_sleep_val_14_we; - logic [1:0] mio_out_sleep_val_15_qs; - logic [1:0] mio_out_sleep_val_15_wd; - logic mio_out_sleep_val_15_we; - logic [1:0] mio_out_sleep_val_16_qs; - logic [1:0] mio_out_sleep_val_16_wd; - logic mio_out_sleep_val_16_we; - logic [1:0] mio_out_sleep_val_17_qs; - logic [1:0] mio_out_sleep_val_17_wd; - logic mio_out_sleep_val_17_we; - logic [1:0] mio_out_sleep_val_18_qs; - logic [1:0] mio_out_sleep_val_18_wd; - logic mio_out_sleep_val_18_we; - logic [1:0] mio_out_sleep_val_19_qs; - logic [1:0] mio_out_sleep_val_19_wd; - logic mio_out_sleep_val_19_we; - logic [1:0] mio_out_sleep_val_20_qs; - logic [1:0] mio_out_sleep_val_20_wd; - logic mio_out_sleep_val_20_we; - logic [1:0] mio_out_sleep_val_21_qs; - logic [1:0] mio_out_sleep_val_21_wd; - logic mio_out_sleep_val_21_we; - logic [1:0] mio_out_sleep_val_22_qs; - logic [1:0] mio_out_sleep_val_22_wd; - logic mio_out_sleep_val_22_we; - logic [1:0] mio_out_sleep_val_23_qs; - logic [1:0] mio_out_sleep_val_23_wd; - logic mio_out_sleep_val_23_we; - logic [1:0] mio_out_sleep_val_24_qs; - logic [1:0] mio_out_sleep_val_24_wd; - logic mio_out_sleep_val_24_we; - logic [1:0] mio_out_sleep_val_25_qs; - logic [1:0] mio_out_sleep_val_25_wd; - logic mio_out_sleep_val_25_we; - logic [1:0] mio_out_sleep_val_26_qs; - logic [1:0] mio_out_sleep_val_26_wd; - logic mio_out_sleep_val_26_we; - logic [1:0] mio_out_sleep_val_27_qs; - logic [1:0] mio_out_sleep_val_27_wd; - logic mio_out_sleep_val_27_we; - logic [1:0] mio_out_sleep_val_28_qs; - logic [1:0] mio_out_sleep_val_28_wd; - logic mio_out_sleep_val_28_we; - logic [1:0] mio_out_sleep_val_29_qs; - logic [1:0] mio_out_sleep_val_29_wd; - logic mio_out_sleep_val_29_we; - logic [1:0] mio_out_sleep_val_30_qs; - logic [1:0] mio_out_sleep_val_30_wd; - logic mio_out_sleep_val_30_we; - logic [1:0] mio_out_sleep_val_31_qs; - logic [1:0] mio_out_sleep_val_31_wd; - logic mio_out_sleep_val_31_we; - logic dio_out_sleep_regwen_0_qs; - logic dio_out_sleep_regwen_0_wd; - logic dio_out_sleep_regwen_0_we; - logic dio_out_sleep_regwen_1_qs; - logic dio_out_sleep_regwen_1_wd; - logic dio_out_sleep_regwen_1_we; - logic dio_out_sleep_regwen_2_qs; - logic dio_out_sleep_regwen_2_wd; - logic dio_out_sleep_regwen_2_we; - logic dio_out_sleep_regwen_3_qs; - logic dio_out_sleep_regwen_3_wd; - logic dio_out_sleep_regwen_3_we; - logic dio_out_sleep_regwen_4_qs; - logic dio_out_sleep_regwen_4_wd; - logic dio_out_sleep_regwen_4_we; - logic dio_out_sleep_regwen_5_qs; - logic dio_out_sleep_regwen_5_wd; - logic dio_out_sleep_regwen_5_we; - logic dio_out_sleep_regwen_6_qs; - logic dio_out_sleep_regwen_6_wd; - logic dio_out_sleep_regwen_6_we; - logic dio_out_sleep_regwen_7_qs; - logic dio_out_sleep_regwen_7_wd; - logic dio_out_sleep_regwen_7_we; - logic dio_out_sleep_regwen_8_qs; - logic dio_out_sleep_regwen_8_wd; - logic dio_out_sleep_regwen_8_we; - logic dio_out_sleep_regwen_9_qs; - logic dio_out_sleep_regwen_9_wd; - logic dio_out_sleep_regwen_9_we; - logic dio_out_sleep_regwen_10_qs; - logic dio_out_sleep_regwen_10_wd; - logic dio_out_sleep_regwen_10_we; - logic dio_out_sleep_regwen_11_qs; - logic dio_out_sleep_regwen_11_wd; - logic dio_out_sleep_regwen_11_we; - logic dio_out_sleep_regwen_12_qs; - logic dio_out_sleep_regwen_12_wd; - logic dio_out_sleep_regwen_12_we; - logic dio_out_sleep_regwen_13_qs; - logic dio_out_sleep_regwen_13_wd; - logic dio_out_sleep_regwen_13_we; - logic dio_out_sleep_regwen_14_qs; - logic dio_out_sleep_regwen_14_wd; - logic dio_out_sleep_regwen_14_we; - logic dio_out_sleep_regwen_15_qs; - logic dio_out_sleep_regwen_15_wd; - logic dio_out_sleep_regwen_15_we; - logic [1:0] dio_out_sleep_val_0_qs; - logic [1:0] dio_out_sleep_val_0_wd; - logic dio_out_sleep_val_0_we; - logic dio_out_sleep_val_0_re; - logic [1:0] dio_out_sleep_val_1_qs; - logic [1:0] dio_out_sleep_val_1_wd; - logic dio_out_sleep_val_1_we; - logic dio_out_sleep_val_1_re; - logic [1:0] dio_out_sleep_val_2_qs; - logic [1:0] dio_out_sleep_val_2_wd; - logic dio_out_sleep_val_2_we; - logic dio_out_sleep_val_2_re; - logic [1:0] dio_out_sleep_val_3_qs; - logic [1:0] dio_out_sleep_val_3_wd; - logic dio_out_sleep_val_3_we; - logic dio_out_sleep_val_3_re; - logic [1:0] dio_out_sleep_val_4_qs; - logic [1:0] dio_out_sleep_val_4_wd; - logic dio_out_sleep_val_4_we; - logic dio_out_sleep_val_4_re; - logic [1:0] dio_out_sleep_val_5_qs; - logic [1:0] dio_out_sleep_val_5_wd; - logic dio_out_sleep_val_5_we; - logic dio_out_sleep_val_5_re; - logic [1:0] dio_out_sleep_val_6_qs; - logic [1:0] dio_out_sleep_val_6_wd; - logic dio_out_sleep_val_6_we; - logic dio_out_sleep_val_6_re; - logic [1:0] dio_out_sleep_val_7_qs; - logic [1:0] dio_out_sleep_val_7_wd; - logic dio_out_sleep_val_7_we; - logic dio_out_sleep_val_7_re; - logic [1:0] dio_out_sleep_val_8_qs; - logic [1:0] dio_out_sleep_val_8_wd; - logic dio_out_sleep_val_8_we; - logic dio_out_sleep_val_8_re; - logic [1:0] dio_out_sleep_val_9_qs; - logic [1:0] dio_out_sleep_val_9_wd; - logic dio_out_sleep_val_9_we; - logic dio_out_sleep_val_9_re; - logic [1:0] dio_out_sleep_val_10_qs; - logic [1:0] dio_out_sleep_val_10_wd; - logic dio_out_sleep_val_10_we; - logic dio_out_sleep_val_10_re; - logic [1:0] dio_out_sleep_val_11_qs; - logic [1:0] dio_out_sleep_val_11_wd; - logic dio_out_sleep_val_11_we; - logic dio_out_sleep_val_11_re; - logic [1:0] dio_out_sleep_val_12_qs; - logic [1:0] dio_out_sleep_val_12_wd; - logic dio_out_sleep_val_12_we; - logic dio_out_sleep_val_12_re; - logic [1:0] dio_out_sleep_val_13_qs; - logic [1:0] dio_out_sleep_val_13_wd; - logic dio_out_sleep_val_13_we; - logic dio_out_sleep_val_13_re; - logic [1:0] dio_out_sleep_val_14_qs; - logic [1:0] dio_out_sleep_val_14_wd; - logic dio_out_sleep_val_14_we; - logic dio_out_sleep_val_14_re; - logic [1:0] dio_out_sleep_val_15_qs; - logic [1:0] dio_out_sleep_val_15_wd; - logic dio_out_sleep_val_15_we; - logic dio_out_sleep_val_15_re; + logic mio_pad_attr_regwen_0_qs; + logic mio_pad_attr_regwen_0_wd; + logic mio_pad_attr_regwen_0_we; + logic mio_pad_attr_regwen_1_qs; + logic mio_pad_attr_regwen_1_wd; + logic mio_pad_attr_regwen_1_we; + logic mio_pad_attr_regwen_2_qs; + logic mio_pad_attr_regwen_2_wd; + logic mio_pad_attr_regwen_2_we; + logic mio_pad_attr_regwen_3_qs; + logic mio_pad_attr_regwen_3_wd; + logic mio_pad_attr_regwen_3_we; + logic mio_pad_attr_regwen_4_qs; + logic mio_pad_attr_regwen_4_wd; + logic mio_pad_attr_regwen_4_we; + logic mio_pad_attr_regwen_5_qs; + logic mio_pad_attr_regwen_5_wd; + logic mio_pad_attr_regwen_5_we; + logic mio_pad_attr_regwen_6_qs; + logic mio_pad_attr_regwen_6_wd; + logic mio_pad_attr_regwen_6_we; + logic mio_pad_attr_regwen_7_qs; + logic mio_pad_attr_regwen_7_wd; + logic mio_pad_attr_regwen_7_we; + logic mio_pad_attr_regwen_8_qs; + logic mio_pad_attr_regwen_8_wd; + logic mio_pad_attr_regwen_8_we; + logic mio_pad_attr_regwen_9_qs; + logic mio_pad_attr_regwen_9_wd; + logic mio_pad_attr_regwen_9_we; + logic mio_pad_attr_regwen_10_qs; + logic mio_pad_attr_regwen_10_wd; + logic mio_pad_attr_regwen_10_we; + logic mio_pad_attr_regwen_11_qs; + logic mio_pad_attr_regwen_11_wd; + logic mio_pad_attr_regwen_11_we; + logic mio_pad_attr_regwen_12_qs; + logic mio_pad_attr_regwen_12_wd; + logic mio_pad_attr_regwen_12_we; + logic mio_pad_attr_regwen_13_qs; + logic mio_pad_attr_regwen_13_wd; + logic mio_pad_attr_regwen_13_we; + logic mio_pad_attr_regwen_14_qs; + logic mio_pad_attr_regwen_14_wd; + logic mio_pad_attr_regwen_14_we; + logic mio_pad_attr_regwen_15_qs; + logic mio_pad_attr_regwen_15_wd; + logic mio_pad_attr_regwen_15_we; + logic mio_pad_attr_regwen_16_qs; + logic mio_pad_attr_regwen_16_wd; + logic mio_pad_attr_regwen_16_we; + logic mio_pad_attr_regwen_17_qs; + logic mio_pad_attr_regwen_17_wd; + logic mio_pad_attr_regwen_17_we; + logic mio_pad_attr_regwen_18_qs; + logic mio_pad_attr_regwen_18_wd; + logic mio_pad_attr_regwen_18_we; + logic mio_pad_attr_regwen_19_qs; + logic mio_pad_attr_regwen_19_wd; + logic mio_pad_attr_regwen_19_we; + logic mio_pad_attr_regwen_20_qs; + logic mio_pad_attr_regwen_20_wd; + logic mio_pad_attr_regwen_20_we; + logic mio_pad_attr_regwen_21_qs; + logic mio_pad_attr_regwen_21_wd; + logic mio_pad_attr_regwen_21_we; + logic mio_pad_attr_regwen_22_qs; + logic mio_pad_attr_regwen_22_wd; + logic mio_pad_attr_regwen_22_we; + logic mio_pad_attr_regwen_23_qs; + logic mio_pad_attr_regwen_23_wd; + logic mio_pad_attr_regwen_23_we; + logic mio_pad_attr_regwen_24_qs; + logic mio_pad_attr_regwen_24_wd; + logic mio_pad_attr_regwen_24_we; + logic mio_pad_attr_regwen_25_qs; + logic mio_pad_attr_regwen_25_wd; + logic mio_pad_attr_regwen_25_we; + logic mio_pad_attr_regwen_26_qs; + logic mio_pad_attr_regwen_26_wd; + logic mio_pad_attr_regwen_26_we; + logic mio_pad_attr_regwen_27_qs; + logic mio_pad_attr_regwen_27_wd; + logic mio_pad_attr_regwen_27_we; + logic mio_pad_attr_regwen_28_qs; + logic mio_pad_attr_regwen_28_wd; + logic mio_pad_attr_regwen_28_we; + logic mio_pad_attr_regwen_29_qs; + logic mio_pad_attr_regwen_29_wd; + logic mio_pad_attr_regwen_29_we; + logic mio_pad_attr_regwen_30_qs; + logic mio_pad_attr_regwen_30_wd; + logic mio_pad_attr_regwen_30_we; + logic mio_pad_attr_regwen_31_qs; + logic mio_pad_attr_regwen_31_wd; + logic mio_pad_attr_regwen_31_we; + logic [9:0] mio_pad_attr_0_qs; + logic [9:0] mio_pad_attr_0_wd; + logic mio_pad_attr_0_we; + logic mio_pad_attr_0_re; + logic [9:0] mio_pad_attr_1_qs; + logic [9:0] mio_pad_attr_1_wd; + logic mio_pad_attr_1_we; + logic mio_pad_attr_1_re; + logic [9:0] mio_pad_attr_2_qs; + logic [9:0] mio_pad_attr_2_wd; + logic mio_pad_attr_2_we; + logic mio_pad_attr_2_re; + logic [9:0] mio_pad_attr_3_qs; + logic [9:0] mio_pad_attr_3_wd; + logic mio_pad_attr_3_we; + logic mio_pad_attr_3_re; + logic [9:0] mio_pad_attr_4_qs; + logic [9:0] mio_pad_attr_4_wd; + logic mio_pad_attr_4_we; + logic mio_pad_attr_4_re; + logic [9:0] mio_pad_attr_5_qs; + logic [9:0] mio_pad_attr_5_wd; + logic mio_pad_attr_5_we; + logic mio_pad_attr_5_re; + logic [9:0] mio_pad_attr_6_qs; + logic [9:0] mio_pad_attr_6_wd; + logic mio_pad_attr_6_we; + logic mio_pad_attr_6_re; + logic [9:0] mio_pad_attr_7_qs; + logic [9:0] mio_pad_attr_7_wd; + logic mio_pad_attr_7_we; + logic mio_pad_attr_7_re; + logic [9:0] mio_pad_attr_8_qs; + logic [9:0] mio_pad_attr_8_wd; + logic mio_pad_attr_8_we; + logic mio_pad_attr_8_re; + logic [9:0] mio_pad_attr_9_qs; + logic [9:0] mio_pad_attr_9_wd; + logic mio_pad_attr_9_we; + logic mio_pad_attr_9_re; + logic [9:0] mio_pad_attr_10_qs; + logic [9:0] mio_pad_attr_10_wd; + logic mio_pad_attr_10_we; + logic mio_pad_attr_10_re; + logic [9:0] mio_pad_attr_11_qs; + logic [9:0] mio_pad_attr_11_wd; + logic mio_pad_attr_11_we; + logic mio_pad_attr_11_re; + logic [9:0] mio_pad_attr_12_qs; + logic [9:0] mio_pad_attr_12_wd; + logic mio_pad_attr_12_we; + logic mio_pad_attr_12_re; + logic [9:0] mio_pad_attr_13_qs; + logic [9:0] mio_pad_attr_13_wd; + logic mio_pad_attr_13_we; + logic mio_pad_attr_13_re; + logic [9:0] mio_pad_attr_14_qs; + logic [9:0] mio_pad_attr_14_wd; + logic mio_pad_attr_14_we; + logic mio_pad_attr_14_re; + logic [9:0] mio_pad_attr_15_qs; + logic [9:0] mio_pad_attr_15_wd; + logic mio_pad_attr_15_we; + logic mio_pad_attr_15_re; + logic [9:0] mio_pad_attr_16_qs; + logic [9:0] mio_pad_attr_16_wd; + logic mio_pad_attr_16_we; + logic mio_pad_attr_16_re; + logic [9:0] mio_pad_attr_17_qs; + logic [9:0] mio_pad_attr_17_wd; + logic mio_pad_attr_17_we; + logic mio_pad_attr_17_re; + logic [9:0] mio_pad_attr_18_qs; + logic [9:0] mio_pad_attr_18_wd; + logic mio_pad_attr_18_we; + logic mio_pad_attr_18_re; + logic [9:0] mio_pad_attr_19_qs; + logic [9:0] mio_pad_attr_19_wd; + logic mio_pad_attr_19_we; + logic mio_pad_attr_19_re; + logic [9:0] mio_pad_attr_20_qs; + logic [9:0] mio_pad_attr_20_wd; + logic mio_pad_attr_20_we; + logic mio_pad_attr_20_re; + logic [9:0] mio_pad_attr_21_qs; + logic [9:0] mio_pad_attr_21_wd; + logic mio_pad_attr_21_we; + logic mio_pad_attr_21_re; + logic [9:0] mio_pad_attr_22_qs; + logic [9:0] mio_pad_attr_22_wd; + logic mio_pad_attr_22_we; + logic mio_pad_attr_22_re; + logic [9:0] mio_pad_attr_23_qs; + logic [9:0] mio_pad_attr_23_wd; + logic mio_pad_attr_23_we; + logic mio_pad_attr_23_re; + logic [9:0] mio_pad_attr_24_qs; + logic [9:0] mio_pad_attr_24_wd; + logic mio_pad_attr_24_we; + logic mio_pad_attr_24_re; + logic [9:0] mio_pad_attr_25_qs; + logic [9:0] mio_pad_attr_25_wd; + logic mio_pad_attr_25_we; + logic mio_pad_attr_25_re; + logic [9:0] mio_pad_attr_26_qs; + logic [9:0] mio_pad_attr_26_wd; + logic mio_pad_attr_26_we; + logic mio_pad_attr_26_re; + logic [9:0] mio_pad_attr_27_qs; + logic [9:0] mio_pad_attr_27_wd; + logic mio_pad_attr_27_we; + logic mio_pad_attr_27_re; + logic [9:0] mio_pad_attr_28_qs; + logic [9:0] mio_pad_attr_28_wd; + logic mio_pad_attr_28_we; + logic mio_pad_attr_28_re; + logic [9:0] mio_pad_attr_29_qs; + logic [9:0] mio_pad_attr_29_wd; + logic mio_pad_attr_29_we; + logic mio_pad_attr_29_re; + logic [9:0] mio_pad_attr_30_qs; + logic [9:0] mio_pad_attr_30_wd; + logic mio_pad_attr_30_we; + logic mio_pad_attr_30_re; + logic [9:0] mio_pad_attr_31_qs; + logic [9:0] mio_pad_attr_31_wd; + logic mio_pad_attr_31_we; + logic mio_pad_attr_31_re; + logic dio_pad_attr_regwen_0_qs; + logic dio_pad_attr_regwen_0_wd; + logic dio_pad_attr_regwen_0_we; + logic dio_pad_attr_regwen_1_qs; + logic dio_pad_attr_regwen_1_wd; + logic dio_pad_attr_regwen_1_we; + logic dio_pad_attr_regwen_2_qs; + logic dio_pad_attr_regwen_2_wd; + logic dio_pad_attr_regwen_2_we; + logic dio_pad_attr_regwen_3_qs; + logic dio_pad_attr_regwen_3_wd; + logic dio_pad_attr_regwen_3_we; + logic dio_pad_attr_regwen_4_qs; + logic dio_pad_attr_regwen_4_wd; + logic dio_pad_attr_regwen_4_we; + logic dio_pad_attr_regwen_5_qs; + logic dio_pad_attr_regwen_5_wd; + logic dio_pad_attr_regwen_5_we; + logic dio_pad_attr_regwen_6_qs; + logic dio_pad_attr_regwen_6_wd; + logic dio_pad_attr_regwen_6_we; + logic dio_pad_attr_regwen_7_qs; + logic dio_pad_attr_regwen_7_wd; + logic dio_pad_attr_regwen_7_we; + logic dio_pad_attr_regwen_8_qs; + logic dio_pad_attr_regwen_8_wd; + logic dio_pad_attr_regwen_8_we; + logic dio_pad_attr_regwen_9_qs; + logic dio_pad_attr_regwen_9_wd; + logic dio_pad_attr_regwen_9_we; + logic dio_pad_attr_regwen_10_qs; + logic dio_pad_attr_regwen_10_wd; + logic dio_pad_attr_regwen_10_we; + logic dio_pad_attr_regwen_11_qs; + logic dio_pad_attr_regwen_11_wd; + logic dio_pad_attr_regwen_11_we; + logic dio_pad_attr_regwen_12_qs; + logic dio_pad_attr_regwen_12_wd; + logic dio_pad_attr_regwen_12_we; + logic dio_pad_attr_regwen_13_qs; + logic dio_pad_attr_regwen_13_wd; + logic dio_pad_attr_regwen_13_we; + logic dio_pad_attr_regwen_14_qs; + logic dio_pad_attr_regwen_14_wd; + logic dio_pad_attr_regwen_14_we; + logic dio_pad_attr_regwen_15_qs; + logic dio_pad_attr_regwen_15_wd; + logic dio_pad_attr_regwen_15_we; + logic [9:0] dio_pad_attr_0_qs; + logic [9:0] dio_pad_attr_0_wd; + logic dio_pad_attr_0_we; + logic dio_pad_attr_0_re; + logic [9:0] dio_pad_attr_1_qs; + logic [9:0] dio_pad_attr_1_wd; + logic dio_pad_attr_1_we; + logic dio_pad_attr_1_re; + logic [9:0] dio_pad_attr_2_qs; + logic [9:0] dio_pad_attr_2_wd; + logic dio_pad_attr_2_we; + logic dio_pad_attr_2_re; + logic [9:0] dio_pad_attr_3_qs; + logic [9:0] dio_pad_attr_3_wd; + logic dio_pad_attr_3_we; + logic dio_pad_attr_3_re; + logic [9:0] dio_pad_attr_4_qs; + logic [9:0] dio_pad_attr_4_wd; + logic dio_pad_attr_4_we; + logic dio_pad_attr_4_re; + logic [9:0] dio_pad_attr_5_qs; + logic [9:0] dio_pad_attr_5_wd; + logic dio_pad_attr_5_we; + logic dio_pad_attr_5_re; + logic [9:0] dio_pad_attr_6_qs; + logic [9:0] dio_pad_attr_6_wd; + logic dio_pad_attr_6_we; + logic dio_pad_attr_6_re; + logic [9:0] dio_pad_attr_7_qs; + logic [9:0] dio_pad_attr_7_wd; + logic dio_pad_attr_7_we; + logic dio_pad_attr_7_re; + logic [9:0] dio_pad_attr_8_qs; + logic [9:0] dio_pad_attr_8_wd; + logic dio_pad_attr_8_we; + logic dio_pad_attr_8_re; + logic [9:0] dio_pad_attr_9_qs; + logic [9:0] dio_pad_attr_9_wd; + logic dio_pad_attr_9_we; + logic dio_pad_attr_9_re; + logic [9:0] dio_pad_attr_10_qs; + logic [9:0] dio_pad_attr_10_wd; + logic dio_pad_attr_10_we; + logic dio_pad_attr_10_re; + logic [9:0] dio_pad_attr_11_qs; + logic [9:0] dio_pad_attr_11_wd; + logic dio_pad_attr_11_we; + logic dio_pad_attr_11_re; + logic [9:0] dio_pad_attr_12_qs; + logic [9:0] dio_pad_attr_12_wd; + logic dio_pad_attr_12_we; + logic dio_pad_attr_12_re; + logic [9:0] dio_pad_attr_13_qs; + logic [9:0] dio_pad_attr_13_wd; + logic dio_pad_attr_13_we; + logic dio_pad_attr_13_re; + logic [9:0] dio_pad_attr_14_qs; + logic [9:0] dio_pad_attr_14_wd; + logic dio_pad_attr_14_we; + logic dio_pad_attr_14_re; + logic [9:0] dio_pad_attr_15_qs; + logic [9:0] dio_pad_attr_15_wd; + logic dio_pad_attr_15_we; + logic dio_pad_attr_15_re; + logic mio_pad_sleep_status_en_0_qs; + logic mio_pad_sleep_status_en_0_wd; + logic mio_pad_sleep_status_en_0_we; + logic mio_pad_sleep_status_en_1_qs; + logic mio_pad_sleep_status_en_1_wd; + logic mio_pad_sleep_status_en_1_we; + logic mio_pad_sleep_status_en_2_qs; + logic mio_pad_sleep_status_en_2_wd; + logic mio_pad_sleep_status_en_2_we; + logic mio_pad_sleep_status_en_3_qs; + logic mio_pad_sleep_status_en_3_wd; + logic mio_pad_sleep_status_en_3_we; + logic mio_pad_sleep_status_en_4_qs; + logic mio_pad_sleep_status_en_4_wd; + logic mio_pad_sleep_status_en_4_we; + logic mio_pad_sleep_status_en_5_qs; + logic mio_pad_sleep_status_en_5_wd; + logic mio_pad_sleep_status_en_5_we; + logic mio_pad_sleep_status_en_6_qs; + logic mio_pad_sleep_status_en_6_wd; + logic mio_pad_sleep_status_en_6_we; + logic mio_pad_sleep_status_en_7_qs; + logic mio_pad_sleep_status_en_7_wd; + logic mio_pad_sleep_status_en_7_we; + logic mio_pad_sleep_status_en_8_qs; + logic mio_pad_sleep_status_en_8_wd; + logic mio_pad_sleep_status_en_8_we; + logic mio_pad_sleep_status_en_9_qs; + logic mio_pad_sleep_status_en_9_wd; + logic mio_pad_sleep_status_en_9_we; + logic mio_pad_sleep_status_en_10_qs; + logic mio_pad_sleep_status_en_10_wd; + logic mio_pad_sleep_status_en_10_we; + logic mio_pad_sleep_status_en_11_qs; + logic mio_pad_sleep_status_en_11_wd; + logic mio_pad_sleep_status_en_11_we; + logic mio_pad_sleep_status_en_12_qs; + logic mio_pad_sleep_status_en_12_wd; + logic mio_pad_sleep_status_en_12_we; + logic mio_pad_sleep_status_en_13_qs; + logic mio_pad_sleep_status_en_13_wd; + logic mio_pad_sleep_status_en_13_we; + logic mio_pad_sleep_status_en_14_qs; + logic mio_pad_sleep_status_en_14_wd; + logic mio_pad_sleep_status_en_14_we; + logic mio_pad_sleep_status_en_15_qs; + logic mio_pad_sleep_status_en_15_wd; + logic mio_pad_sleep_status_en_15_we; + logic mio_pad_sleep_status_en_16_qs; + logic mio_pad_sleep_status_en_16_wd; + logic mio_pad_sleep_status_en_16_we; + logic mio_pad_sleep_status_en_17_qs; + logic mio_pad_sleep_status_en_17_wd; + logic mio_pad_sleep_status_en_17_we; + logic mio_pad_sleep_status_en_18_qs; + logic mio_pad_sleep_status_en_18_wd; + logic mio_pad_sleep_status_en_18_we; + logic mio_pad_sleep_status_en_19_qs; + logic mio_pad_sleep_status_en_19_wd; + logic mio_pad_sleep_status_en_19_we; + logic mio_pad_sleep_status_en_20_qs; + logic mio_pad_sleep_status_en_20_wd; + logic mio_pad_sleep_status_en_20_we; + logic mio_pad_sleep_status_en_21_qs; + logic mio_pad_sleep_status_en_21_wd; + logic mio_pad_sleep_status_en_21_we; + logic mio_pad_sleep_status_en_22_qs; + logic mio_pad_sleep_status_en_22_wd; + logic mio_pad_sleep_status_en_22_we; + logic mio_pad_sleep_status_en_23_qs; + logic mio_pad_sleep_status_en_23_wd; + logic mio_pad_sleep_status_en_23_we; + logic mio_pad_sleep_status_en_24_qs; + logic mio_pad_sleep_status_en_24_wd; + logic mio_pad_sleep_status_en_24_we; + logic mio_pad_sleep_status_en_25_qs; + logic mio_pad_sleep_status_en_25_wd; + logic mio_pad_sleep_status_en_25_we; + logic mio_pad_sleep_status_en_26_qs; + logic mio_pad_sleep_status_en_26_wd; + logic mio_pad_sleep_status_en_26_we; + logic mio_pad_sleep_status_en_27_qs; + logic mio_pad_sleep_status_en_27_wd; + logic mio_pad_sleep_status_en_27_we; + logic mio_pad_sleep_status_en_28_qs; + logic mio_pad_sleep_status_en_28_wd; + logic mio_pad_sleep_status_en_28_we; + logic mio_pad_sleep_status_en_29_qs; + logic mio_pad_sleep_status_en_29_wd; + logic mio_pad_sleep_status_en_29_we; + logic mio_pad_sleep_status_en_30_qs; + logic mio_pad_sleep_status_en_30_wd; + logic mio_pad_sleep_status_en_30_we; + logic mio_pad_sleep_status_en_31_qs; + logic mio_pad_sleep_status_en_31_wd; + logic mio_pad_sleep_status_en_31_we; + logic mio_pad_sleep_regwen_0_qs; + logic mio_pad_sleep_regwen_0_wd; + logic mio_pad_sleep_regwen_0_we; + logic mio_pad_sleep_regwen_1_qs; + logic mio_pad_sleep_regwen_1_wd; + logic mio_pad_sleep_regwen_1_we; + logic mio_pad_sleep_regwen_2_qs; + logic mio_pad_sleep_regwen_2_wd; + logic mio_pad_sleep_regwen_2_we; + logic mio_pad_sleep_regwen_3_qs; + logic mio_pad_sleep_regwen_3_wd; + logic mio_pad_sleep_regwen_3_we; + logic mio_pad_sleep_regwen_4_qs; + logic mio_pad_sleep_regwen_4_wd; + logic mio_pad_sleep_regwen_4_we; + logic mio_pad_sleep_regwen_5_qs; + logic mio_pad_sleep_regwen_5_wd; + logic mio_pad_sleep_regwen_5_we; + logic mio_pad_sleep_regwen_6_qs; + logic mio_pad_sleep_regwen_6_wd; + logic mio_pad_sleep_regwen_6_we; + logic mio_pad_sleep_regwen_7_qs; + logic mio_pad_sleep_regwen_7_wd; + logic mio_pad_sleep_regwen_7_we; + logic mio_pad_sleep_regwen_8_qs; + logic mio_pad_sleep_regwen_8_wd; + logic mio_pad_sleep_regwen_8_we; + logic mio_pad_sleep_regwen_9_qs; + logic mio_pad_sleep_regwen_9_wd; + logic mio_pad_sleep_regwen_9_we; + logic mio_pad_sleep_regwen_10_qs; + logic mio_pad_sleep_regwen_10_wd; + logic mio_pad_sleep_regwen_10_we; + logic mio_pad_sleep_regwen_11_qs; + logic mio_pad_sleep_regwen_11_wd; + logic mio_pad_sleep_regwen_11_we; + logic mio_pad_sleep_regwen_12_qs; + logic mio_pad_sleep_regwen_12_wd; + logic mio_pad_sleep_regwen_12_we; + logic mio_pad_sleep_regwen_13_qs; + logic mio_pad_sleep_regwen_13_wd; + logic mio_pad_sleep_regwen_13_we; + logic mio_pad_sleep_regwen_14_qs; + logic mio_pad_sleep_regwen_14_wd; + logic mio_pad_sleep_regwen_14_we; + logic mio_pad_sleep_regwen_15_qs; + logic mio_pad_sleep_regwen_15_wd; + logic mio_pad_sleep_regwen_15_we; + logic mio_pad_sleep_regwen_16_qs; + logic mio_pad_sleep_regwen_16_wd; + logic mio_pad_sleep_regwen_16_we; + logic mio_pad_sleep_regwen_17_qs; + logic mio_pad_sleep_regwen_17_wd; + logic mio_pad_sleep_regwen_17_we; + logic mio_pad_sleep_regwen_18_qs; + logic mio_pad_sleep_regwen_18_wd; + logic mio_pad_sleep_regwen_18_we; + logic mio_pad_sleep_regwen_19_qs; + logic mio_pad_sleep_regwen_19_wd; + logic mio_pad_sleep_regwen_19_we; + logic mio_pad_sleep_regwen_20_qs; + logic mio_pad_sleep_regwen_20_wd; + logic mio_pad_sleep_regwen_20_we; + logic mio_pad_sleep_regwen_21_qs; + logic mio_pad_sleep_regwen_21_wd; + logic mio_pad_sleep_regwen_21_we; + logic mio_pad_sleep_regwen_22_qs; + logic mio_pad_sleep_regwen_22_wd; + logic mio_pad_sleep_regwen_22_we; + logic mio_pad_sleep_regwen_23_qs; + logic mio_pad_sleep_regwen_23_wd; + logic mio_pad_sleep_regwen_23_we; + logic mio_pad_sleep_regwen_24_qs; + logic mio_pad_sleep_regwen_24_wd; + logic mio_pad_sleep_regwen_24_we; + logic mio_pad_sleep_regwen_25_qs; + logic mio_pad_sleep_regwen_25_wd; + logic mio_pad_sleep_regwen_25_we; + logic mio_pad_sleep_regwen_26_qs; + logic mio_pad_sleep_regwen_26_wd; + logic mio_pad_sleep_regwen_26_we; + logic mio_pad_sleep_regwen_27_qs; + logic mio_pad_sleep_regwen_27_wd; + logic mio_pad_sleep_regwen_27_we; + logic mio_pad_sleep_regwen_28_qs; + logic mio_pad_sleep_regwen_28_wd; + logic mio_pad_sleep_regwen_28_we; + logic mio_pad_sleep_regwen_29_qs; + logic mio_pad_sleep_regwen_29_wd; + logic mio_pad_sleep_regwen_29_we; + logic mio_pad_sleep_regwen_30_qs; + logic mio_pad_sleep_regwen_30_wd; + logic mio_pad_sleep_regwen_30_we; + logic mio_pad_sleep_regwen_31_qs; + logic mio_pad_sleep_regwen_31_wd; + logic mio_pad_sleep_regwen_31_we; + logic mio_pad_sleep_en_0_qs; + logic mio_pad_sleep_en_0_wd; + logic mio_pad_sleep_en_0_we; + logic mio_pad_sleep_en_1_qs; + logic mio_pad_sleep_en_1_wd; + logic mio_pad_sleep_en_1_we; + logic mio_pad_sleep_en_2_qs; + logic mio_pad_sleep_en_2_wd; + logic mio_pad_sleep_en_2_we; + logic mio_pad_sleep_en_3_qs; + logic mio_pad_sleep_en_3_wd; + logic mio_pad_sleep_en_3_we; + logic mio_pad_sleep_en_4_qs; + logic mio_pad_sleep_en_4_wd; + logic mio_pad_sleep_en_4_we; + logic mio_pad_sleep_en_5_qs; + logic mio_pad_sleep_en_5_wd; + logic mio_pad_sleep_en_5_we; + logic mio_pad_sleep_en_6_qs; + logic mio_pad_sleep_en_6_wd; + logic mio_pad_sleep_en_6_we; + logic mio_pad_sleep_en_7_qs; + logic mio_pad_sleep_en_7_wd; + logic mio_pad_sleep_en_7_we; + logic mio_pad_sleep_en_8_qs; + logic mio_pad_sleep_en_8_wd; + logic mio_pad_sleep_en_8_we; + logic mio_pad_sleep_en_9_qs; + logic mio_pad_sleep_en_9_wd; + logic mio_pad_sleep_en_9_we; + logic mio_pad_sleep_en_10_qs; + logic mio_pad_sleep_en_10_wd; + logic mio_pad_sleep_en_10_we; + logic mio_pad_sleep_en_11_qs; + logic mio_pad_sleep_en_11_wd; + logic mio_pad_sleep_en_11_we; + logic mio_pad_sleep_en_12_qs; + logic mio_pad_sleep_en_12_wd; + logic mio_pad_sleep_en_12_we; + logic mio_pad_sleep_en_13_qs; + logic mio_pad_sleep_en_13_wd; + logic mio_pad_sleep_en_13_we; + logic mio_pad_sleep_en_14_qs; + logic mio_pad_sleep_en_14_wd; + logic mio_pad_sleep_en_14_we; + logic mio_pad_sleep_en_15_qs; + logic mio_pad_sleep_en_15_wd; + logic mio_pad_sleep_en_15_we; + logic mio_pad_sleep_en_16_qs; + logic mio_pad_sleep_en_16_wd; + logic mio_pad_sleep_en_16_we; + logic mio_pad_sleep_en_17_qs; + logic mio_pad_sleep_en_17_wd; + logic mio_pad_sleep_en_17_we; + logic mio_pad_sleep_en_18_qs; + logic mio_pad_sleep_en_18_wd; + logic mio_pad_sleep_en_18_we; + logic mio_pad_sleep_en_19_qs; + logic mio_pad_sleep_en_19_wd; + logic mio_pad_sleep_en_19_we; + logic mio_pad_sleep_en_20_qs; + logic mio_pad_sleep_en_20_wd; + logic mio_pad_sleep_en_20_we; + logic mio_pad_sleep_en_21_qs; + logic mio_pad_sleep_en_21_wd; + logic mio_pad_sleep_en_21_we; + logic mio_pad_sleep_en_22_qs; + logic mio_pad_sleep_en_22_wd; + logic mio_pad_sleep_en_22_we; + logic mio_pad_sleep_en_23_qs; + logic mio_pad_sleep_en_23_wd; + logic mio_pad_sleep_en_23_we; + logic mio_pad_sleep_en_24_qs; + logic mio_pad_sleep_en_24_wd; + logic mio_pad_sleep_en_24_we; + logic mio_pad_sleep_en_25_qs; + logic mio_pad_sleep_en_25_wd; + logic mio_pad_sleep_en_25_we; + logic mio_pad_sleep_en_26_qs; + logic mio_pad_sleep_en_26_wd; + logic mio_pad_sleep_en_26_we; + logic mio_pad_sleep_en_27_qs; + logic mio_pad_sleep_en_27_wd; + logic mio_pad_sleep_en_27_we; + logic mio_pad_sleep_en_28_qs; + logic mio_pad_sleep_en_28_wd; + logic mio_pad_sleep_en_28_we; + logic mio_pad_sleep_en_29_qs; + logic mio_pad_sleep_en_29_wd; + logic mio_pad_sleep_en_29_we; + logic mio_pad_sleep_en_30_qs; + logic mio_pad_sleep_en_30_wd; + logic mio_pad_sleep_en_30_we; + logic mio_pad_sleep_en_31_qs; + logic mio_pad_sleep_en_31_wd; + logic mio_pad_sleep_en_31_we; + logic [1:0] mio_pad_sleep_mode_0_qs; + logic [1:0] mio_pad_sleep_mode_0_wd; + logic mio_pad_sleep_mode_0_we; + logic [1:0] mio_pad_sleep_mode_1_qs; + logic [1:0] mio_pad_sleep_mode_1_wd; + logic mio_pad_sleep_mode_1_we; + logic [1:0] mio_pad_sleep_mode_2_qs; + logic [1:0] mio_pad_sleep_mode_2_wd; + logic mio_pad_sleep_mode_2_we; + logic [1:0] mio_pad_sleep_mode_3_qs; + logic [1:0] mio_pad_sleep_mode_3_wd; + logic mio_pad_sleep_mode_3_we; + logic [1:0] mio_pad_sleep_mode_4_qs; + logic [1:0] mio_pad_sleep_mode_4_wd; + logic mio_pad_sleep_mode_4_we; + logic [1:0] mio_pad_sleep_mode_5_qs; + logic [1:0] mio_pad_sleep_mode_5_wd; + logic mio_pad_sleep_mode_5_we; + logic [1:0] mio_pad_sleep_mode_6_qs; + logic [1:0] mio_pad_sleep_mode_6_wd; + logic mio_pad_sleep_mode_6_we; + logic [1:0] mio_pad_sleep_mode_7_qs; + logic [1:0] mio_pad_sleep_mode_7_wd; + logic mio_pad_sleep_mode_7_we; + logic [1:0] mio_pad_sleep_mode_8_qs; + logic [1:0] mio_pad_sleep_mode_8_wd; + logic mio_pad_sleep_mode_8_we; + logic [1:0] mio_pad_sleep_mode_9_qs; + logic [1:0] mio_pad_sleep_mode_9_wd; + logic mio_pad_sleep_mode_9_we; + logic [1:0] mio_pad_sleep_mode_10_qs; + logic [1:0] mio_pad_sleep_mode_10_wd; + logic mio_pad_sleep_mode_10_we; + logic [1:0] mio_pad_sleep_mode_11_qs; + logic [1:0] mio_pad_sleep_mode_11_wd; + logic mio_pad_sleep_mode_11_we; + logic [1:0] mio_pad_sleep_mode_12_qs; + logic [1:0] mio_pad_sleep_mode_12_wd; + logic mio_pad_sleep_mode_12_we; + logic [1:0] mio_pad_sleep_mode_13_qs; + logic [1:0] mio_pad_sleep_mode_13_wd; + logic mio_pad_sleep_mode_13_we; + logic [1:0] mio_pad_sleep_mode_14_qs; + logic [1:0] mio_pad_sleep_mode_14_wd; + logic mio_pad_sleep_mode_14_we; + logic [1:0] mio_pad_sleep_mode_15_qs; + logic [1:0] mio_pad_sleep_mode_15_wd; + logic mio_pad_sleep_mode_15_we; + logic [1:0] mio_pad_sleep_mode_16_qs; + logic [1:0] mio_pad_sleep_mode_16_wd; + logic mio_pad_sleep_mode_16_we; + logic [1:0] mio_pad_sleep_mode_17_qs; + logic [1:0] mio_pad_sleep_mode_17_wd; + logic mio_pad_sleep_mode_17_we; + logic [1:0] mio_pad_sleep_mode_18_qs; + logic [1:0] mio_pad_sleep_mode_18_wd; + logic mio_pad_sleep_mode_18_we; + logic [1:0] mio_pad_sleep_mode_19_qs; + logic [1:0] mio_pad_sleep_mode_19_wd; + logic mio_pad_sleep_mode_19_we; + logic [1:0] mio_pad_sleep_mode_20_qs; + logic [1:0] mio_pad_sleep_mode_20_wd; + logic mio_pad_sleep_mode_20_we; + logic [1:0] mio_pad_sleep_mode_21_qs; + logic [1:0] mio_pad_sleep_mode_21_wd; + logic mio_pad_sleep_mode_21_we; + logic [1:0] mio_pad_sleep_mode_22_qs; + logic [1:0] mio_pad_sleep_mode_22_wd; + logic mio_pad_sleep_mode_22_we; + logic [1:0] mio_pad_sleep_mode_23_qs; + logic [1:0] mio_pad_sleep_mode_23_wd; + logic mio_pad_sleep_mode_23_we; + logic [1:0] mio_pad_sleep_mode_24_qs; + logic [1:0] mio_pad_sleep_mode_24_wd; + logic mio_pad_sleep_mode_24_we; + logic [1:0] mio_pad_sleep_mode_25_qs; + logic [1:0] mio_pad_sleep_mode_25_wd; + logic mio_pad_sleep_mode_25_we; + logic [1:0] mio_pad_sleep_mode_26_qs; + logic [1:0] mio_pad_sleep_mode_26_wd; + logic mio_pad_sleep_mode_26_we; + logic [1:0] mio_pad_sleep_mode_27_qs; + logic [1:0] mio_pad_sleep_mode_27_wd; + logic mio_pad_sleep_mode_27_we; + logic [1:0] mio_pad_sleep_mode_28_qs; + logic [1:0] mio_pad_sleep_mode_28_wd; + logic mio_pad_sleep_mode_28_we; + logic [1:0] mio_pad_sleep_mode_29_qs; + logic [1:0] mio_pad_sleep_mode_29_wd; + logic mio_pad_sleep_mode_29_we; + logic [1:0] mio_pad_sleep_mode_30_qs; + logic [1:0] mio_pad_sleep_mode_30_wd; + logic mio_pad_sleep_mode_30_we; + logic [1:0] mio_pad_sleep_mode_31_qs; + logic [1:0] mio_pad_sleep_mode_31_wd; + logic mio_pad_sleep_mode_31_we; + logic dio_pad_sleep_status_en_0_qs; + logic dio_pad_sleep_status_en_0_wd; + logic dio_pad_sleep_status_en_0_we; + logic dio_pad_sleep_status_en_1_qs; + logic dio_pad_sleep_status_en_1_wd; + logic dio_pad_sleep_status_en_1_we; + logic dio_pad_sleep_status_en_2_qs; + logic dio_pad_sleep_status_en_2_wd; + logic dio_pad_sleep_status_en_2_we; + logic dio_pad_sleep_status_en_3_qs; + logic dio_pad_sleep_status_en_3_wd; + logic dio_pad_sleep_status_en_3_we; + logic dio_pad_sleep_status_en_4_qs; + logic dio_pad_sleep_status_en_4_wd; + logic dio_pad_sleep_status_en_4_we; + logic dio_pad_sleep_status_en_5_qs; + logic dio_pad_sleep_status_en_5_wd; + logic dio_pad_sleep_status_en_5_we; + logic dio_pad_sleep_status_en_6_qs; + logic dio_pad_sleep_status_en_6_wd; + logic dio_pad_sleep_status_en_6_we; + logic dio_pad_sleep_status_en_7_qs; + logic dio_pad_sleep_status_en_7_wd; + logic dio_pad_sleep_status_en_7_we; + logic dio_pad_sleep_status_en_8_qs; + logic dio_pad_sleep_status_en_8_wd; + logic dio_pad_sleep_status_en_8_we; + logic dio_pad_sleep_status_en_9_qs; + logic dio_pad_sleep_status_en_9_wd; + logic dio_pad_sleep_status_en_9_we; + logic dio_pad_sleep_status_en_10_qs; + logic dio_pad_sleep_status_en_10_wd; + logic dio_pad_sleep_status_en_10_we; + logic dio_pad_sleep_status_en_11_qs; + logic dio_pad_sleep_status_en_11_wd; + logic dio_pad_sleep_status_en_11_we; + logic dio_pad_sleep_status_en_12_qs; + logic dio_pad_sleep_status_en_12_wd; + logic dio_pad_sleep_status_en_12_we; + logic dio_pad_sleep_status_en_13_qs; + logic dio_pad_sleep_status_en_13_wd; + logic dio_pad_sleep_status_en_13_we; + logic dio_pad_sleep_status_en_14_qs; + logic dio_pad_sleep_status_en_14_wd; + logic dio_pad_sleep_status_en_14_we; + logic dio_pad_sleep_status_en_15_qs; + logic dio_pad_sleep_status_en_15_wd; + logic dio_pad_sleep_status_en_15_we; + logic dio_pad_sleep_regwen_0_qs; + logic dio_pad_sleep_regwen_0_wd; + logic dio_pad_sleep_regwen_0_we; + logic dio_pad_sleep_regwen_1_qs; + logic dio_pad_sleep_regwen_1_wd; + logic dio_pad_sleep_regwen_1_we; + logic dio_pad_sleep_regwen_2_qs; + logic dio_pad_sleep_regwen_2_wd; + logic dio_pad_sleep_regwen_2_we; + logic dio_pad_sleep_regwen_3_qs; + logic dio_pad_sleep_regwen_3_wd; + logic dio_pad_sleep_regwen_3_we; + logic dio_pad_sleep_regwen_4_qs; + logic dio_pad_sleep_regwen_4_wd; + logic dio_pad_sleep_regwen_4_we; + logic dio_pad_sleep_regwen_5_qs; + logic dio_pad_sleep_regwen_5_wd; + logic dio_pad_sleep_regwen_5_we; + logic dio_pad_sleep_regwen_6_qs; + logic dio_pad_sleep_regwen_6_wd; + logic dio_pad_sleep_regwen_6_we; + logic dio_pad_sleep_regwen_7_qs; + logic dio_pad_sleep_regwen_7_wd; + logic dio_pad_sleep_regwen_7_we; + logic dio_pad_sleep_regwen_8_qs; + logic dio_pad_sleep_regwen_8_wd; + logic dio_pad_sleep_regwen_8_we; + logic dio_pad_sleep_regwen_9_qs; + logic dio_pad_sleep_regwen_9_wd; + logic dio_pad_sleep_regwen_9_we; + logic dio_pad_sleep_regwen_10_qs; + logic dio_pad_sleep_regwen_10_wd; + logic dio_pad_sleep_regwen_10_we; + logic dio_pad_sleep_regwen_11_qs; + logic dio_pad_sleep_regwen_11_wd; + logic dio_pad_sleep_regwen_11_we; + logic dio_pad_sleep_regwen_12_qs; + logic dio_pad_sleep_regwen_12_wd; + logic dio_pad_sleep_regwen_12_we; + logic dio_pad_sleep_regwen_13_qs; + logic dio_pad_sleep_regwen_13_wd; + logic dio_pad_sleep_regwen_13_we; + logic dio_pad_sleep_regwen_14_qs; + logic dio_pad_sleep_regwen_14_wd; + logic dio_pad_sleep_regwen_14_we; + logic dio_pad_sleep_regwen_15_qs; + logic dio_pad_sleep_regwen_15_wd; + logic dio_pad_sleep_regwen_15_we; + logic dio_pad_sleep_en_0_qs; + logic dio_pad_sleep_en_0_wd; + logic dio_pad_sleep_en_0_we; + logic dio_pad_sleep_en_1_qs; + logic dio_pad_sleep_en_1_wd; + logic dio_pad_sleep_en_1_we; + logic dio_pad_sleep_en_2_qs; + logic dio_pad_sleep_en_2_wd; + logic dio_pad_sleep_en_2_we; + logic dio_pad_sleep_en_3_qs; + logic dio_pad_sleep_en_3_wd; + logic dio_pad_sleep_en_3_we; + logic dio_pad_sleep_en_4_qs; + logic dio_pad_sleep_en_4_wd; + logic dio_pad_sleep_en_4_we; + logic dio_pad_sleep_en_5_qs; + logic dio_pad_sleep_en_5_wd; + logic dio_pad_sleep_en_5_we; + logic dio_pad_sleep_en_6_qs; + logic dio_pad_sleep_en_6_wd; + logic dio_pad_sleep_en_6_we; + logic dio_pad_sleep_en_7_qs; + logic dio_pad_sleep_en_7_wd; + logic dio_pad_sleep_en_7_we; + logic dio_pad_sleep_en_8_qs; + logic dio_pad_sleep_en_8_wd; + logic dio_pad_sleep_en_8_we; + logic dio_pad_sleep_en_9_qs; + logic dio_pad_sleep_en_9_wd; + logic dio_pad_sleep_en_9_we; + logic dio_pad_sleep_en_10_qs; + logic dio_pad_sleep_en_10_wd; + logic dio_pad_sleep_en_10_we; + logic dio_pad_sleep_en_11_qs; + logic dio_pad_sleep_en_11_wd; + logic dio_pad_sleep_en_11_we; + logic dio_pad_sleep_en_12_qs; + logic dio_pad_sleep_en_12_wd; + logic dio_pad_sleep_en_12_we; + logic dio_pad_sleep_en_13_qs; + logic dio_pad_sleep_en_13_wd; + logic dio_pad_sleep_en_13_we; + logic dio_pad_sleep_en_14_qs; + logic dio_pad_sleep_en_14_wd; + logic dio_pad_sleep_en_14_we; + logic dio_pad_sleep_en_15_qs; + logic dio_pad_sleep_en_15_wd; + logic dio_pad_sleep_en_15_we; + logic [1:0] dio_pad_sleep_mode_0_qs; + logic [1:0] dio_pad_sleep_mode_0_wd; + logic dio_pad_sleep_mode_0_we; + logic [1:0] dio_pad_sleep_mode_1_qs; + logic [1:0] dio_pad_sleep_mode_1_wd; + logic dio_pad_sleep_mode_1_we; + logic [1:0] dio_pad_sleep_mode_2_qs; + logic [1:0] dio_pad_sleep_mode_2_wd; + logic dio_pad_sleep_mode_2_we; + logic [1:0] dio_pad_sleep_mode_3_qs; + logic [1:0] dio_pad_sleep_mode_3_wd; + logic dio_pad_sleep_mode_3_we; + logic [1:0] dio_pad_sleep_mode_4_qs; + logic [1:0] dio_pad_sleep_mode_4_wd; + logic dio_pad_sleep_mode_4_we; + logic [1:0] dio_pad_sleep_mode_5_qs; + logic [1:0] dio_pad_sleep_mode_5_wd; + logic dio_pad_sleep_mode_5_we; + logic [1:0] dio_pad_sleep_mode_6_qs; + logic [1:0] dio_pad_sleep_mode_6_wd; + logic dio_pad_sleep_mode_6_we; + logic [1:0] dio_pad_sleep_mode_7_qs; + logic [1:0] dio_pad_sleep_mode_7_wd; + logic dio_pad_sleep_mode_7_we; + logic [1:0] dio_pad_sleep_mode_8_qs; + logic [1:0] dio_pad_sleep_mode_8_wd; + logic dio_pad_sleep_mode_8_we; + logic [1:0] dio_pad_sleep_mode_9_qs; + logic [1:0] dio_pad_sleep_mode_9_wd; + logic dio_pad_sleep_mode_9_we; + logic [1:0] dio_pad_sleep_mode_10_qs; + logic [1:0] dio_pad_sleep_mode_10_wd; + logic dio_pad_sleep_mode_10_we; + logic [1:0] dio_pad_sleep_mode_11_qs; + logic [1:0] dio_pad_sleep_mode_11_wd; + logic dio_pad_sleep_mode_11_we; + logic [1:0] dio_pad_sleep_mode_12_qs; + logic [1:0] dio_pad_sleep_mode_12_wd; + logic dio_pad_sleep_mode_12_we; + logic [1:0] dio_pad_sleep_mode_13_qs; + logic [1:0] dio_pad_sleep_mode_13_wd; + logic dio_pad_sleep_mode_13_we; + logic [1:0] dio_pad_sleep_mode_14_qs; + logic [1:0] dio_pad_sleep_mode_14_wd; + logic dio_pad_sleep_mode_14_we; + logic [1:0] dio_pad_sleep_mode_15_qs; + logic [1:0] dio_pad_sleep_mode_15_wd; + logic dio_pad_sleep_mode_15_we; logic wkup_detector_regwen_0_qs; logic wkup_detector_regwen_0_wd; logic wkup_detector_regwen_0_we; @@ -4486,20 +5094,20 @@ - // Subregister 0 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_0]: V(False) + // Subregister 0 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_0]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_0 ( + ) u_mio_pad_attr_regwen_0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_0_we), - .wd (mio_out_sleep_regwen_0_wd), + .we (mio_pad_attr_regwen_0_we), + .wd (mio_pad_attr_regwen_0_wd), // from internal hardware .de (1'b0), @@ -4510,23 +5118,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_0_qs) + .qs (mio_pad_attr_regwen_0_qs) ); - // Subregister 1 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_1]: V(False) + // Subregister 1 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_1]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_1 ( + ) u_mio_pad_attr_regwen_1 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_1_we), - .wd (mio_out_sleep_regwen_1_wd), + .we (mio_pad_attr_regwen_1_we), + .wd (mio_pad_attr_regwen_1_wd), // from internal hardware .de (1'b0), @@ -4537,23 +5145,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_1_qs) + .qs (mio_pad_attr_regwen_1_qs) ); - // Subregister 2 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_2]: V(False) + // Subregister 2 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_2]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_2 ( + ) u_mio_pad_attr_regwen_2 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_2_we), - .wd (mio_out_sleep_regwen_2_wd), + .we (mio_pad_attr_regwen_2_we), + .wd (mio_pad_attr_regwen_2_wd), // from internal hardware .de (1'b0), @@ -4564,23 +5172,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_2_qs) + .qs (mio_pad_attr_regwen_2_qs) ); - // Subregister 3 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_3]: V(False) + // Subregister 3 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_3]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_3 ( + ) u_mio_pad_attr_regwen_3 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_3_we), - .wd (mio_out_sleep_regwen_3_wd), + .we (mio_pad_attr_regwen_3_we), + .wd (mio_pad_attr_regwen_3_wd), // from internal hardware .de (1'b0), @@ -4591,23 +5199,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_3_qs) + .qs (mio_pad_attr_regwen_3_qs) ); - // Subregister 4 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_4]: V(False) + // Subregister 4 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_4]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_4 ( + ) u_mio_pad_attr_regwen_4 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_4_we), - .wd (mio_out_sleep_regwen_4_wd), + .we (mio_pad_attr_regwen_4_we), + .wd (mio_pad_attr_regwen_4_wd), // from internal hardware .de (1'b0), @@ -4618,23 +5226,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_4_qs) + .qs (mio_pad_attr_regwen_4_qs) ); - // Subregister 5 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_5]: V(False) + // Subregister 5 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_5]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_5 ( + ) u_mio_pad_attr_regwen_5 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_5_we), - .wd (mio_out_sleep_regwen_5_wd), + .we (mio_pad_attr_regwen_5_we), + .wd (mio_pad_attr_regwen_5_wd), // from internal hardware .de (1'b0), @@ -4645,23 +5253,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_5_qs) + .qs (mio_pad_attr_regwen_5_qs) ); - // Subregister 6 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_6]: V(False) + // Subregister 6 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_6]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_6 ( + ) u_mio_pad_attr_regwen_6 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_6_we), - .wd (mio_out_sleep_regwen_6_wd), + .we (mio_pad_attr_regwen_6_we), + .wd (mio_pad_attr_regwen_6_wd), // from internal hardware .de (1'b0), @@ -4672,23 +5280,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_6_qs) + .qs (mio_pad_attr_regwen_6_qs) ); - // Subregister 7 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_7]: V(False) + // Subregister 7 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_7]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_7 ( + ) u_mio_pad_attr_regwen_7 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_7_we), - .wd (mio_out_sleep_regwen_7_wd), + .we (mio_pad_attr_regwen_7_we), + .wd (mio_pad_attr_regwen_7_wd), // from internal hardware .de (1'b0), @@ -4699,23 +5307,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_7_qs) + .qs (mio_pad_attr_regwen_7_qs) ); - // Subregister 8 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_8]: V(False) + // Subregister 8 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_8]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_8 ( + ) u_mio_pad_attr_regwen_8 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_8_we), - .wd (mio_out_sleep_regwen_8_wd), + .we (mio_pad_attr_regwen_8_we), + .wd (mio_pad_attr_regwen_8_wd), // from internal hardware .de (1'b0), @@ -4726,23 +5334,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_8_qs) + .qs (mio_pad_attr_regwen_8_qs) ); - // Subregister 9 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_9]: V(False) + // Subregister 9 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_9]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_9 ( + ) u_mio_pad_attr_regwen_9 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_9_we), - .wd (mio_out_sleep_regwen_9_wd), + .we (mio_pad_attr_regwen_9_we), + .wd (mio_pad_attr_regwen_9_wd), // from internal hardware .de (1'b0), @@ -4753,23 +5361,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_9_qs) + .qs (mio_pad_attr_regwen_9_qs) ); - // Subregister 10 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_10]: V(False) + // Subregister 10 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_10]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_10 ( + ) u_mio_pad_attr_regwen_10 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_10_we), - .wd (mio_out_sleep_regwen_10_wd), + .we (mio_pad_attr_regwen_10_we), + .wd (mio_pad_attr_regwen_10_wd), // from internal hardware .de (1'b0), @@ -4780,23 +5388,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_10_qs) + .qs (mio_pad_attr_regwen_10_qs) ); - // Subregister 11 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_11]: V(False) + // Subregister 11 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_11]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_11 ( + ) u_mio_pad_attr_regwen_11 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_11_we), - .wd (mio_out_sleep_regwen_11_wd), + .we (mio_pad_attr_regwen_11_we), + .wd (mio_pad_attr_regwen_11_wd), // from internal hardware .de (1'b0), @@ -4807,23 +5415,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_11_qs) + .qs (mio_pad_attr_regwen_11_qs) ); - // Subregister 12 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_12]: V(False) + // Subregister 12 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_12]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_12 ( + ) u_mio_pad_attr_regwen_12 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_12_we), - .wd (mio_out_sleep_regwen_12_wd), + .we (mio_pad_attr_regwen_12_we), + .wd (mio_pad_attr_regwen_12_wd), // from internal hardware .de (1'b0), @@ -4834,23 +5442,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_12_qs) + .qs (mio_pad_attr_regwen_12_qs) ); - // Subregister 13 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_13]: V(False) + // Subregister 13 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_13]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_13 ( + ) u_mio_pad_attr_regwen_13 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_13_we), - .wd (mio_out_sleep_regwen_13_wd), + .we (mio_pad_attr_regwen_13_we), + .wd (mio_pad_attr_regwen_13_wd), // from internal hardware .de (1'b0), @@ -4861,23 +5469,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_13_qs) + .qs (mio_pad_attr_regwen_13_qs) ); - // Subregister 14 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_14]: V(False) + // Subregister 14 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_14]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_14 ( + ) u_mio_pad_attr_regwen_14 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_14_we), - .wd (mio_out_sleep_regwen_14_wd), + .we (mio_pad_attr_regwen_14_we), + .wd (mio_pad_attr_regwen_14_wd), // from internal hardware .de (1'b0), @@ -4888,23 +5496,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_14_qs) + .qs (mio_pad_attr_regwen_14_qs) ); - // Subregister 15 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_15]: V(False) + // Subregister 15 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_15]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_15 ( + ) u_mio_pad_attr_regwen_15 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_15_we), - .wd (mio_out_sleep_regwen_15_wd), + .we (mio_pad_attr_regwen_15_we), + .wd (mio_pad_attr_regwen_15_wd), // from internal hardware .de (1'b0), @@ -4915,23 +5523,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_15_qs) + .qs (mio_pad_attr_regwen_15_qs) ); - // Subregister 16 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_16]: V(False) + // Subregister 16 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_16]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_16 ( + ) u_mio_pad_attr_regwen_16 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_16_we), - .wd (mio_out_sleep_regwen_16_wd), + .we (mio_pad_attr_regwen_16_we), + .wd (mio_pad_attr_regwen_16_wd), // from internal hardware .de (1'b0), @@ -4942,23 +5550,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_16_qs) + .qs (mio_pad_attr_regwen_16_qs) ); - // Subregister 17 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_17]: V(False) + // Subregister 17 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_17]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_17 ( + ) u_mio_pad_attr_regwen_17 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_17_we), - .wd (mio_out_sleep_regwen_17_wd), + .we (mio_pad_attr_regwen_17_we), + .wd (mio_pad_attr_regwen_17_wd), // from internal hardware .de (1'b0), @@ -4969,23 +5577,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_17_qs) + .qs (mio_pad_attr_regwen_17_qs) ); - // Subregister 18 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_18]: V(False) + // Subregister 18 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_18]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_18 ( + ) u_mio_pad_attr_regwen_18 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_18_we), - .wd (mio_out_sleep_regwen_18_wd), + .we (mio_pad_attr_regwen_18_we), + .wd (mio_pad_attr_regwen_18_wd), // from internal hardware .de (1'b0), @@ -4996,23 +5604,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_18_qs) + .qs (mio_pad_attr_regwen_18_qs) ); - // Subregister 19 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_19]: V(False) + // Subregister 19 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_19]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_19 ( + ) u_mio_pad_attr_regwen_19 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_19_we), - .wd (mio_out_sleep_regwen_19_wd), + .we (mio_pad_attr_regwen_19_we), + .wd (mio_pad_attr_regwen_19_wd), // from internal hardware .de (1'b0), @@ -5023,23 +5631,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_19_qs) + .qs (mio_pad_attr_regwen_19_qs) ); - // Subregister 20 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_20]: V(False) + // Subregister 20 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_20]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_20 ( + ) u_mio_pad_attr_regwen_20 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_20_we), - .wd (mio_out_sleep_regwen_20_wd), + .we (mio_pad_attr_regwen_20_we), + .wd (mio_pad_attr_regwen_20_wd), // from internal hardware .de (1'b0), @@ -5050,23 +5658,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_20_qs) + .qs (mio_pad_attr_regwen_20_qs) ); - // Subregister 21 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_21]: V(False) + // Subregister 21 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_21]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_21 ( + ) u_mio_pad_attr_regwen_21 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_21_we), - .wd (mio_out_sleep_regwen_21_wd), + .we (mio_pad_attr_regwen_21_we), + .wd (mio_pad_attr_regwen_21_wd), // from internal hardware .de (1'b0), @@ -5077,23 +5685,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_21_qs) + .qs (mio_pad_attr_regwen_21_qs) ); - // Subregister 22 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_22]: V(False) + // Subregister 22 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_22]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_22 ( + ) u_mio_pad_attr_regwen_22 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_22_we), - .wd (mio_out_sleep_regwen_22_wd), + .we (mio_pad_attr_regwen_22_we), + .wd (mio_pad_attr_regwen_22_wd), // from internal hardware .de (1'b0), @@ -5104,23 +5712,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_22_qs) + .qs (mio_pad_attr_regwen_22_qs) ); - // Subregister 23 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_23]: V(False) + // Subregister 23 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_23]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_23 ( + ) u_mio_pad_attr_regwen_23 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_23_we), - .wd (mio_out_sleep_regwen_23_wd), + .we (mio_pad_attr_regwen_23_we), + .wd (mio_pad_attr_regwen_23_wd), // from internal hardware .de (1'b0), @@ -5131,23 +5739,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_23_qs) + .qs (mio_pad_attr_regwen_23_qs) ); - // Subregister 24 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_24]: V(False) + // Subregister 24 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_24]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_24 ( + ) u_mio_pad_attr_regwen_24 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_24_we), - .wd (mio_out_sleep_regwen_24_wd), + .we (mio_pad_attr_regwen_24_we), + .wd (mio_pad_attr_regwen_24_wd), // from internal hardware .de (1'b0), @@ -5158,23 +5766,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_24_qs) + .qs (mio_pad_attr_regwen_24_qs) ); - // Subregister 25 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_25]: V(False) + // Subregister 25 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_25]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_25 ( + ) u_mio_pad_attr_regwen_25 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_25_we), - .wd (mio_out_sleep_regwen_25_wd), + .we (mio_pad_attr_regwen_25_we), + .wd (mio_pad_attr_regwen_25_wd), // from internal hardware .de (1'b0), @@ -5185,23 +5793,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_25_qs) + .qs (mio_pad_attr_regwen_25_qs) ); - // Subregister 26 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_26]: V(False) + // Subregister 26 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_26]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_26 ( + ) u_mio_pad_attr_regwen_26 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_26_we), - .wd (mio_out_sleep_regwen_26_wd), + .we (mio_pad_attr_regwen_26_we), + .wd (mio_pad_attr_regwen_26_wd), // from internal hardware .de (1'b0), @@ -5212,23 +5820,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_26_qs) + .qs (mio_pad_attr_regwen_26_qs) ); - // Subregister 27 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_27]: V(False) + // Subregister 27 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_27]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_27 ( + ) u_mio_pad_attr_regwen_27 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_27_we), - .wd (mio_out_sleep_regwen_27_wd), + .we (mio_pad_attr_regwen_27_we), + .wd (mio_pad_attr_regwen_27_wd), // from internal hardware .de (1'b0), @@ -5239,23 +5847,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_27_qs) + .qs (mio_pad_attr_regwen_27_qs) ); - // Subregister 28 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_28]: V(False) + // Subregister 28 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_28]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_28 ( + ) u_mio_pad_attr_regwen_28 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_28_we), - .wd (mio_out_sleep_regwen_28_wd), + .we (mio_pad_attr_regwen_28_we), + .wd (mio_pad_attr_regwen_28_wd), // from internal hardware .de (1'b0), @@ -5266,23 +5874,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_28_qs) + .qs (mio_pad_attr_regwen_28_qs) ); - // Subregister 29 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_29]: V(False) + // Subregister 29 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_29]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_29 ( + ) u_mio_pad_attr_regwen_29 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_29_we), - .wd (mio_out_sleep_regwen_29_wd), + .we (mio_pad_attr_regwen_29_we), + .wd (mio_pad_attr_regwen_29_wd), // from internal hardware .de (1'b0), @@ -5293,23 +5901,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_29_qs) + .qs (mio_pad_attr_regwen_29_qs) ); - // Subregister 30 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_30]: V(False) + // Subregister 30 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_30]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_30 ( + ) u_mio_pad_attr_regwen_30 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_30_we), - .wd (mio_out_sleep_regwen_30_wd), + .we (mio_pad_attr_regwen_30_we), + .wd (mio_pad_attr_regwen_30_wd), // from internal hardware .de (1'b0), @@ -5320,23 +5928,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_30_qs) + .qs (mio_pad_attr_regwen_30_qs) ); - // Subregister 31 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_31]: V(False) + // Subregister 31 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_31]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_31 ( + ) u_mio_pad_attr_regwen_31 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_31_we), - .wd (mio_out_sleep_regwen_31_wd), + .we (mio_pad_attr_regwen_31_we), + .wd (mio_pad_attr_regwen_31_wd), // from internal hardware .de (1'b0), @@ -5347,1581 +5955,6419 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_31_qs) + .qs (mio_pad_attr_regwen_31_qs) ); - // Subregister 0 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_0]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_0_we & mio_out_sleep_regwen_0_qs), - .wd (mio_out_sleep_val_0_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[0].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_0_qs) - ); - - // Subregister 1 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_1]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_1_we & mio_out_sleep_regwen_1_qs), - .wd (mio_out_sleep_val_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[1].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_1_qs) - ); - - // Subregister 2 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_2]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_2_we & mio_out_sleep_regwen_2_qs), - .wd (mio_out_sleep_val_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[2].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_2_qs) - ); - - // Subregister 3 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_3]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_3_we & mio_out_sleep_regwen_3_qs), - .wd (mio_out_sleep_val_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[3].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_3_qs) - ); - - // Subregister 4 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_4]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_4_we & mio_out_sleep_regwen_4_qs), - .wd (mio_out_sleep_val_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[4].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_4_qs) - ); - - // Subregister 5 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_5]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_5_we & mio_out_sleep_regwen_5_qs), - .wd (mio_out_sleep_val_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[5].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_5_qs) - ); - - // Subregister 6 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_6]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_6_we & mio_out_sleep_regwen_6_qs), - .wd (mio_out_sleep_val_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[6].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_6_qs) - ); - - // Subregister 7 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_7]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_7_we & mio_out_sleep_regwen_7_qs), - .wd (mio_out_sleep_val_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[7].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_7_qs) - ); - - // Subregister 8 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_8]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_8_we & mio_out_sleep_regwen_8_qs), - .wd (mio_out_sleep_val_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[8].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_8_qs) - ); - - // Subregister 9 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_9]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_9_we & mio_out_sleep_regwen_9_qs), - .wd (mio_out_sleep_val_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[9].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_9_qs) - ); - - // Subregister 10 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_10]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_10_we & mio_out_sleep_regwen_10_qs), - .wd (mio_out_sleep_val_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[10].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_10_qs) - ); - - // Subregister 11 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_11]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_11_we & mio_out_sleep_regwen_11_qs), - .wd (mio_out_sleep_val_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[11].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_11_qs) - ); - - // Subregister 12 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_12]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_12_we & mio_out_sleep_regwen_12_qs), - .wd (mio_out_sleep_val_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[12].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_12_qs) - ); - - // Subregister 13 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_13]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_13_we & mio_out_sleep_regwen_13_qs), - .wd (mio_out_sleep_val_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[13].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_13_qs) - ); - - // Subregister 14 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_14]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_14_we & mio_out_sleep_regwen_14_qs), - .wd (mio_out_sleep_val_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[14].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_14_qs) - ); - - // Subregister 15 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_15]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_15_we & mio_out_sleep_regwen_15_qs), - .wd (mio_out_sleep_val_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[15].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_15_qs) - ); - - // Subregister 16 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_16]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_16 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_16_we & mio_out_sleep_regwen_16_qs), - .wd (mio_out_sleep_val_16_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[16].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_16_qs) - ); - - // Subregister 17 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_17]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_17 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_17_we & mio_out_sleep_regwen_17_qs), - .wd (mio_out_sleep_val_17_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[17].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_17_qs) - ); - - // Subregister 18 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_18]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_18 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_18_we & mio_out_sleep_regwen_18_qs), - .wd (mio_out_sleep_val_18_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[18].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_18_qs) - ); - - // Subregister 19 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_19]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_19 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_19_we & mio_out_sleep_regwen_19_qs), - .wd (mio_out_sleep_val_19_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[19].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_19_qs) - ); - - // Subregister 20 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_20]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_20 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_20_we & mio_out_sleep_regwen_20_qs), - .wd (mio_out_sleep_val_20_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[20].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_20_qs) - ); - - // Subregister 21 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_21]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_21 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_21_we & mio_out_sleep_regwen_21_qs), - .wd (mio_out_sleep_val_21_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[21].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_21_qs) - ); - - // Subregister 22 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_22]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_22 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_22_we & mio_out_sleep_regwen_22_qs), - .wd (mio_out_sleep_val_22_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[22].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_22_qs) - ); - - // Subregister 23 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_23]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_23 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_23_we & mio_out_sleep_regwen_23_qs), - .wd (mio_out_sleep_val_23_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[23].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_23_qs) - ); - - // Subregister 24 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_24]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_24 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_24_we & mio_out_sleep_regwen_24_qs), - .wd (mio_out_sleep_val_24_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[24].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_24_qs) - ); - - // Subregister 25 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_25]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_25 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_25_we & mio_out_sleep_regwen_25_qs), - .wd (mio_out_sleep_val_25_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[25].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_25_qs) - ); - - // Subregister 26 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_26]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_26 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_26_we & mio_out_sleep_regwen_26_qs), - .wd (mio_out_sleep_val_26_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[26].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_26_qs) - ); - - // Subregister 27 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_27]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_27 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_27_we & mio_out_sleep_regwen_27_qs), - .wd (mio_out_sleep_val_27_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[27].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_27_qs) - ); - - // Subregister 28 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_28]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_28 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_28_we & mio_out_sleep_regwen_28_qs), - .wd (mio_out_sleep_val_28_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[28].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_28_qs) - ); - - // Subregister 29 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_29]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_29 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_29_we & mio_out_sleep_regwen_29_qs), - .wd (mio_out_sleep_val_29_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[29].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_29_qs) - ); - - // Subregister 30 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_30]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_30 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_30_we & mio_out_sleep_regwen_30_qs), - .wd (mio_out_sleep_val_30_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[30].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_30_qs) - ); - - // Subregister 31 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_31]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_31 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_31_we & mio_out_sleep_regwen_31_qs), - .wd (mio_out_sleep_val_31_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[31].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_31_qs) - ); - - - - // Subregister 0 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_0]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_0_we), - .wd (dio_out_sleep_regwen_0_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_0_qs) - ); - - // Subregister 1 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_1]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_1_we), - .wd (dio_out_sleep_regwen_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_1_qs) - ); - - // Subregister 2 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_2]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_2_we), - .wd (dio_out_sleep_regwen_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_2_qs) - ); - - // Subregister 3 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_3]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_3_we), - .wd (dio_out_sleep_regwen_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_3_qs) - ); - - // Subregister 4 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_4]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_4_we), - .wd (dio_out_sleep_regwen_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_4_qs) - ); - - // Subregister 5 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_5]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_5_we), - .wd (dio_out_sleep_regwen_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_5_qs) - ); - - // Subregister 6 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_6]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_6_we), - .wd (dio_out_sleep_regwen_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_6_qs) - ); - - // Subregister 7 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_7]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_7_we), - .wd (dio_out_sleep_regwen_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_7_qs) - ); - - // Subregister 8 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_8]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_8_we), - .wd (dio_out_sleep_regwen_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_8_qs) - ); - - // Subregister 9 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_9]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_9_we), - .wd (dio_out_sleep_regwen_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_9_qs) - ); - - // Subregister 10 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_10]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_10_we), - .wd (dio_out_sleep_regwen_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_10_qs) - ); - - // Subregister 11 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_11]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_11_we), - .wd (dio_out_sleep_regwen_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_11_qs) - ); - - // Subregister 12 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_12]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_12_we), - .wd (dio_out_sleep_regwen_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_12_qs) - ); - - // Subregister 13 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_13]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_13_we), - .wd (dio_out_sleep_regwen_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_13_qs) - ); - - // Subregister 14 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_14]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_14_we), - .wd (dio_out_sleep_regwen_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_14_qs) - ); - - // Subregister 15 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_15]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_15_we), - .wd (dio_out_sleep_regwen_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_15_qs) - ); - - - - // Subregister 0 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_0]: V(True) + // Subregister 0 of Multireg mio_pad_attr + // R[mio_pad_attr_0]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_0 ( - .re (dio_out_sleep_val_0_re), + .DW (10) + ) u_mio_pad_attr_0 ( + .re (mio_pad_attr_0_re), // qualified with register enable - .we (dio_out_sleep_val_0_we & dio_out_sleep_regwen_0_qs), - .wd (dio_out_sleep_val_0_wd), - .d (hw2reg.dio_out_sleep_val[0].d), + .we (mio_pad_attr_0_we & mio_pad_attr_regwen_0_qs), + .wd (mio_pad_attr_0_wd), + .d (hw2reg.mio_pad_attr[0].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[0].qe), - .q (reg2hw.dio_out_sleep_val[0].q ), - .qs (dio_out_sleep_val_0_qs) + .qe (reg2hw.mio_pad_attr[0].qe), + .q (reg2hw.mio_pad_attr[0].q ), + .qs (mio_pad_attr_0_qs) ); - // Subregister 1 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_1]: V(True) + // Subregister 1 of Multireg mio_pad_attr + // R[mio_pad_attr_1]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_1 ( - .re (dio_out_sleep_val_1_re), + .DW (10) + ) u_mio_pad_attr_1 ( + .re (mio_pad_attr_1_re), // qualified with register enable - .we (dio_out_sleep_val_1_we & dio_out_sleep_regwen_1_qs), - .wd (dio_out_sleep_val_1_wd), - .d (hw2reg.dio_out_sleep_val[1].d), + .we (mio_pad_attr_1_we & mio_pad_attr_regwen_1_qs), + .wd (mio_pad_attr_1_wd), + .d (hw2reg.mio_pad_attr[1].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[1].qe), - .q (reg2hw.dio_out_sleep_val[1].q ), - .qs (dio_out_sleep_val_1_qs) + .qe (reg2hw.mio_pad_attr[1].qe), + .q (reg2hw.mio_pad_attr[1].q ), + .qs (mio_pad_attr_1_qs) ); - // Subregister 2 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_2]: V(True) + // Subregister 2 of Multireg mio_pad_attr + // R[mio_pad_attr_2]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_2 ( - .re (dio_out_sleep_val_2_re), + .DW (10) + ) u_mio_pad_attr_2 ( + .re (mio_pad_attr_2_re), // qualified with register enable - .we (dio_out_sleep_val_2_we & dio_out_sleep_regwen_2_qs), - .wd (dio_out_sleep_val_2_wd), - .d (hw2reg.dio_out_sleep_val[2].d), + .we (mio_pad_attr_2_we & mio_pad_attr_regwen_2_qs), + .wd (mio_pad_attr_2_wd), + .d (hw2reg.mio_pad_attr[2].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[2].qe), - .q (reg2hw.dio_out_sleep_val[2].q ), - .qs (dio_out_sleep_val_2_qs) + .qe (reg2hw.mio_pad_attr[2].qe), + .q (reg2hw.mio_pad_attr[2].q ), + .qs (mio_pad_attr_2_qs) ); - // Subregister 3 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_3]: V(True) + // Subregister 3 of Multireg mio_pad_attr + // R[mio_pad_attr_3]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_3 ( - .re (dio_out_sleep_val_3_re), + .DW (10) + ) u_mio_pad_attr_3 ( + .re (mio_pad_attr_3_re), // qualified with register enable - .we (dio_out_sleep_val_3_we & dio_out_sleep_regwen_3_qs), - .wd (dio_out_sleep_val_3_wd), - .d (hw2reg.dio_out_sleep_val[3].d), + .we (mio_pad_attr_3_we & mio_pad_attr_regwen_3_qs), + .wd (mio_pad_attr_3_wd), + .d (hw2reg.mio_pad_attr[3].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[3].qe), - .q (reg2hw.dio_out_sleep_val[3].q ), - .qs (dio_out_sleep_val_3_qs) + .qe (reg2hw.mio_pad_attr[3].qe), + .q (reg2hw.mio_pad_attr[3].q ), + .qs (mio_pad_attr_3_qs) ); - // Subregister 4 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_4]: V(True) + // Subregister 4 of Multireg mio_pad_attr + // R[mio_pad_attr_4]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_4 ( - .re (dio_out_sleep_val_4_re), + .DW (10) + ) u_mio_pad_attr_4 ( + .re (mio_pad_attr_4_re), // qualified with register enable - .we (dio_out_sleep_val_4_we & dio_out_sleep_regwen_4_qs), - .wd (dio_out_sleep_val_4_wd), - .d (hw2reg.dio_out_sleep_val[4].d), + .we (mio_pad_attr_4_we & mio_pad_attr_regwen_4_qs), + .wd (mio_pad_attr_4_wd), + .d (hw2reg.mio_pad_attr[4].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[4].qe), - .q (reg2hw.dio_out_sleep_val[4].q ), - .qs (dio_out_sleep_val_4_qs) + .qe (reg2hw.mio_pad_attr[4].qe), + .q (reg2hw.mio_pad_attr[4].q ), + .qs (mio_pad_attr_4_qs) ); - // Subregister 5 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_5]: V(True) + // Subregister 5 of Multireg mio_pad_attr + // R[mio_pad_attr_5]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_5 ( - .re (dio_out_sleep_val_5_re), + .DW (10) + ) u_mio_pad_attr_5 ( + .re (mio_pad_attr_5_re), // qualified with register enable - .we (dio_out_sleep_val_5_we & dio_out_sleep_regwen_5_qs), - .wd (dio_out_sleep_val_5_wd), - .d (hw2reg.dio_out_sleep_val[5].d), + .we (mio_pad_attr_5_we & mio_pad_attr_regwen_5_qs), + .wd (mio_pad_attr_5_wd), + .d (hw2reg.mio_pad_attr[5].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[5].qe), - .q (reg2hw.dio_out_sleep_val[5].q ), - .qs (dio_out_sleep_val_5_qs) + .qe (reg2hw.mio_pad_attr[5].qe), + .q (reg2hw.mio_pad_attr[5].q ), + .qs (mio_pad_attr_5_qs) ); - // Subregister 6 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_6]: V(True) + // Subregister 6 of Multireg mio_pad_attr + // R[mio_pad_attr_6]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_6 ( - .re (dio_out_sleep_val_6_re), + .DW (10) + ) u_mio_pad_attr_6 ( + .re (mio_pad_attr_6_re), // qualified with register enable - .we (dio_out_sleep_val_6_we & dio_out_sleep_regwen_6_qs), - .wd (dio_out_sleep_val_6_wd), - .d (hw2reg.dio_out_sleep_val[6].d), + .we (mio_pad_attr_6_we & mio_pad_attr_regwen_6_qs), + .wd (mio_pad_attr_6_wd), + .d (hw2reg.mio_pad_attr[6].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[6].qe), - .q (reg2hw.dio_out_sleep_val[6].q ), - .qs (dio_out_sleep_val_6_qs) + .qe (reg2hw.mio_pad_attr[6].qe), + .q (reg2hw.mio_pad_attr[6].q ), + .qs (mio_pad_attr_6_qs) ); - // Subregister 7 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_7]: V(True) + // Subregister 7 of Multireg mio_pad_attr + // R[mio_pad_attr_7]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_7 ( - .re (dio_out_sleep_val_7_re), + .DW (10) + ) u_mio_pad_attr_7 ( + .re (mio_pad_attr_7_re), // qualified with register enable - .we (dio_out_sleep_val_7_we & dio_out_sleep_regwen_7_qs), - .wd (dio_out_sleep_val_7_wd), - .d (hw2reg.dio_out_sleep_val[7].d), + .we (mio_pad_attr_7_we & mio_pad_attr_regwen_7_qs), + .wd (mio_pad_attr_7_wd), + .d (hw2reg.mio_pad_attr[7].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[7].qe), - .q (reg2hw.dio_out_sleep_val[7].q ), - .qs (dio_out_sleep_val_7_qs) + .qe (reg2hw.mio_pad_attr[7].qe), + .q (reg2hw.mio_pad_attr[7].q ), + .qs (mio_pad_attr_7_qs) ); - // Subregister 8 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_8]: V(True) + // Subregister 8 of Multireg mio_pad_attr + // R[mio_pad_attr_8]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_8 ( - .re (dio_out_sleep_val_8_re), + .DW (10) + ) u_mio_pad_attr_8 ( + .re (mio_pad_attr_8_re), // qualified with register enable - .we (dio_out_sleep_val_8_we & dio_out_sleep_regwen_8_qs), - .wd (dio_out_sleep_val_8_wd), - .d (hw2reg.dio_out_sleep_val[8].d), + .we (mio_pad_attr_8_we & mio_pad_attr_regwen_8_qs), + .wd (mio_pad_attr_8_wd), + .d (hw2reg.mio_pad_attr[8].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[8].qe), - .q (reg2hw.dio_out_sleep_val[8].q ), - .qs (dio_out_sleep_val_8_qs) + .qe (reg2hw.mio_pad_attr[8].qe), + .q (reg2hw.mio_pad_attr[8].q ), + .qs (mio_pad_attr_8_qs) ); - // Subregister 9 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_9]: V(True) + // Subregister 9 of Multireg mio_pad_attr + // R[mio_pad_attr_9]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_9 ( - .re (dio_out_sleep_val_9_re), + .DW (10) + ) u_mio_pad_attr_9 ( + .re (mio_pad_attr_9_re), // qualified with register enable - .we (dio_out_sleep_val_9_we & dio_out_sleep_regwen_9_qs), - .wd (dio_out_sleep_val_9_wd), - .d (hw2reg.dio_out_sleep_val[9].d), + .we (mio_pad_attr_9_we & mio_pad_attr_regwen_9_qs), + .wd (mio_pad_attr_9_wd), + .d (hw2reg.mio_pad_attr[9].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[9].qe), - .q (reg2hw.dio_out_sleep_val[9].q ), - .qs (dio_out_sleep_val_9_qs) + .qe (reg2hw.mio_pad_attr[9].qe), + .q (reg2hw.mio_pad_attr[9].q ), + .qs (mio_pad_attr_9_qs) ); - // Subregister 10 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_10]: V(True) + // Subregister 10 of Multireg mio_pad_attr + // R[mio_pad_attr_10]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_10 ( - .re (dio_out_sleep_val_10_re), + .DW (10) + ) u_mio_pad_attr_10 ( + .re (mio_pad_attr_10_re), // qualified with register enable - .we (dio_out_sleep_val_10_we & dio_out_sleep_regwen_10_qs), - .wd (dio_out_sleep_val_10_wd), - .d (hw2reg.dio_out_sleep_val[10].d), + .we (mio_pad_attr_10_we & mio_pad_attr_regwen_10_qs), + .wd (mio_pad_attr_10_wd), + .d (hw2reg.mio_pad_attr[10].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[10].qe), - .q (reg2hw.dio_out_sleep_val[10].q ), - .qs (dio_out_sleep_val_10_qs) + .qe (reg2hw.mio_pad_attr[10].qe), + .q (reg2hw.mio_pad_attr[10].q ), + .qs (mio_pad_attr_10_qs) ); - // Subregister 11 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_11]: V(True) + // Subregister 11 of Multireg mio_pad_attr + // R[mio_pad_attr_11]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_11 ( - .re (dio_out_sleep_val_11_re), + .DW (10) + ) u_mio_pad_attr_11 ( + .re (mio_pad_attr_11_re), // qualified with register enable - .we (dio_out_sleep_val_11_we & dio_out_sleep_regwen_11_qs), - .wd (dio_out_sleep_val_11_wd), - .d (hw2reg.dio_out_sleep_val[11].d), + .we (mio_pad_attr_11_we & mio_pad_attr_regwen_11_qs), + .wd (mio_pad_attr_11_wd), + .d (hw2reg.mio_pad_attr[11].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[11].qe), - .q (reg2hw.dio_out_sleep_val[11].q ), - .qs (dio_out_sleep_val_11_qs) + .qe (reg2hw.mio_pad_attr[11].qe), + .q (reg2hw.mio_pad_attr[11].q ), + .qs (mio_pad_attr_11_qs) ); - // Subregister 12 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_12]: V(True) + // Subregister 12 of Multireg mio_pad_attr + // R[mio_pad_attr_12]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_12 ( - .re (dio_out_sleep_val_12_re), + .DW (10) + ) u_mio_pad_attr_12 ( + .re (mio_pad_attr_12_re), // qualified with register enable - .we (dio_out_sleep_val_12_we & dio_out_sleep_regwen_12_qs), - .wd (dio_out_sleep_val_12_wd), - .d (hw2reg.dio_out_sleep_val[12].d), + .we (mio_pad_attr_12_we & mio_pad_attr_regwen_12_qs), + .wd (mio_pad_attr_12_wd), + .d (hw2reg.mio_pad_attr[12].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[12].qe), - .q (reg2hw.dio_out_sleep_val[12].q ), - .qs (dio_out_sleep_val_12_qs) + .qe (reg2hw.mio_pad_attr[12].qe), + .q (reg2hw.mio_pad_attr[12].q ), + .qs (mio_pad_attr_12_qs) ); - // Subregister 13 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_13]: V(True) + // Subregister 13 of Multireg mio_pad_attr + // R[mio_pad_attr_13]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_13 ( - .re (dio_out_sleep_val_13_re), + .DW (10) + ) u_mio_pad_attr_13 ( + .re (mio_pad_attr_13_re), // qualified with register enable - .we (dio_out_sleep_val_13_we & dio_out_sleep_regwen_13_qs), - .wd (dio_out_sleep_val_13_wd), - .d (hw2reg.dio_out_sleep_val[13].d), + .we (mio_pad_attr_13_we & mio_pad_attr_regwen_13_qs), + .wd (mio_pad_attr_13_wd), + .d (hw2reg.mio_pad_attr[13].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[13].qe), - .q (reg2hw.dio_out_sleep_val[13].q ), - .qs (dio_out_sleep_val_13_qs) + .qe (reg2hw.mio_pad_attr[13].qe), + .q (reg2hw.mio_pad_attr[13].q ), + .qs (mio_pad_attr_13_qs) ); - // Subregister 14 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_14]: V(True) + // Subregister 14 of Multireg mio_pad_attr + // R[mio_pad_attr_14]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_14 ( - .re (dio_out_sleep_val_14_re), + .DW (10) + ) u_mio_pad_attr_14 ( + .re (mio_pad_attr_14_re), // qualified with register enable - .we (dio_out_sleep_val_14_we & dio_out_sleep_regwen_14_qs), - .wd (dio_out_sleep_val_14_wd), - .d (hw2reg.dio_out_sleep_val[14].d), + .we (mio_pad_attr_14_we & mio_pad_attr_regwen_14_qs), + .wd (mio_pad_attr_14_wd), + .d (hw2reg.mio_pad_attr[14].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[14].qe), - .q (reg2hw.dio_out_sleep_val[14].q ), - .qs (dio_out_sleep_val_14_qs) + .qe (reg2hw.mio_pad_attr[14].qe), + .q (reg2hw.mio_pad_attr[14].q ), + .qs (mio_pad_attr_14_qs) ); - // Subregister 15 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_15]: V(True) + // Subregister 15 of Multireg mio_pad_attr + // R[mio_pad_attr_15]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_15 ( - .re (dio_out_sleep_val_15_re), + .DW (10) + ) u_mio_pad_attr_15 ( + .re (mio_pad_attr_15_re), // qualified with register enable - .we (dio_out_sleep_val_15_we & dio_out_sleep_regwen_15_qs), - .wd (dio_out_sleep_val_15_wd), - .d (hw2reg.dio_out_sleep_val[15].d), + .we (mio_pad_attr_15_we & mio_pad_attr_regwen_15_qs), + .wd (mio_pad_attr_15_wd), + .d (hw2reg.mio_pad_attr[15].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[15].qe), - .q (reg2hw.dio_out_sleep_val[15].q ), - .qs (dio_out_sleep_val_15_qs) + .qe (reg2hw.mio_pad_attr[15].qe), + .q (reg2hw.mio_pad_attr[15].q ), + .qs (mio_pad_attr_15_qs) + ); + + // Subregister 16 of Multireg mio_pad_attr + // R[mio_pad_attr_16]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_16 ( + .re (mio_pad_attr_16_re), + // qualified with register enable + .we (mio_pad_attr_16_we & mio_pad_attr_regwen_16_qs), + .wd (mio_pad_attr_16_wd), + .d (hw2reg.mio_pad_attr[16].d), + .qre (), + .qe (reg2hw.mio_pad_attr[16].qe), + .q (reg2hw.mio_pad_attr[16].q ), + .qs (mio_pad_attr_16_qs) + ); + + // Subregister 17 of Multireg mio_pad_attr + // R[mio_pad_attr_17]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_17 ( + .re (mio_pad_attr_17_re), + // qualified with register enable + .we (mio_pad_attr_17_we & mio_pad_attr_regwen_17_qs), + .wd (mio_pad_attr_17_wd), + .d (hw2reg.mio_pad_attr[17].d), + .qre (), + .qe (reg2hw.mio_pad_attr[17].qe), + .q (reg2hw.mio_pad_attr[17].q ), + .qs (mio_pad_attr_17_qs) + ); + + // Subregister 18 of Multireg mio_pad_attr + // R[mio_pad_attr_18]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_18 ( + .re (mio_pad_attr_18_re), + // qualified with register enable + .we (mio_pad_attr_18_we & mio_pad_attr_regwen_18_qs), + .wd (mio_pad_attr_18_wd), + .d (hw2reg.mio_pad_attr[18].d), + .qre (), + .qe (reg2hw.mio_pad_attr[18].qe), + .q (reg2hw.mio_pad_attr[18].q ), + .qs (mio_pad_attr_18_qs) + ); + + // Subregister 19 of Multireg mio_pad_attr + // R[mio_pad_attr_19]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_19 ( + .re (mio_pad_attr_19_re), + // qualified with register enable + .we (mio_pad_attr_19_we & mio_pad_attr_regwen_19_qs), + .wd (mio_pad_attr_19_wd), + .d (hw2reg.mio_pad_attr[19].d), + .qre (), + .qe (reg2hw.mio_pad_attr[19].qe), + .q (reg2hw.mio_pad_attr[19].q ), + .qs (mio_pad_attr_19_qs) + ); + + // Subregister 20 of Multireg mio_pad_attr + // R[mio_pad_attr_20]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_20 ( + .re (mio_pad_attr_20_re), + // qualified with register enable + .we (mio_pad_attr_20_we & mio_pad_attr_regwen_20_qs), + .wd (mio_pad_attr_20_wd), + .d (hw2reg.mio_pad_attr[20].d), + .qre (), + .qe (reg2hw.mio_pad_attr[20].qe), + .q (reg2hw.mio_pad_attr[20].q ), + .qs (mio_pad_attr_20_qs) + ); + + // Subregister 21 of Multireg mio_pad_attr + // R[mio_pad_attr_21]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_21 ( + .re (mio_pad_attr_21_re), + // qualified with register enable + .we (mio_pad_attr_21_we & mio_pad_attr_regwen_21_qs), + .wd (mio_pad_attr_21_wd), + .d (hw2reg.mio_pad_attr[21].d), + .qre (), + .qe (reg2hw.mio_pad_attr[21].qe), + .q (reg2hw.mio_pad_attr[21].q ), + .qs (mio_pad_attr_21_qs) + ); + + // Subregister 22 of Multireg mio_pad_attr + // R[mio_pad_attr_22]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_22 ( + .re (mio_pad_attr_22_re), + // qualified with register enable + .we (mio_pad_attr_22_we & mio_pad_attr_regwen_22_qs), + .wd (mio_pad_attr_22_wd), + .d (hw2reg.mio_pad_attr[22].d), + .qre (), + .qe (reg2hw.mio_pad_attr[22].qe), + .q (reg2hw.mio_pad_attr[22].q ), + .qs (mio_pad_attr_22_qs) + ); + + // Subregister 23 of Multireg mio_pad_attr + // R[mio_pad_attr_23]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_23 ( + .re (mio_pad_attr_23_re), + // qualified with register enable + .we (mio_pad_attr_23_we & mio_pad_attr_regwen_23_qs), + .wd (mio_pad_attr_23_wd), + .d (hw2reg.mio_pad_attr[23].d), + .qre (), + .qe (reg2hw.mio_pad_attr[23].qe), + .q (reg2hw.mio_pad_attr[23].q ), + .qs (mio_pad_attr_23_qs) + ); + + // Subregister 24 of Multireg mio_pad_attr + // R[mio_pad_attr_24]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_24 ( + .re (mio_pad_attr_24_re), + // qualified with register enable + .we (mio_pad_attr_24_we & mio_pad_attr_regwen_24_qs), + .wd (mio_pad_attr_24_wd), + .d (hw2reg.mio_pad_attr[24].d), + .qre (), + .qe (reg2hw.mio_pad_attr[24].qe), + .q (reg2hw.mio_pad_attr[24].q ), + .qs (mio_pad_attr_24_qs) + ); + + // Subregister 25 of Multireg mio_pad_attr + // R[mio_pad_attr_25]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_25 ( + .re (mio_pad_attr_25_re), + // qualified with register enable + .we (mio_pad_attr_25_we & mio_pad_attr_regwen_25_qs), + .wd (mio_pad_attr_25_wd), + .d (hw2reg.mio_pad_attr[25].d), + .qre (), + .qe (reg2hw.mio_pad_attr[25].qe), + .q (reg2hw.mio_pad_attr[25].q ), + .qs (mio_pad_attr_25_qs) + ); + + // Subregister 26 of Multireg mio_pad_attr + // R[mio_pad_attr_26]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_26 ( + .re (mio_pad_attr_26_re), + // qualified with register enable + .we (mio_pad_attr_26_we & mio_pad_attr_regwen_26_qs), + .wd (mio_pad_attr_26_wd), + .d (hw2reg.mio_pad_attr[26].d), + .qre (), + .qe (reg2hw.mio_pad_attr[26].qe), + .q (reg2hw.mio_pad_attr[26].q ), + .qs (mio_pad_attr_26_qs) + ); + + // Subregister 27 of Multireg mio_pad_attr + // R[mio_pad_attr_27]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_27 ( + .re (mio_pad_attr_27_re), + // qualified with register enable + .we (mio_pad_attr_27_we & mio_pad_attr_regwen_27_qs), + .wd (mio_pad_attr_27_wd), + .d (hw2reg.mio_pad_attr[27].d), + .qre (), + .qe (reg2hw.mio_pad_attr[27].qe), + .q (reg2hw.mio_pad_attr[27].q ), + .qs (mio_pad_attr_27_qs) + ); + + // Subregister 28 of Multireg mio_pad_attr + // R[mio_pad_attr_28]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_28 ( + .re (mio_pad_attr_28_re), + // qualified with register enable + .we (mio_pad_attr_28_we & mio_pad_attr_regwen_28_qs), + .wd (mio_pad_attr_28_wd), + .d (hw2reg.mio_pad_attr[28].d), + .qre (), + .qe (reg2hw.mio_pad_attr[28].qe), + .q (reg2hw.mio_pad_attr[28].q ), + .qs (mio_pad_attr_28_qs) + ); + + // Subregister 29 of Multireg mio_pad_attr + // R[mio_pad_attr_29]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_29 ( + .re (mio_pad_attr_29_re), + // qualified with register enable + .we (mio_pad_attr_29_we & mio_pad_attr_regwen_29_qs), + .wd (mio_pad_attr_29_wd), + .d (hw2reg.mio_pad_attr[29].d), + .qre (), + .qe (reg2hw.mio_pad_attr[29].qe), + .q (reg2hw.mio_pad_attr[29].q ), + .qs (mio_pad_attr_29_qs) + ); + + // Subregister 30 of Multireg mio_pad_attr + // R[mio_pad_attr_30]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_30 ( + .re (mio_pad_attr_30_re), + // qualified with register enable + .we (mio_pad_attr_30_we & mio_pad_attr_regwen_30_qs), + .wd (mio_pad_attr_30_wd), + .d (hw2reg.mio_pad_attr[30].d), + .qre (), + .qe (reg2hw.mio_pad_attr[30].qe), + .q (reg2hw.mio_pad_attr[30].q ), + .qs (mio_pad_attr_30_qs) + ); + + // Subregister 31 of Multireg mio_pad_attr + // R[mio_pad_attr_31]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_31 ( + .re (mio_pad_attr_31_re), + // qualified with register enable + .we (mio_pad_attr_31_we & mio_pad_attr_regwen_31_qs), + .wd (mio_pad_attr_31_wd), + .d (hw2reg.mio_pad_attr[31].d), + .qre (), + .qe (reg2hw.mio_pad_attr[31].qe), + .q (reg2hw.mio_pad_attr[31].q ), + .qs (mio_pad_attr_31_qs) + ); + + + + // Subregister 0 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_0]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_0_we), + .wd (dio_pad_attr_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_0_qs) + ); + + // Subregister 1 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_1]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_1_we), + .wd (dio_pad_attr_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_1_qs) + ); + + // Subregister 2 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_2]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_2_we), + .wd (dio_pad_attr_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_2_qs) + ); + + // Subregister 3 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_3]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_3_we), + .wd (dio_pad_attr_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_3_qs) + ); + + // Subregister 4 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_4]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_4_we), + .wd (dio_pad_attr_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_4_qs) + ); + + // Subregister 5 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_5]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_5_we), + .wd (dio_pad_attr_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_5_qs) + ); + + // Subregister 6 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_6]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_6_we), + .wd (dio_pad_attr_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_6_qs) + ); + + // Subregister 7 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_7]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_7_we), + .wd (dio_pad_attr_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_7_qs) + ); + + // Subregister 8 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_8]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_8_we), + .wd (dio_pad_attr_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_8_qs) + ); + + // Subregister 9 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_9]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_9_we), + .wd (dio_pad_attr_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_9_qs) + ); + + // Subregister 10 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_10]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_10_we), + .wd (dio_pad_attr_regwen_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_10_qs) + ); + + // Subregister 11 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_11]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_11_we), + .wd (dio_pad_attr_regwen_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_11_qs) + ); + + // Subregister 12 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_12]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_12_we), + .wd (dio_pad_attr_regwen_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_12_qs) + ); + + // Subregister 13 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_13]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_13_we), + .wd (dio_pad_attr_regwen_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_13_qs) + ); + + // Subregister 14 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_14]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_14_we), + .wd (dio_pad_attr_regwen_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_14_qs) + ); + + // Subregister 15 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_15]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_15_we), + .wd (dio_pad_attr_regwen_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_15_qs) + ); + + + + // Subregister 0 of Multireg dio_pad_attr + // R[dio_pad_attr_0]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_0 ( + .re (dio_pad_attr_0_re), + // qualified with register enable + .we (dio_pad_attr_0_we & dio_pad_attr_regwen_0_qs), + .wd (dio_pad_attr_0_wd), + .d (hw2reg.dio_pad_attr[0].d), + .qre (), + .qe (reg2hw.dio_pad_attr[0].qe), + .q (reg2hw.dio_pad_attr[0].q ), + .qs (dio_pad_attr_0_qs) + ); + + // Subregister 1 of Multireg dio_pad_attr + // R[dio_pad_attr_1]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_1 ( + .re (dio_pad_attr_1_re), + // qualified with register enable + .we (dio_pad_attr_1_we & dio_pad_attr_regwen_1_qs), + .wd (dio_pad_attr_1_wd), + .d (hw2reg.dio_pad_attr[1].d), + .qre (), + .qe (reg2hw.dio_pad_attr[1].qe), + .q (reg2hw.dio_pad_attr[1].q ), + .qs (dio_pad_attr_1_qs) + ); + + // Subregister 2 of Multireg dio_pad_attr + // R[dio_pad_attr_2]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_2 ( + .re (dio_pad_attr_2_re), + // qualified with register enable + .we (dio_pad_attr_2_we & dio_pad_attr_regwen_2_qs), + .wd (dio_pad_attr_2_wd), + .d (hw2reg.dio_pad_attr[2].d), + .qre (), + .qe (reg2hw.dio_pad_attr[2].qe), + .q (reg2hw.dio_pad_attr[2].q ), + .qs (dio_pad_attr_2_qs) + ); + + // Subregister 3 of Multireg dio_pad_attr + // R[dio_pad_attr_3]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_3 ( + .re (dio_pad_attr_3_re), + // qualified with register enable + .we (dio_pad_attr_3_we & dio_pad_attr_regwen_3_qs), + .wd (dio_pad_attr_3_wd), + .d (hw2reg.dio_pad_attr[3].d), + .qre (), + .qe (reg2hw.dio_pad_attr[3].qe), + .q (reg2hw.dio_pad_attr[3].q ), + .qs (dio_pad_attr_3_qs) + ); + + // Subregister 4 of Multireg dio_pad_attr + // R[dio_pad_attr_4]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_4 ( + .re (dio_pad_attr_4_re), + // qualified with register enable + .we (dio_pad_attr_4_we & dio_pad_attr_regwen_4_qs), + .wd (dio_pad_attr_4_wd), + .d (hw2reg.dio_pad_attr[4].d), + .qre (), + .qe (reg2hw.dio_pad_attr[4].qe), + .q (reg2hw.dio_pad_attr[4].q ), + .qs (dio_pad_attr_4_qs) + ); + + // Subregister 5 of Multireg dio_pad_attr + // R[dio_pad_attr_5]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_5 ( + .re (dio_pad_attr_5_re), + // qualified with register enable + .we (dio_pad_attr_5_we & dio_pad_attr_regwen_5_qs), + .wd (dio_pad_attr_5_wd), + .d (hw2reg.dio_pad_attr[5].d), + .qre (), + .qe (reg2hw.dio_pad_attr[5].qe), + .q (reg2hw.dio_pad_attr[5].q ), + .qs (dio_pad_attr_5_qs) + ); + + // Subregister 6 of Multireg dio_pad_attr + // R[dio_pad_attr_6]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_6 ( + .re (dio_pad_attr_6_re), + // qualified with register enable + .we (dio_pad_attr_6_we & dio_pad_attr_regwen_6_qs), + .wd (dio_pad_attr_6_wd), + .d (hw2reg.dio_pad_attr[6].d), + .qre (), + .qe (reg2hw.dio_pad_attr[6].qe), + .q (reg2hw.dio_pad_attr[6].q ), + .qs (dio_pad_attr_6_qs) + ); + + // Subregister 7 of Multireg dio_pad_attr + // R[dio_pad_attr_7]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_7 ( + .re (dio_pad_attr_7_re), + // qualified with register enable + .we (dio_pad_attr_7_we & dio_pad_attr_regwen_7_qs), + .wd (dio_pad_attr_7_wd), + .d (hw2reg.dio_pad_attr[7].d), + .qre (), + .qe (reg2hw.dio_pad_attr[7].qe), + .q (reg2hw.dio_pad_attr[7].q ), + .qs (dio_pad_attr_7_qs) + ); + + // Subregister 8 of Multireg dio_pad_attr + // R[dio_pad_attr_8]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_8 ( + .re (dio_pad_attr_8_re), + // qualified with register enable + .we (dio_pad_attr_8_we & dio_pad_attr_regwen_8_qs), + .wd (dio_pad_attr_8_wd), + .d (hw2reg.dio_pad_attr[8].d), + .qre (), + .qe (reg2hw.dio_pad_attr[8].qe), + .q (reg2hw.dio_pad_attr[8].q ), + .qs (dio_pad_attr_8_qs) + ); + + // Subregister 9 of Multireg dio_pad_attr + // R[dio_pad_attr_9]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_9 ( + .re (dio_pad_attr_9_re), + // qualified with register enable + .we (dio_pad_attr_9_we & dio_pad_attr_regwen_9_qs), + .wd (dio_pad_attr_9_wd), + .d (hw2reg.dio_pad_attr[9].d), + .qre (), + .qe (reg2hw.dio_pad_attr[9].qe), + .q (reg2hw.dio_pad_attr[9].q ), + .qs (dio_pad_attr_9_qs) + ); + + // Subregister 10 of Multireg dio_pad_attr + // R[dio_pad_attr_10]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_10 ( + .re (dio_pad_attr_10_re), + // qualified with register enable + .we (dio_pad_attr_10_we & dio_pad_attr_regwen_10_qs), + .wd (dio_pad_attr_10_wd), + .d (hw2reg.dio_pad_attr[10].d), + .qre (), + .qe (reg2hw.dio_pad_attr[10].qe), + .q (reg2hw.dio_pad_attr[10].q ), + .qs (dio_pad_attr_10_qs) + ); + + // Subregister 11 of Multireg dio_pad_attr + // R[dio_pad_attr_11]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_11 ( + .re (dio_pad_attr_11_re), + // qualified with register enable + .we (dio_pad_attr_11_we & dio_pad_attr_regwen_11_qs), + .wd (dio_pad_attr_11_wd), + .d (hw2reg.dio_pad_attr[11].d), + .qre (), + .qe (reg2hw.dio_pad_attr[11].qe), + .q (reg2hw.dio_pad_attr[11].q ), + .qs (dio_pad_attr_11_qs) + ); + + // Subregister 12 of Multireg dio_pad_attr + // R[dio_pad_attr_12]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_12 ( + .re (dio_pad_attr_12_re), + // qualified with register enable + .we (dio_pad_attr_12_we & dio_pad_attr_regwen_12_qs), + .wd (dio_pad_attr_12_wd), + .d (hw2reg.dio_pad_attr[12].d), + .qre (), + .qe (reg2hw.dio_pad_attr[12].qe), + .q (reg2hw.dio_pad_attr[12].q ), + .qs (dio_pad_attr_12_qs) + ); + + // Subregister 13 of Multireg dio_pad_attr + // R[dio_pad_attr_13]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_13 ( + .re (dio_pad_attr_13_re), + // qualified with register enable + .we (dio_pad_attr_13_we & dio_pad_attr_regwen_13_qs), + .wd (dio_pad_attr_13_wd), + .d (hw2reg.dio_pad_attr[13].d), + .qre (), + .qe (reg2hw.dio_pad_attr[13].qe), + .q (reg2hw.dio_pad_attr[13].q ), + .qs (dio_pad_attr_13_qs) + ); + + // Subregister 14 of Multireg dio_pad_attr + // R[dio_pad_attr_14]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_14 ( + .re (dio_pad_attr_14_re), + // qualified with register enable + .we (dio_pad_attr_14_we & dio_pad_attr_regwen_14_qs), + .wd (dio_pad_attr_14_wd), + .d (hw2reg.dio_pad_attr[14].d), + .qre (), + .qe (reg2hw.dio_pad_attr[14].qe), + .q (reg2hw.dio_pad_attr[14].q ), + .qs (dio_pad_attr_14_qs) + ); + + // Subregister 15 of Multireg dio_pad_attr + // R[dio_pad_attr_15]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_15 ( + .re (dio_pad_attr_15_re), + // qualified with register enable + .we (dio_pad_attr_15_we & dio_pad_attr_regwen_15_qs), + .wd (dio_pad_attr_15_wd), + .d (hw2reg.dio_pad_attr[15].d), + .qre (), + .qe (reg2hw.dio_pad_attr[15].qe), + .q (reg2hw.dio_pad_attr[15].q ), + .qs (dio_pad_attr_15_qs) + ); + + + + // Subregister 0 of Multireg mio_pad_sleep_status + // R[mio_pad_sleep_status]: V(False) + + // F[en_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_0_we), + .wd (mio_pad_sleep_status_en_0_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[0].de), + .d (hw2reg.mio_pad_sleep_status[0].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[0].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_0_qs) + ); + + + // F[en_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_1_we), + .wd (mio_pad_sleep_status_en_1_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[1].de), + .d (hw2reg.mio_pad_sleep_status[1].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[1].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_1_qs) + ); + + + // F[en_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_2_we), + .wd (mio_pad_sleep_status_en_2_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[2].de), + .d (hw2reg.mio_pad_sleep_status[2].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[2].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_2_qs) + ); + + + // F[en_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_3_we), + .wd (mio_pad_sleep_status_en_3_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[3].de), + .d (hw2reg.mio_pad_sleep_status[3].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[3].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_3_qs) + ); + + + // F[en_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_4_we), + .wd (mio_pad_sleep_status_en_4_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[4].de), + .d (hw2reg.mio_pad_sleep_status[4].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[4].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_4_qs) + ); + + + // F[en_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_5_we), + .wd (mio_pad_sleep_status_en_5_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[5].de), + .d (hw2reg.mio_pad_sleep_status[5].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[5].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_5_qs) + ); + + + // F[en_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_6_we), + .wd (mio_pad_sleep_status_en_6_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[6].de), + .d (hw2reg.mio_pad_sleep_status[6].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[6].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_6_qs) + ); + + + // F[en_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_7_we), + .wd (mio_pad_sleep_status_en_7_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[7].de), + .d (hw2reg.mio_pad_sleep_status[7].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[7].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_7_qs) + ); + + + // F[en_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_8_we), + .wd (mio_pad_sleep_status_en_8_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[8].de), + .d (hw2reg.mio_pad_sleep_status[8].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[8].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_8_qs) + ); + + + // F[en_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_9_we), + .wd (mio_pad_sleep_status_en_9_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[9].de), + .d (hw2reg.mio_pad_sleep_status[9].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[9].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_9_qs) + ); + + + // F[en_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_10_we), + .wd (mio_pad_sleep_status_en_10_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[10].de), + .d (hw2reg.mio_pad_sleep_status[10].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[10].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_10_qs) + ); + + + // F[en_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_11_we), + .wd (mio_pad_sleep_status_en_11_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[11].de), + .d (hw2reg.mio_pad_sleep_status[11].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[11].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_11_qs) + ); + + + // F[en_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_12_we), + .wd (mio_pad_sleep_status_en_12_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[12].de), + .d (hw2reg.mio_pad_sleep_status[12].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[12].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_12_qs) + ); + + + // F[en_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_13_we), + .wd (mio_pad_sleep_status_en_13_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[13].de), + .d (hw2reg.mio_pad_sleep_status[13].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[13].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_13_qs) + ); + + + // F[en_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_14_we), + .wd (mio_pad_sleep_status_en_14_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[14].de), + .d (hw2reg.mio_pad_sleep_status[14].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[14].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_14_qs) + ); + + + // F[en_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_15_we), + .wd (mio_pad_sleep_status_en_15_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[15].de), + .d (hw2reg.mio_pad_sleep_status[15].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[15].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_15_qs) + ); + + + // F[en_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_16_we), + .wd (mio_pad_sleep_status_en_16_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[16].de), + .d (hw2reg.mio_pad_sleep_status[16].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[16].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_16_qs) + ); + + + // F[en_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_17_we), + .wd (mio_pad_sleep_status_en_17_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[17].de), + .d (hw2reg.mio_pad_sleep_status[17].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[17].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_17_qs) + ); + + + // F[en_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_18_we), + .wd (mio_pad_sleep_status_en_18_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[18].de), + .d (hw2reg.mio_pad_sleep_status[18].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[18].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_18_qs) + ); + + + // F[en_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_19_we), + .wd (mio_pad_sleep_status_en_19_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[19].de), + .d (hw2reg.mio_pad_sleep_status[19].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[19].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_19_qs) + ); + + + // F[en_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_20_we), + .wd (mio_pad_sleep_status_en_20_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[20].de), + .d (hw2reg.mio_pad_sleep_status[20].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[20].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_20_qs) + ); + + + // F[en_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_21_we), + .wd (mio_pad_sleep_status_en_21_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[21].de), + .d (hw2reg.mio_pad_sleep_status[21].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[21].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_21_qs) + ); + + + // F[en_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_22_we), + .wd (mio_pad_sleep_status_en_22_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[22].de), + .d (hw2reg.mio_pad_sleep_status[22].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[22].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_22_qs) + ); + + + // F[en_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_23_we), + .wd (mio_pad_sleep_status_en_23_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[23].de), + .d (hw2reg.mio_pad_sleep_status[23].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[23].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_23_qs) + ); + + + // F[en_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_24_we), + .wd (mio_pad_sleep_status_en_24_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[24].de), + .d (hw2reg.mio_pad_sleep_status[24].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[24].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_24_qs) + ); + + + // F[en_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_25_we), + .wd (mio_pad_sleep_status_en_25_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[25].de), + .d (hw2reg.mio_pad_sleep_status[25].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[25].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_25_qs) + ); + + + // F[en_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_26_we), + .wd (mio_pad_sleep_status_en_26_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[26].de), + .d (hw2reg.mio_pad_sleep_status[26].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[26].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_26_qs) + ); + + + // F[en_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_27_we), + .wd (mio_pad_sleep_status_en_27_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[27].de), + .d (hw2reg.mio_pad_sleep_status[27].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[27].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_27_qs) + ); + + + // F[en_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_28_we), + .wd (mio_pad_sleep_status_en_28_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[28].de), + .d (hw2reg.mio_pad_sleep_status[28].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[28].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_28_qs) + ); + + + // F[en_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_29_we), + .wd (mio_pad_sleep_status_en_29_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[29].de), + .d (hw2reg.mio_pad_sleep_status[29].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[29].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_29_qs) + ); + + + // F[en_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_30_we), + .wd (mio_pad_sleep_status_en_30_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[30].de), + .d (hw2reg.mio_pad_sleep_status[30].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[30].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_30_qs) + ); + + + // F[en_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_31_we), + .wd (mio_pad_sleep_status_en_31_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[31].de), + .d (hw2reg.mio_pad_sleep_status[31].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[31].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_31_qs) + ); + + + + + // Subregister 0 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_0]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_0_we), + .wd (mio_pad_sleep_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_0_qs) + ); + + // Subregister 1 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_1]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_1_we), + .wd (mio_pad_sleep_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_1_qs) + ); + + // Subregister 2 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_2]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_2_we), + .wd (mio_pad_sleep_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_2_qs) + ); + + // Subregister 3 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_3]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_3_we), + .wd (mio_pad_sleep_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_3_qs) + ); + + // Subregister 4 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_4]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_4_we), + .wd (mio_pad_sleep_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_4_qs) + ); + + // Subregister 5 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_5]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_5_we), + .wd (mio_pad_sleep_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_5_qs) + ); + + // Subregister 6 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_6]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_6_we), + .wd (mio_pad_sleep_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_6_qs) + ); + + // Subregister 7 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_7]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_7_we), + .wd (mio_pad_sleep_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_7_qs) + ); + + // Subregister 8 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_8]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_8_we), + .wd (mio_pad_sleep_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_8_qs) + ); + + // Subregister 9 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_9]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_9_we), + .wd (mio_pad_sleep_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_9_qs) + ); + + // Subregister 10 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_10]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_10_we), + .wd (mio_pad_sleep_regwen_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_10_qs) + ); + + // Subregister 11 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_11]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_11_we), + .wd (mio_pad_sleep_regwen_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_11_qs) + ); + + // Subregister 12 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_12]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_12_we), + .wd (mio_pad_sleep_regwen_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_12_qs) + ); + + // Subregister 13 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_13]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_13_we), + .wd (mio_pad_sleep_regwen_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_13_qs) + ); + + // Subregister 14 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_14]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_14_we), + .wd (mio_pad_sleep_regwen_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_14_qs) + ); + + // Subregister 15 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_15]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_15_we), + .wd (mio_pad_sleep_regwen_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_15_qs) + ); + + // Subregister 16 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_16]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_16_we), + .wd (mio_pad_sleep_regwen_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_16_qs) + ); + + // Subregister 17 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_17]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_17_we), + .wd (mio_pad_sleep_regwen_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_17_qs) + ); + + // Subregister 18 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_18]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_18_we), + .wd (mio_pad_sleep_regwen_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_18_qs) + ); + + // Subregister 19 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_19]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_19_we), + .wd (mio_pad_sleep_regwen_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_19_qs) + ); + + // Subregister 20 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_20]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_20_we), + .wd (mio_pad_sleep_regwen_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_20_qs) + ); + + // Subregister 21 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_21]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_21_we), + .wd (mio_pad_sleep_regwen_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_21_qs) + ); + + // Subregister 22 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_22]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_22_we), + .wd (mio_pad_sleep_regwen_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_22_qs) + ); + + // Subregister 23 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_23]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_23_we), + .wd (mio_pad_sleep_regwen_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_23_qs) + ); + + // Subregister 24 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_24]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_24_we), + .wd (mio_pad_sleep_regwen_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_24_qs) + ); + + // Subregister 25 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_25]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_25_we), + .wd (mio_pad_sleep_regwen_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_25_qs) + ); + + // Subregister 26 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_26]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_26_we), + .wd (mio_pad_sleep_regwen_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_26_qs) + ); + + // Subregister 27 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_27]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_27_we), + .wd (mio_pad_sleep_regwen_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_27_qs) + ); + + // Subregister 28 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_28]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_28_we), + .wd (mio_pad_sleep_regwen_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_28_qs) + ); + + // Subregister 29 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_29]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_29_we), + .wd (mio_pad_sleep_regwen_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_29_qs) + ); + + // Subregister 30 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_30]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_30_we), + .wd (mio_pad_sleep_regwen_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_30_qs) + ); + + // Subregister 31 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_31]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_31_we), + .wd (mio_pad_sleep_regwen_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_31_qs) + ); + + + + // Subregister 0 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_0]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_0_we & mio_pad_sleep_regwen_0_qs), + .wd (mio_pad_sleep_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[0].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_0_qs) + ); + + // Subregister 1 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_1]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_1_we & mio_pad_sleep_regwen_1_qs), + .wd (mio_pad_sleep_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[1].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_1_qs) + ); + + // Subregister 2 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_2]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_2_we & mio_pad_sleep_regwen_2_qs), + .wd (mio_pad_sleep_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[2].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_2_qs) + ); + + // Subregister 3 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_3]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_3_we & mio_pad_sleep_regwen_3_qs), + .wd (mio_pad_sleep_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[3].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_3_qs) + ); + + // Subregister 4 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_4]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_4_we & mio_pad_sleep_regwen_4_qs), + .wd (mio_pad_sleep_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[4].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_4_qs) + ); + + // Subregister 5 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_5]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_5_we & mio_pad_sleep_regwen_5_qs), + .wd (mio_pad_sleep_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[5].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_5_qs) + ); + + // Subregister 6 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_6]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_6_we & mio_pad_sleep_regwen_6_qs), + .wd (mio_pad_sleep_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[6].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_6_qs) + ); + + // Subregister 7 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_7]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_7_we & mio_pad_sleep_regwen_7_qs), + .wd (mio_pad_sleep_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[7].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_7_qs) + ); + + // Subregister 8 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_8]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_8_we & mio_pad_sleep_regwen_8_qs), + .wd (mio_pad_sleep_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[8].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_8_qs) + ); + + // Subregister 9 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_9]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_9_we & mio_pad_sleep_regwen_9_qs), + .wd (mio_pad_sleep_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[9].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_9_qs) + ); + + // Subregister 10 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_10]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_10_we & mio_pad_sleep_regwen_10_qs), + .wd (mio_pad_sleep_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[10].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_10_qs) + ); + + // Subregister 11 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_11]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_11_we & mio_pad_sleep_regwen_11_qs), + .wd (mio_pad_sleep_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[11].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_11_qs) + ); + + // Subregister 12 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_12]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_12_we & mio_pad_sleep_regwen_12_qs), + .wd (mio_pad_sleep_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[12].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_12_qs) + ); + + // Subregister 13 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_13]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_13_we & mio_pad_sleep_regwen_13_qs), + .wd (mio_pad_sleep_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[13].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_13_qs) + ); + + // Subregister 14 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_14]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_14_we & mio_pad_sleep_regwen_14_qs), + .wd (mio_pad_sleep_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[14].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_14_qs) + ); + + // Subregister 15 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_15]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_15_we & mio_pad_sleep_regwen_15_qs), + .wd (mio_pad_sleep_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[15].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_15_qs) + ); + + // Subregister 16 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_16]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_16_we & mio_pad_sleep_regwen_16_qs), + .wd (mio_pad_sleep_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[16].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_16_qs) + ); + + // Subregister 17 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_17]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_17_we & mio_pad_sleep_regwen_17_qs), + .wd (mio_pad_sleep_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[17].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_17_qs) + ); + + // Subregister 18 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_18]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_18_we & mio_pad_sleep_regwen_18_qs), + .wd (mio_pad_sleep_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[18].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_18_qs) + ); + + // Subregister 19 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_19]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_19_we & mio_pad_sleep_regwen_19_qs), + .wd (mio_pad_sleep_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[19].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_19_qs) + ); + + // Subregister 20 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_20]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_20_we & mio_pad_sleep_regwen_20_qs), + .wd (mio_pad_sleep_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[20].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_20_qs) + ); + + // Subregister 21 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_21]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_21_we & mio_pad_sleep_regwen_21_qs), + .wd (mio_pad_sleep_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[21].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_21_qs) + ); + + // Subregister 22 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_22]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_22_we & mio_pad_sleep_regwen_22_qs), + .wd (mio_pad_sleep_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[22].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_22_qs) + ); + + // Subregister 23 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_23]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_23_we & mio_pad_sleep_regwen_23_qs), + .wd (mio_pad_sleep_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[23].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_23_qs) + ); + + // Subregister 24 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_24]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_24_we & mio_pad_sleep_regwen_24_qs), + .wd (mio_pad_sleep_en_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[24].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_24_qs) + ); + + // Subregister 25 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_25]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_25_we & mio_pad_sleep_regwen_25_qs), + .wd (mio_pad_sleep_en_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[25].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_25_qs) + ); + + // Subregister 26 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_26]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_26_we & mio_pad_sleep_regwen_26_qs), + .wd (mio_pad_sleep_en_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[26].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_26_qs) + ); + + // Subregister 27 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_27]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_27_we & mio_pad_sleep_regwen_27_qs), + .wd (mio_pad_sleep_en_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[27].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_27_qs) + ); + + // Subregister 28 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_28]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_28_we & mio_pad_sleep_regwen_28_qs), + .wd (mio_pad_sleep_en_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[28].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_28_qs) + ); + + // Subregister 29 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_29]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_29_we & mio_pad_sleep_regwen_29_qs), + .wd (mio_pad_sleep_en_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[29].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_29_qs) + ); + + // Subregister 30 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_30]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_30_we & mio_pad_sleep_regwen_30_qs), + .wd (mio_pad_sleep_en_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[30].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_30_qs) + ); + + // Subregister 31 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_31]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_31_we & mio_pad_sleep_regwen_31_qs), + .wd (mio_pad_sleep_en_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[31].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_31_qs) + ); + + + + // Subregister 0 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_0]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_0_we & mio_pad_sleep_regwen_0_qs), + .wd (mio_pad_sleep_mode_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[0].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_0_qs) + ); + + // Subregister 1 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_1]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_1_we & mio_pad_sleep_regwen_1_qs), + .wd (mio_pad_sleep_mode_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[1].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_1_qs) + ); + + // Subregister 2 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_2]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_2_we & mio_pad_sleep_regwen_2_qs), + .wd (mio_pad_sleep_mode_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[2].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_2_qs) + ); + + // Subregister 3 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_3]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_3_we & mio_pad_sleep_regwen_3_qs), + .wd (mio_pad_sleep_mode_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[3].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_3_qs) + ); + + // Subregister 4 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_4]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_4_we & mio_pad_sleep_regwen_4_qs), + .wd (mio_pad_sleep_mode_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[4].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_4_qs) + ); + + // Subregister 5 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_5]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_5_we & mio_pad_sleep_regwen_5_qs), + .wd (mio_pad_sleep_mode_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[5].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_5_qs) + ); + + // Subregister 6 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_6]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_6_we & mio_pad_sleep_regwen_6_qs), + .wd (mio_pad_sleep_mode_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[6].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_6_qs) + ); + + // Subregister 7 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_7]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_7_we & mio_pad_sleep_regwen_7_qs), + .wd (mio_pad_sleep_mode_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[7].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_7_qs) + ); + + // Subregister 8 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_8]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_8_we & mio_pad_sleep_regwen_8_qs), + .wd (mio_pad_sleep_mode_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[8].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_8_qs) + ); + + // Subregister 9 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_9]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_9_we & mio_pad_sleep_regwen_9_qs), + .wd (mio_pad_sleep_mode_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[9].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_9_qs) + ); + + // Subregister 10 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_10]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_10_we & mio_pad_sleep_regwen_10_qs), + .wd (mio_pad_sleep_mode_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[10].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_10_qs) + ); + + // Subregister 11 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_11]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_11_we & mio_pad_sleep_regwen_11_qs), + .wd (mio_pad_sleep_mode_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[11].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_11_qs) + ); + + // Subregister 12 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_12]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_12_we & mio_pad_sleep_regwen_12_qs), + .wd (mio_pad_sleep_mode_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[12].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_12_qs) + ); + + // Subregister 13 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_13]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_13_we & mio_pad_sleep_regwen_13_qs), + .wd (mio_pad_sleep_mode_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[13].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_13_qs) + ); + + // Subregister 14 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_14]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_14_we & mio_pad_sleep_regwen_14_qs), + .wd (mio_pad_sleep_mode_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[14].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_14_qs) + ); + + // Subregister 15 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_15]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_15_we & mio_pad_sleep_regwen_15_qs), + .wd (mio_pad_sleep_mode_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[15].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_15_qs) + ); + + // Subregister 16 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_16]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_16_we & mio_pad_sleep_regwen_16_qs), + .wd (mio_pad_sleep_mode_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[16].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_16_qs) + ); + + // Subregister 17 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_17]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_17_we & mio_pad_sleep_regwen_17_qs), + .wd (mio_pad_sleep_mode_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[17].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_17_qs) + ); + + // Subregister 18 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_18]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_18_we & mio_pad_sleep_regwen_18_qs), + .wd (mio_pad_sleep_mode_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[18].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_18_qs) + ); + + // Subregister 19 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_19]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_19_we & mio_pad_sleep_regwen_19_qs), + .wd (mio_pad_sleep_mode_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[19].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_19_qs) + ); + + // Subregister 20 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_20]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_20_we & mio_pad_sleep_regwen_20_qs), + .wd (mio_pad_sleep_mode_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[20].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_20_qs) + ); + + // Subregister 21 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_21]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_21_we & mio_pad_sleep_regwen_21_qs), + .wd (mio_pad_sleep_mode_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[21].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_21_qs) + ); + + // Subregister 22 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_22]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_22_we & mio_pad_sleep_regwen_22_qs), + .wd (mio_pad_sleep_mode_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[22].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_22_qs) + ); + + // Subregister 23 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_23]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_23_we & mio_pad_sleep_regwen_23_qs), + .wd (mio_pad_sleep_mode_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[23].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_23_qs) + ); + + // Subregister 24 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_24]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_24_we & mio_pad_sleep_regwen_24_qs), + .wd (mio_pad_sleep_mode_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[24].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_24_qs) + ); + + // Subregister 25 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_25]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_25_we & mio_pad_sleep_regwen_25_qs), + .wd (mio_pad_sleep_mode_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[25].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_25_qs) + ); + + // Subregister 26 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_26]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_26_we & mio_pad_sleep_regwen_26_qs), + .wd (mio_pad_sleep_mode_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[26].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_26_qs) + ); + + // Subregister 27 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_27]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_27_we & mio_pad_sleep_regwen_27_qs), + .wd (mio_pad_sleep_mode_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[27].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_27_qs) + ); + + // Subregister 28 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_28]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_28_we & mio_pad_sleep_regwen_28_qs), + .wd (mio_pad_sleep_mode_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[28].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_28_qs) + ); + + // Subregister 29 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_29]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_29_we & mio_pad_sleep_regwen_29_qs), + .wd (mio_pad_sleep_mode_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[29].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_29_qs) + ); + + // Subregister 30 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_30]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_30_we & mio_pad_sleep_regwen_30_qs), + .wd (mio_pad_sleep_mode_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[30].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_30_qs) + ); + + // Subregister 31 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_31]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_31_we & mio_pad_sleep_regwen_31_qs), + .wd (mio_pad_sleep_mode_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[31].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_31_qs) + ); + + + + // Subregister 0 of Multireg dio_pad_sleep_status + // R[dio_pad_sleep_status]: V(False) + + // F[en_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_0_we), + .wd (dio_pad_sleep_status_en_0_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[0].de), + .d (hw2reg.dio_pad_sleep_status[0].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[0].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_0_qs) + ); + + + // F[en_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_1_we), + .wd (dio_pad_sleep_status_en_1_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[1].de), + .d (hw2reg.dio_pad_sleep_status[1].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[1].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_1_qs) + ); + + + // F[en_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_2_we), + .wd (dio_pad_sleep_status_en_2_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[2].de), + .d (hw2reg.dio_pad_sleep_status[2].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[2].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_2_qs) + ); + + + // F[en_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_3_we), + .wd (dio_pad_sleep_status_en_3_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[3].de), + .d (hw2reg.dio_pad_sleep_status[3].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[3].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_3_qs) + ); + + + // F[en_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_4_we), + .wd (dio_pad_sleep_status_en_4_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[4].de), + .d (hw2reg.dio_pad_sleep_status[4].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[4].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_4_qs) + ); + + + // F[en_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_5_we), + .wd (dio_pad_sleep_status_en_5_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[5].de), + .d (hw2reg.dio_pad_sleep_status[5].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[5].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_5_qs) + ); + + + // F[en_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_6_we), + .wd (dio_pad_sleep_status_en_6_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[6].de), + .d (hw2reg.dio_pad_sleep_status[6].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[6].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_6_qs) + ); + + + // F[en_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_7_we), + .wd (dio_pad_sleep_status_en_7_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[7].de), + .d (hw2reg.dio_pad_sleep_status[7].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[7].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_7_qs) + ); + + + // F[en_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_8_we), + .wd (dio_pad_sleep_status_en_8_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[8].de), + .d (hw2reg.dio_pad_sleep_status[8].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[8].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_8_qs) + ); + + + // F[en_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_9_we), + .wd (dio_pad_sleep_status_en_9_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[9].de), + .d (hw2reg.dio_pad_sleep_status[9].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[9].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_9_qs) + ); + + + // F[en_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_10_we), + .wd (dio_pad_sleep_status_en_10_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[10].de), + .d (hw2reg.dio_pad_sleep_status[10].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[10].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_10_qs) + ); + + + // F[en_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_11_we), + .wd (dio_pad_sleep_status_en_11_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[11].de), + .d (hw2reg.dio_pad_sleep_status[11].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[11].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_11_qs) + ); + + + // F[en_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_12_we), + .wd (dio_pad_sleep_status_en_12_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[12].de), + .d (hw2reg.dio_pad_sleep_status[12].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[12].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_12_qs) + ); + + + // F[en_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_13_we), + .wd (dio_pad_sleep_status_en_13_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[13].de), + .d (hw2reg.dio_pad_sleep_status[13].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[13].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_13_qs) + ); + + + // F[en_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_14_we), + .wd (dio_pad_sleep_status_en_14_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[14].de), + .d (hw2reg.dio_pad_sleep_status[14].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[14].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_14_qs) + ); + + + // F[en_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_15_we), + .wd (dio_pad_sleep_status_en_15_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[15].de), + .d (hw2reg.dio_pad_sleep_status[15].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[15].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_15_qs) + ); + + + + + // Subregister 0 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_0]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_0_we), + .wd (dio_pad_sleep_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_0_qs) + ); + + // Subregister 1 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_1]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_1_we), + .wd (dio_pad_sleep_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_1_qs) + ); + + // Subregister 2 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_2]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_2_we), + .wd (dio_pad_sleep_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_2_qs) + ); + + // Subregister 3 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_3]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_3_we), + .wd (dio_pad_sleep_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_3_qs) + ); + + // Subregister 4 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_4]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_4_we), + .wd (dio_pad_sleep_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_4_qs) + ); + + // Subregister 5 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_5]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_5_we), + .wd (dio_pad_sleep_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_5_qs) + ); + + // Subregister 6 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_6]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_6_we), + .wd (dio_pad_sleep_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_6_qs) + ); + + // Subregister 7 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_7]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_7_we), + .wd (dio_pad_sleep_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_7_qs) + ); + + // Subregister 8 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_8]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_8_we), + .wd (dio_pad_sleep_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_8_qs) + ); + + // Subregister 9 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_9]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_9_we), + .wd (dio_pad_sleep_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_9_qs) + ); + + // Subregister 10 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_10]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_10_we), + .wd (dio_pad_sleep_regwen_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_10_qs) + ); + + // Subregister 11 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_11]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_11_we), + .wd (dio_pad_sleep_regwen_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_11_qs) + ); + + // Subregister 12 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_12]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_12_we), + .wd (dio_pad_sleep_regwen_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_12_qs) + ); + + // Subregister 13 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_13]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_13_we), + .wd (dio_pad_sleep_regwen_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_13_qs) + ); + + // Subregister 14 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_14]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_14_we), + .wd (dio_pad_sleep_regwen_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_14_qs) + ); + + // Subregister 15 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_15]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_15_we), + .wd (dio_pad_sleep_regwen_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_15_qs) + ); + + + + // Subregister 0 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_0]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_0_we & dio_pad_sleep_regwen_0_qs), + .wd (dio_pad_sleep_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[0].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_0_qs) + ); + + // Subregister 1 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_1]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_1_we & dio_pad_sleep_regwen_1_qs), + .wd (dio_pad_sleep_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[1].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_1_qs) + ); + + // Subregister 2 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_2]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_2_we & dio_pad_sleep_regwen_2_qs), + .wd (dio_pad_sleep_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[2].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_2_qs) + ); + + // Subregister 3 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_3]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_3_we & dio_pad_sleep_regwen_3_qs), + .wd (dio_pad_sleep_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[3].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_3_qs) + ); + + // Subregister 4 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_4]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_4_we & dio_pad_sleep_regwen_4_qs), + .wd (dio_pad_sleep_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[4].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_4_qs) + ); + + // Subregister 5 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_5]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_5_we & dio_pad_sleep_regwen_5_qs), + .wd (dio_pad_sleep_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[5].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_5_qs) + ); + + // Subregister 6 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_6]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_6_we & dio_pad_sleep_regwen_6_qs), + .wd (dio_pad_sleep_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[6].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_6_qs) + ); + + // Subregister 7 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_7]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_7_we & dio_pad_sleep_regwen_7_qs), + .wd (dio_pad_sleep_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[7].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_7_qs) + ); + + // Subregister 8 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_8]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_8_we & dio_pad_sleep_regwen_8_qs), + .wd (dio_pad_sleep_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[8].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_8_qs) + ); + + // Subregister 9 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_9]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_9_we & dio_pad_sleep_regwen_9_qs), + .wd (dio_pad_sleep_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[9].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_9_qs) + ); + + // Subregister 10 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_10]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_10_we & dio_pad_sleep_regwen_10_qs), + .wd (dio_pad_sleep_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[10].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_10_qs) + ); + + // Subregister 11 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_11]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_11_we & dio_pad_sleep_regwen_11_qs), + .wd (dio_pad_sleep_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[11].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_11_qs) + ); + + // Subregister 12 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_12]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_12_we & dio_pad_sleep_regwen_12_qs), + .wd (dio_pad_sleep_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[12].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_12_qs) + ); + + // Subregister 13 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_13]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_13_we & dio_pad_sleep_regwen_13_qs), + .wd (dio_pad_sleep_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[13].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_13_qs) + ); + + // Subregister 14 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_14]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_14_we & dio_pad_sleep_regwen_14_qs), + .wd (dio_pad_sleep_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[14].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_14_qs) + ); + + // Subregister 15 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_15]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_15_we & dio_pad_sleep_regwen_15_qs), + .wd (dio_pad_sleep_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[15].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_15_qs) + ); + + + + // Subregister 0 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_0]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_0_we & dio_pad_sleep_regwen_0_qs), + .wd (dio_pad_sleep_mode_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[0].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_0_qs) + ); + + // Subregister 1 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_1]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_1_we & dio_pad_sleep_regwen_1_qs), + .wd (dio_pad_sleep_mode_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[1].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_1_qs) + ); + + // Subregister 2 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_2]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_2_we & dio_pad_sleep_regwen_2_qs), + .wd (dio_pad_sleep_mode_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[2].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_2_qs) + ); + + // Subregister 3 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_3]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_3_we & dio_pad_sleep_regwen_3_qs), + .wd (dio_pad_sleep_mode_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[3].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_3_qs) + ); + + // Subregister 4 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_4]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_4_we & dio_pad_sleep_regwen_4_qs), + .wd (dio_pad_sleep_mode_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[4].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_4_qs) + ); + + // Subregister 5 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_5]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_5_we & dio_pad_sleep_regwen_5_qs), + .wd (dio_pad_sleep_mode_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[5].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_5_qs) + ); + + // Subregister 6 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_6]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_6_we & dio_pad_sleep_regwen_6_qs), + .wd (dio_pad_sleep_mode_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[6].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_6_qs) + ); + + // Subregister 7 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_7]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_7_we & dio_pad_sleep_regwen_7_qs), + .wd (dio_pad_sleep_mode_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[7].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_7_qs) + ); + + // Subregister 8 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_8]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_8_we & dio_pad_sleep_regwen_8_qs), + .wd (dio_pad_sleep_mode_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[8].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_8_qs) + ); + + // Subregister 9 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_9]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_9_we & dio_pad_sleep_regwen_9_qs), + .wd (dio_pad_sleep_mode_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[9].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_9_qs) + ); + + // Subregister 10 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_10]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_10_we & dio_pad_sleep_regwen_10_qs), + .wd (dio_pad_sleep_mode_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[10].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_10_qs) + ); + + // Subregister 11 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_11]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_11_we & dio_pad_sleep_regwen_11_qs), + .wd (dio_pad_sleep_mode_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[11].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_11_qs) + ); + + // Subregister 12 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_12]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_12_we & dio_pad_sleep_regwen_12_qs), + .wd (dio_pad_sleep_mode_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[12].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_12_qs) + ); + + // Subregister 13 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_13]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_13_we & dio_pad_sleep_regwen_13_qs), + .wd (dio_pad_sleep_mode_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[13].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_13_qs) + ); + + // Subregister 14 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_14]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_14_we & dio_pad_sleep_regwen_14_qs), + .wd (dio_pad_sleep_mode_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[14].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_14_qs) + ); + + // Subregister 15 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_15]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_15_we & dio_pad_sleep_regwen_15_qs), + .wd (dio_pad_sleep_mode_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[15].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_15_qs) ); @@ -8574,7 +14020,7 @@ - logic [266:0] addr_hit; + logic [412:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET); @@ -8707,143 +14153,289 @@ addr_hit[127] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET); addr_hit[128] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET); addr_hit[129] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET); - addr_hit[130] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_0_OFFSET); - addr_hit[131] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_1_OFFSET); - addr_hit[132] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_2_OFFSET); - addr_hit[133] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_3_OFFSET); - addr_hit[134] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_4_OFFSET); - addr_hit[135] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_5_OFFSET); - addr_hit[136] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_6_OFFSET); - addr_hit[137] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_7_OFFSET); - addr_hit[138] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_8_OFFSET); - addr_hit[139] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_9_OFFSET); - addr_hit[140] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_10_OFFSET); - addr_hit[141] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_11_OFFSET); - addr_hit[142] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_12_OFFSET); - addr_hit[143] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_13_OFFSET); - addr_hit[144] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_14_OFFSET); - addr_hit[145] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_15_OFFSET); - addr_hit[146] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_16_OFFSET); - addr_hit[147] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_17_OFFSET); - addr_hit[148] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_18_OFFSET); - addr_hit[149] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_19_OFFSET); - addr_hit[150] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_20_OFFSET); - addr_hit[151] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_21_OFFSET); - addr_hit[152] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_22_OFFSET); - addr_hit[153] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_23_OFFSET); - addr_hit[154] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_24_OFFSET); - addr_hit[155] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_25_OFFSET); - addr_hit[156] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_26_OFFSET); - addr_hit[157] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_27_OFFSET); - addr_hit[158] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_28_OFFSET); - addr_hit[159] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_29_OFFSET); - addr_hit[160] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_30_OFFSET); - addr_hit[161] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_31_OFFSET); - addr_hit[162] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_0_OFFSET); - addr_hit[163] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_1_OFFSET); - addr_hit[164] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_2_OFFSET); - addr_hit[165] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_3_OFFSET); - addr_hit[166] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_4_OFFSET); - addr_hit[167] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_5_OFFSET); - addr_hit[168] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_6_OFFSET); - addr_hit[169] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_7_OFFSET); - addr_hit[170] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_8_OFFSET); - addr_hit[171] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_9_OFFSET); - addr_hit[172] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_10_OFFSET); - addr_hit[173] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_11_OFFSET); - addr_hit[174] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_12_OFFSET); - addr_hit[175] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_13_OFFSET); - addr_hit[176] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_14_OFFSET); - addr_hit[177] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_15_OFFSET); - addr_hit[178] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_16_OFFSET); - addr_hit[179] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_17_OFFSET); - addr_hit[180] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_18_OFFSET); - addr_hit[181] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_19_OFFSET); - addr_hit[182] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_20_OFFSET); - addr_hit[183] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_21_OFFSET); - addr_hit[184] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_22_OFFSET); - addr_hit[185] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_23_OFFSET); - addr_hit[186] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_24_OFFSET); - addr_hit[187] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_25_OFFSET); - addr_hit[188] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_26_OFFSET); - addr_hit[189] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_27_OFFSET); - addr_hit[190] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_28_OFFSET); - addr_hit[191] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_29_OFFSET); - addr_hit[192] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_30_OFFSET); - addr_hit[193] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_31_OFFSET); - addr_hit[194] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_0_OFFSET); - addr_hit[195] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_1_OFFSET); - addr_hit[196] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_2_OFFSET); - addr_hit[197] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_3_OFFSET); - addr_hit[198] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_4_OFFSET); - addr_hit[199] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_5_OFFSET); - addr_hit[200] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_6_OFFSET); - addr_hit[201] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_7_OFFSET); - addr_hit[202] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_8_OFFSET); - addr_hit[203] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_9_OFFSET); - addr_hit[204] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_10_OFFSET); - addr_hit[205] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_11_OFFSET); - addr_hit[206] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_12_OFFSET); - addr_hit[207] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_13_OFFSET); - addr_hit[208] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_14_OFFSET); - addr_hit[209] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_15_OFFSET); - addr_hit[210] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_0_OFFSET); - addr_hit[211] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_1_OFFSET); - addr_hit[212] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_2_OFFSET); - addr_hit[213] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_3_OFFSET); - addr_hit[214] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_4_OFFSET); - addr_hit[215] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_5_OFFSET); - addr_hit[216] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_6_OFFSET); - addr_hit[217] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_7_OFFSET); - addr_hit[218] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_8_OFFSET); - addr_hit[219] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_9_OFFSET); - addr_hit[220] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_10_OFFSET); - addr_hit[221] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_11_OFFSET); - addr_hit[222] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_12_OFFSET); - addr_hit[223] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_13_OFFSET); - addr_hit[224] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_14_OFFSET); - addr_hit[225] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_15_OFFSET); - addr_hit[226] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET); - addr_hit[227] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET); - addr_hit[228] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET); - addr_hit[229] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET); - addr_hit[230] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET); - addr_hit[231] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET); - addr_hit[232] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET); - addr_hit[233] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET); - addr_hit[234] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET); - addr_hit[235] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET); - addr_hit[236] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET); - addr_hit[237] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET); - addr_hit[238] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET); - addr_hit[239] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET); - addr_hit[240] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET); - addr_hit[241] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET); - addr_hit[242] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET); - addr_hit[243] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET); - addr_hit[244] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET); - addr_hit[245] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET); - addr_hit[246] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET); - addr_hit[247] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET); - addr_hit[248] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET); - addr_hit[249] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET); - addr_hit[250] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET); - addr_hit[251] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET); - addr_hit[252] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET); - addr_hit[253] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET); - addr_hit[254] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET); - addr_hit[255] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET); - addr_hit[256] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET); - addr_hit[257] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET); - addr_hit[258] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET); - addr_hit[259] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET); - addr_hit[260] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET); - addr_hit[261] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET); - addr_hit[262] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET); - addr_hit[263] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET); - addr_hit[264] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET); - addr_hit[265] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET); - addr_hit[266] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET); + addr_hit[130] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET); + addr_hit[131] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET); + addr_hit[132] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET); + addr_hit[133] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET); + addr_hit[134] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET); + addr_hit[135] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET); + addr_hit[136] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET); + addr_hit[137] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET); + addr_hit[138] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET); + addr_hit[139] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET); + addr_hit[140] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET); + addr_hit[141] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET); + addr_hit[142] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET); + addr_hit[143] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET); + addr_hit[144] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET); + addr_hit[145] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET); + addr_hit[146] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET); + addr_hit[147] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET); + addr_hit[148] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET); + addr_hit[149] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET); + addr_hit[150] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET); + addr_hit[151] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET); + addr_hit[152] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET); + addr_hit[153] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET); + addr_hit[154] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET); + addr_hit[155] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET); + addr_hit[156] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET); + addr_hit[157] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET); + addr_hit[158] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET); + addr_hit[159] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET); + addr_hit[160] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET); + addr_hit[161] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET); + addr_hit[162] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET); + addr_hit[163] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET); + addr_hit[164] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET); + addr_hit[165] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET); + addr_hit[166] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET); + addr_hit[167] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET); + addr_hit[168] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET); + addr_hit[169] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET); + addr_hit[170] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET); + addr_hit[171] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET); + addr_hit[172] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET); + addr_hit[173] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET); + addr_hit[174] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET); + addr_hit[175] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET); + addr_hit[176] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET); + addr_hit[177] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET); + addr_hit[178] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET); + addr_hit[179] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET); + addr_hit[180] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET); + addr_hit[181] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET); + addr_hit[182] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET); + addr_hit[183] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET); + addr_hit[184] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET); + addr_hit[185] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET); + addr_hit[186] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET); + addr_hit[187] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET); + addr_hit[188] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET); + addr_hit[189] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET); + addr_hit[190] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET); + addr_hit[191] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET); + addr_hit[192] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET); + addr_hit[193] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET); + addr_hit[194] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET); + addr_hit[195] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET); + addr_hit[196] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET); + addr_hit[197] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET); + addr_hit[198] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET); + addr_hit[199] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET); + addr_hit[200] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET); + addr_hit[201] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET); + addr_hit[202] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET); + addr_hit[203] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET); + addr_hit[204] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET); + addr_hit[205] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET); + addr_hit[206] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET); + addr_hit[207] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET); + addr_hit[208] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET); + addr_hit[209] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET); + addr_hit[210] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET); + addr_hit[211] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET); + addr_hit[212] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET); + addr_hit[213] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET); + addr_hit[214] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET); + addr_hit[215] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET); + addr_hit[216] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET); + addr_hit[217] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET); + addr_hit[218] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET); + addr_hit[219] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET); + addr_hit[220] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET); + addr_hit[221] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET); + addr_hit[222] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET); + addr_hit[223] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET); + addr_hit[224] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET); + addr_hit[225] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET); + addr_hit[226] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_OFFSET); + addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET); + addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET); + addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET); + addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET); + addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET); + addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET); + addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET); + addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET); + addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET); + addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET); + addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET); + addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET); + addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET); + addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET); + addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET); + addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET); + addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET); + addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET); + addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET); + addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET); + addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET); + addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET); + addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET); + addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET); + addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET); + addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET); + addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET); + addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET); + addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET); + addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET); + addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET); + addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET); + addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET); + addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET); + addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET); + addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET); + addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET); + addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET); + addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET); + addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET); + addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET); + addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET); + addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET); + addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET); + addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET); + addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET); + addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET); + addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET); + addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET); + addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET); + addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET); + addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET); + addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET); + addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET); + addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET); + addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET); + addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET); + addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET); + addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET); + addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET); + addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET); + addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET); + addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET); + addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET); + addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET); + addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET); + addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET); + addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET); + addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET); + addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET); + addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET); + addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET); + addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET); + addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET); + addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET); + addr_hit[302] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET); + addr_hit[303] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET); + addr_hit[304] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET); + addr_hit[305] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET); + addr_hit[306] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET); + addr_hit[307] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET); + addr_hit[308] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET); + addr_hit[309] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET); + addr_hit[310] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET); + addr_hit[311] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET); + addr_hit[312] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET); + addr_hit[313] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET); + addr_hit[314] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET); + addr_hit[315] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET); + addr_hit[316] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET); + addr_hit[317] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET); + addr_hit[318] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET); + addr_hit[319] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET); + addr_hit[320] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET); + addr_hit[321] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET); + addr_hit[322] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET); + addr_hit[323] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET); + addr_hit[324] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET); + addr_hit[325] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET); + addr_hit[326] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET); + addr_hit[327] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET); + addr_hit[328] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET); + addr_hit[329] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET); + addr_hit[330] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET); + addr_hit[331] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET); + addr_hit[332] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET); + addr_hit[333] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET); + addr_hit[334] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET); + addr_hit[335] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET); + addr_hit[336] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET); + addr_hit[337] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET); + addr_hit[338] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET); + addr_hit[339] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET); + addr_hit[340] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET); + addr_hit[341] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET); + addr_hit[342] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET); + addr_hit[343] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET); + addr_hit[344] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET); + addr_hit[345] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET); + addr_hit[346] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET); + addr_hit[347] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET); + addr_hit[348] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET); + addr_hit[349] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET); + addr_hit[350] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET); + addr_hit[351] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET); + addr_hit[352] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET); + addr_hit[353] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET); + addr_hit[354] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET); + addr_hit[355] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET); + addr_hit[356] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET); + addr_hit[357] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET); + addr_hit[358] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET); + addr_hit[359] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET); + addr_hit[360] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET); + addr_hit[361] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET); + addr_hit[362] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET); + addr_hit[363] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET); + addr_hit[364] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET); + addr_hit[365] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET); + addr_hit[366] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET); + addr_hit[367] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET); + addr_hit[368] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET); + addr_hit[369] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET); + addr_hit[370] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET); + addr_hit[371] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET); + addr_hit[372] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET); + addr_hit[373] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET); + addr_hit[374] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET); + addr_hit[375] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET); + addr_hit[376] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET); + addr_hit[377] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET); + addr_hit[378] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET); + addr_hit[379] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET); + addr_hit[380] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET); + addr_hit[381] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET); + addr_hit[382] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET); + addr_hit[383] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET); + addr_hit[384] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET); + addr_hit[385] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET); + addr_hit[386] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET); + addr_hit[387] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET); + addr_hit[388] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET); + addr_hit[389] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET); + addr_hit[390] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET); + addr_hit[391] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET); + addr_hit[392] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET); + addr_hit[393] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET); + addr_hit[394] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET); + addr_hit[395] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET); + addr_hit[396] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET); + addr_hit[397] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET); + addr_hit[398] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET); + addr_hit[399] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET); + addr_hit[400] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET); + addr_hit[401] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET); + addr_hit[402] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET); + addr_hit[403] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET); + addr_hit[404] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET); + addr_hit[405] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET); + addr_hit[406] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET); + addr_hit[407] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET); + addr_hit[408] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET); + addr_hit[409] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET); + addr_hit[410] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET); + addr_hit[411] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET); + addr_hit[412] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -9118,6 +14710,152 @@ if (addr_hit[264] && reg_we && (PINMUX_PERMIT[264] != (PINMUX_PERMIT[264] & reg_be))) wr_err = 1'b1 ; if (addr_hit[265] && reg_we && (PINMUX_PERMIT[265] != (PINMUX_PERMIT[265] & reg_be))) wr_err = 1'b1 ; if (addr_hit[266] && reg_we && (PINMUX_PERMIT[266] != (PINMUX_PERMIT[266] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[267] && reg_we && (PINMUX_PERMIT[267] != (PINMUX_PERMIT[267] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[268] && reg_we && (PINMUX_PERMIT[268] != (PINMUX_PERMIT[268] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[269] && reg_we && (PINMUX_PERMIT[269] != (PINMUX_PERMIT[269] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[270] && reg_we && (PINMUX_PERMIT[270] != (PINMUX_PERMIT[270] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[271] && reg_we && (PINMUX_PERMIT[271] != (PINMUX_PERMIT[271] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[272] && reg_we && (PINMUX_PERMIT[272] != (PINMUX_PERMIT[272] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[273] && reg_we && (PINMUX_PERMIT[273] != (PINMUX_PERMIT[273] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[274] && reg_we && (PINMUX_PERMIT[274] != (PINMUX_PERMIT[274] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[275] && reg_we && (PINMUX_PERMIT[275] != (PINMUX_PERMIT[275] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[276] && reg_we && (PINMUX_PERMIT[276] != (PINMUX_PERMIT[276] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[277] && reg_we && (PINMUX_PERMIT[277] != (PINMUX_PERMIT[277] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[278] && reg_we && (PINMUX_PERMIT[278] != (PINMUX_PERMIT[278] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[279] && reg_we && (PINMUX_PERMIT[279] != (PINMUX_PERMIT[279] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[280] && reg_we && (PINMUX_PERMIT[280] != (PINMUX_PERMIT[280] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[281] && reg_we && (PINMUX_PERMIT[281] != (PINMUX_PERMIT[281] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[282] && reg_we && (PINMUX_PERMIT[282] != (PINMUX_PERMIT[282] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[283] && reg_we && (PINMUX_PERMIT[283] != (PINMUX_PERMIT[283] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[284] && reg_we && (PINMUX_PERMIT[284] != (PINMUX_PERMIT[284] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[285] && reg_we && (PINMUX_PERMIT[285] != (PINMUX_PERMIT[285] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[286] && reg_we && (PINMUX_PERMIT[286] != (PINMUX_PERMIT[286] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[287] && reg_we && (PINMUX_PERMIT[287] != (PINMUX_PERMIT[287] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[288] && reg_we && (PINMUX_PERMIT[288] != (PINMUX_PERMIT[288] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[289] && reg_we && (PINMUX_PERMIT[289] != (PINMUX_PERMIT[289] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[290] && reg_we && (PINMUX_PERMIT[290] != (PINMUX_PERMIT[290] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[291] && reg_we && (PINMUX_PERMIT[291] != (PINMUX_PERMIT[291] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[292] && reg_we && (PINMUX_PERMIT[292] != (PINMUX_PERMIT[292] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[293] && reg_we && (PINMUX_PERMIT[293] != (PINMUX_PERMIT[293] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[294] && reg_we && (PINMUX_PERMIT[294] != (PINMUX_PERMIT[294] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[295] && reg_we && (PINMUX_PERMIT[295] != (PINMUX_PERMIT[295] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[296] && reg_we && (PINMUX_PERMIT[296] != (PINMUX_PERMIT[296] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[297] && reg_we && (PINMUX_PERMIT[297] != (PINMUX_PERMIT[297] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[298] && reg_we && (PINMUX_PERMIT[298] != (PINMUX_PERMIT[298] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[299] && reg_we && (PINMUX_PERMIT[299] != (PINMUX_PERMIT[299] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[300] && reg_we && (PINMUX_PERMIT[300] != (PINMUX_PERMIT[300] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[301] && reg_we && (PINMUX_PERMIT[301] != (PINMUX_PERMIT[301] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[302] && reg_we && (PINMUX_PERMIT[302] != (PINMUX_PERMIT[302] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[303] && reg_we && (PINMUX_PERMIT[303] != (PINMUX_PERMIT[303] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[304] && reg_we && (PINMUX_PERMIT[304] != (PINMUX_PERMIT[304] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[305] && reg_we && (PINMUX_PERMIT[305] != (PINMUX_PERMIT[305] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[306] && reg_we && (PINMUX_PERMIT[306] != (PINMUX_PERMIT[306] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[307] && reg_we && (PINMUX_PERMIT[307] != (PINMUX_PERMIT[307] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[308] && reg_we && (PINMUX_PERMIT[308] != (PINMUX_PERMIT[308] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[309] && reg_we && (PINMUX_PERMIT[309] != (PINMUX_PERMIT[309] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[310] && reg_we && (PINMUX_PERMIT[310] != (PINMUX_PERMIT[310] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[311] && reg_we && (PINMUX_PERMIT[311] != (PINMUX_PERMIT[311] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[312] && reg_we && (PINMUX_PERMIT[312] != (PINMUX_PERMIT[312] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[313] && reg_we && (PINMUX_PERMIT[313] != (PINMUX_PERMIT[313] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[314] && reg_we && (PINMUX_PERMIT[314] != (PINMUX_PERMIT[314] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[315] && reg_we && (PINMUX_PERMIT[315] != (PINMUX_PERMIT[315] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[316] && reg_we && (PINMUX_PERMIT[316] != (PINMUX_PERMIT[316] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[317] && reg_we && (PINMUX_PERMIT[317] != (PINMUX_PERMIT[317] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[318] && reg_we && (PINMUX_PERMIT[318] != (PINMUX_PERMIT[318] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[319] && reg_we && (PINMUX_PERMIT[319] != (PINMUX_PERMIT[319] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[320] && reg_we && (PINMUX_PERMIT[320] != (PINMUX_PERMIT[320] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[321] && reg_we && (PINMUX_PERMIT[321] != (PINMUX_PERMIT[321] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[322] && reg_we && (PINMUX_PERMIT[322] != (PINMUX_PERMIT[322] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[323] && reg_we && (PINMUX_PERMIT[323] != (PINMUX_PERMIT[323] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[324] && reg_we && (PINMUX_PERMIT[324] != (PINMUX_PERMIT[324] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[325] && reg_we && (PINMUX_PERMIT[325] != (PINMUX_PERMIT[325] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[326] && reg_we && (PINMUX_PERMIT[326] != (PINMUX_PERMIT[326] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[327] && reg_we && (PINMUX_PERMIT[327] != (PINMUX_PERMIT[327] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[328] && reg_we && (PINMUX_PERMIT[328] != (PINMUX_PERMIT[328] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[329] && reg_we && (PINMUX_PERMIT[329] != (PINMUX_PERMIT[329] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[330] && reg_we && (PINMUX_PERMIT[330] != (PINMUX_PERMIT[330] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[331] && reg_we && (PINMUX_PERMIT[331] != (PINMUX_PERMIT[331] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[332] && reg_we && (PINMUX_PERMIT[332] != (PINMUX_PERMIT[332] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[333] && reg_we && (PINMUX_PERMIT[333] != (PINMUX_PERMIT[333] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[334] && reg_we && (PINMUX_PERMIT[334] != (PINMUX_PERMIT[334] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[335] && reg_we && (PINMUX_PERMIT[335] != (PINMUX_PERMIT[335] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[336] && reg_we && (PINMUX_PERMIT[336] != (PINMUX_PERMIT[336] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[337] && reg_we && (PINMUX_PERMIT[337] != (PINMUX_PERMIT[337] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[338] && reg_we && (PINMUX_PERMIT[338] != (PINMUX_PERMIT[338] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[339] && reg_we && (PINMUX_PERMIT[339] != (PINMUX_PERMIT[339] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[340] && reg_we && (PINMUX_PERMIT[340] != (PINMUX_PERMIT[340] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[341] && reg_we && (PINMUX_PERMIT[341] != (PINMUX_PERMIT[341] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[342] && reg_we && (PINMUX_PERMIT[342] != (PINMUX_PERMIT[342] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[343] && reg_we && (PINMUX_PERMIT[343] != (PINMUX_PERMIT[343] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[344] && reg_we && (PINMUX_PERMIT[344] != (PINMUX_PERMIT[344] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[345] && reg_we && (PINMUX_PERMIT[345] != (PINMUX_PERMIT[345] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[346] && reg_we && (PINMUX_PERMIT[346] != (PINMUX_PERMIT[346] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[347] && reg_we && (PINMUX_PERMIT[347] != (PINMUX_PERMIT[347] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[348] && reg_we && (PINMUX_PERMIT[348] != (PINMUX_PERMIT[348] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[349] && reg_we && (PINMUX_PERMIT[349] != (PINMUX_PERMIT[349] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[350] && reg_we && (PINMUX_PERMIT[350] != (PINMUX_PERMIT[350] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[351] && reg_we && (PINMUX_PERMIT[351] != (PINMUX_PERMIT[351] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[352] && reg_we && (PINMUX_PERMIT[352] != (PINMUX_PERMIT[352] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[353] && reg_we && (PINMUX_PERMIT[353] != (PINMUX_PERMIT[353] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[354] && reg_we && (PINMUX_PERMIT[354] != (PINMUX_PERMIT[354] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[355] && reg_we && (PINMUX_PERMIT[355] != (PINMUX_PERMIT[355] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[356] && reg_we && (PINMUX_PERMIT[356] != (PINMUX_PERMIT[356] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[357] && reg_we && (PINMUX_PERMIT[357] != (PINMUX_PERMIT[357] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[358] && reg_we && (PINMUX_PERMIT[358] != (PINMUX_PERMIT[358] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[359] && reg_we && (PINMUX_PERMIT[359] != (PINMUX_PERMIT[359] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[360] && reg_we && (PINMUX_PERMIT[360] != (PINMUX_PERMIT[360] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[361] && reg_we && (PINMUX_PERMIT[361] != (PINMUX_PERMIT[361] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[362] && reg_we && (PINMUX_PERMIT[362] != (PINMUX_PERMIT[362] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[363] && reg_we && (PINMUX_PERMIT[363] != (PINMUX_PERMIT[363] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[364] && reg_we && (PINMUX_PERMIT[364] != (PINMUX_PERMIT[364] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[365] && reg_we && (PINMUX_PERMIT[365] != (PINMUX_PERMIT[365] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[366] && reg_we && (PINMUX_PERMIT[366] != (PINMUX_PERMIT[366] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[367] && reg_we && (PINMUX_PERMIT[367] != (PINMUX_PERMIT[367] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[368] && reg_we && (PINMUX_PERMIT[368] != (PINMUX_PERMIT[368] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[369] && reg_we && (PINMUX_PERMIT[369] != (PINMUX_PERMIT[369] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[370] && reg_we && (PINMUX_PERMIT[370] != (PINMUX_PERMIT[370] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[371] && reg_we && (PINMUX_PERMIT[371] != (PINMUX_PERMIT[371] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[372] && reg_we && (PINMUX_PERMIT[372] != (PINMUX_PERMIT[372] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[373] && reg_we && (PINMUX_PERMIT[373] != (PINMUX_PERMIT[373] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[374] && reg_we && (PINMUX_PERMIT[374] != (PINMUX_PERMIT[374] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[375] && reg_we && (PINMUX_PERMIT[375] != (PINMUX_PERMIT[375] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[376] && reg_we && (PINMUX_PERMIT[376] != (PINMUX_PERMIT[376] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[377] && reg_we && (PINMUX_PERMIT[377] != (PINMUX_PERMIT[377] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[378] && reg_we && (PINMUX_PERMIT[378] != (PINMUX_PERMIT[378] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[379] && reg_we && (PINMUX_PERMIT[379] != (PINMUX_PERMIT[379] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[380] && reg_we && (PINMUX_PERMIT[380] != (PINMUX_PERMIT[380] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[381] && reg_we && (PINMUX_PERMIT[381] != (PINMUX_PERMIT[381] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[382] && reg_we && (PINMUX_PERMIT[382] != (PINMUX_PERMIT[382] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[383] && reg_we && (PINMUX_PERMIT[383] != (PINMUX_PERMIT[383] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[384] && reg_we && (PINMUX_PERMIT[384] != (PINMUX_PERMIT[384] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[385] && reg_we && (PINMUX_PERMIT[385] != (PINMUX_PERMIT[385] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[386] && reg_we && (PINMUX_PERMIT[386] != (PINMUX_PERMIT[386] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[387] && reg_we && (PINMUX_PERMIT[387] != (PINMUX_PERMIT[387] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[388] && reg_we && (PINMUX_PERMIT[388] != (PINMUX_PERMIT[388] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[389] && reg_we && (PINMUX_PERMIT[389] != (PINMUX_PERMIT[389] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[390] && reg_we && (PINMUX_PERMIT[390] != (PINMUX_PERMIT[390] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[391] && reg_we && (PINMUX_PERMIT[391] != (PINMUX_PERMIT[391] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[392] && reg_we && (PINMUX_PERMIT[392] != (PINMUX_PERMIT[392] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[393] && reg_we && (PINMUX_PERMIT[393] != (PINMUX_PERMIT[393] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[394] && reg_we && (PINMUX_PERMIT[394] != (PINMUX_PERMIT[394] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[395] && reg_we && (PINMUX_PERMIT[395] != (PINMUX_PERMIT[395] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[396] && reg_we && (PINMUX_PERMIT[396] != (PINMUX_PERMIT[396] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[397] && reg_we && (PINMUX_PERMIT[397] != (PINMUX_PERMIT[397] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[398] && reg_we && (PINMUX_PERMIT[398] != (PINMUX_PERMIT[398] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[399] && reg_we && (PINMUX_PERMIT[399] != (PINMUX_PERMIT[399] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[400] && reg_we && (PINMUX_PERMIT[400] != (PINMUX_PERMIT[400] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[401] && reg_we && (PINMUX_PERMIT[401] != (PINMUX_PERMIT[401] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[402] && reg_we && (PINMUX_PERMIT[402] != (PINMUX_PERMIT[402] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[403] && reg_we && (PINMUX_PERMIT[403] != (PINMUX_PERMIT[403] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[404] && reg_we && (PINMUX_PERMIT[404] != (PINMUX_PERMIT[404] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[405] && reg_we && (PINMUX_PERMIT[405] != (PINMUX_PERMIT[405] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[406] && reg_we && (PINMUX_PERMIT[406] != (PINMUX_PERMIT[406] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[407] && reg_we && (PINMUX_PERMIT[407] != (PINMUX_PERMIT[407] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[408] && reg_we && (PINMUX_PERMIT[408] != (PINMUX_PERMIT[408] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[409] && reg_we && (PINMUX_PERMIT[409] != (PINMUX_PERMIT[409] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[410] && reg_we && (PINMUX_PERMIT[410] != (PINMUX_PERMIT[410] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[411] && reg_we && (PINMUX_PERMIT[411] != (PINMUX_PERMIT[411] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[412] && reg_we && (PINMUX_PERMIT[412] != (PINMUX_PERMIT[412] & reg_be))) wr_err = 1'b1 ; end assign mio_periph_insel_regwen_0_we = addr_hit[0] & reg_we & ~wr_err; @@ -9510,509 +15248,1117 @@ assign mio_outsel_31_we = addr_hit[129] & reg_we & ~wr_err; assign mio_outsel_31_wd = reg_wdata[5:0]; - assign mio_out_sleep_regwen_0_we = addr_hit[130] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_0_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_0_we = addr_hit[130] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_0_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_1_we = addr_hit[131] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_1_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_2_we = addr_hit[132] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_2_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_3_we = addr_hit[133] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_3_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_4_we = addr_hit[134] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_4_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_5_we = addr_hit[135] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_5_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_6_we = addr_hit[136] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_6_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_7_we = addr_hit[137] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_7_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_8_we = addr_hit[138] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_8_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_9_we = addr_hit[139] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_9_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_10_we = addr_hit[140] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_10_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_11_we = addr_hit[141] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_11_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_12_we = addr_hit[142] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_12_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_13_we = addr_hit[143] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_13_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_14_we = addr_hit[144] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_14_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_15_we = addr_hit[145] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_15_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_16_we = addr_hit[146] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_16_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_17_we = addr_hit[147] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_17_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_18_we = addr_hit[148] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_18_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_19_we = addr_hit[149] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_19_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_20_we = addr_hit[150] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_20_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_21_we = addr_hit[151] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_21_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_22_we = addr_hit[152] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_22_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_23_we = addr_hit[153] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_23_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_24_we = addr_hit[154] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_24_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_25_we = addr_hit[155] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_25_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_26_we = addr_hit[156] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_26_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_27_we = addr_hit[157] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_27_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_28_we = addr_hit[158] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_28_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_29_we = addr_hit[159] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_29_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_30_we = addr_hit[160] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_30_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_31_we = addr_hit[161] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_31_wd = reg_wdata[0]; + + assign mio_pad_attr_0_we = addr_hit[162] & reg_we & ~wr_err; + assign mio_pad_attr_0_wd = reg_wdata[9:0]; + assign mio_pad_attr_0_re = addr_hit[162] && reg_re; + + assign mio_pad_attr_1_we = addr_hit[163] & reg_we & ~wr_err; + assign mio_pad_attr_1_wd = reg_wdata[9:0]; + assign mio_pad_attr_1_re = addr_hit[163] && reg_re; + + assign mio_pad_attr_2_we = addr_hit[164] & reg_we & ~wr_err; + assign mio_pad_attr_2_wd = reg_wdata[9:0]; + assign mio_pad_attr_2_re = addr_hit[164] && reg_re; + + assign mio_pad_attr_3_we = addr_hit[165] & reg_we & ~wr_err; + assign mio_pad_attr_3_wd = reg_wdata[9:0]; + assign mio_pad_attr_3_re = addr_hit[165] && reg_re; + + assign mio_pad_attr_4_we = addr_hit[166] & reg_we & ~wr_err; + assign mio_pad_attr_4_wd = reg_wdata[9:0]; + assign mio_pad_attr_4_re = addr_hit[166] && reg_re; + + assign mio_pad_attr_5_we = addr_hit[167] & reg_we & ~wr_err; + assign mio_pad_attr_5_wd = reg_wdata[9:0]; + assign mio_pad_attr_5_re = addr_hit[167] && reg_re; + + assign mio_pad_attr_6_we = addr_hit[168] & reg_we & ~wr_err; + assign mio_pad_attr_6_wd = reg_wdata[9:0]; + assign mio_pad_attr_6_re = addr_hit[168] && reg_re; + + assign mio_pad_attr_7_we = addr_hit[169] & reg_we & ~wr_err; + assign mio_pad_attr_7_wd = reg_wdata[9:0]; + assign mio_pad_attr_7_re = addr_hit[169] && reg_re; + + assign mio_pad_attr_8_we = addr_hit[170] & reg_we & ~wr_err; + assign mio_pad_attr_8_wd = reg_wdata[9:0]; + assign mio_pad_attr_8_re = addr_hit[170] && reg_re; + + assign mio_pad_attr_9_we = addr_hit[171] & reg_we & ~wr_err; + assign mio_pad_attr_9_wd = reg_wdata[9:0]; + assign mio_pad_attr_9_re = addr_hit[171] && reg_re; + + assign mio_pad_attr_10_we = addr_hit[172] & reg_we & ~wr_err; + assign mio_pad_attr_10_wd = reg_wdata[9:0]; + assign mio_pad_attr_10_re = addr_hit[172] && reg_re; + + assign mio_pad_attr_11_we = addr_hit[173] & reg_we & ~wr_err; + assign mio_pad_attr_11_wd = reg_wdata[9:0]; + assign mio_pad_attr_11_re = addr_hit[173] && reg_re; + + assign mio_pad_attr_12_we = addr_hit[174] & reg_we & ~wr_err; + assign mio_pad_attr_12_wd = reg_wdata[9:0]; + assign mio_pad_attr_12_re = addr_hit[174] && reg_re; + + assign mio_pad_attr_13_we = addr_hit[175] & reg_we & ~wr_err; + assign mio_pad_attr_13_wd = reg_wdata[9:0]; + assign mio_pad_attr_13_re = addr_hit[175] && reg_re; + + assign mio_pad_attr_14_we = addr_hit[176] & reg_we & ~wr_err; + assign mio_pad_attr_14_wd = reg_wdata[9:0]; + assign mio_pad_attr_14_re = addr_hit[176] && reg_re; + + assign mio_pad_attr_15_we = addr_hit[177] & reg_we & ~wr_err; + assign mio_pad_attr_15_wd = reg_wdata[9:0]; + assign mio_pad_attr_15_re = addr_hit[177] && reg_re; + + assign mio_pad_attr_16_we = addr_hit[178] & reg_we & ~wr_err; + assign mio_pad_attr_16_wd = reg_wdata[9:0]; + assign mio_pad_attr_16_re = addr_hit[178] && reg_re; + + assign mio_pad_attr_17_we = addr_hit[179] & reg_we & ~wr_err; + assign mio_pad_attr_17_wd = reg_wdata[9:0]; + assign mio_pad_attr_17_re = addr_hit[179] && reg_re; + + assign mio_pad_attr_18_we = addr_hit[180] & reg_we & ~wr_err; + assign mio_pad_attr_18_wd = reg_wdata[9:0]; + assign mio_pad_attr_18_re = addr_hit[180] && reg_re; + + assign mio_pad_attr_19_we = addr_hit[181] & reg_we & ~wr_err; + assign mio_pad_attr_19_wd = reg_wdata[9:0]; + assign mio_pad_attr_19_re = addr_hit[181] && reg_re; + + assign mio_pad_attr_20_we = addr_hit[182] & reg_we & ~wr_err; + assign mio_pad_attr_20_wd = reg_wdata[9:0]; + assign mio_pad_attr_20_re = addr_hit[182] && reg_re; + + assign mio_pad_attr_21_we = addr_hit[183] & reg_we & ~wr_err; + assign mio_pad_attr_21_wd = reg_wdata[9:0]; + assign mio_pad_attr_21_re = addr_hit[183] && reg_re; + + assign mio_pad_attr_22_we = addr_hit[184] & reg_we & ~wr_err; + assign mio_pad_attr_22_wd = reg_wdata[9:0]; + assign mio_pad_attr_22_re = addr_hit[184] && reg_re; + + assign mio_pad_attr_23_we = addr_hit[185] & reg_we & ~wr_err; + assign mio_pad_attr_23_wd = reg_wdata[9:0]; + assign mio_pad_attr_23_re = addr_hit[185] && reg_re; + + assign mio_pad_attr_24_we = addr_hit[186] & reg_we & ~wr_err; + assign mio_pad_attr_24_wd = reg_wdata[9:0]; + assign mio_pad_attr_24_re = addr_hit[186] && reg_re; + + assign mio_pad_attr_25_we = addr_hit[187] & reg_we & ~wr_err; + assign mio_pad_attr_25_wd = reg_wdata[9:0]; + assign mio_pad_attr_25_re = addr_hit[187] && reg_re; + + assign mio_pad_attr_26_we = addr_hit[188] & reg_we & ~wr_err; + assign mio_pad_attr_26_wd = reg_wdata[9:0]; + assign mio_pad_attr_26_re = addr_hit[188] && reg_re; + + assign mio_pad_attr_27_we = addr_hit[189] & reg_we & ~wr_err; + assign mio_pad_attr_27_wd = reg_wdata[9:0]; + assign mio_pad_attr_27_re = addr_hit[189] && reg_re; + + assign mio_pad_attr_28_we = addr_hit[190] & reg_we & ~wr_err; + assign mio_pad_attr_28_wd = reg_wdata[9:0]; + assign mio_pad_attr_28_re = addr_hit[190] && reg_re; + + assign mio_pad_attr_29_we = addr_hit[191] & reg_we & ~wr_err; + assign mio_pad_attr_29_wd = reg_wdata[9:0]; + assign mio_pad_attr_29_re = addr_hit[191] && reg_re; + + assign mio_pad_attr_30_we = addr_hit[192] & reg_we & ~wr_err; + assign mio_pad_attr_30_wd = reg_wdata[9:0]; + assign mio_pad_attr_30_re = addr_hit[192] && reg_re; + + assign mio_pad_attr_31_we = addr_hit[193] & reg_we & ~wr_err; + assign mio_pad_attr_31_wd = reg_wdata[9:0]; + assign mio_pad_attr_31_re = addr_hit[193] && reg_re; + + assign dio_pad_attr_regwen_0_we = addr_hit[194] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_0_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_1_we = addr_hit[195] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_1_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_2_we = addr_hit[196] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_2_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_3_we = addr_hit[197] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_3_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_4_we = addr_hit[198] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_4_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_5_we = addr_hit[199] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_5_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_6_we = addr_hit[200] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_6_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_7_we = addr_hit[201] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_7_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_8_we = addr_hit[202] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_8_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_9_we = addr_hit[203] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_9_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_10_we = addr_hit[204] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_10_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_11_we = addr_hit[205] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_11_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_12_we = addr_hit[206] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_12_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_13_we = addr_hit[207] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_13_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_14_we = addr_hit[208] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_14_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_15_we = addr_hit[209] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_15_wd = reg_wdata[0]; + + assign dio_pad_attr_0_we = addr_hit[210] & reg_we & ~wr_err; + assign dio_pad_attr_0_wd = reg_wdata[9:0]; + assign dio_pad_attr_0_re = addr_hit[210] && reg_re; + + assign dio_pad_attr_1_we = addr_hit[211] & reg_we & ~wr_err; + assign dio_pad_attr_1_wd = reg_wdata[9:0]; + assign dio_pad_attr_1_re = addr_hit[211] && reg_re; + + assign dio_pad_attr_2_we = addr_hit[212] & reg_we & ~wr_err; + assign dio_pad_attr_2_wd = reg_wdata[9:0]; + assign dio_pad_attr_2_re = addr_hit[212] && reg_re; + + assign dio_pad_attr_3_we = addr_hit[213] & reg_we & ~wr_err; + assign dio_pad_attr_3_wd = reg_wdata[9:0]; + assign dio_pad_attr_3_re = addr_hit[213] && reg_re; + + assign dio_pad_attr_4_we = addr_hit[214] & reg_we & ~wr_err; + assign dio_pad_attr_4_wd = reg_wdata[9:0]; + assign dio_pad_attr_4_re = addr_hit[214] && reg_re; + + assign dio_pad_attr_5_we = addr_hit[215] & reg_we & ~wr_err; + assign dio_pad_attr_5_wd = reg_wdata[9:0]; + assign dio_pad_attr_5_re = addr_hit[215] && reg_re; + + assign dio_pad_attr_6_we = addr_hit[216] & reg_we & ~wr_err; + assign dio_pad_attr_6_wd = reg_wdata[9:0]; + assign dio_pad_attr_6_re = addr_hit[216] && reg_re; + + assign dio_pad_attr_7_we = addr_hit[217] & reg_we & ~wr_err; + assign dio_pad_attr_7_wd = reg_wdata[9:0]; + assign dio_pad_attr_7_re = addr_hit[217] && reg_re; + + assign dio_pad_attr_8_we = addr_hit[218] & reg_we & ~wr_err; + assign dio_pad_attr_8_wd = reg_wdata[9:0]; + assign dio_pad_attr_8_re = addr_hit[218] && reg_re; + + assign dio_pad_attr_9_we = addr_hit[219] & reg_we & ~wr_err; + assign dio_pad_attr_9_wd = reg_wdata[9:0]; + assign dio_pad_attr_9_re = addr_hit[219] && reg_re; + + assign dio_pad_attr_10_we = addr_hit[220] & reg_we & ~wr_err; + assign dio_pad_attr_10_wd = reg_wdata[9:0]; + assign dio_pad_attr_10_re = addr_hit[220] && reg_re; + + assign dio_pad_attr_11_we = addr_hit[221] & reg_we & ~wr_err; + assign dio_pad_attr_11_wd = reg_wdata[9:0]; + assign dio_pad_attr_11_re = addr_hit[221] && reg_re; + + assign dio_pad_attr_12_we = addr_hit[222] & reg_we & ~wr_err; + assign dio_pad_attr_12_wd = reg_wdata[9:0]; + assign dio_pad_attr_12_re = addr_hit[222] && reg_re; + + assign dio_pad_attr_13_we = addr_hit[223] & reg_we & ~wr_err; + assign dio_pad_attr_13_wd = reg_wdata[9:0]; + assign dio_pad_attr_13_re = addr_hit[223] && reg_re; + + assign dio_pad_attr_14_we = addr_hit[224] & reg_we & ~wr_err; + assign dio_pad_attr_14_wd = reg_wdata[9:0]; + assign dio_pad_attr_14_re = addr_hit[224] && reg_re; + + assign dio_pad_attr_15_we = addr_hit[225] & reg_we & ~wr_err; + assign dio_pad_attr_15_wd = reg_wdata[9:0]; + assign dio_pad_attr_15_re = addr_hit[225] && reg_re; + + assign mio_pad_sleep_status_en_0_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_0_wd = reg_wdata[0]; + + assign mio_pad_sleep_status_en_1_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_1_wd = reg_wdata[1]; + + assign mio_pad_sleep_status_en_2_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_2_wd = reg_wdata[2]; + + assign mio_pad_sleep_status_en_3_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_3_wd = reg_wdata[3]; + + assign mio_pad_sleep_status_en_4_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_4_wd = reg_wdata[4]; + + assign mio_pad_sleep_status_en_5_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_5_wd = reg_wdata[5]; + + assign mio_pad_sleep_status_en_6_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_6_wd = reg_wdata[6]; + + assign mio_pad_sleep_status_en_7_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_7_wd = reg_wdata[7]; + + assign mio_pad_sleep_status_en_8_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_8_wd = reg_wdata[8]; + + assign mio_pad_sleep_status_en_9_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_9_wd = reg_wdata[9]; + + assign mio_pad_sleep_status_en_10_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_10_wd = reg_wdata[10]; + + assign mio_pad_sleep_status_en_11_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_11_wd = reg_wdata[11]; + + assign mio_pad_sleep_status_en_12_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_12_wd = reg_wdata[12]; + + assign mio_pad_sleep_status_en_13_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_13_wd = reg_wdata[13]; + + assign mio_pad_sleep_status_en_14_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_14_wd = reg_wdata[14]; + + assign mio_pad_sleep_status_en_15_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_15_wd = reg_wdata[15]; + + assign mio_pad_sleep_status_en_16_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_16_wd = reg_wdata[16]; + + assign mio_pad_sleep_status_en_17_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_17_wd = reg_wdata[17]; + + assign mio_pad_sleep_status_en_18_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_18_wd = reg_wdata[18]; + + assign mio_pad_sleep_status_en_19_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_19_wd = reg_wdata[19]; + + assign mio_pad_sleep_status_en_20_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_20_wd = reg_wdata[20]; + + assign mio_pad_sleep_status_en_21_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_21_wd = reg_wdata[21]; + + assign mio_pad_sleep_status_en_22_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_22_wd = reg_wdata[22]; + + assign mio_pad_sleep_status_en_23_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_23_wd = reg_wdata[23]; + + assign mio_pad_sleep_status_en_24_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_24_wd = reg_wdata[24]; + + assign mio_pad_sleep_status_en_25_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_25_wd = reg_wdata[25]; + + assign mio_pad_sleep_status_en_26_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_26_wd = reg_wdata[26]; + + assign mio_pad_sleep_status_en_27_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_27_wd = reg_wdata[27]; + + assign mio_pad_sleep_status_en_28_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_28_wd = reg_wdata[28]; + + assign mio_pad_sleep_status_en_29_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_29_wd = reg_wdata[29]; + + assign mio_pad_sleep_status_en_30_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_30_wd = reg_wdata[30]; + + assign mio_pad_sleep_status_en_31_we = addr_hit[226] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_31_wd = reg_wdata[31]; + + assign mio_pad_sleep_regwen_0_we = addr_hit[227] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_0_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_1_we = addr_hit[228] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_1_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_2_we = addr_hit[229] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_2_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_3_we = addr_hit[230] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_3_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_4_we = addr_hit[231] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_4_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_5_we = addr_hit[232] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_5_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_6_we = addr_hit[233] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_6_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_7_we = addr_hit[234] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_7_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_8_we = addr_hit[235] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_8_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_9_we = addr_hit[236] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_9_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_10_we = addr_hit[237] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_10_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_11_we = addr_hit[238] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_11_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_12_we = addr_hit[239] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_12_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_13_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_13_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_14_we = addr_hit[241] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_14_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_15_we = addr_hit[242] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_15_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_16_we = addr_hit[243] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_16_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_17_we = addr_hit[244] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_17_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_18_we = addr_hit[245] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_18_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_19_we = addr_hit[246] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_19_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_20_we = addr_hit[247] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_20_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_21_we = addr_hit[248] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_21_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_22_we = addr_hit[249] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_22_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_23_we = addr_hit[250] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_23_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_24_we = addr_hit[251] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_24_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_25_we = addr_hit[252] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_25_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_26_we = addr_hit[253] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_26_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_27_we = addr_hit[254] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_27_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_28_we = addr_hit[255] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_28_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_29_we = addr_hit[256] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_29_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_30_we = addr_hit[257] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_30_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_31_we = addr_hit[258] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_31_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_0_we = addr_hit[259] & reg_we & ~wr_err; + assign mio_pad_sleep_en_0_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_1_we = addr_hit[260] & reg_we & ~wr_err; + assign mio_pad_sleep_en_1_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_2_we = addr_hit[261] & reg_we & ~wr_err; + assign mio_pad_sleep_en_2_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_3_we = addr_hit[262] & reg_we & ~wr_err; + assign mio_pad_sleep_en_3_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_4_we = addr_hit[263] & reg_we & ~wr_err; + assign mio_pad_sleep_en_4_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_5_we = addr_hit[264] & reg_we & ~wr_err; + assign mio_pad_sleep_en_5_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_6_we = addr_hit[265] & reg_we & ~wr_err; + assign mio_pad_sleep_en_6_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_7_we = addr_hit[266] & reg_we & ~wr_err; + assign mio_pad_sleep_en_7_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_8_we = addr_hit[267] & reg_we & ~wr_err; + assign mio_pad_sleep_en_8_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_9_we = addr_hit[268] & reg_we & ~wr_err; + assign mio_pad_sleep_en_9_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_10_we = addr_hit[269] & reg_we & ~wr_err; + assign mio_pad_sleep_en_10_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_11_we = addr_hit[270] & reg_we & ~wr_err; + assign mio_pad_sleep_en_11_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_12_we = addr_hit[271] & reg_we & ~wr_err; + assign mio_pad_sleep_en_12_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_13_we = addr_hit[272] & reg_we & ~wr_err; + assign mio_pad_sleep_en_13_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_14_we = addr_hit[273] & reg_we & ~wr_err; + assign mio_pad_sleep_en_14_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_15_we = addr_hit[274] & reg_we & ~wr_err; + assign mio_pad_sleep_en_15_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_16_we = addr_hit[275] & reg_we & ~wr_err; + assign mio_pad_sleep_en_16_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_17_we = addr_hit[276] & reg_we & ~wr_err; + assign mio_pad_sleep_en_17_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_18_we = addr_hit[277] & reg_we & ~wr_err; + assign mio_pad_sleep_en_18_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_19_we = addr_hit[278] & reg_we & ~wr_err; + assign mio_pad_sleep_en_19_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_20_we = addr_hit[279] & reg_we & ~wr_err; + assign mio_pad_sleep_en_20_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_21_we = addr_hit[280] & reg_we & ~wr_err; + assign mio_pad_sleep_en_21_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_22_we = addr_hit[281] & reg_we & ~wr_err; + assign mio_pad_sleep_en_22_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_23_we = addr_hit[282] & reg_we & ~wr_err; + assign mio_pad_sleep_en_23_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_24_we = addr_hit[283] & reg_we & ~wr_err; + assign mio_pad_sleep_en_24_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_25_we = addr_hit[284] & reg_we & ~wr_err; + assign mio_pad_sleep_en_25_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_26_we = addr_hit[285] & reg_we & ~wr_err; + assign mio_pad_sleep_en_26_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_27_we = addr_hit[286] & reg_we & ~wr_err; + assign mio_pad_sleep_en_27_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_28_we = addr_hit[287] & reg_we & ~wr_err; + assign mio_pad_sleep_en_28_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_29_we = addr_hit[288] & reg_we & ~wr_err; + assign mio_pad_sleep_en_29_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_30_we = addr_hit[289] & reg_we & ~wr_err; + assign mio_pad_sleep_en_30_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_31_we = addr_hit[290] & reg_we & ~wr_err; + assign mio_pad_sleep_en_31_wd = reg_wdata[0]; + + assign mio_pad_sleep_mode_0_we = addr_hit[291] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_0_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_1_we = addr_hit[131] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_1_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_1_we = addr_hit[292] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_1_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_2_we = addr_hit[132] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_2_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_2_we = addr_hit[293] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_2_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_3_we = addr_hit[133] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_3_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_3_we = addr_hit[294] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_3_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_4_we = addr_hit[134] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_4_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_4_we = addr_hit[295] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_4_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_5_we = addr_hit[135] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_5_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_5_we = addr_hit[296] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_5_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_6_we = addr_hit[136] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_6_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_6_we = addr_hit[297] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_6_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_7_we = addr_hit[137] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_7_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_7_we = addr_hit[298] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_7_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_8_we = addr_hit[138] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_8_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_8_we = addr_hit[299] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_8_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_9_we = addr_hit[139] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_9_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_9_we = addr_hit[300] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_9_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_10_we = addr_hit[140] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_10_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_10_we = addr_hit[301] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_10_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_11_we = addr_hit[141] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_11_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_11_we = addr_hit[302] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_11_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_12_we = addr_hit[142] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_12_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_12_we = addr_hit[303] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_12_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_13_we = addr_hit[143] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_13_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_13_we = addr_hit[304] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_13_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_14_we = addr_hit[144] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_14_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_14_we = addr_hit[305] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_14_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_15_we = addr_hit[145] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_15_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_15_we = addr_hit[306] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_15_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_16_we = addr_hit[146] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_16_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_16_we = addr_hit[307] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_16_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_17_we = addr_hit[147] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_17_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_17_we = addr_hit[308] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_17_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_18_we = addr_hit[148] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_18_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_18_we = addr_hit[309] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_18_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_19_we = addr_hit[149] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_19_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_19_we = addr_hit[310] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_19_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_20_we = addr_hit[150] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_20_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_20_we = addr_hit[311] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_20_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_21_we = addr_hit[151] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_21_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_21_we = addr_hit[312] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_21_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_22_we = addr_hit[152] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_22_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_22_we = addr_hit[313] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_22_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_23_we = addr_hit[153] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_23_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_23_we = addr_hit[314] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_23_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_24_we = addr_hit[154] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_24_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_24_we = addr_hit[315] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_24_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_25_we = addr_hit[155] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_25_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_25_we = addr_hit[316] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_25_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_26_we = addr_hit[156] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_26_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_26_we = addr_hit[317] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_26_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_27_we = addr_hit[157] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_27_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_27_we = addr_hit[318] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_27_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_28_we = addr_hit[158] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_28_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_28_we = addr_hit[319] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_28_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_29_we = addr_hit[159] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_29_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_29_we = addr_hit[320] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_29_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_30_we = addr_hit[160] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_30_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_30_we = addr_hit[321] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_30_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_31_we = addr_hit[161] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_31_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_31_we = addr_hit[322] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_31_wd = reg_wdata[1:0]; - assign mio_out_sleep_val_0_we = addr_hit[162] & reg_we & ~wr_err; - assign mio_out_sleep_val_0_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_0_we = addr_hit[323] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_0_wd = reg_wdata[0]; - assign mio_out_sleep_val_1_we = addr_hit[163] & reg_we & ~wr_err; - assign mio_out_sleep_val_1_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_1_we = addr_hit[323] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_1_wd = reg_wdata[1]; - assign mio_out_sleep_val_2_we = addr_hit[164] & reg_we & ~wr_err; - assign mio_out_sleep_val_2_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_2_we = addr_hit[323] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_2_wd = reg_wdata[2]; - assign mio_out_sleep_val_3_we = addr_hit[165] & reg_we & ~wr_err; - assign mio_out_sleep_val_3_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_3_we = addr_hit[323] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_3_wd = reg_wdata[3]; - assign mio_out_sleep_val_4_we = addr_hit[166] & reg_we & ~wr_err; - assign mio_out_sleep_val_4_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_4_we = addr_hit[323] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_4_wd = reg_wdata[4]; - assign mio_out_sleep_val_5_we = addr_hit[167] & reg_we & ~wr_err; - assign mio_out_sleep_val_5_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_5_we = addr_hit[323] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_5_wd = reg_wdata[5]; - assign mio_out_sleep_val_6_we = addr_hit[168] & reg_we & ~wr_err; - assign mio_out_sleep_val_6_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_6_we = addr_hit[323] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_6_wd = reg_wdata[6]; - assign mio_out_sleep_val_7_we = addr_hit[169] & reg_we & ~wr_err; - assign mio_out_sleep_val_7_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_7_we = addr_hit[323] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_7_wd = reg_wdata[7]; - assign mio_out_sleep_val_8_we = addr_hit[170] & reg_we & ~wr_err; - assign mio_out_sleep_val_8_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_8_we = addr_hit[323] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_8_wd = reg_wdata[8]; - assign mio_out_sleep_val_9_we = addr_hit[171] & reg_we & ~wr_err; - assign mio_out_sleep_val_9_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_9_we = addr_hit[323] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_9_wd = reg_wdata[9]; - assign mio_out_sleep_val_10_we = addr_hit[172] & reg_we & ~wr_err; - assign mio_out_sleep_val_10_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_10_we = addr_hit[323] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_10_wd = reg_wdata[10]; - assign mio_out_sleep_val_11_we = addr_hit[173] & reg_we & ~wr_err; - assign mio_out_sleep_val_11_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_11_we = addr_hit[323] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_11_wd = reg_wdata[11]; - assign mio_out_sleep_val_12_we = addr_hit[174] & reg_we & ~wr_err; - assign mio_out_sleep_val_12_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_12_we = addr_hit[323] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_12_wd = reg_wdata[12]; - assign mio_out_sleep_val_13_we = addr_hit[175] & reg_we & ~wr_err; - assign mio_out_sleep_val_13_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_13_we = addr_hit[323] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_13_wd = reg_wdata[13]; - assign mio_out_sleep_val_14_we = addr_hit[176] & reg_we & ~wr_err; - assign mio_out_sleep_val_14_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_14_we = addr_hit[323] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_14_wd = reg_wdata[14]; - assign mio_out_sleep_val_15_we = addr_hit[177] & reg_we & ~wr_err; - assign mio_out_sleep_val_15_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_15_we = addr_hit[323] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_15_wd = reg_wdata[15]; - assign mio_out_sleep_val_16_we = addr_hit[178] & reg_we & ~wr_err; - assign mio_out_sleep_val_16_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_0_we = addr_hit[324] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_0_wd = reg_wdata[0]; - assign mio_out_sleep_val_17_we = addr_hit[179] & reg_we & ~wr_err; - assign mio_out_sleep_val_17_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_1_we = addr_hit[325] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_1_wd = reg_wdata[0]; - assign mio_out_sleep_val_18_we = addr_hit[180] & reg_we & ~wr_err; - assign mio_out_sleep_val_18_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_2_we = addr_hit[326] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_2_wd = reg_wdata[0]; - assign mio_out_sleep_val_19_we = addr_hit[181] & reg_we & ~wr_err; - assign mio_out_sleep_val_19_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_3_we = addr_hit[327] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_3_wd = reg_wdata[0]; - assign mio_out_sleep_val_20_we = addr_hit[182] & reg_we & ~wr_err; - assign mio_out_sleep_val_20_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_4_we = addr_hit[328] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_4_wd = reg_wdata[0]; - assign mio_out_sleep_val_21_we = addr_hit[183] & reg_we & ~wr_err; - assign mio_out_sleep_val_21_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_5_we = addr_hit[329] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_5_wd = reg_wdata[0]; - assign mio_out_sleep_val_22_we = addr_hit[184] & reg_we & ~wr_err; - assign mio_out_sleep_val_22_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_6_we = addr_hit[330] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_6_wd = reg_wdata[0]; - assign mio_out_sleep_val_23_we = addr_hit[185] & reg_we & ~wr_err; - assign mio_out_sleep_val_23_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_7_we = addr_hit[331] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_7_wd = reg_wdata[0]; - assign mio_out_sleep_val_24_we = addr_hit[186] & reg_we & ~wr_err; - assign mio_out_sleep_val_24_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_8_we = addr_hit[332] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_8_wd = reg_wdata[0]; - assign mio_out_sleep_val_25_we = addr_hit[187] & reg_we & ~wr_err; - assign mio_out_sleep_val_25_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_9_we = addr_hit[333] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_9_wd = reg_wdata[0]; - assign mio_out_sleep_val_26_we = addr_hit[188] & reg_we & ~wr_err; - assign mio_out_sleep_val_26_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_10_we = addr_hit[334] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_10_wd = reg_wdata[0]; - assign mio_out_sleep_val_27_we = addr_hit[189] & reg_we & ~wr_err; - assign mio_out_sleep_val_27_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_11_we = addr_hit[335] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_11_wd = reg_wdata[0]; - assign mio_out_sleep_val_28_we = addr_hit[190] & reg_we & ~wr_err; - assign mio_out_sleep_val_28_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_12_we = addr_hit[336] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_12_wd = reg_wdata[0]; - assign mio_out_sleep_val_29_we = addr_hit[191] & reg_we & ~wr_err; - assign mio_out_sleep_val_29_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_13_we = addr_hit[337] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_13_wd = reg_wdata[0]; - assign mio_out_sleep_val_30_we = addr_hit[192] & reg_we & ~wr_err; - assign mio_out_sleep_val_30_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_14_we = addr_hit[338] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_14_wd = reg_wdata[0]; - assign mio_out_sleep_val_31_we = addr_hit[193] & reg_we & ~wr_err; - assign mio_out_sleep_val_31_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_15_we = addr_hit[339] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_15_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_0_we = addr_hit[194] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_0_wd = reg_wdata[0]; + assign dio_pad_sleep_en_0_we = addr_hit[340] & reg_we & ~wr_err; + assign dio_pad_sleep_en_0_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_1_we = addr_hit[195] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_1_wd = reg_wdata[0]; + assign dio_pad_sleep_en_1_we = addr_hit[341] & reg_we & ~wr_err; + assign dio_pad_sleep_en_1_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_2_we = addr_hit[196] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_2_wd = reg_wdata[0]; + assign dio_pad_sleep_en_2_we = addr_hit[342] & reg_we & ~wr_err; + assign dio_pad_sleep_en_2_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_3_we = addr_hit[197] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_3_wd = reg_wdata[0]; + assign dio_pad_sleep_en_3_we = addr_hit[343] & reg_we & ~wr_err; + assign dio_pad_sleep_en_3_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_4_we = addr_hit[198] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_4_wd = reg_wdata[0]; + assign dio_pad_sleep_en_4_we = addr_hit[344] & reg_we & ~wr_err; + assign dio_pad_sleep_en_4_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_5_we = addr_hit[199] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_5_wd = reg_wdata[0]; + assign dio_pad_sleep_en_5_we = addr_hit[345] & reg_we & ~wr_err; + assign dio_pad_sleep_en_5_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_6_we = addr_hit[200] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_6_wd = reg_wdata[0]; + assign dio_pad_sleep_en_6_we = addr_hit[346] & reg_we & ~wr_err; + assign dio_pad_sleep_en_6_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_7_we = addr_hit[201] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_7_wd = reg_wdata[0]; + assign dio_pad_sleep_en_7_we = addr_hit[347] & reg_we & ~wr_err; + assign dio_pad_sleep_en_7_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_8_we = addr_hit[202] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_8_wd = reg_wdata[0]; + assign dio_pad_sleep_en_8_we = addr_hit[348] & reg_we & ~wr_err; + assign dio_pad_sleep_en_8_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_9_we = addr_hit[203] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_9_wd = reg_wdata[0]; + assign dio_pad_sleep_en_9_we = addr_hit[349] & reg_we & ~wr_err; + assign dio_pad_sleep_en_9_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_10_we = addr_hit[204] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_10_wd = reg_wdata[0]; + assign dio_pad_sleep_en_10_we = addr_hit[350] & reg_we & ~wr_err; + assign dio_pad_sleep_en_10_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_11_we = addr_hit[205] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_11_wd = reg_wdata[0]; + assign dio_pad_sleep_en_11_we = addr_hit[351] & reg_we & ~wr_err; + assign dio_pad_sleep_en_11_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_12_we = addr_hit[206] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_12_wd = reg_wdata[0]; + assign dio_pad_sleep_en_12_we = addr_hit[352] & reg_we & ~wr_err; + assign dio_pad_sleep_en_12_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_13_we = addr_hit[207] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_13_wd = reg_wdata[0]; + assign dio_pad_sleep_en_13_we = addr_hit[353] & reg_we & ~wr_err; + assign dio_pad_sleep_en_13_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_14_we = addr_hit[208] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_14_wd = reg_wdata[0]; + assign dio_pad_sleep_en_14_we = addr_hit[354] & reg_we & ~wr_err; + assign dio_pad_sleep_en_14_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_15_we = addr_hit[209] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_15_wd = reg_wdata[0]; + assign dio_pad_sleep_en_15_we = addr_hit[355] & reg_we & ~wr_err; + assign dio_pad_sleep_en_15_wd = reg_wdata[0]; - assign dio_out_sleep_val_0_we = addr_hit[210] & reg_we & ~wr_err; - assign dio_out_sleep_val_0_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_0_re = addr_hit[210] && reg_re; + assign dio_pad_sleep_mode_0_we = addr_hit[356] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_0_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_1_we = addr_hit[211] & reg_we & ~wr_err; - assign dio_out_sleep_val_1_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_1_re = addr_hit[211] && reg_re; + assign dio_pad_sleep_mode_1_we = addr_hit[357] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_1_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_2_we = addr_hit[212] & reg_we & ~wr_err; - assign dio_out_sleep_val_2_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_2_re = addr_hit[212] && reg_re; + assign dio_pad_sleep_mode_2_we = addr_hit[358] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_2_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_3_we = addr_hit[213] & reg_we & ~wr_err; - assign dio_out_sleep_val_3_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_3_re = addr_hit[213] && reg_re; + assign dio_pad_sleep_mode_3_we = addr_hit[359] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_3_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_4_we = addr_hit[214] & reg_we & ~wr_err; - assign dio_out_sleep_val_4_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_4_re = addr_hit[214] && reg_re; + assign dio_pad_sleep_mode_4_we = addr_hit[360] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_4_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_5_we = addr_hit[215] & reg_we & ~wr_err; - assign dio_out_sleep_val_5_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_5_re = addr_hit[215] && reg_re; + assign dio_pad_sleep_mode_5_we = addr_hit[361] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_5_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_6_we = addr_hit[216] & reg_we & ~wr_err; - assign dio_out_sleep_val_6_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_6_re = addr_hit[216] && reg_re; + assign dio_pad_sleep_mode_6_we = addr_hit[362] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_6_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_7_we = addr_hit[217] & reg_we & ~wr_err; - assign dio_out_sleep_val_7_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_7_re = addr_hit[217] && reg_re; + assign dio_pad_sleep_mode_7_we = addr_hit[363] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_7_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_8_we = addr_hit[218] & reg_we & ~wr_err; - assign dio_out_sleep_val_8_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_8_re = addr_hit[218] && reg_re; + assign dio_pad_sleep_mode_8_we = addr_hit[364] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_8_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_9_we = addr_hit[219] & reg_we & ~wr_err; - assign dio_out_sleep_val_9_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_9_re = addr_hit[219] && reg_re; + assign dio_pad_sleep_mode_9_we = addr_hit[365] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_9_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_10_we = addr_hit[220] & reg_we & ~wr_err; - assign dio_out_sleep_val_10_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_10_re = addr_hit[220] && reg_re; + assign dio_pad_sleep_mode_10_we = addr_hit[366] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_10_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_11_we = addr_hit[221] & reg_we & ~wr_err; - assign dio_out_sleep_val_11_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_11_re = addr_hit[221] && reg_re; + assign dio_pad_sleep_mode_11_we = addr_hit[367] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_11_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_12_we = addr_hit[222] & reg_we & ~wr_err; - assign dio_out_sleep_val_12_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_12_re = addr_hit[222] && reg_re; + assign dio_pad_sleep_mode_12_we = addr_hit[368] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_12_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_13_we = addr_hit[223] & reg_we & ~wr_err; - assign dio_out_sleep_val_13_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_13_re = addr_hit[223] && reg_re; + assign dio_pad_sleep_mode_13_we = addr_hit[369] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_13_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_14_we = addr_hit[224] & reg_we & ~wr_err; - assign dio_out_sleep_val_14_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_14_re = addr_hit[224] && reg_re; + assign dio_pad_sleep_mode_14_we = addr_hit[370] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_14_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_15_we = addr_hit[225] & reg_we & ~wr_err; - assign dio_out_sleep_val_15_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_15_re = addr_hit[225] && reg_re; + assign dio_pad_sleep_mode_15_we = addr_hit[371] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_15_wd = reg_wdata[1:0]; - assign wkup_detector_regwen_0_we = addr_hit[226] & reg_we & ~wr_err; + assign wkup_detector_regwen_0_we = addr_hit[372] & reg_we & ~wr_err; assign wkup_detector_regwen_0_wd = reg_wdata[0]; - assign wkup_detector_regwen_1_we = addr_hit[227] & reg_we & ~wr_err; + assign wkup_detector_regwen_1_we = addr_hit[373] & reg_we & ~wr_err; assign wkup_detector_regwen_1_wd = reg_wdata[0]; - assign wkup_detector_regwen_2_we = addr_hit[228] & reg_we & ~wr_err; + assign wkup_detector_regwen_2_we = addr_hit[374] & reg_we & ~wr_err; assign wkup_detector_regwen_2_wd = reg_wdata[0]; - assign wkup_detector_regwen_3_we = addr_hit[229] & reg_we & ~wr_err; + assign wkup_detector_regwen_3_we = addr_hit[375] & reg_we & ~wr_err; assign wkup_detector_regwen_3_wd = reg_wdata[0]; - assign wkup_detector_regwen_4_we = addr_hit[230] & reg_we & ~wr_err; + assign wkup_detector_regwen_4_we = addr_hit[376] & reg_we & ~wr_err; assign wkup_detector_regwen_4_wd = reg_wdata[0]; - assign wkup_detector_regwen_5_we = addr_hit[231] & reg_we & ~wr_err; + assign wkup_detector_regwen_5_we = addr_hit[377] & reg_we & ~wr_err; assign wkup_detector_regwen_5_wd = reg_wdata[0]; - assign wkup_detector_regwen_6_we = addr_hit[232] & reg_we & ~wr_err; + assign wkup_detector_regwen_6_we = addr_hit[378] & reg_we & ~wr_err; assign wkup_detector_regwen_6_wd = reg_wdata[0]; - assign wkup_detector_regwen_7_we = addr_hit[233] & reg_we & ~wr_err; + assign wkup_detector_regwen_7_we = addr_hit[379] & reg_we & ~wr_err; assign wkup_detector_regwen_7_wd = reg_wdata[0]; - assign wkup_detector_en_0_we = addr_hit[234] & reg_we & ~wr_err; + assign wkup_detector_en_0_we = addr_hit[380] & reg_we & ~wr_err; assign wkup_detector_en_0_wd = reg_wdata[0]; - assign wkup_detector_en_1_we = addr_hit[235] & reg_we & ~wr_err; + assign wkup_detector_en_1_we = addr_hit[381] & reg_we & ~wr_err; assign wkup_detector_en_1_wd = reg_wdata[0]; - assign wkup_detector_en_2_we = addr_hit[236] & reg_we & ~wr_err; + assign wkup_detector_en_2_we = addr_hit[382] & reg_we & ~wr_err; assign wkup_detector_en_2_wd = reg_wdata[0]; - assign wkup_detector_en_3_we = addr_hit[237] & reg_we & ~wr_err; + assign wkup_detector_en_3_we = addr_hit[383] & reg_we & ~wr_err; assign wkup_detector_en_3_wd = reg_wdata[0]; - assign wkup_detector_en_4_we = addr_hit[238] & reg_we & ~wr_err; + assign wkup_detector_en_4_we = addr_hit[384] & reg_we & ~wr_err; assign wkup_detector_en_4_wd = reg_wdata[0]; - assign wkup_detector_en_5_we = addr_hit[239] & reg_we & ~wr_err; + assign wkup_detector_en_5_we = addr_hit[385] & reg_we & ~wr_err; assign wkup_detector_en_5_wd = reg_wdata[0]; - assign wkup_detector_en_6_we = addr_hit[240] & reg_we & ~wr_err; + assign wkup_detector_en_6_we = addr_hit[386] & reg_we & ~wr_err; assign wkup_detector_en_6_wd = reg_wdata[0]; - assign wkup_detector_en_7_we = addr_hit[241] & reg_we & ~wr_err; + assign wkup_detector_en_7_we = addr_hit[387] & reg_we & ~wr_err; assign wkup_detector_en_7_wd = reg_wdata[0]; - assign wkup_detector_0_mode_0_we = addr_hit[242] & reg_we & ~wr_err; + assign wkup_detector_0_mode_0_we = addr_hit[388] & reg_we & ~wr_err; assign wkup_detector_0_mode_0_wd = reg_wdata[2:0]; - assign wkup_detector_0_filter_0_we = addr_hit[242] & reg_we & ~wr_err; + assign wkup_detector_0_filter_0_we = addr_hit[388] & reg_we & ~wr_err; assign wkup_detector_0_filter_0_wd = reg_wdata[3]; - assign wkup_detector_0_miodio_0_we = addr_hit[242] & reg_we & ~wr_err; + assign wkup_detector_0_miodio_0_we = addr_hit[388] & reg_we & ~wr_err; assign wkup_detector_0_miodio_0_wd = reg_wdata[4]; - assign wkup_detector_1_mode_1_we = addr_hit[243] & reg_we & ~wr_err; + assign wkup_detector_1_mode_1_we = addr_hit[389] & reg_we & ~wr_err; assign wkup_detector_1_mode_1_wd = reg_wdata[2:0]; - assign wkup_detector_1_filter_1_we = addr_hit[243] & reg_we & ~wr_err; + assign wkup_detector_1_filter_1_we = addr_hit[389] & reg_we & ~wr_err; assign wkup_detector_1_filter_1_wd = reg_wdata[3]; - assign wkup_detector_1_miodio_1_we = addr_hit[243] & reg_we & ~wr_err; + assign wkup_detector_1_miodio_1_we = addr_hit[389] & reg_we & ~wr_err; assign wkup_detector_1_miodio_1_wd = reg_wdata[4]; - assign wkup_detector_2_mode_2_we = addr_hit[244] & reg_we & ~wr_err; + assign wkup_detector_2_mode_2_we = addr_hit[390] & reg_we & ~wr_err; assign wkup_detector_2_mode_2_wd = reg_wdata[2:0]; - assign wkup_detector_2_filter_2_we = addr_hit[244] & reg_we & ~wr_err; + assign wkup_detector_2_filter_2_we = addr_hit[390] & reg_we & ~wr_err; assign wkup_detector_2_filter_2_wd = reg_wdata[3]; - assign wkup_detector_2_miodio_2_we = addr_hit[244] & reg_we & ~wr_err; + assign wkup_detector_2_miodio_2_we = addr_hit[390] & reg_we & ~wr_err; assign wkup_detector_2_miodio_2_wd = reg_wdata[4]; - assign wkup_detector_3_mode_3_we = addr_hit[245] & reg_we & ~wr_err; + assign wkup_detector_3_mode_3_we = addr_hit[391] & reg_we & ~wr_err; assign wkup_detector_3_mode_3_wd = reg_wdata[2:0]; - assign wkup_detector_3_filter_3_we = addr_hit[245] & reg_we & ~wr_err; + assign wkup_detector_3_filter_3_we = addr_hit[391] & reg_we & ~wr_err; assign wkup_detector_3_filter_3_wd = reg_wdata[3]; - assign wkup_detector_3_miodio_3_we = addr_hit[245] & reg_we & ~wr_err; + assign wkup_detector_3_miodio_3_we = addr_hit[391] & reg_we & ~wr_err; assign wkup_detector_3_miodio_3_wd = reg_wdata[4]; - assign wkup_detector_4_mode_4_we = addr_hit[246] & reg_we & ~wr_err; + assign wkup_detector_4_mode_4_we = addr_hit[392] & reg_we & ~wr_err; assign wkup_detector_4_mode_4_wd = reg_wdata[2:0]; - assign wkup_detector_4_filter_4_we = addr_hit[246] & reg_we & ~wr_err; + assign wkup_detector_4_filter_4_we = addr_hit[392] & reg_we & ~wr_err; assign wkup_detector_4_filter_4_wd = reg_wdata[3]; - assign wkup_detector_4_miodio_4_we = addr_hit[246] & reg_we & ~wr_err; + assign wkup_detector_4_miodio_4_we = addr_hit[392] & reg_we & ~wr_err; assign wkup_detector_4_miodio_4_wd = reg_wdata[4]; - assign wkup_detector_5_mode_5_we = addr_hit[247] & reg_we & ~wr_err; + assign wkup_detector_5_mode_5_we = addr_hit[393] & reg_we & ~wr_err; assign wkup_detector_5_mode_5_wd = reg_wdata[2:0]; - assign wkup_detector_5_filter_5_we = addr_hit[247] & reg_we & ~wr_err; + assign wkup_detector_5_filter_5_we = addr_hit[393] & reg_we & ~wr_err; assign wkup_detector_5_filter_5_wd = reg_wdata[3]; - assign wkup_detector_5_miodio_5_we = addr_hit[247] & reg_we & ~wr_err; + assign wkup_detector_5_miodio_5_we = addr_hit[393] & reg_we & ~wr_err; assign wkup_detector_5_miodio_5_wd = reg_wdata[4]; - assign wkup_detector_6_mode_6_we = addr_hit[248] & reg_we & ~wr_err; + assign wkup_detector_6_mode_6_we = addr_hit[394] & reg_we & ~wr_err; assign wkup_detector_6_mode_6_wd = reg_wdata[2:0]; - assign wkup_detector_6_filter_6_we = addr_hit[248] & reg_we & ~wr_err; + assign wkup_detector_6_filter_6_we = addr_hit[394] & reg_we & ~wr_err; assign wkup_detector_6_filter_6_wd = reg_wdata[3]; - assign wkup_detector_6_miodio_6_we = addr_hit[248] & reg_we & ~wr_err; + assign wkup_detector_6_miodio_6_we = addr_hit[394] & reg_we & ~wr_err; assign wkup_detector_6_miodio_6_wd = reg_wdata[4]; - assign wkup_detector_7_mode_7_we = addr_hit[249] & reg_we & ~wr_err; + assign wkup_detector_7_mode_7_we = addr_hit[395] & reg_we & ~wr_err; assign wkup_detector_7_mode_7_wd = reg_wdata[2:0]; - assign wkup_detector_7_filter_7_we = addr_hit[249] & reg_we & ~wr_err; + assign wkup_detector_7_filter_7_we = addr_hit[395] & reg_we & ~wr_err; assign wkup_detector_7_filter_7_wd = reg_wdata[3]; - assign wkup_detector_7_miodio_7_we = addr_hit[249] & reg_we & ~wr_err; + assign wkup_detector_7_miodio_7_we = addr_hit[395] & reg_we & ~wr_err; assign wkup_detector_7_miodio_7_wd = reg_wdata[4]; - assign wkup_detector_cnt_th_0_we = addr_hit[250] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_0_we = addr_hit[396] & reg_we & ~wr_err; assign wkup_detector_cnt_th_0_wd = reg_wdata[7:0]; - assign wkup_detector_cnt_th_1_we = addr_hit[251] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_1_we = addr_hit[397] & reg_we & ~wr_err; assign wkup_detector_cnt_th_1_wd = reg_wdata[7:0]; - assign wkup_detector_cnt_th_2_we = addr_hit[252] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_2_we = addr_hit[398] & reg_we & ~wr_err; assign wkup_detector_cnt_th_2_wd = reg_wdata[7:0]; - assign wkup_detector_cnt_th_3_we = addr_hit[253] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_3_we = addr_hit[399] & reg_we & ~wr_err; assign wkup_detector_cnt_th_3_wd = reg_wdata[7:0]; - assign wkup_detector_cnt_th_4_we = addr_hit[254] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_4_we = addr_hit[400] & reg_we & ~wr_err; assign wkup_detector_cnt_th_4_wd = reg_wdata[7:0]; - assign wkup_detector_cnt_th_5_we = addr_hit[255] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_5_we = addr_hit[401] & reg_we & ~wr_err; assign wkup_detector_cnt_th_5_wd = reg_wdata[7:0]; - assign wkup_detector_cnt_th_6_we = addr_hit[256] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_6_we = addr_hit[402] & reg_we & ~wr_err; assign wkup_detector_cnt_th_6_wd = reg_wdata[7:0]; - assign wkup_detector_cnt_th_7_we = addr_hit[257] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_7_we = addr_hit[403] & reg_we & ~wr_err; assign wkup_detector_cnt_th_7_wd = reg_wdata[7:0]; - assign wkup_detector_padsel_0_we = addr_hit[258] & reg_we & ~wr_err; + assign wkup_detector_padsel_0_we = addr_hit[404] & reg_we & ~wr_err; assign wkup_detector_padsel_0_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_1_we = addr_hit[259] & reg_we & ~wr_err; + assign wkup_detector_padsel_1_we = addr_hit[405] & reg_we & ~wr_err; assign wkup_detector_padsel_1_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_2_we = addr_hit[260] & reg_we & ~wr_err; + assign wkup_detector_padsel_2_we = addr_hit[406] & reg_we & ~wr_err; assign wkup_detector_padsel_2_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_3_we = addr_hit[261] & reg_we & ~wr_err; + assign wkup_detector_padsel_3_we = addr_hit[407] & reg_we & ~wr_err; assign wkup_detector_padsel_3_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_4_we = addr_hit[262] & reg_we & ~wr_err; + assign wkup_detector_padsel_4_we = addr_hit[408] & reg_we & ~wr_err; assign wkup_detector_padsel_4_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_5_we = addr_hit[263] & reg_we & ~wr_err; + assign wkup_detector_padsel_5_we = addr_hit[409] & reg_we & ~wr_err; assign wkup_detector_padsel_5_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_6_we = addr_hit[264] & reg_we & ~wr_err; + assign wkup_detector_padsel_6_we = addr_hit[410] & reg_we & ~wr_err; assign wkup_detector_padsel_6_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_7_we = addr_hit[265] & reg_we & ~wr_err; + assign wkup_detector_padsel_7_we = addr_hit[411] & reg_we & ~wr_err; assign wkup_detector_padsel_7_wd = reg_wdata[5:0]; - assign wkup_cause_cause_0_we = addr_hit[266] & reg_we & ~wr_err; + assign wkup_cause_cause_0_we = addr_hit[412] & reg_we & ~wr_err; assign wkup_cause_cause_0_wd = reg_wdata[0]; - assign wkup_cause_cause_0_re = addr_hit[266] && reg_re; + assign wkup_cause_cause_0_re = addr_hit[412] && reg_re; - assign wkup_cause_cause_1_we = addr_hit[266] & reg_we & ~wr_err; + assign wkup_cause_cause_1_we = addr_hit[412] & reg_we & ~wr_err; assign wkup_cause_cause_1_wd = reg_wdata[1]; - assign wkup_cause_cause_1_re = addr_hit[266] && reg_re; + assign wkup_cause_cause_1_re = addr_hit[412] && reg_re; - assign wkup_cause_cause_2_we = addr_hit[266] & reg_we & ~wr_err; + assign wkup_cause_cause_2_we = addr_hit[412] & reg_we & ~wr_err; assign wkup_cause_cause_2_wd = reg_wdata[2]; - assign wkup_cause_cause_2_re = addr_hit[266] && reg_re; + assign wkup_cause_cause_2_re = addr_hit[412] && reg_re; - assign wkup_cause_cause_3_we = addr_hit[266] & reg_we & ~wr_err; + assign wkup_cause_cause_3_we = addr_hit[412] & reg_we & ~wr_err; assign wkup_cause_cause_3_wd = reg_wdata[3]; - assign wkup_cause_cause_3_re = addr_hit[266] && reg_re; + assign wkup_cause_cause_3_re = addr_hit[412] && reg_re; - assign wkup_cause_cause_4_we = addr_hit[266] & reg_we & ~wr_err; + assign wkup_cause_cause_4_we = addr_hit[412] & reg_we & ~wr_err; assign wkup_cause_cause_4_wd = reg_wdata[4]; - assign wkup_cause_cause_4_re = addr_hit[266] && reg_re; + assign wkup_cause_cause_4_re = addr_hit[412] && reg_re; - assign wkup_cause_cause_5_we = addr_hit[266] & reg_we & ~wr_err; + assign wkup_cause_cause_5_we = addr_hit[412] & reg_we & ~wr_err; assign wkup_cause_cause_5_wd = reg_wdata[5]; - assign wkup_cause_cause_5_re = addr_hit[266] && reg_re; + assign wkup_cause_cause_5_re = addr_hit[412] && reg_re; - assign wkup_cause_cause_6_we = addr_hit[266] & reg_we & ~wr_err; + assign wkup_cause_cause_6_we = addr_hit[412] & reg_we & ~wr_err; assign wkup_cause_cause_6_wd = reg_wdata[6]; - assign wkup_cause_cause_6_re = addr_hit[266] && reg_re; + assign wkup_cause_cause_6_re = addr_hit[412] && reg_re; - assign wkup_cause_cause_7_we = addr_hit[266] & reg_we & ~wr_err; + assign wkup_cause_cause_7_we = addr_hit[412] & reg_we & ~wr_err; assign wkup_cause_cause_7_wd = reg_wdata[7]; - assign wkup_cause_cause_7_re = addr_hit[266] && reg_re; + assign wkup_cause_cause_7_re = addr_hit[412] && reg_re; // Read data return always_comb begin @@ -10539,566 +16885,1196 @@ end addr_hit[130]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_0_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_0_qs; end addr_hit[131]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_1_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_1_qs; end addr_hit[132]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_2_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_2_qs; end addr_hit[133]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_3_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_3_qs; end addr_hit[134]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_4_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_4_qs; end addr_hit[135]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_5_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_5_qs; end addr_hit[136]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_6_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_6_qs; end addr_hit[137]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_7_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_7_qs; end addr_hit[138]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_8_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_8_qs; end addr_hit[139]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_9_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_9_qs; end addr_hit[140]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_10_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_10_qs; end addr_hit[141]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_11_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_11_qs; end addr_hit[142]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_12_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_12_qs; end addr_hit[143]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_13_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_13_qs; end addr_hit[144]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_14_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_14_qs; end addr_hit[145]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_15_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_15_qs; end addr_hit[146]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_16_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_16_qs; end addr_hit[147]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_17_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_17_qs; end addr_hit[148]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_18_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_18_qs; end addr_hit[149]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_19_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_19_qs; end addr_hit[150]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_20_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_20_qs; end addr_hit[151]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_21_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_21_qs; end addr_hit[152]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_22_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_22_qs; end addr_hit[153]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_23_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_23_qs; end addr_hit[154]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_24_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_24_qs; end addr_hit[155]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_25_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_25_qs; end addr_hit[156]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_26_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_26_qs; end addr_hit[157]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_27_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_27_qs; end addr_hit[158]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_28_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_28_qs; end addr_hit[159]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_29_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_29_qs; end addr_hit[160]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_30_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_30_qs; end addr_hit[161]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_31_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_31_qs; end addr_hit[162]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_0_qs; + reg_rdata_next[9:0] = mio_pad_attr_0_qs; end addr_hit[163]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_1_qs; + reg_rdata_next[9:0] = mio_pad_attr_1_qs; end addr_hit[164]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_2_qs; + reg_rdata_next[9:0] = mio_pad_attr_2_qs; end addr_hit[165]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_3_qs; + reg_rdata_next[9:0] = mio_pad_attr_3_qs; end addr_hit[166]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_4_qs; + reg_rdata_next[9:0] = mio_pad_attr_4_qs; end addr_hit[167]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_5_qs; + reg_rdata_next[9:0] = mio_pad_attr_5_qs; end addr_hit[168]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_6_qs; + reg_rdata_next[9:0] = mio_pad_attr_6_qs; end addr_hit[169]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_7_qs; + reg_rdata_next[9:0] = mio_pad_attr_7_qs; end addr_hit[170]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_8_qs; + reg_rdata_next[9:0] = mio_pad_attr_8_qs; end addr_hit[171]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_9_qs; + reg_rdata_next[9:0] = mio_pad_attr_9_qs; end addr_hit[172]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_10_qs; + reg_rdata_next[9:0] = mio_pad_attr_10_qs; end addr_hit[173]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_11_qs; + reg_rdata_next[9:0] = mio_pad_attr_11_qs; end addr_hit[174]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_12_qs; + reg_rdata_next[9:0] = mio_pad_attr_12_qs; end addr_hit[175]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_13_qs; + reg_rdata_next[9:0] = mio_pad_attr_13_qs; end addr_hit[176]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_14_qs; + reg_rdata_next[9:0] = mio_pad_attr_14_qs; end addr_hit[177]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_15_qs; + reg_rdata_next[9:0] = mio_pad_attr_15_qs; end addr_hit[178]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_16_qs; + reg_rdata_next[9:0] = mio_pad_attr_16_qs; end addr_hit[179]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_17_qs; + reg_rdata_next[9:0] = mio_pad_attr_17_qs; end addr_hit[180]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_18_qs; + reg_rdata_next[9:0] = mio_pad_attr_18_qs; end addr_hit[181]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_19_qs; + reg_rdata_next[9:0] = mio_pad_attr_19_qs; end addr_hit[182]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_20_qs; + reg_rdata_next[9:0] = mio_pad_attr_20_qs; end addr_hit[183]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_21_qs; + reg_rdata_next[9:0] = mio_pad_attr_21_qs; end addr_hit[184]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_22_qs; + reg_rdata_next[9:0] = mio_pad_attr_22_qs; end addr_hit[185]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_23_qs; + reg_rdata_next[9:0] = mio_pad_attr_23_qs; end addr_hit[186]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_24_qs; + reg_rdata_next[9:0] = mio_pad_attr_24_qs; end addr_hit[187]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_25_qs; + reg_rdata_next[9:0] = mio_pad_attr_25_qs; end addr_hit[188]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_26_qs; + reg_rdata_next[9:0] = mio_pad_attr_26_qs; end addr_hit[189]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_27_qs; + reg_rdata_next[9:0] = mio_pad_attr_27_qs; end addr_hit[190]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_28_qs; + reg_rdata_next[9:0] = mio_pad_attr_28_qs; end addr_hit[191]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_29_qs; + reg_rdata_next[9:0] = mio_pad_attr_29_qs; end addr_hit[192]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_30_qs; + reg_rdata_next[9:0] = mio_pad_attr_30_qs; end addr_hit[193]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_31_qs; + reg_rdata_next[9:0] = mio_pad_attr_31_qs; end addr_hit[194]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_0_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_0_qs; end addr_hit[195]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_1_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_1_qs; end addr_hit[196]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_2_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_2_qs; end addr_hit[197]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_3_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_3_qs; end addr_hit[198]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_4_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_4_qs; end addr_hit[199]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_5_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_5_qs; end addr_hit[200]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_6_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_6_qs; end addr_hit[201]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_7_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_7_qs; end addr_hit[202]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_8_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_8_qs; end addr_hit[203]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_9_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_9_qs; end addr_hit[204]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_10_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_10_qs; end addr_hit[205]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_11_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_11_qs; end addr_hit[206]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_12_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_12_qs; end addr_hit[207]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_13_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_13_qs; end addr_hit[208]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_14_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_14_qs; end addr_hit[209]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_15_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_15_qs; end addr_hit[210]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_0_qs; + reg_rdata_next[9:0] = dio_pad_attr_0_qs; end addr_hit[211]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_1_qs; + reg_rdata_next[9:0] = dio_pad_attr_1_qs; end addr_hit[212]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_2_qs; + reg_rdata_next[9:0] = dio_pad_attr_2_qs; end addr_hit[213]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_3_qs; + reg_rdata_next[9:0] = dio_pad_attr_3_qs; end addr_hit[214]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_4_qs; + reg_rdata_next[9:0] = dio_pad_attr_4_qs; end addr_hit[215]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_5_qs; + reg_rdata_next[9:0] = dio_pad_attr_5_qs; end addr_hit[216]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_6_qs; + reg_rdata_next[9:0] = dio_pad_attr_6_qs; end addr_hit[217]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_7_qs; + reg_rdata_next[9:0] = dio_pad_attr_7_qs; end addr_hit[218]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_8_qs; + reg_rdata_next[9:0] = dio_pad_attr_8_qs; end addr_hit[219]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_9_qs; + reg_rdata_next[9:0] = dio_pad_attr_9_qs; end addr_hit[220]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_10_qs; + reg_rdata_next[9:0] = dio_pad_attr_10_qs; end addr_hit[221]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_11_qs; + reg_rdata_next[9:0] = dio_pad_attr_11_qs; end addr_hit[222]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_12_qs; + reg_rdata_next[9:0] = dio_pad_attr_12_qs; end addr_hit[223]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_13_qs; + reg_rdata_next[9:0] = dio_pad_attr_13_qs; end addr_hit[224]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_14_qs; + reg_rdata_next[9:0] = dio_pad_attr_14_qs; end addr_hit[225]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_15_qs; + reg_rdata_next[9:0] = dio_pad_attr_15_qs; end addr_hit[226]: begin - reg_rdata_next[0] = wkup_detector_regwen_0_qs; + reg_rdata_next[0] = mio_pad_sleep_status_en_0_qs; + reg_rdata_next[1] = mio_pad_sleep_status_en_1_qs; + reg_rdata_next[2] = mio_pad_sleep_status_en_2_qs; + reg_rdata_next[3] = mio_pad_sleep_status_en_3_qs; + reg_rdata_next[4] = mio_pad_sleep_status_en_4_qs; + reg_rdata_next[5] = mio_pad_sleep_status_en_5_qs; + reg_rdata_next[6] = mio_pad_sleep_status_en_6_qs; + reg_rdata_next[7] = mio_pad_sleep_status_en_7_qs; + reg_rdata_next[8] = mio_pad_sleep_status_en_8_qs; + reg_rdata_next[9] = mio_pad_sleep_status_en_9_qs; + reg_rdata_next[10] = mio_pad_sleep_status_en_10_qs; + reg_rdata_next[11] = mio_pad_sleep_status_en_11_qs; + reg_rdata_next[12] = mio_pad_sleep_status_en_12_qs; + reg_rdata_next[13] = mio_pad_sleep_status_en_13_qs; + reg_rdata_next[14] = mio_pad_sleep_status_en_14_qs; + reg_rdata_next[15] = mio_pad_sleep_status_en_15_qs; + reg_rdata_next[16] = mio_pad_sleep_status_en_16_qs; + reg_rdata_next[17] = mio_pad_sleep_status_en_17_qs; + reg_rdata_next[18] = mio_pad_sleep_status_en_18_qs; + reg_rdata_next[19] = mio_pad_sleep_status_en_19_qs; + reg_rdata_next[20] = mio_pad_sleep_status_en_20_qs; + reg_rdata_next[21] = mio_pad_sleep_status_en_21_qs; + reg_rdata_next[22] = mio_pad_sleep_status_en_22_qs; + reg_rdata_next[23] = mio_pad_sleep_status_en_23_qs; + reg_rdata_next[24] = mio_pad_sleep_status_en_24_qs; + reg_rdata_next[25] = mio_pad_sleep_status_en_25_qs; + reg_rdata_next[26] = mio_pad_sleep_status_en_26_qs; + reg_rdata_next[27] = mio_pad_sleep_status_en_27_qs; + reg_rdata_next[28] = mio_pad_sleep_status_en_28_qs; + reg_rdata_next[29] = mio_pad_sleep_status_en_29_qs; + reg_rdata_next[30] = mio_pad_sleep_status_en_30_qs; + reg_rdata_next[31] = mio_pad_sleep_status_en_31_qs; end addr_hit[227]: begin - reg_rdata_next[0] = wkup_detector_regwen_1_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_0_qs; end addr_hit[228]: begin - reg_rdata_next[0] = wkup_detector_regwen_2_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_1_qs; end addr_hit[229]: begin - reg_rdata_next[0] = wkup_detector_regwen_3_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_2_qs; end addr_hit[230]: begin - reg_rdata_next[0] = wkup_detector_regwen_4_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_3_qs; end addr_hit[231]: begin - reg_rdata_next[0] = wkup_detector_regwen_5_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_4_qs; end addr_hit[232]: begin - reg_rdata_next[0] = wkup_detector_regwen_6_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_5_qs; end addr_hit[233]: begin - reg_rdata_next[0] = wkup_detector_regwen_7_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_6_qs; end addr_hit[234]: begin - reg_rdata_next[0] = wkup_detector_en_0_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_7_qs; end addr_hit[235]: begin - reg_rdata_next[0] = wkup_detector_en_1_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_8_qs; end addr_hit[236]: begin - reg_rdata_next[0] = wkup_detector_en_2_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_9_qs; end addr_hit[237]: begin - reg_rdata_next[0] = wkup_detector_en_3_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_10_qs; end addr_hit[238]: begin - reg_rdata_next[0] = wkup_detector_en_4_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_11_qs; end addr_hit[239]: begin - reg_rdata_next[0] = wkup_detector_en_5_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_12_qs; end addr_hit[240]: begin - reg_rdata_next[0] = wkup_detector_en_6_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_13_qs; end addr_hit[241]: begin - reg_rdata_next[0] = wkup_detector_en_7_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_14_qs; end addr_hit[242]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_15_qs; + end + + addr_hit[243]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_16_qs; + end + + addr_hit[244]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_17_qs; + end + + addr_hit[245]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_18_qs; + end + + addr_hit[246]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_19_qs; + end + + addr_hit[247]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_20_qs; + end + + addr_hit[248]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_21_qs; + end + + addr_hit[249]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_22_qs; + end + + addr_hit[250]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_23_qs; + end + + addr_hit[251]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_24_qs; + end + + addr_hit[252]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_25_qs; + end + + addr_hit[253]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_26_qs; + end + + addr_hit[254]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_27_qs; + end + + addr_hit[255]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_28_qs; + end + + addr_hit[256]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_29_qs; + end + + addr_hit[257]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_30_qs; + end + + addr_hit[258]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_31_qs; + end + + addr_hit[259]: begin + reg_rdata_next[0] = mio_pad_sleep_en_0_qs; + end + + addr_hit[260]: begin + reg_rdata_next[0] = mio_pad_sleep_en_1_qs; + end + + addr_hit[261]: begin + reg_rdata_next[0] = mio_pad_sleep_en_2_qs; + end + + addr_hit[262]: begin + reg_rdata_next[0] = mio_pad_sleep_en_3_qs; + end + + addr_hit[263]: begin + reg_rdata_next[0] = mio_pad_sleep_en_4_qs; + end + + addr_hit[264]: begin + reg_rdata_next[0] = mio_pad_sleep_en_5_qs; + end + + addr_hit[265]: begin + reg_rdata_next[0] = mio_pad_sleep_en_6_qs; + end + + addr_hit[266]: begin + reg_rdata_next[0] = mio_pad_sleep_en_7_qs; + end + + addr_hit[267]: begin + reg_rdata_next[0] = mio_pad_sleep_en_8_qs; + end + + addr_hit[268]: begin + reg_rdata_next[0] = mio_pad_sleep_en_9_qs; + end + + addr_hit[269]: begin + reg_rdata_next[0] = mio_pad_sleep_en_10_qs; + end + + addr_hit[270]: begin + reg_rdata_next[0] = mio_pad_sleep_en_11_qs; + end + + addr_hit[271]: begin + reg_rdata_next[0] = mio_pad_sleep_en_12_qs; + end + + addr_hit[272]: begin + reg_rdata_next[0] = mio_pad_sleep_en_13_qs; + end + + addr_hit[273]: begin + reg_rdata_next[0] = mio_pad_sleep_en_14_qs; + end + + addr_hit[274]: begin + reg_rdata_next[0] = mio_pad_sleep_en_15_qs; + end + + addr_hit[275]: begin + reg_rdata_next[0] = mio_pad_sleep_en_16_qs; + end + + addr_hit[276]: begin + reg_rdata_next[0] = mio_pad_sleep_en_17_qs; + end + + addr_hit[277]: begin + reg_rdata_next[0] = mio_pad_sleep_en_18_qs; + end + + addr_hit[278]: begin + reg_rdata_next[0] = mio_pad_sleep_en_19_qs; + end + + addr_hit[279]: begin + reg_rdata_next[0] = mio_pad_sleep_en_20_qs; + end + + addr_hit[280]: begin + reg_rdata_next[0] = mio_pad_sleep_en_21_qs; + end + + addr_hit[281]: begin + reg_rdata_next[0] = mio_pad_sleep_en_22_qs; + end + + addr_hit[282]: begin + reg_rdata_next[0] = mio_pad_sleep_en_23_qs; + end + + addr_hit[283]: begin + reg_rdata_next[0] = mio_pad_sleep_en_24_qs; + end + + addr_hit[284]: begin + reg_rdata_next[0] = mio_pad_sleep_en_25_qs; + end + + addr_hit[285]: begin + reg_rdata_next[0] = mio_pad_sleep_en_26_qs; + end + + addr_hit[286]: begin + reg_rdata_next[0] = mio_pad_sleep_en_27_qs; + end + + addr_hit[287]: begin + reg_rdata_next[0] = mio_pad_sleep_en_28_qs; + end + + addr_hit[288]: begin + reg_rdata_next[0] = mio_pad_sleep_en_29_qs; + end + + addr_hit[289]: begin + reg_rdata_next[0] = mio_pad_sleep_en_30_qs; + end + + addr_hit[290]: begin + reg_rdata_next[0] = mio_pad_sleep_en_31_qs; + end + + addr_hit[291]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_0_qs; + end + + addr_hit[292]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_1_qs; + end + + addr_hit[293]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_2_qs; + end + + addr_hit[294]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_3_qs; + end + + addr_hit[295]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_4_qs; + end + + addr_hit[296]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_5_qs; + end + + addr_hit[297]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_6_qs; + end + + addr_hit[298]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_7_qs; + end + + addr_hit[299]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_8_qs; + end + + addr_hit[300]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_9_qs; + end + + addr_hit[301]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_10_qs; + end + + addr_hit[302]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_11_qs; + end + + addr_hit[303]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_12_qs; + end + + addr_hit[304]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_13_qs; + end + + addr_hit[305]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_14_qs; + end + + addr_hit[306]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_15_qs; + end + + addr_hit[307]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_16_qs; + end + + addr_hit[308]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_17_qs; + end + + addr_hit[309]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_18_qs; + end + + addr_hit[310]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_19_qs; + end + + addr_hit[311]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_20_qs; + end + + addr_hit[312]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_21_qs; + end + + addr_hit[313]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_22_qs; + end + + addr_hit[314]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_23_qs; + end + + addr_hit[315]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_24_qs; + end + + addr_hit[316]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_25_qs; + end + + addr_hit[317]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_26_qs; + end + + addr_hit[318]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_27_qs; + end + + addr_hit[319]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_28_qs; + end + + addr_hit[320]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_29_qs; + end + + addr_hit[321]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_30_qs; + end + + addr_hit[322]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_31_qs; + end + + addr_hit[323]: begin + reg_rdata_next[0] = dio_pad_sleep_status_en_0_qs; + reg_rdata_next[1] = dio_pad_sleep_status_en_1_qs; + reg_rdata_next[2] = dio_pad_sleep_status_en_2_qs; + reg_rdata_next[3] = dio_pad_sleep_status_en_3_qs; + reg_rdata_next[4] = dio_pad_sleep_status_en_4_qs; + reg_rdata_next[5] = dio_pad_sleep_status_en_5_qs; + reg_rdata_next[6] = dio_pad_sleep_status_en_6_qs; + reg_rdata_next[7] = dio_pad_sleep_status_en_7_qs; + reg_rdata_next[8] = dio_pad_sleep_status_en_8_qs; + reg_rdata_next[9] = dio_pad_sleep_status_en_9_qs; + reg_rdata_next[10] = dio_pad_sleep_status_en_10_qs; + reg_rdata_next[11] = dio_pad_sleep_status_en_11_qs; + reg_rdata_next[12] = dio_pad_sleep_status_en_12_qs; + reg_rdata_next[13] = dio_pad_sleep_status_en_13_qs; + reg_rdata_next[14] = dio_pad_sleep_status_en_14_qs; + reg_rdata_next[15] = dio_pad_sleep_status_en_15_qs; + end + + addr_hit[324]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_0_qs; + end + + addr_hit[325]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_1_qs; + end + + addr_hit[326]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_2_qs; + end + + addr_hit[327]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_3_qs; + end + + addr_hit[328]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_4_qs; + end + + addr_hit[329]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_5_qs; + end + + addr_hit[330]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_6_qs; + end + + addr_hit[331]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_7_qs; + end + + addr_hit[332]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_8_qs; + end + + addr_hit[333]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_9_qs; + end + + addr_hit[334]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_10_qs; + end + + addr_hit[335]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_11_qs; + end + + addr_hit[336]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_12_qs; + end + + addr_hit[337]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_13_qs; + end + + addr_hit[338]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_14_qs; + end + + addr_hit[339]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_15_qs; + end + + addr_hit[340]: begin + reg_rdata_next[0] = dio_pad_sleep_en_0_qs; + end + + addr_hit[341]: begin + reg_rdata_next[0] = dio_pad_sleep_en_1_qs; + end + + addr_hit[342]: begin + reg_rdata_next[0] = dio_pad_sleep_en_2_qs; + end + + addr_hit[343]: begin + reg_rdata_next[0] = dio_pad_sleep_en_3_qs; + end + + addr_hit[344]: begin + reg_rdata_next[0] = dio_pad_sleep_en_4_qs; + end + + addr_hit[345]: begin + reg_rdata_next[0] = dio_pad_sleep_en_5_qs; + end + + addr_hit[346]: begin + reg_rdata_next[0] = dio_pad_sleep_en_6_qs; + end + + addr_hit[347]: begin + reg_rdata_next[0] = dio_pad_sleep_en_7_qs; + end + + addr_hit[348]: begin + reg_rdata_next[0] = dio_pad_sleep_en_8_qs; + end + + addr_hit[349]: begin + reg_rdata_next[0] = dio_pad_sleep_en_9_qs; + end + + addr_hit[350]: begin + reg_rdata_next[0] = dio_pad_sleep_en_10_qs; + end + + addr_hit[351]: begin + reg_rdata_next[0] = dio_pad_sleep_en_11_qs; + end + + addr_hit[352]: begin + reg_rdata_next[0] = dio_pad_sleep_en_12_qs; + end + + addr_hit[353]: begin + reg_rdata_next[0] = dio_pad_sleep_en_13_qs; + end + + addr_hit[354]: begin + reg_rdata_next[0] = dio_pad_sleep_en_14_qs; + end + + addr_hit[355]: begin + reg_rdata_next[0] = dio_pad_sleep_en_15_qs; + end + + addr_hit[356]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_0_qs; + end + + addr_hit[357]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_1_qs; + end + + addr_hit[358]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_2_qs; + end + + addr_hit[359]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_3_qs; + end + + addr_hit[360]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_4_qs; + end + + addr_hit[361]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_5_qs; + end + + addr_hit[362]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_6_qs; + end + + addr_hit[363]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_7_qs; + end + + addr_hit[364]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_8_qs; + end + + addr_hit[365]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_9_qs; + end + + addr_hit[366]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_10_qs; + end + + addr_hit[367]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_11_qs; + end + + addr_hit[368]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_12_qs; + end + + addr_hit[369]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_13_qs; + end + + addr_hit[370]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_14_qs; + end + + addr_hit[371]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_15_qs; + end + + addr_hit[372]: begin + reg_rdata_next[0] = wkup_detector_regwen_0_qs; + end + + addr_hit[373]: begin + reg_rdata_next[0] = wkup_detector_regwen_1_qs; + end + + addr_hit[374]: begin + reg_rdata_next[0] = wkup_detector_regwen_2_qs; + end + + addr_hit[375]: begin + reg_rdata_next[0] = wkup_detector_regwen_3_qs; + end + + addr_hit[376]: begin + reg_rdata_next[0] = wkup_detector_regwen_4_qs; + end + + addr_hit[377]: begin + reg_rdata_next[0] = wkup_detector_regwen_5_qs; + end + + addr_hit[378]: begin + reg_rdata_next[0] = wkup_detector_regwen_6_qs; + end + + addr_hit[379]: begin + reg_rdata_next[0] = wkup_detector_regwen_7_qs; + end + + addr_hit[380]: begin + reg_rdata_next[0] = wkup_detector_en_0_qs; + end + + addr_hit[381]: begin + reg_rdata_next[0] = wkup_detector_en_1_qs; + end + + addr_hit[382]: begin + reg_rdata_next[0] = wkup_detector_en_2_qs; + end + + addr_hit[383]: begin + reg_rdata_next[0] = wkup_detector_en_3_qs; + end + + addr_hit[384]: begin + reg_rdata_next[0] = wkup_detector_en_4_qs; + end + + addr_hit[385]: begin + reg_rdata_next[0] = wkup_detector_en_5_qs; + end + + addr_hit[386]: begin + reg_rdata_next[0] = wkup_detector_en_6_qs; + end + + addr_hit[387]: begin + reg_rdata_next[0] = wkup_detector_en_7_qs; + end + + addr_hit[388]: begin reg_rdata_next[2:0] = wkup_detector_0_mode_0_qs; reg_rdata_next[3] = wkup_detector_0_filter_0_qs; reg_rdata_next[4] = wkup_detector_0_miodio_0_qs; end - addr_hit[243]: begin + addr_hit[389]: begin reg_rdata_next[2:0] = wkup_detector_1_mode_1_qs; reg_rdata_next[3] = wkup_detector_1_filter_1_qs; reg_rdata_next[4] = wkup_detector_1_miodio_1_qs; end - addr_hit[244]: begin + addr_hit[390]: begin reg_rdata_next[2:0] = wkup_detector_2_mode_2_qs; reg_rdata_next[3] = wkup_detector_2_filter_2_qs; reg_rdata_next[4] = wkup_detector_2_miodio_2_qs; end - addr_hit[245]: begin + addr_hit[391]: begin reg_rdata_next[2:0] = wkup_detector_3_mode_3_qs; reg_rdata_next[3] = wkup_detector_3_filter_3_qs; reg_rdata_next[4] = wkup_detector_3_miodio_3_qs; end - addr_hit[246]: begin + addr_hit[392]: begin reg_rdata_next[2:0] = wkup_detector_4_mode_4_qs; reg_rdata_next[3] = wkup_detector_4_filter_4_qs; reg_rdata_next[4] = wkup_detector_4_miodio_4_qs; end - addr_hit[247]: begin + addr_hit[393]: begin reg_rdata_next[2:0] = wkup_detector_5_mode_5_qs; reg_rdata_next[3] = wkup_detector_5_filter_5_qs; reg_rdata_next[4] = wkup_detector_5_miodio_5_qs; end - addr_hit[248]: begin + addr_hit[394]: begin reg_rdata_next[2:0] = wkup_detector_6_mode_6_qs; reg_rdata_next[3] = wkup_detector_6_filter_6_qs; reg_rdata_next[4] = wkup_detector_6_miodio_6_qs; end - addr_hit[249]: begin + addr_hit[395]: begin reg_rdata_next[2:0] = wkup_detector_7_mode_7_qs; reg_rdata_next[3] = wkup_detector_7_filter_7_qs; reg_rdata_next[4] = wkup_detector_7_miodio_7_qs; end - addr_hit[250]: begin + addr_hit[396]: begin reg_rdata_next[7:0] = wkup_detector_cnt_th_0_qs; end - addr_hit[251]: begin + addr_hit[397]: begin reg_rdata_next[7:0] = wkup_detector_cnt_th_1_qs; end - addr_hit[252]: begin + addr_hit[398]: begin reg_rdata_next[7:0] = wkup_detector_cnt_th_2_qs; end - addr_hit[253]: begin + addr_hit[399]: begin reg_rdata_next[7:0] = wkup_detector_cnt_th_3_qs; end - addr_hit[254]: begin + addr_hit[400]: begin reg_rdata_next[7:0] = wkup_detector_cnt_th_4_qs; end - addr_hit[255]: begin + addr_hit[401]: begin reg_rdata_next[7:0] = wkup_detector_cnt_th_5_qs; end - addr_hit[256]: begin + addr_hit[402]: begin reg_rdata_next[7:0] = wkup_detector_cnt_th_6_qs; end - addr_hit[257]: begin + addr_hit[403]: begin reg_rdata_next[7:0] = wkup_detector_cnt_th_7_qs; end - addr_hit[258]: begin + addr_hit[404]: begin reg_rdata_next[5:0] = wkup_detector_padsel_0_qs; end - addr_hit[259]: begin + addr_hit[405]: begin reg_rdata_next[5:0] = wkup_detector_padsel_1_qs; end - addr_hit[260]: begin + addr_hit[406]: begin reg_rdata_next[5:0] = wkup_detector_padsel_2_qs; end - addr_hit[261]: begin + addr_hit[407]: begin reg_rdata_next[5:0] = wkup_detector_padsel_3_qs; end - addr_hit[262]: begin + addr_hit[408]: begin reg_rdata_next[5:0] = wkup_detector_padsel_4_qs; end - addr_hit[263]: begin + addr_hit[409]: begin reg_rdata_next[5:0] = wkup_detector_padsel_5_qs; end - addr_hit[264]: begin + addr_hit[410]: begin reg_rdata_next[5:0] = wkup_detector_padsel_6_qs; end - addr_hit[265]: begin + addr_hit[411]: begin reg_rdata_next[5:0] = wkup_detector_padsel_7_qs; end - addr_hit[266]: begin + addr_hit[412]: begin reg_rdata_next[0] = wkup_cause_cause_0_qs; reg_rdata_next[1] = wkup_cause_cause_1_qs; reg_rdata_next[2] = wkup_cause_cause_2_qs;
diff --git a/hw/ip/pinmux/util/reg_pinmux.py b/hw/ip/pinmux/util/reg_pinmux.py index c732e6f..9493058 100755 --- a/hw/ip/pinmux/util/reg_pinmux.py +++ b/hw/ip/pinmux/util/reg_pinmux.py
@@ -51,6 +51,11 @@ type=int, help='With of wakeup counters', default=8) + parser.add_argument('--attr_dw', + type=int, + help='Pad attribute data width', + default = 10) + args = parser.parse_args() @@ -67,6 +72,7 @@ n_dio_pads=args.n_dio_pads, n_wkup_detect=args.n_wkup_detect, wkup_cnt_width=args.wkup_cnt_width, + attr_dw=args.attr_dw, usb_start_pos=0, n_usb_pins=0, usb_dp_sel=0,
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index d6c99a8..e8916e8 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -4482,56 +4482,6 @@ ] } { - name: padctrl_aon - type: padctrl - clock: main - clock_srcs: - { - clk_i: io_div4 - } - clock_group: secure - reset_connections: - { - rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel] - } - domain: Aon - base_addr: 0x40470000 - generated: "true" - clock_connections: - { - clk_i: clkmgr_aon_clocks.clk_io_div4_secure - } - size: 0x1000 - bus_device: tlul - bus_host: none - available_input_list: [] - available_output_list: [] - available_inout_list: [] - param_list: [] - interrupt_list: [] - alert_list: [] - wakeup_list: [] - reset_request_list: [] - scan: "false" - scan_reset: "false" - inter_signal_list: - [ - { - struct: tl - package: tlul_pkg - type: req_rsp - act: rsp - name: tl - inst_name: padctrl_aon - width: 1 - default: "" - end_idx: -1 - top_signame: padctrl_aon_tl - index: -1 - } - ] - } - { name: sensor_ctrl_aon type: sensor_ctrl clock_srcs: @@ -7526,10 +7476,6 @@ [ peri.tl_pinmux_aon ] - padctrl_aon.tl: - [ - peri.tl_padctrl_aon - ] ram_ret_aon.tl: [ peri.tl_ram_ret_aon @@ -8294,7 +8240,6 @@ rstmgr_aon clkmgr_aon pinmux_aon - padctrl_aon ram_ret_aon otp_ctrl lc_ctrl @@ -8607,24 +8552,6 @@ pipeline_byp: "true" } { - name: padctrl_aon - type: device - clock: clk_peri_i - reset: rst_peri_ni - pipeline: "false" - inst_type: padctrl - addr_range: - [ - { - base_addr: 0x40470000 - size_byte: 0x1000 - } - ] - xbar: false - stub: false - pipeline_byp: "true" - } - { name: ram_ret_aon type: device clock: clk_peri_i @@ -8979,18 +8906,6 @@ { struct: tl type: req_rsp - name: tl_padctrl_aon - act: req - package: tlul_pkg - inst_name: peri - width: 1 - default: "" - top_signame: padctrl_aon_tl - index: -1 - } - { - struct: tl - type: req_rsp name: tl_ram_ret_aon act: req package: tlul_pkg @@ -13280,19 +13195,6 @@ index: -1 } { - struct: tl - package: tlul_pkg - type: req_rsp - act: rsp - name: tl - inst_name: padctrl_aon - width: 1 - default: "" - end_idx: -1 - top_signame: padctrl_aon_tl - index: -1 - } - { struct: ast_alert type: req_rsp name: ast_alert @@ -14701,18 +14603,6 @@ { struct: tl type: req_rsp - name: tl_padctrl_aon - act: req - package: tlul_pkg - inst_name: peri - width: 1 - default: "" - top_signame: padctrl_aon_tl - index: -1 - } - { - struct: tl - type: req_rsp name: tl_ram_ret_aon act: req package: tlul_pkg @@ -16638,28 +16528,6 @@ { package: tlul_pkg struct: tl_h2d - signame: padctrl_aon_tl_req - width: 1 - type: req_rsp - end_idx: -1 - act: rsp - suffix: req - default: "" - } - { - package: tlul_pkg - struct: tl_d2h - signame: padctrl_aon_tl_rsp - width: 1 - type: req_rsp - end_idx: -1 - act: rsp - suffix: rsp - default: "" - } - { - package: tlul_pkg - struct: tl_h2d signame: ram_ret_aon_tl_req width: 1 type: req_rsp
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index 012cc96..5e2e5a2 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -387,8 +387,6 @@ base_addr: "0x40420000", generated: "true" }, - // pinmux is currently allocated to main fabric, - // however this should probably be moved to peri fabric { name: "pinmux_aon", type: "pinmux", clock: "main", @@ -399,17 +397,6 @@ base_addr: "0x40460000", generated: "true" }, - // see comment regarding pinmux above - { name: "padctrl_aon", - type: "padctrl", - clock: "main", - clock_srcs: {clk_i: "io_div4"}, - clock_group: "secure", - reset_connections: {rst_ni: "sys_io_div4"}, - domain: "Aon", - base_addr: "0x40470000", - generated: "true" - }, { name: "sensor_ctrl_aon", type: "sensor_ctrl", clock_srcs: {clk_i: "io_div4"}, @@ -852,7 +839,7 @@ alert: [ ] - // TODO: PINMUX + // TODO: need to overhaul this datastructure. pinmux: { // Total number of Multiplexed I/O @@ -904,6 +891,7 @@ // ] } + // TODO: need to overhaul this datastructure. // PADS instantiation // Number of in/outs and the numer of PAD instances doesn't have to be // same. The number given below excludes clock/reset and other necessary
diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl index c13b417..ec494a0 100644 --- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl +++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -72,12 +72,12 @@ output logic ${lib.bitarray(num_dio, max_sigwidth)} dio_oe_o, % endif -% if "padctrl" in top: +% if "pinmux" in top: // pad attributes to padring - output logic[padctrl_reg_pkg::NMioPads-1:0] - [padctrl_reg_pkg::AttrDw-1:0] mio_attr_o, - output logic[padctrl_reg_pkg::NDioPads-1:0] - [padctrl_reg_pkg::AttrDw-1:0] dio_attr_o, + output logic[pinmux_reg_pkg::NMioPads-1:0] + [pinmux_reg_pkg::AttrDw-1:0] mio_attr_o, + output logic[pinmux_reg_pkg::NDioPads-1:0] + [pinmux_reg_pkg::AttrDw-1:0] dio_attr_o, % endif % if num_im != 0: @@ -635,6 +635,7 @@ .periph_to_mio_oe_i (mio_d2p_en ), .mio_to_periph_o (mio_p2d ), + .mio_attr_o, .mio_out_o, .mio_oe_o, .mio_in_i, @@ -643,14 +644,11 @@ .periph_to_dio_oe_i (dio_d2p_en ), .dio_to_periph_o (dio_p2d ), + .dio_attr_o, .dio_out_o, .dio_oe_o, .dio_in_i, - % endif - % if m["type"] == "padctrl": - .mio_attr_o, - .dio_attr_o, % endif % if m["type"] == "alert_handler": // alert signals
diff --git a/hw/top_earlgrey/data/xbar_peri.hjson b/hw/top_earlgrey/data/xbar_peri.hjson index ea4b0cd..ee57b0e 100644 --- a/hw/top_earlgrey/data/xbar_peri.hjson +++ b/hw/top_earlgrey/data/xbar_peri.hjson
@@ -111,12 +111,6 @@ reset: "rst_peri_ni", pipeline: "false" }, - { name: "padctrl_aon", - type: "device", - clock: "clk_peri_i", - reset: "rst_peri_ni", - pipeline: "false" - }, { name: "ram_ret_aon", type: "device", clock: "clk_peri_i", @@ -179,7 +173,7 @@ connections: { main: ["uart0", "uart1", "uart2", "uart3", "i2c0", "i2c1", "i2c2", "pattgen", "gpio", "spi_device", "rv_timer", "usbdev", "pwrmgr_aon", "rstmgr_aon", "clkmgr_aon", - "pinmux_aon", "padctrl_aon", "ram_ret_aon", "otp_ctrl", "lc_ctrl", "sensor_ctrl_aon", + "pinmux_aon", "ram_ret_aon", "otp_ctrl", "lc_ctrl", "sensor_ctrl_aon", "alert_handler", "nmi_gen", "ast_wrapper", "sram_ctrl_ret_aon"], }, }
diff --git a/hw/top_earlgrey/doc/_index.md b/hw/top_earlgrey/doc/_index.md index 5ad950d..c9420c7 100644 --- a/hw/top_earlgrey/doc/_index.md +++ b/hw/top_earlgrey/doc/_index.md
@@ -246,6 +246,8 @@ ##### Pin Multiplexor (`pinmux`) and Pad Control (`padctrl`) +**TODO: this section needs to be updated to reflect the pinmux/padctrl merger** + The pin multiplexor's purpose is to route between peripherals and the available multiplexable IO (`MIO_00 .. MIO_31`) of the chip. At this time, the pin multiplexor is provided, but it is not used to its full potential. In addition, the `padctrl` device manages control or pad attributes like drive strength, technology (OD, OS, etc), pull up, pull down, etc., of the chip's external IO. @@ -255,8 +257,7 @@ Their effect, however, over things like drive strength and Open Drain technology are highly platform-dependent, and are not finalized at this time. Both `pinmux` and `padctrl` are themselves peripherals on the TLUL bus, with collections of registers that provide software configurability. -See the [pinmux specification]({{< relref "hw/ip/pinmux/doc" >}}) for how to connect peripheral IO to chip IO. -See the [padctrl specification]({{< relref "hw/ip/padctrl/doc" >}}) for information on pad control features available in the future. +See the [pinmux specification]({{< relref "hw/ip/pinmux/doc" >}}) for how to connect peripheral IO to chip IO and for information on pad control features. ##### UART
diff --git a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv index 7fcbc62..0b13a83 100644 --- a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
@@ -65,7 +65,6 @@ tl_if rstmgr_aon_tl_if(clk_io_div4, rst_n); tl_if clkmgr_aon_tl_if(clk_io_div4, rst_n); tl_if pinmux_aon_tl_if(clk_io_div4, rst_n); -tl_if padctrl_aon_tl_if(clk_io_div4, rst_n); tl_if ram_ret_aon_tl_if(clk_io_div4, rst_n); tl_if otp_ctrl_tl_if(clk_io_div4, rst_n); tl_if lc_ctrl_tl_if(clk_io_div4, rst_n); @@ -134,7 +133,6 @@ `DRIVE_CHIP_TL_DEVICE_IF(rstmgr_aon, rstmgr_aon, tl) `DRIVE_CHIP_TL_DEVICE_IF(clkmgr_aon, clkmgr_aon, tl) `DRIVE_CHIP_TL_DEVICE_IF(pinmux_aon, pinmux_aon, tl) - `DRIVE_CHIP_TL_DEVICE_IF(padctrl_aon, padctrl_aon, tl) `DRIVE_CHIP_TL_DEVICE_IF(ram_ret_aon, tl_adapter_ram_ret_aon, tl) `DRIVE_CHIP_TL_DEVICE_IF(otp_ctrl, otp_ctrl, tl) `DRIVE_CHIP_TL_DEVICE_IF(lc_ctrl, lc_ctrl, tl)
diff --git a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv index a5ae1c9..1e345d4 100644 --- a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
@@ -103,9 +103,6 @@ '{"pinmux_aon", '{ '{32'h40460000, 32'h40460fff} }}, - '{"padctrl_aon", '{ - '{32'h40470000, 32'h40470fff} - }}, '{"ram_ret_aon", '{ '{32'h40600000, 32'h40600fff} }}, @@ -160,7 +157,6 @@ "rstmgr_aon", "clkmgr_aon", "pinmux_aon", - "padctrl_aon", "ram_ret_aon", "otp_ctrl", "lc_ctrl", @@ -202,7 +198,6 @@ "rstmgr_aon", "clkmgr_aon", "pinmux_aon", - "padctrl_aon", "ram_ret_aon", "otp_ctrl", "lc_ctrl",
diff --git a/hw/top_earlgrey/dv/cov/chip_assert_cover.cfg b/hw/top_earlgrey/dv/cov/chip_assert_cover.cfg index ce307f9..3aadf02 100644 --- a/hw/top_earlgrey/dv/cov/chip_assert_cover.cfg +++ b/hw/top_earlgrey/dv/cov/chip_assert_cover.cfg
@@ -14,7 +14,6 @@ +tree tb.dut.top_earlgrey.u_clkmgr +tree tb.dut.top_earlgrey.u_nmi_gen -+tree tb.dut.top_earlgrey.u_padctrl +tree tb.dut.top_earlgrey.u_pinmux +tree tb.dut.top_earlgrey.u_pwrmgr +tree tb.dut.top_earlgrey.u_rstmgr
diff --git a/hw/top_earlgrey/dv/cov/chip_cover.cfg b/hw/top_earlgrey/dv/cov/chip_cover.cfg index 68dce60..abef508 100644 --- a/hw/top_earlgrey/dv/cov/chip_cover.cfg +++ b/hw/top_earlgrey/dv/cov/chip_cover.cfg
@@ -28,7 +28,6 @@ +moduletree clkmgr +moduletree nmi_gen - +moduletree padctrl +moduletree pinmux +moduletree pwrmgr +moduletree rstmgr
diff --git a/hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg b/hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg index b4db92c..99fce39 100644 --- a/hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg +++ b/hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg
@@ -6,7 +6,6 @@ -tree * +tree tb.dut.top_earlgrey.u_clkmgr.u_reg +tree tb.dut.top_earlgrey.u_nmi_gen.u_reg -+tree tb.dut.top_earlgrey.u_padctrl.u_reg +tree tb.dut.top_earlgrey.u_pinmux.u_reg +tree tb.dut.top_earlgrey.u_pwrmgr.u_reg +tree tb.dut.top_earlgrey.u_rstmgr.u_reg
diff --git a/hw/top_earlgrey/fpv/top_earlgrey_fpv_cfgs.hjson b/hw/top_earlgrey/fpv/top_earlgrey_fpv_cfgs.hjson index 4e71b2b..e61c2f4 100644 --- a/hw/top_earlgrey/fpv/top_earlgrey_fpv_cfgs.hjson +++ b/hw/top_earlgrey/fpv/top_earlgrey_fpv_cfgs.hjson
@@ -125,12 +125,6 @@ cov: true } { - name: padctrl_fpv - fusesoc_core: lowrisc:fpv:padctrl_fpv - import_cfgs: ["{proj_root}/hw/formal/tools/dvsim/common_fpv_cfg.hjson"] - cov: true - } - { name: pinmux_fpv fusesoc_core: lowrisc:fpv:pinmux_fpv import_cfgs: ["{proj_root}/hw/formal/tools/dvsim/common_fpv_cfg.hjson"]
diff --git a/hw/top_earlgrey/ip/padctrl/data/autogen/padctrl.hjson b/hw/top_earlgrey/ip/padctrl/data/autogen/padctrl.hjson deleted file mode 100644 index 6e6ed89..0000000 --- a/hw/top_earlgrey/ip/padctrl/data/autogen/padctrl.hjson +++ /dev/null
@@ -1,134 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// -// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: -// util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ - -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -# PADCTRL register template -# -# Parameter (given by Python tool) -# - n_dio_pads: Number of dedicated IO pads -# - n_mio_pads: Number of muxed IO pads -# - attr_dw: Attribute datawidth -{ - name: "PADCTRL", - clock_primary: "clk_i", - bus_device: "tlul", - regwidth: "32", - param_list: [ - { name: "NDioPads", - desc: "Number of dedicated IO pads", - type: "int", - default: "15", - local: "true" - }, - { name: "NMioPads", - desc: "Number of muxed IO pads", - type: "int", - default: "32", - local: "true" - }, - { name: "AttrDw", - desc: "Pad attribute data width", - type: "int", - default: "10", - local: "true" - }, - ], - registers: [ - { name: "REGWEN", - desc: ''' - Register write enable for all control registers. - ''', - swaccess: "rw0c", - hwaccess: "none", - fields: [ - { - bits: "0", - name: "wen", - desc: ''' When true, all configuration registers can be modified. - When false, they become read-only. Defaults true, write zero to clear. - ''' - resval: 1, - }, - ] - }, -# dedicated pads - { multireg: { name: "DIO_PADS", - desc: '''Dedicated pad attributes. - This register has WARL behavior as some attributes may not be implemented. - ''', - count: "NDioPads", - swaccess: "rw", - hwaccess: "hrw", - hwext: "true", - hwqe: "true", - regwen: "REGWEN", - cname: "ATTR", - fields: [ - { bits: "9:0", - name: "ATTR", - desc: '''Bit 0: input/output inversion, - Bit 1: Virtual open drain enable. - Bit 2: Pull enable. - Bit 3: Pull select (0: pull down, 1: pull up). - Bit 4: Keeper enable. - Bit 5: Schmitt trigger enable. - Bit 6: Slew rate (0: slow, 1: fast). - Bit 7/8: Drive strength (00: weakest, 11: strongest). - Bit 9: Reserved. - ''' - resval: 0 - } - ], - // these CSRs have WARL behavior and may not - // read back the same value that was written to them. - // further, they have hardware side effects since they drive the - // pad attributes, and hence no random data should be written to them. - tags: ["excl:CsrAllTests:CsrExclWrite"] - } - }, -# muxed pads - { multireg: { name: "MIO_PADS", - desc: '''Muxed pad attributes. - This register has WARL behavior as some attributes may not be implemented. - ''', - count: "NMioPads", - swaccess: "rw", - hwaccess: "hrw", - hwext: "true", - hwqe: "true", - regwen: "REGWEN", - cname: "ATTR", - fields: [ - { bits: "9:0", - name: "ATTR", - desc: '''Bit 0: input/output inversion, - Bit 1: Virtual open drain enable. - Bit 2: Pull enable. - Bit 3: Pull select (0: pull down, 1: pull up). - Bit 4: Keeper enable. - Bit 5: Schmitt trigger enable. - Bit 6: Slew rate (0: slow, 1: fast). - Bit 7/8: Drive strength (00: weakest, 11: strongest). - Bit 9: Reserved. - ''' - resval: 0 - } - ], - // these CSRs have WARL behavior and may not - // read back the same value that was written to them. - // further, they have hardware side effects since they drive the - // pad attributes, and hence no random data should be written to them. - tags: ["excl:CsrAllTests:CsrExclWrite"] - } - }, - ], -} -
diff --git a/hw/top_earlgrey/ip/padctrl/padctrl_reg.core b/hw/top_earlgrey/ip/padctrl/padctrl_reg.core deleted file mode 100644 index 5443b06..0000000 --- a/hw/top_earlgrey/ip/padctrl/padctrl_reg.core +++ /dev/null
@@ -1,21 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:top_earlgrey:padctrl_reg:0.1" -description: "Auto-generated padctrl register sources for top_earlgrey chip." -filesets: - files_rtl: - depend: - - lowrisc:tlul:headers - - files: - - rtl/autogen/padctrl_reg_pkg.sv - - rtl/autogen/padctrl_reg_top.sv - file_type: systemVerilogSource - - -targets: - default: &default_target - filesets: - - files_rtl
diff --git a/hw/top_earlgrey/ip/padctrl/rtl/autogen/padctrl_reg_pkg.sv b/hw/top_earlgrey/ip/padctrl/rtl/autogen/padctrl_reg_pkg.sv deleted file mode 100644 index 3099a8b..0000000 --- a/hw/top_earlgrey/ip/padctrl/rtl/autogen/padctrl_reg_pkg.sv +++ /dev/null
@@ -1,118 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Package auto-generated by `reggen` containing data structure - -package padctrl_reg_pkg; - - // Param list - parameter int NDioPads = 15; - parameter int NMioPads = 32; - parameter int AttrDw = 10; - - // Address width within the block - parameter int BlockAw = 7; - - //////////////////////////// - // Typedefs for registers // - //////////////////////////// - typedef struct packed { - logic [9:0] q; - logic qe; - } padctrl_reg2hw_dio_pads_mreg_t; - - typedef struct packed { - logic [9:0] q; - logic qe; - } padctrl_reg2hw_mio_pads_mreg_t; - - - typedef struct packed { - logic [9:0] d; - } padctrl_hw2reg_dio_pads_mreg_t; - - typedef struct packed { - logic [9:0] d; - } padctrl_hw2reg_mio_pads_mreg_t; - - - /////////////////////////////////////// - // Register to internal design logic // - /////////////////////////////////////// - typedef struct packed { - padctrl_reg2hw_dio_pads_mreg_t [14:0] dio_pads; // [516:352] - padctrl_reg2hw_mio_pads_mreg_t [31:0] mio_pads; // [351:0] - } padctrl_reg2hw_t; - - /////////////////////////////////////// - // Internal design logic to register // - /////////////////////////////////////// - typedef struct packed { - padctrl_hw2reg_dio_pads_mreg_t [14:0] dio_pads; // [469:320] - padctrl_hw2reg_mio_pads_mreg_t [31:0] mio_pads; // [319:0] - } padctrl_hw2reg_t; - - // Register Address - parameter logic [BlockAw-1:0] PADCTRL_REGWEN_OFFSET = 7'h 0; - parameter logic [BlockAw-1:0] PADCTRL_DIO_PADS_0_OFFSET = 7'h 4; - parameter logic [BlockAw-1:0] PADCTRL_DIO_PADS_1_OFFSET = 7'h 8; - parameter logic [BlockAw-1:0] PADCTRL_DIO_PADS_2_OFFSET = 7'h c; - parameter logic [BlockAw-1:0] PADCTRL_DIO_PADS_3_OFFSET = 7'h 10; - parameter logic [BlockAw-1:0] PADCTRL_DIO_PADS_4_OFFSET = 7'h 14; - parameter logic [BlockAw-1:0] PADCTRL_MIO_PADS_0_OFFSET = 7'h 18; - parameter logic [BlockAw-1:0] PADCTRL_MIO_PADS_1_OFFSET = 7'h 1c; - parameter logic [BlockAw-1:0] PADCTRL_MIO_PADS_2_OFFSET = 7'h 20; - parameter logic [BlockAw-1:0] PADCTRL_MIO_PADS_3_OFFSET = 7'h 24; - parameter logic [BlockAw-1:0] PADCTRL_MIO_PADS_4_OFFSET = 7'h 28; - parameter logic [BlockAw-1:0] PADCTRL_MIO_PADS_5_OFFSET = 7'h 2c; - parameter logic [BlockAw-1:0] PADCTRL_MIO_PADS_6_OFFSET = 7'h 30; - parameter logic [BlockAw-1:0] PADCTRL_MIO_PADS_7_OFFSET = 7'h 34; - parameter logic [BlockAw-1:0] PADCTRL_MIO_PADS_8_OFFSET = 7'h 38; - parameter logic [BlockAw-1:0] PADCTRL_MIO_PADS_9_OFFSET = 7'h 3c; - parameter logic [BlockAw-1:0] PADCTRL_MIO_PADS_10_OFFSET = 7'h 40; - - - // Register Index - typedef enum int { - PADCTRL_REGWEN, - PADCTRL_DIO_PADS_0, - PADCTRL_DIO_PADS_1, - PADCTRL_DIO_PADS_2, - PADCTRL_DIO_PADS_3, - PADCTRL_DIO_PADS_4, - PADCTRL_MIO_PADS_0, - PADCTRL_MIO_PADS_1, - PADCTRL_MIO_PADS_2, - PADCTRL_MIO_PADS_3, - PADCTRL_MIO_PADS_4, - PADCTRL_MIO_PADS_5, - PADCTRL_MIO_PADS_6, - PADCTRL_MIO_PADS_7, - PADCTRL_MIO_PADS_8, - PADCTRL_MIO_PADS_9, - PADCTRL_MIO_PADS_10 - } padctrl_id_e; - - // Register width information to check illegal writes - parameter logic [3:0] PADCTRL_PERMIT [17] = '{ - 4'b 0001, // index[ 0] PADCTRL_REGWEN - 4'b 1111, // index[ 1] PADCTRL_DIO_PADS_0 - 4'b 1111, // index[ 2] PADCTRL_DIO_PADS_1 - 4'b 1111, // index[ 3] PADCTRL_DIO_PADS_2 - 4'b 1111, // index[ 4] PADCTRL_DIO_PADS_3 - 4'b 1111, // index[ 5] PADCTRL_DIO_PADS_4 - 4'b 1111, // index[ 6] PADCTRL_MIO_PADS_0 - 4'b 1111, // index[ 7] PADCTRL_MIO_PADS_1 - 4'b 1111, // index[ 8] PADCTRL_MIO_PADS_2 - 4'b 1111, // index[ 9] PADCTRL_MIO_PADS_3 - 4'b 1111, // index[10] PADCTRL_MIO_PADS_4 - 4'b 1111, // index[11] PADCTRL_MIO_PADS_5 - 4'b 1111, // index[12] PADCTRL_MIO_PADS_6 - 4'b 1111, // index[13] PADCTRL_MIO_PADS_7 - 4'b 1111, // index[14] PADCTRL_MIO_PADS_8 - 4'b 1111, // index[15] PADCTRL_MIO_PADS_9 - 4'b 0111 // index[16] PADCTRL_MIO_PADS_10 - }; -endpackage -
diff --git a/hw/top_earlgrey/ip/padctrl/rtl/autogen/padctrl_reg_top.sv b/hw/top_earlgrey/ip/padctrl/rtl/autogen/padctrl_reg_top.sv deleted file mode 100644 index a70b615..0000000 --- a/hw/top_earlgrey/ip/padctrl/rtl/autogen/padctrl_reg_top.sv +++ /dev/null
@@ -1,1458 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Top module auto-generated by `reggen` - -`include "prim_assert.sv" - -module padctrl_reg_top ( - input clk_i, - input rst_ni, - - // Below Regster interface can be changed - input tlul_pkg::tl_h2d_t tl_i, - output tlul_pkg::tl_d2h_t tl_o, - // To HW - output padctrl_reg_pkg::padctrl_reg2hw_t reg2hw, // Write - input padctrl_reg_pkg::padctrl_hw2reg_t hw2reg, // Read - - // Config - input devmode_i // If 1, explicit error return for unmapped register access -); - - import padctrl_reg_pkg::* ; - - localparam int AW = 7; - localparam int DW = 32; - localparam int DBW = DW/8; // Byte Width - - // register signals - logic reg_we; - logic reg_re; - logic [AW-1:0] reg_addr; - logic [DW-1:0] reg_wdata; - logic [DBW-1:0] reg_be; - logic [DW-1:0] reg_rdata; - logic reg_error; - - logic addrmiss, wr_err; - - logic [DW-1:0] reg_rdata_next; - - tlul_pkg::tl_h2d_t tl_reg_h2d; - tlul_pkg::tl_d2h_t tl_reg_d2h; - - assign tl_reg_h2d = tl_i; - assign tl_o = tl_reg_d2h; - - tlul_adapter_reg #( - .RegAw(AW), - .RegDw(DW) - ) u_reg_if ( - .clk_i, - .rst_ni, - - .tl_i (tl_reg_h2d), - .tl_o (tl_reg_d2h), - - .we_o (reg_we), - .re_o (reg_re), - .addr_o (reg_addr), - .wdata_o (reg_wdata), - .be_o (reg_be), - .rdata_i (reg_rdata), - .error_i (reg_error) - ); - - assign reg_rdata = reg_rdata_next ; - assign reg_error = (devmode_i & addrmiss) | wr_err ; - - // Define SW related signals - // Format: <reg>_<field>_{wd|we|qs} - // or <reg>_{wd|we|qs} if field == 1 or 0 - logic regwen_qs; - logic regwen_wd; - logic regwen_we; - logic [9:0] dio_pads_0_attr_0_qs; - logic [9:0] dio_pads_0_attr_0_wd; - logic dio_pads_0_attr_0_we; - logic dio_pads_0_attr_0_re; - logic [9:0] dio_pads_0_attr_1_qs; - logic [9:0] dio_pads_0_attr_1_wd; - logic dio_pads_0_attr_1_we; - logic dio_pads_0_attr_1_re; - logic [9:0] dio_pads_0_attr_2_qs; - logic [9:0] dio_pads_0_attr_2_wd; - logic dio_pads_0_attr_2_we; - logic dio_pads_0_attr_2_re; - logic [9:0] dio_pads_1_attr_3_qs; - logic [9:0] dio_pads_1_attr_3_wd; - logic dio_pads_1_attr_3_we; - logic dio_pads_1_attr_3_re; - logic [9:0] dio_pads_1_attr_4_qs; - logic [9:0] dio_pads_1_attr_4_wd; - logic dio_pads_1_attr_4_we; - logic dio_pads_1_attr_4_re; - logic [9:0] dio_pads_1_attr_5_qs; - logic [9:0] dio_pads_1_attr_5_wd; - logic dio_pads_1_attr_5_we; - logic dio_pads_1_attr_5_re; - logic [9:0] dio_pads_2_attr_6_qs; - logic [9:0] dio_pads_2_attr_6_wd; - logic dio_pads_2_attr_6_we; - logic dio_pads_2_attr_6_re; - logic [9:0] dio_pads_2_attr_7_qs; - logic [9:0] dio_pads_2_attr_7_wd; - logic dio_pads_2_attr_7_we; - logic dio_pads_2_attr_7_re; - logic [9:0] dio_pads_2_attr_8_qs; - logic [9:0] dio_pads_2_attr_8_wd; - logic dio_pads_2_attr_8_we; - logic dio_pads_2_attr_8_re; - logic [9:0] dio_pads_3_attr_9_qs; - logic [9:0] dio_pads_3_attr_9_wd; - logic dio_pads_3_attr_9_we; - logic dio_pads_3_attr_9_re; - logic [9:0] dio_pads_3_attr_10_qs; - logic [9:0] dio_pads_3_attr_10_wd; - logic dio_pads_3_attr_10_we; - logic dio_pads_3_attr_10_re; - logic [9:0] dio_pads_3_attr_11_qs; - logic [9:0] dio_pads_3_attr_11_wd; - logic dio_pads_3_attr_11_we; - logic dio_pads_3_attr_11_re; - logic [9:0] dio_pads_4_attr_12_qs; - logic [9:0] dio_pads_4_attr_12_wd; - logic dio_pads_4_attr_12_we; - logic dio_pads_4_attr_12_re; - logic [9:0] dio_pads_4_attr_13_qs; - logic [9:0] dio_pads_4_attr_13_wd; - logic dio_pads_4_attr_13_we; - logic dio_pads_4_attr_13_re; - logic [9:0] dio_pads_4_attr_14_qs; - logic [9:0] dio_pads_4_attr_14_wd; - logic dio_pads_4_attr_14_we; - logic dio_pads_4_attr_14_re; - logic [9:0] mio_pads_0_attr_0_qs; - logic [9:0] mio_pads_0_attr_0_wd; - logic mio_pads_0_attr_0_we; - logic mio_pads_0_attr_0_re; - logic [9:0] mio_pads_0_attr_1_qs; - logic [9:0] mio_pads_0_attr_1_wd; - logic mio_pads_0_attr_1_we; - logic mio_pads_0_attr_1_re; - logic [9:0] mio_pads_0_attr_2_qs; - logic [9:0] mio_pads_0_attr_2_wd; - logic mio_pads_0_attr_2_we; - logic mio_pads_0_attr_2_re; - logic [9:0] mio_pads_1_attr_3_qs; - logic [9:0] mio_pads_1_attr_3_wd; - logic mio_pads_1_attr_3_we; - logic mio_pads_1_attr_3_re; - logic [9:0] mio_pads_1_attr_4_qs; - logic [9:0] mio_pads_1_attr_4_wd; - logic mio_pads_1_attr_4_we; - logic mio_pads_1_attr_4_re; - logic [9:0] mio_pads_1_attr_5_qs; - logic [9:0] mio_pads_1_attr_5_wd; - logic mio_pads_1_attr_5_we; - logic mio_pads_1_attr_5_re; - logic [9:0] mio_pads_2_attr_6_qs; - logic [9:0] mio_pads_2_attr_6_wd; - logic mio_pads_2_attr_6_we; - logic mio_pads_2_attr_6_re; - logic [9:0] mio_pads_2_attr_7_qs; - logic [9:0] mio_pads_2_attr_7_wd; - logic mio_pads_2_attr_7_we; - logic mio_pads_2_attr_7_re; - logic [9:0] mio_pads_2_attr_8_qs; - logic [9:0] mio_pads_2_attr_8_wd; - logic mio_pads_2_attr_8_we; - logic mio_pads_2_attr_8_re; - logic [9:0] mio_pads_3_attr_9_qs; - logic [9:0] mio_pads_3_attr_9_wd; - logic mio_pads_3_attr_9_we; - logic mio_pads_3_attr_9_re; - logic [9:0] mio_pads_3_attr_10_qs; - logic [9:0] mio_pads_3_attr_10_wd; - logic mio_pads_3_attr_10_we; - logic mio_pads_3_attr_10_re; - logic [9:0] mio_pads_3_attr_11_qs; - logic [9:0] mio_pads_3_attr_11_wd; - logic mio_pads_3_attr_11_we; - logic mio_pads_3_attr_11_re; - logic [9:0] mio_pads_4_attr_12_qs; - logic [9:0] mio_pads_4_attr_12_wd; - logic mio_pads_4_attr_12_we; - logic mio_pads_4_attr_12_re; - logic [9:0] mio_pads_4_attr_13_qs; - logic [9:0] mio_pads_4_attr_13_wd; - logic mio_pads_4_attr_13_we; - logic mio_pads_4_attr_13_re; - logic [9:0] mio_pads_4_attr_14_qs; - logic [9:0] mio_pads_4_attr_14_wd; - logic mio_pads_4_attr_14_we; - logic mio_pads_4_attr_14_re; - logic [9:0] mio_pads_5_attr_15_qs; - logic [9:0] mio_pads_5_attr_15_wd; - logic mio_pads_5_attr_15_we; - logic mio_pads_5_attr_15_re; - logic [9:0] mio_pads_5_attr_16_qs; - logic [9:0] mio_pads_5_attr_16_wd; - logic mio_pads_5_attr_16_we; - logic mio_pads_5_attr_16_re; - logic [9:0] mio_pads_5_attr_17_qs; - logic [9:0] mio_pads_5_attr_17_wd; - logic mio_pads_5_attr_17_we; - logic mio_pads_5_attr_17_re; - logic [9:0] mio_pads_6_attr_18_qs; - logic [9:0] mio_pads_6_attr_18_wd; - logic mio_pads_6_attr_18_we; - logic mio_pads_6_attr_18_re; - logic [9:0] mio_pads_6_attr_19_qs; - logic [9:0] mio_pads_6_attr_19_wd; - logic mio_pads_6_attr_19_we; - logic mio_pads_6_attr_19_re; - logic [9:0] mio_pads_6_attr_20_qs; - logic [9:0] mio_pads_6_attr_20_wd; - logic mio_pads_6_attr_20_we; - logic mio_pads_6_attr_20_re; - logic [9:0] mio_pads_7_attr_21_qs; - logic [9:0] mio_pads_7_attr_21_wd; - logic mio_pads_7_attr_21_we; - logic mio_pads_7_attr_21_re; - logic [9:0] mio_pads_7_attr_22_qs; - logic [9:0] mio_pads_7_attr_22_wd; - logic mio_pads_7_attr_22_we; - logic mio_pads_7_attr_22_re; - logic [9:0] mio_pads_7_attr_23_qs; - logic [9:0] mio_pads_7_attr_23_wd; - logic mio_pads_7_attr_23_we; - logic mio_pads_7_attr_23_re; - logic [9:0] mio_pads_8_attr_24_qs; - logic [9:0] mio_pads_8_attr_24_wd; - logic mio_pads_8_attr_24_we; - logic mio_pads_8_attr_24_re; - logic [9:0] mio_pads_8_attr_25_qs; - logic [9:0] mio_pads_8_attr_25_wd; - logic mio_pads_8_attr_25_we; - logic mio_pads_8_attr_25_re; - logic [9:0] mio_pads_8_attr_26_qs; - logic [9:0] mio_pads_8_attr_26_wd; - logic mio_pads_8_attr_26_we; - logic mio_pads_8_attr_26_re; - logic [9:0] mio_pads_9_attr_27_qs; - logic [9:0] mio_pads_9_attr_27_wd; - logic mio_pads_9_attr_27_we; - logic mio_pads_9_attr_27_re; - logic [9:0] mio_pads_9_attr_28_qs; - logic [9:0] mio_pads_9_attr_28_wd; - logic mio_pads_9_attr_28_we; - logic mio_pads_9_attr_28_re; - logic [9:0] mio_pads_9_attr_29_qs; - logic [9:0] mio_pads_9_attr_29_wd; - logic mio_pads_9_attr_29_we; - logic mio_pads_9_attr_29_re; - logic [9:0] mio_pads_10_attr_30_qs; - logic [9:0] mio_pads_10_attr_30_wd; - logic mio_pads_10_attr_30_we; - logic mio_pads_10_attr_30_re; - logic [9:0] mio_pads_10_attr_31_qs; - logic [9:0] mio_pads_10_attr_31_wd; - logic mio_pads_10_attr_31_we; - logic mio_pads_10_attr_31_re; - - // Register instances - // R[regwen]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_regwen ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (regwen_we), - .wd (regwen_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (regwen_qs) - ); - - - - // Subregister 0 of Multireg dio_pads - // R[dio_pads_0]: V(True) - - // F[attr_0]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_dio_pads_0_attr_0 ( - .re (dio_pads_0_attr_0_re), - // qualified with register enable - .we (dio_pads_0_attr_0_we & regwen_qs), - .wd (dio_pads_0_attr_0_wd), - .d (hw2reg.dio_pads[0].d), - .qre (), - .qe (reg2hw.dio_pads[0].qe), - .q (reg2hw.dio_pads[0].q ), - .qs (dio_pads_0_attr_0_qs) - ); - - - // F[attr_1]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_dio_pads_0_attr_1 ( - .re (dio_pads_0_attr_1_re), - // qualified with register enable - .we (dio_pads_0_attr_1_we & regwen_qs), - .wd (dio_pads_0_attr_1_wd), - .d (hw2reg.dio_pads[1].d), - .qre (), - .qe (reg2hw.dio_pads[1].qe), - .q (reg2hw.dio_pads[1].q ), - .qs (dio_pads_0_attr_1_qs) - ); - - - // F[attr_2]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_dio_pads_0_attr_2 ( - .re (dio_pads_0_attr_2_re), - // qualified with register enable - .we (dio_pads_0_attr_2_we & regwen_qs), - .wd (dio_pads_0_attr_2_wd), - .d (hw2reg.dio_pads[2].d), - .qre (), - .qe (reg2hw.dio_pads[2].qe), - .q (reg2hw.dio_pads[2].q ), - .qs (dio_pads_0_attr_2_qs) - ); - - - // Subregister 3 of Multireg dio_pads - // R[dio_pads_1]: V(True) - - // F[attr_3]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_dio_pads_1_attr_3 ( - .re (dio_pads_1_attr_3_re), - // qualified with register enable - .we (dio_pads_1_attr_3_we & regwen_qs), - .wd (dio_pads_1_attr_3_wd), - .d (hw2reg.dio_pads[3].d), - .qre (), - .qe (reg2hw.dio_pads[3].qe), - .q (reg2hw.dio_pads[3].q ), - .qs (dio_pads_1_attr_3_qs) - ); - - - // F[attr_4]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_dio_pads_1_attr_4 ( - .re (dio_pads_1_attr_4_re), - // qualified with register enable - .we (dio_pads_1_attr_4_we & regwen_qs), - .wd (dio_pads_1_attr_4_wd), - .d (hw2reg.dio_pads[4].d), - .qre (), - .qe (reg2hw.dio_pads[4].qe), - .q (reg2hw.dio_pads[4].q ), - .qs (dio_pads_1_attr_4_qs) - ); - - - // F[attr_5]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_dio_pads_1_attr_5 ( - .re (dio_pads_1_attr_5_re), - // qualified with register enable - .we (dio_pads_1_attr_5_we & regwen_qs), - .wd (dio_pads_1_attr_5_wd), - .d (hw2reg.dio_pads[5].d), - .qre (), - .qe (reg2hw.dio_pads[5].qe), - .q (reg2hw.dio_pads[5].q ), - .qs (dio_pads_1_attr_5_qs) - ); - - - // Subregister 6 of Multireg dio_pads - // R[dio_pads_2]: V(True) - - // F[attr_6]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_dio_pads_2_attr_6 ( - .re (dio_pads_2_attr_6_re), - // qualified with register enable - .we (dio_pads_2_attr_6_we & regwen_qs), - .wd (dio_pads_2_attr_6_wd), - .d (hw2reg.dio_pads[6].d), - .qre (), - .qe (reg2hw.dio_pads[6].qe), - .q (reg2hw.dio_pads[6].q ), - .qs (dio_pads_2_attr_6_qs) - ); - - - // F[attr_7]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_dio_pads_2_attr_7 ( - .re (dio_pads_2_attr_7_re), - // qualified with register enable - .we (dio_pads_2_attr_7_we & regwen_qs), - .wd (dio_pads_2_attr_7_wd), - .d (hw2reg.dio_pads[7].d), - .qre (), - .qe (reg2hw.dio_pads[7].qe), - .q (reg2hw.dio_pads[7].q ), - .qs (dio_pads_2_attr_7_qs) - ); - - - // F[attr_8]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_dio_pads_2_attr_8 ( - .re (dio_pads_2_attr_8_re), - // qualified with register enable - .we (dio_pads_2_attr_8_we & regwen_qs), - .wd (dio_pads_2_attr_8_wd), - .d (hw2reg.dio_pads[8].d), - .qre (), - .qe (reg2hw.dio_pads[8].qe), - .q (reg2hw.dio_pads[8].q ), - .qs (dio_pads_2_attr_8_qs) - ); - - - // Subregister 9 of Multireg dio_pads - // R[dio_pads_3]: V(True) - - // F[attr_9]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_dio_pads_3_attr_9 ( - .re (dio_pads_3_attr_9_re), - // qualified with register enable - .we (dio_pads_3_attr_9_we & regwen_qs), - .wd (dio_pads_3_attr_9_wd), - .d (hw2reg.dio_pads[9].d), - .qre (), - .qe (reg2hw.dio_pads[9].qe), - .q (reg2hw.dio_pads[9].q ), - .qs (dio_pads_3_attr_9_qs) - ); - - - // F[attr_10]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_dio_pads_3_attr_10 ( - .re (dio_pads_3_attr_10_re), - // qualified with register enable - .we (dio_pads_3_attr_10_we & regwen_qs), - .wd (dio_pads_3_attr_10_wd), - .d (hw2reg.dio_pads[10].d), - .qre (), - .qe (reg2hw.dio_pads[10].qe), - .q (reg2hw.dio_pads[10].q ), - .qs (dio_pads_3_attr_10_qs) - ); - - - // F[attr_11]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_dio_pads_3_attr_11 ( - .re (dio_pads_3_attr_11_re), - // qualified with register enable - .we (dio_pads_3_attr_11_we & regwen_qs), - .wd (dio_pads_3_attr_11_wd), - .d (hw2reg.dio_pads[11].d), - .qre (), - .qe (reg2hw.dio_pads[11].qe), - .q (reg2hw.dio_pads[11].q ), - .qs (dio_pads_3_attr_11_qs) - ); - - - // Subregister 12 of Multireg dio_pads - // R[dio_pads_4]: V(True) - - // F[attr_12]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_dio_pads_4_attr_12 ( - .re (dio_pads_4_attr_12_re), - // qualified with register enable - .we (dio_pads_4_attr_12_we & regwen_qs), - .wd (dio_pads_4_attr_12_wd), - .d (hw2reg.dio_pads[12].d), - .qre (), - .qe (reg2hw.dio_pads[12].qe), - .q (reg2hw.dio_pads[12].q ), - .qs (dio_pads_4_attr_12_qs) - ); - - - // F[attr_13]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_dio_pads_4_attr_13 ( - .re (dio_pads_4_attr_13_re), - // qualified with register enable - .we (dio_pads_4_attr_13_we & regwen_qs), - .wd (dio_pads_4_attr_13_wd), - .d (hw2reg.dio_pads[13].d), - .qre (), - .qe (reg2hw.dio_pads[13].qe), - .q (reg2hw.dio_pads[13].q ), - .qs (dio_pads_4_attr_13_qs) - ); - - - // F[attr_14]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_dio_pads_4_attr_14 ( - .re (dio_pads_4_attr_14_re), - // qualified with register enable - .we (dio_pads_4_attr_14_we & regwen_qs), - .wd (dio_pads_4_attr_14_wd), - .d (hw2reg.dio_pads[14].d), - .qre (), - .qe (reg2hw.dio_pads[14].qe), - .q (reg2hw.dio_pads[14].q ), - .qs (dio_pads_4_attr_14_qs) - ); - - - - - // Subregister 0 of Multireg mio_pads - // R[mio_pads_0]: V(True) - - // F[attr_0]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_0_attr_0 ( - .re (mio_pads_0_attr_0_re), - // qualified with register enable - .we (mio_pads_0_attr_0_we & regwen_qs), - .wd (mio_pads_0_attr_0_wd), - .d (hw2reg.mio_pads[0].d), - .qre (), - .qe (reg2hw.mio_pads[0].qe), - .q (reg2hw.mio_pads[0].q ), - .qs (mio_pads_0_attr_0_qs) - ); - - - // F[attr_1]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_0_attr_1 ( - .re (mio_pads_0_attr_1_re), - // qualified with register enable - .we (mio_pads_0_attr_1_we & regwen_qs), - .wd (mio_pads_0_attr_1_wd), - .d (hw2reg.mio_pads[1].d), - .qre (), - .qe (reg2hw.mio_pads[1].qe), - .q (reg2hw.mio_pads[1].q ), - .qs (mio_pads_0_attr_1_qs) - ); - - - // F[attr_2]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_0_attr_2 ( - .re (mio_pads_0_attr_2_re), - // qualified with register enable - .we (mio_pads_0_attr_2_we & regwen_qs), - .wd (mio_pads_0_attr_2_wd), - .d (hw2reg.mio_pads[2].d), - .qre (), - .qe (reg2hw.mio_pads[2].qe), - .q (reg2hw.mio_pads[2].q ), - .qs (mio_pads_0_attr_2_qs) - ); - - - // Subregister 3 of Multireg mio_pads - // R[mio_pads_1]: V(True) - - // F[attr_3]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_1_attr_3 ( - .re (mio_pads_1_attr_3_re), - // qualified with register enable - .we (mio_pads_1_attr_3_we & regwen_qs), - .wd (mio_pads_1_attr_3_wd), - .d (hw2reg.mio_pads[3].d), - .qre (), - .qe (reg2hw.mio_pads[3].qe), - .q (reg2hw.mio_pads[3].q ), - .qs (mio_pads_1_attr_3_qs) - ); - - - // F[attr_4]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_1_attr_4 ( - .re (mio_pads_1_attr_4_re), - // qualified with register enable - .we (mio_pads_1_attr_4_we & regwen_qs), - .wd (mio_pads_1_attr_4_wd), - .d (hw2reg.mio_pads[4].d), - .qre (), - .qe (reg2hw.mio_pads[4].qe), - .q (reg2hw.mio_pads[4].q ), - .qs (mio_pads_1_attr_4_qs) - ); - - - // F[attr_5]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_1_attr_5 ( - .re (mio_pads_1_attr_5_re), - // qualified with register enable - .we (mio_pads_1_attr_5_we & regwen_qs), - .wd (mio_pads_1_attr_5_wd), - .d (hw2reg.mio_pads[5].d), - .qre (), - .qe (reg2hw.mio_pads[5].qe), - .q (reg2hw.mio_pads[5].q ), - .qs (mio_pads_1_attr_5_qs) - ); - - - // Subregister 6 of Multireg mio_pads - // R[mio_pads_2]: V(True) - - // F[attr_6]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_2_attr_6 ( - .re (mio_pads_2_attr_6_re), - // qualified with register enable - .we (mio_pads_2_attr_6_we & regwen_qs), - .wd (mio_pads_2_attr_6_wd), - .d (hw2reg.mio_pads[6].d), - .qre (), - .qe (reg2hw.mio_pads[6].qe), - .q (reg2hw.mio_pads[6].q ), - .qs (mio_pads_2_attr_6_qs) - ); - - - // F[attr_7]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_2_attr_7 ( - .re (mio_pads_2_attr_7_re), - // qualified with register enable - .we (mio_pads_2_attr_7_we & regwen_qs), - .wd (mio_pads_2_attr_7_wd), - .d (hw2reg.mio_pads[7].d), - .qre (), - .qe (reg2hw.mio_pads[7].qe), - .q (reg2hw.mio_pads[7].q ), - .qs (mio_pads_2_attr_7_qs) - ); - - - // F[attr_8]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_2_attr_8 ( - .re (mio_pads_2_attr_8_re), - // qualified with register enable - .we (mio_pads_2_attr_8_we & regwen_qs), - .wd (mio_pads_2_attr_8_wd), - .d (hw2reg.mio_pads[8].d), - .qre (), - .qe (reg2hw.mio_pads[8].qe), - .q (reg2hw.mio_pads[8].q ), - .qs (mio_pads_2_attr_8_qs) - ); - - - // Subregister 9 of Multireg mio_pads - // R[mio_pads_3]: V(True) - - // F[attr_9]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_3_attr_9 ( - .re (mio_pads_3_attr_9_re), - // qualified with register enable - .we (mio_pads_3_attr_9_we & regwen_qs), - .wd (mio_pads_3_attr_9_wd), - .d (hw2reg.mio_pads[9].d), - .qre (), - .qe (reg2hw.mio_pads[9].qe), - .q (reg2hw.mio_pads[9].q ), - .qs (mio_pads_3_attr_9_qs) - ); - - - // F[attr_10]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_3_attr_10 ( - .re (mio_pads_3_attr_10_re), - // qualified with register enable - .we (mio_pads_3_attr_10_we & regwen_qs), - .wd (mio_pads_3_attr_10_wd), - .d (hw2reg.mio_pads[10].d), - .qre (), - .qe (reg2hw.mio_pads[10].qe), - .q (reg2hw.mio_pads[10].q ), - .qs (mio_pads_3_attr_10_qs) - ); - - - // F[attr_11]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_3_attr_11 ( - .re (mio_pads_3_attr_11_re), - // qualified with register enable - .we (mio_pads_3_attr_11_we & regwen_qs), - .wd (mio_pads_3_attr_11_wd), - .d (hw2reg.mio_pads[11].d), - .qre (), - .qe (reg2hw.mio_pads[11].qe), - .q (reg2hw.mio_pads[11].q ), - .qs (mio_pads_3_attr_11_qs) - ); - - - // Subregister 12 of Multireg mio_pads - // R[mio_pads_4]: V(True) - - // F[attr_12]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_4_attr_12 ( - .re (mio_pads_4_attr_12_re), - // qualified with register enable - .we (mio_pads_4_attr_12_we & regwen_qs), - .wd (mio_pads_4_attr_12_wd), - .d (hw2reg.mio_pads[12].d), - .qre (), - .qe (reg2hw.mio_pads[12].qe), - .q (reg2hw.mio_pads[12].q ), - .qs (mio_pads_4_attr_12_qs) - ); - - - // F[attr_13]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_4_attr_13 ( - .re (mio_pads_4_attr_13_re), - // qualified with register enable - .we (mio_pads_4_attr_13_we & regwen_qs), - .wd (mio_pads_4_attr_13_wd), - .d (hw2reg.mio_pads[13].d), - .qre (), - .qe (reg2hw.mio_pads[13].qe), - .q (reg2hw.mio_pads[13].q ), - .qs (mio_pads_4_attr_13_qs) - ); - - - // F[attr_14]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_4_attr_14 ( - .re (mio_pads_4_attr_14_re), - // qualified with register enable - .we (mio_pads_4_attr_14_we & regwen_qs), - .wd (mio_pads_4_attr_14_wd), - .d (hw2reg.mio_pads[14].d), - .qre (), - .qe (reg2hw.mio_pads[14].qe), - .q (reg2hw.mio_pads[14].q ), - .qs (mio_pads_4_attr_14_qs) - ); - - - // Subregister 15 of Multireg mio_pads - // R[mio_pads_5]: V(True) - - // F[attr_15]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_5_attr_15 ( - .re (mio_pads_5_attr_15_re), - // qualified with register enable - .we (mio_pads_5_attr_15_we & regwen_qs), - .wd (mio_pads_5_attr_15_wd), - .d (hw2reg.mio_pads[15].d), - .qre (), - .qe (reg2hw.mio_pads[15].qe), - .q (reg2hw.mio_pads[15].q ), - .qs (mio_pads_5_attr_15_qs) - ); - - - // F[attr_16]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_5_attr_16 ( - .re (mio_pads_5_attr_16_re), - // qualified with register enable - .we (mio_pads_5_attr_16_we & regwen_qs), - .wd (mio_pads_5_attr_16_wd), - .d (hw2reg.mio_pads[16].d), - .qre (), - .qe (reg2hw.mio_pads[16].qe), - .q (reg2hw.mio_pads[16].q ), - .qs (mio_pads_5_attr_16_qs) - ); - - - // F[attr_17]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_5_attr_17 ( - .re (mio_pads_5_attr_17_re), - // qualified with register enable - .we (mio_pads_5_attr_17_we & regwen_qs), - .wd (mio_pads_5_attr_17_wd), - .d (hw2reg.mio_pads[17].d), - .qre (), - .qe (reg2hw.mio_pads[17].qe), - .q (reg2hw.mio_pads[17].q ), - .qs (mio_pads_5_attr_17_qs) - ); - - - // Subregister 18 of Multireg mio_pads - // R[mio_pads_6]: V(True) - - // F[attr_18]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_6_attr_18 ( - .re (mio_pads_6_attr_18_re), - // qualified with register enable - .we (mio_pads_6_attr_18_we & regwen_qs), - .wd (mio_pads_6_attr_18_wd), - .d (hw2reg.mio_pads[18].d), - .qre (), - .qe (reg2hw.mio_pads[18].qe), - .q (reg2hw.mio_pads[18].q ), - .qs (mio_pads_6_attr_18_qs) - ); - - - // F[attr_19]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_6_attr_19 ( - .re (mio_pads_6_attr_19_re), - // qualified with register enable - .we (mio_pads_6_attr_19_we & regwen_qs), - .wd (mio_pads_6_attr_19_wd), - .d (hw2reg.mio_pads[19].d), - .qre (), - .qe (reg2hw.mio_pads[19].qe), - .q (reg2hw.mio_pads[19].q ), - .qs (mio_pads_6_attr_19_qs) - ); - - - // F[attr_20]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_6_attr_20 ( - .re (mio_pads_6_attr_20_re), - // qualified with register enable - .we (mio_pads_6_attr_20_we & regwen_qs), - .wd (mio_pads_6_attr_20_wd), - .d (hw2reg.mio_pads[20].d), - .qre (), - .qe (reg2hw.mio_pads[20].qe), - .q (reg2hw.mio_pads[20].q ), - .qs (mio_pads_6_attr_20_qs) - ); - - - // Subregister 21 of Multireg mio_pads - // R[mio_pads_7]: V(True) - - // F[attr_21]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_7_attr_21 ( - .re (mio_pads_7_attr_21_re), - // qualified with register enable - .we (mio_pads_7_attr_21_we & regwen_qs), - .wd (mio_pads_7_attr_21_wd), - .d (hw2reg.mio_pads[21].d), - .qre (), - .qe (reg2hw.mio_pads[21].qe), - .q (reg2hw.mio_pads[21].q ), - .qs (mio_pads_7_attr_21_qs) - ); - - - // F[attr_22]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_7_attr_22 ( - .re (mio_pads_7_attr_22_re), - // qualified with register enable - .we (mio_pads_7_attr_22_we & regwen_qs), - .wd (mio_pads_7_attr_22_wd), - .d (hw2reg.mio_pads[22].d), - .qre (), - .qe (reg2hw.mio_pads[22].qe), - .q (reg2hw.mio_pads[22].q ), - .qs (mio_pads_7_attr_22_qs) - ); - - - // F[attr_23]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_7_attr_23 ( - .re (mio_pads_7_attr_23_re), - // qualified with register enable - .we (mio_pads_7_attr_23_we & regwen_qs), - .wd (mio_pads_7_attr_23_wd), - .d (hw2reg.mio_pads[23].d), - .qre (), - .qe (reg2hw.mio_pads[23].qe), - .q (reg2hw.mio_pads[23].q ), - .qs (mio_pads_7_attr_23_qs) - ); - - - // Subregister 24 of Multireg mio_pads - // R[mio_pads_8]: V(True) - - // F[attr_24]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_8_attr_24 ( - .re (mio_pads_8_attr_24_re), - // qualified with register enable - .we (mio_pads_8_attr_24_we & regwen_qs), - .wd (mio_pads_8_attr_24_wd), - .d (hw2reg.mio_pads[24].d), - .qre (), - .qe (reg2hw.mio_pads[24].qe), - .q (reg2hw.mio_pads[24].q ), - .qs (mio_pads_8_attr_24_qs) - ); - - - // F[attr_25]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_8_attr_25 ( - .re (mio_pads_8_attr_25_re), - // qualified with register enable - .we (mio_pads_8_attr_25_we & regwen_qs), - .wd (mio_pads_8_attr_25_wd), - .d (hw2reg.mio_pads[25].d), - .qre (), - .qe (reg2hw.mio_pads[25].qe), - .q (reg2hw.mio_pads[25].q ), - .qs (mio_pads_8_attr_25_qs) - ); - - - // F[attr_26]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_8_attr_26 ( - .re (mio_pads_8_attr_26_re), - // qualified with register enable - .we (mio_pads_8_attr_26_we & regwen_qs), - .wd (mio_pads_8_attr_26_wd), - .d (hw2reg.mio_pads[26].d), - .qre (), - .qe (reg2hw.mio_pads[26].qe), - .q (reg2hw.mio_pads[26].q ), - .qs (mio_pads_8_attr_26_qs) - ); - - - // Subregister 27 of Multireg mio_pads - // R[mio_pads_9]: V(True) - - // F[attr_27]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_9_attr_27 ( - .re (mio_pads_9_attr_27_re), - // qualified with register enable - .we (mio_pads_9_attr_27_we & regwen_qs), - .wd (mio_pads_9_attr_27_wd), - .d (hw2reg.mio_pads[27].d), - .qre (), - .qe (reg2hw.mio_pads[27].qe), - .q (reg2hw.mio_pads[27].q ), - .qs (mio_pads_9_attr_27_qs) - ); - - - // F[attr_28]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_9_attr_28 ( - .re (mio_pads_9_attr_28_re), - // qualified with register enable - .we (mio_pads_9_attr_28_we & regwen_qs), - .wd (mio_pads_9_attr_28_wd), - .d (hw2reg.mio_pads[28].d), - .qre (), - .qe (reg2hw.mio_pads[28].qe), - .q (reg2hw.mio_pads[28].q ), - .qs (mio_pads_9_attr_28_qs) - ); - - - // F[attr_29]: 29:20 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_9_attr_29 ( - .re (mio_pads_9_attr_29_re), - // qualified with register enable - .we (mio_pads_9_attr_29_we & regwen_qs), - .wd (mio_pads_9_attr_29_wd), - .d (hw2reg.mio_pads[29].d), - .qre (), - .qe (reg2hw.mio_pads[29].qe), - .q (reg2hw.mio_pads[29].q ), - .qs (mio_pads_9_attr_29_qs) - ); - - - // Subregister 30 of Multireg mio_pads - // R[mio_pads_10]: V(True) - - // F[attr_30]: 9:0 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_10_attr_30 ( - .re (mio_pads_10_attr_30_re), - // qualified with register enable - .we (mio_pads_10_attr_30_we & regwen_qs), - .wd (mio_pads_10_attr_30_wd), - .d (hw2reg.mio_pads[30].d), - .qre (), - .qe (reg2hw.mio_pads[30].qe), - .q (reg2hw.mio_pads[30].q ), - .qs (mio_pads_10_attr_30_qs) - ); - - - // F[attr_31]: 19:10 - prim_subreg_ext #( - .DW (10) - ) u_mio_pads_10_attr_31 ( - .re (mio_pads_10_attr_31_re), - // qualified with register enable - .we (mio_pads_10_attr_31_we & regwen_qs), - .wd (mio_pads_10_attr_31_wd), - .d (hw2reg.mio_pads[31].d), - .qre (), - .qe (reg2hw.mio_pads[31].qe), - .q (reg2hw.mio_pads[31].q ), - .qs (mio_pads_10_attr_31_qs) - ); - - - - - - logic [16:0] addr_hit; - always_comb begin - addr_hit = '0; - addr_hit[ 0] = (reg_addr == PADCTRL_REGWEN_OFFSET); - addr_hit[ 1] = (reg_addr == PADCTRL_DIO_PADS_0_OFFSET); - addr_hit[ 2] = (reg_addr == PADCTRL_DIO_PADS_1_OFFSET); - addr_hit[ 3] = (reg_addr == PADCTRL_DIO_PADS_2_OFFSET); - addr_hit[ 4] = (reg_addr == PADCTRL_DIO_PADS_3_OFFSET); - addr_hit[ 5] = (reg_addr == PADCTRL_DIO_PADS_4_OFFSET); - addr_hit[ 6] = (reg_addr == PADCTRL_MIO_PADS_0_OFFSET); - addr_hit[ 7] = (reg_addr == PADCTRL_MIO_PADS_1_OFFSET); - addr_hit[ 8] = (reg_addr == PADCTRL_MIO_PADS_2_OFFSET); - addr_hit[ 9] = (reg_addr == PADCTRL_MIO_PADS_3_OFFSET); - addr_hit[10] = (reg_addr == PADCTRL_MIO_PADS_4_OFFSET); - addr_hit[11] = (reg_addr == PADCTRL_MIO_PADS_5_OFFSET); - addr_hit[12] = (reg_addr == PADCTRL_MIO_PADS_6_OFFSET); - addr_hit[13] = (reg_addr == PADCTRL_MIO_PADS_7_OFFSET); - addr_hit[14] = (reg_addr == PADCTRL_MIO_PADS_8_OFFSET); - addr_hit[15] = (reg_addr == PADCTRL_MIO_PADS_9_OFFSET); - addr_hit[16] = (reg_addr == PADCTRL_MIO_PADS_10_OFFSET); - end - - assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; - - // Check sub-word write is permitted - always_comb begin - wr_err = 1'b0; - if (addr_hit[ 0] && reg_we && (PADCTRL_PERMIT[ 0] != (PADCTRL_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[ 1] && reg_we && (PADCTRL_PERMIT[ 1] != (PADCTRL_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[ 2] && reg_we && (PADCTRL_PERMIT[ 2] != (PADCTRL_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[ 3] && reg_we && (PADCTRL_PERMIT[ 3] != (PADCTRL_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[ 4] && reg_we && (PADCTRL_PERMIT[ 4] != (PADCTRL_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[ 5] && reg_we && (PADCTRL_PERMIT[ 5] != (PADCTRL_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[ 6] && reg_we && (PADCTRL_PERMIT[ 6] != (PADCTRL_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[ 7] && reg_we && (PADCTRL_PERMIT[ 7] != (PADCTRL_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[ 8] && reg_we && (PADCTRL_PERMIT[ 8] != (PADCTRL_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[ 9] && reg_we && (PADCTRL_PERMIT[ 9] != (PADCTRL_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[10] && reg_we && (PADCTRL_PERMIT[10] != (PADCTRL_PERMIT[10] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[11] && reg_we && (PADCTRL_PERMIT[11] != (PADCTRL_PERMIT[11] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[12] && reg_we && (PADCTRL_PERMIT[12] != (PADCTRL_PERMIT[12] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[13] && reg_we && (PADCTRL_PERMIT[13] != (PADCTRL_PERMIT[13] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[14] && reg_we && (PADCTRL_PERMIT[14] != (PADCTRL_PERMIT[14] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[15] && reg_we && (PADCTRL_PERMIT[15] != (PADCTRL_PERMIT[15] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[16] && reg_we && (PADCTRL_PERMIT[16] != (PADCTRL_PERMIT[16] & reg_be))) wr_err = 1'b1 ; - end - - assign regwen_we = addr_hit[0] & reg_we & ~wr_err; - assign regwen_wd = reg_wdata[0]; - - assign dio_pads_0_attr_0_we = addr_hit[1] & reg_we & ~wr_err; - assign dio_pads_0_attr_0_wd = reg_wdata[9:0]; - assign dio_pads_0_attr_0_re = addr_hit[1] && reg_re; - - assign dio_pads_0_attr_1_we = addr_hit[1] & reg_we & ~wr_err; - assign dio_pads_0_attr_1_wd = reg_wdata[19:10]; - assign dio_pads_0_attr_1_re = addr_hit[1] && reg_re; - - assign dio_pads_0_attr_2_we = addr_hit[1] & reg_we & ~wr_err; - assign dio_pads_0_attr_2_wd = reg_wdata[29:20]; - assign dio_pads_0_attr_2_re = addr_hit[1] && reg_re; - - assign dio_pads_1_attr_3_we = addr_hit[2] & reg_we & ~wr_err; - assign dio_pads_1_attr_3_wd = reg_wdata[9:0]; - assign dio_pads_1_attr_3_re = addr_hit[2] && reg_re; - - assign dio_pads_1_attr_4_we = addr_hit[2] & reg_we & ~wr_err; - assign dio_pads_1_attr_4_wd = reg_wdata[19:10]; - assign dio_pads_1_attr_4_re = addr_hit[2] && reg_re; - - assign dio_pads_1_attr_5_we = addr_hit[2] & reg_we & ~wr_err; - assign dio_pads_1_attr_5_wd = reg_wdata[29:20]; - assign dio_pads_1_attr_5_re = addr_hit[2] && reg_re; - - assign dio_pads_2_attr_6_we = addr_hit[3] & reg_we & ~wr_err; - assign dio_pads_2_attr_6_wd = reg_wdata[9:0]; - assign dio_pads_2_attr_6_re = addr_hit[3] && reg_re; - - assign dio_pads_2_attr_7_we = addr_hit[3] & reg_we & ~wr_err; - assign dio_pads_2_attr_7_wd = reg_wdata[19:10]; - assign dio_pads_2_attr_7_re = addr_hit[3] && reg_re; - - assign dio_pads_2_attr_8_we = addr_hit[3] & reg_we & ~wr_err; - assign dio_pads_2_attr_8_wd = reg_wdata[29:20]; - assign dio_pads_2_attr_8_re = addr_hit[3] && reg_re; - - assign dio_pads_3_attr_9_we = addr_hit[4] & reg_we & ~wr_err; - assign dio_pads_3_attr_9_wd = reg_wdata[9:0]; - assign dio_pads_3_attr_9_re = addr_hit[4] && reg_re; - - assign dio_pads_3_attr_10_we = addr_hit[4] & reg_we & ~wr_err; - assign dio_pads_3_attr_10_wd = reg_wdata[19:10]; - assign dio_pads_3_attr_10_re = addr_hit[4] && reg_re; - - assign dio_pads_3_attr_11_we = addr_hit[4] & reg_we & ~wr_err; - assign dio_pads_3_attr_11_wd = reg_wdata[29:20]; - assign dio_pads_3_attr_11_re = addr_hit[4] && reg_re; - - assign dio_pads_4_attr_12_we = addr_hit[5] & reg_we & ~wr_err; - assign dio_pads_4_attr_12_wd = reg_wdata[9:0]; - assign dio_pads_4_attr_12_re = addr_hit[5] && reg_re; - - assign dio_pads_4_attr_13_we = addr_hit[5] & reg_we & ~wr_err; - assign dio_pads_4_attr_13_wd = reg_wdata[19:10]; - assign dio_pads_4_attr_13_re = addr_hit[5] && reg_re; - - assign dio_pads_4_attr_14_we = addr_hit[5] & reg_we & ~wr_err; - assign dio_pads_4_attr_14_wd = reg_wdata[29:20]; - assign dio_pads_4_attr_14_re = addr_hit[5] && reg_re; - - assign mio_pads_0_attr_0_we = addr_hit[6] & reg_we & ~wr_err; - assign mio_pads_0_attr_0_wd = reg_wdata[9:0]; - assign mio_pads_0_attr_0_re = addr_hit[6] && reg_re; - - assign mio_pads_0_attr_1_we = addr_hit[6] & reg_we & ~wr_err; - assign mio_pads_0_attr_1_wd = reg_wdata[19:10]; - assign mio_pads_0_attr_1_re = addr_hit[6] && reg_re; - - assign mio_pads_0_attr_2_we = addr_hit[6] & reg_we & ~wr_err; - assign mio_pads_0_attr_2_wd = reg_wdata[29:20]; - assign mio_pads_0_attr_2_re = addr_hit[6] && reg_re; - - assign mio_pads_1_attr_3_we = addr_hit[7] & reg_we & ~wr_err; - assign mio_pads_1_attr_3_wd = reg_wdata[9:0]; - assign mio_pads_1_attr_3_re = addr_hit[7] && reg_re; - - assign mio_pads_1_attr_4_we = addr_hit[7] & reg_we & ~wr_err; - assign mio_pads_1_attr_4_wd = reg_wdata[19:10]; - assign mio_pads_1_attr_4_re = addr_hit[7] && reg_re; - - assign mio_pads_1_attr_5_we = addr_hit[7] & reg_we & ~wr_err; - assign mio_pads_1_attr_5_wd = reg_wdata[29:20]; - assign mio_pads_1_attr_5_re = addr_hit[7] && reg_re; - - assign mio_pads_2_attr_6_we = addr_hit[8] & reg_we & ~wr_err; - assign mio_pads_2_attr_6_wd = reg_wdata[9:0]; - assign mio_pads_2_attr_6_re = addr_hit[8] && reg_re; - - assign mio_pads_2_attr_7_we = addr_hit[8] & reg_we & ~wr_err; - assign mio_pads_2_attr_7_wd = reg_wdata[19:10]; - assign mio_pads_2_attr_7_re = addr_hit[8] && reg_re; - - assign mio_pads_2_attr_8_we = addr_hit[8] & reg_we & ~wr_err; - assign mio_pads_2_attr_8_wd = reg_wdata[29:20]; - assign mio_pads_2_attr_8_re = addr_hit[8] && reg_re; - - assign mio_pads_3_attr_9_we = addr_hit[9] & reg_we & ~wr_err; - assign mio_pads_3_attr_9_wd = reg_wdata[9:0]; - assign mio_pads_3_attr_9_re = addr_hit[9] && reg_re; - - assign mio_pads_3_attr_10_we = addr_hit[9] & reg_we & ~wr_err; - assign mio_pads_3_attr_10_wd = reg_wdata[19:10]; - assign mio_pads_3_attr_10_re = addr_hit[9] && reg_re; - - assign mio_pads_3_attr_11_we = addr_hit[9] & reg_we & ~wr_err; - assign mio_pads_3_attr_11_wd = reg_wdata[29:20]; - assign mio_pads_3_attr_11_re = addr_hit[9] && reg_re; - - assign mio_pads_4_attr_12_we = addr_hit[10] & reg_we & ~wr_err; - assign mio_pads_4_attr_12_wd = reg_wdata[9:0]; - assign mio_pads_4_attr_12_re = addr_hit[10] && reg_re; - - assign mio_pads_4_attr_13_we = addr_hit[10] & reg_we & ~wr_err; - assign mio_pads_4_attr_13_wd = reg_wdata[19:10]; - assign mio_pads_4_attr_13_re = addr_hit[10] && reg_re; - - assign mio_pads_4_attr_14_we = addr_hit[10] & reg_we & ~wr_err; - assign mio_pads_4_attr_14_wd = reg_wdata[29:20]; - assign mio_pads_4_attr_14_re = addr_hit[10] && reg_re; - - assign mio_pads_5_attr_15_we = addr_hit[11] & reg_we & ~wr_err; - assign mio_pads_5_attr_15_wd = reg_wdata[9:0]; - assign mio_pads_5_attr_15_re = addr_hit[11] && reg_re; - - assign mio_pads_5_attr_16_we = addr_hit[11] & reg_we & ~wr_err; - assign mio_pads_5_attr_16_wd = reg_wdata[19:10]; - assign mio_pads_5_attr_16_re = addr_hit[11] && reg_re; - - assign mio_pads_5_attr_17_we = addr_hit[11] & reg_we & ~wr_err; - assign mio_pads_5_attr_17_wd = reg_wdata[29:20]; - assign mio_pads_5_attr_17_re = addr_hit[11] && reg_re; - - assign mio_pads_6_attr_18_we = addr_hit[12] & reg_we & ~wr_err; - assign mio_pads_6_attr_18_wd = reg_wdata[9:0]; - assign mio_pads_6_attr_18_re = addr_hit[12] && reg_re; - - assign mio_pads_6_attr_19_we = addr_hit[12] & reg_we & ~wr_err; - assign mio_pads_6_attr_19_wd = reg_wdata[19:10]; - assign mio_pads_6_attr_19_re = addr_hit[12] && reg_re; - - assign mio_pads_6_attr_20_we = addr_hit[12] & reg_we & ~wr_err; - assign mio_pads_6_attr_20_wd = reg_wdata[29:20]; - assign mio_pads_6_attr_20_re = addr_hit[12] && reg_re; - - assign mio_pads_7_attr_21_we = addr_hit[13] & reg_we & ~wr_err; - assign mio_pads_7_attr_21_wd = reg_wdata[9:0]; - assign mio_pads_7_attr_21_re = addr_hit[13] && reg_re; - - assign mio_pads_7_attr_22_we = addr_hit[13] & reg_we & ~wr_err; - assign mio_pads_7_attr_22_wd = reg_wdata[19:10]; - assign mio_pads_7_attr_22_re = addr_hit[13] && reg_re; - - assign mio_pads_7_attr_23_we = addr_hit[13] & reg_we & ~wr_err; - assign mio_pads_7_attr_23_wd = reg_wdata[29:20]; - assign mio_pads_7_attr_23_re = addr_hit[13] && reg_re; - - assign mio_pads_8_attr_24_we = addr_hit[14] & reg_we & ~wr_err; - assign mio_pads_8_attr_24_wd = reg_wdata[9:0]; - assign mio_pads_8_attr_24_re = addr_hit[14] && reg_re; - - assign mio_pads_8_attr_25_we = addr_hit[14] & reg_we & ~wr_err; - assign mio_pads_8_attr_25_wd = reg_wdata[19:10]; - assign mio_pads_8_attr_25_re = addr_hit[14] && reg_re; - - assign mio_pads_8_attr_26_we = addr_hit[14] & reg_we & ~wr_err; - assign mio_pads_8_attr_26_wd = reg_wdata[29:20]; - assign mio_pads_8_attr_26_re = addr_hit[14] && reg_re; - - assign mio_pads_9_attr_27_we = addr_hit[15] & reg_we & ~wr_err; - assign mio_pads_9_attr_27_wd = reg_wdata[9:0]; - assign mio_pads_9_attr_27_re = addr_hit[15] && reg_re; - - assign mio_pads_9_attr_28_we = addr_hit[15] & reg_we & ~wr_err; - assign mio_pads_9_attr_28_wd = reg_wdata[19:10]; - assign mio_pads_9_attr_28_re = addr_hit[15] && reg_re; - - assign mio_pads_9_attr_29_we = addr_hit[15] & reg_we & ~wr_err; - assign mio_pads_9_attr_29_wd = reg_wdata[29:20]; - assign mio_pads_9_attr_29_re = addr_hit[15] && reg_re; - - assign mio_pads_10_attr_30_we = addr_hit[16] & reg_we & ~wr_err; - assign mio_pads_10_attr_30_wd = reg_wdata[9:0]; - assign mio_pads_10_attr_30_re = addr_hit[16] && reg_re; - - assign mio_pads_10_attr_31_we = addr_hit[16] & reg_we & ~wr_err; - assign mio_pads_10_attr_31_wd = reg_wdata[19:10]; - assign mio_pads_10_attr_31_re = addr_hit[16] && reg_re; - - // Read data return - always_comb begin - reg_rdata_next = '0; - unique case (1'b1) - addr_hit[0]: begin - reg_rdata_next[0] = regwen_qs; - end - - addr_hit[1]: begin - reg_rdata_next[9:0] = dio_pads_0_attr_0_qs; - reg_rdata_next[19:10] = dio_pads_0_attr_1_qs; - reg_rdata_next[29:20] = dio_pads_0_attr_2_qs; - end - - addr_hit[2]: begin - reg_rdata_next[9:0] = dio_pads_1_attr_3_qs; - reg_rdata_next[19:10] = dio_pads_1_attr_4_qs; - reg_rdata_next[29:20] = dio_pads_1_attr_5_qs; - end - - addr_hit[3]: begin - reg_rdata_next[9:0] = dio_pads_2_attr_6_qs; - reg_rdata_next[19:10] = dio_pads_2_attr_7_qs; - reg_rdata_next[29:20] = dio_pads_2_attr_8_qs; - end - - addr_hit[4]: begin - reg_rdata_next[9:0] = dio_pads_3_attr_9_qs; - reg_rdata_next[19:10] = dio_pads_3_attr_10_qs; - reg_rdata_next[29:20] = dio_pads_3_attr_11_qs; - end - - addr_hit[5]: begin - reg_rdata_next[9:0] = dio_pads_4_attr_12_qs; - reg_rdata_next[19:10] = dio_pads_4_attr_13_qs; - reg_rdata_next[29:20] = dio_pads_4_attr_14_qs; - end - - addr_hit[6]: begin - reg_rdata_next[9:0] = mio_pads_0_attr_0_qs; - reg_rdata_next[19:10] = mio_pads_0_attr_1_qs; - reg_rdata_next[29:20] = mio_pads_0_attr_2_qs; - end - - addr_hit[7]: begin - reg_rdata_next[9:0] = mio_pads_1_attr_3_qs; - reg_rdata_next[19:10] = mio_pads_1_attr_4_qs; - reg_rdata_next[29:20] = mio_pads_1_attr_5_qs; - end - - addr_hit[8]: begin - reg_rdata_next[9:0] = mio_pads_2_attr_6_qs; - reg_rdata_next[19:10] = mio_pads_2_attr_7_qs; - reg_rdata_next[29:20] = mio_pads_2_attr_8_qs; - end - - addr_hit[9]: begin - reg_rdata_next[9:0] = mio_pads_3_attr_9_qs; - reg_rdata_next[19:10] = mio_pads_3_attr_10_qs; - reg_rdata_next[29:20] = mio_pads_3_attr_11_qs; - end - - addr_hit[10]: begin - reg_rdata_next[9:0] = mio_pads_4_attr_12_qs; - reg_rdata_next[19:10] = mio_pads_4_attr_13_qs; - reg_rdata_next[29:20] = mio_pads_4_attr_14_qs; - end - - addr_hit[11]: begin - reg_rdata_next[9:0] = mio_pads_5_attr_15_qs; - reg_rdata_next[19:10] = mio_pads_5_attr_16_qs; - reg_rdata_next[29:20] = mio_pads_5_attr_17_qs; - end - - addr_hit[12]: begin - reg_rdata_next[9:0] = mio_pads_6_attr_18_qs; - reg_rdata_next[19:10] = mio_pads_6_attr_19_qs; - reg_rdata_next[29:20] = mio_pads_6_attr_20_qs; - end - - addr_hit[13]: begin - reg_rdata_next[9:0] = mio_pads_7_attr_21_qs; - reg_rdata_next[19:10] = mio_pads_7_attr_22_qs; - reg_rdata_next[29:20] = mio_pads_7_attr_23_qs; - end - - addr_hit[14]: begin - reg_rdata_next[9:0] = mio_pads_8_attr_24_qs; - reg_rdata_next[19:10] = mio_pads_8_attr_25_qs; - reg_rdata_next[29:20] = mio_pads_8_attr_26_qs; - end - - addr_hit[15]: begin - reg_rdata_next[9:0] = mio_pads_9_attr_27_qs; - reg_rdata_next[19:10] = mio_pads_9_attr_28_qs; - reg_rdata_next[29:20] = mio_pads_9_attr_29_qs; - end - - addr_hit[16]: begin - reg_rdata_next[9:0] = mio_pads_10_attr_30_qs; - reg_rdata_next[19:10] = mio_pads_10_attr_31_qs; - end - - default: begin - reg_rdata_next = '1; - end - endcase - end - - // Assertions for Register Interface - `ASSERT_PULSE(wePulse, reg_we) - `ASSERT_PULSE(rePulse, reg_re) - - `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid) - - `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) - - // this is formulated as an assumption such that the FPV testbenches do disprove this - // property by mistake - `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0) - -endmodule
diff --git a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson index 7eb67e4..7453cf0 100644 --- a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson +++ b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
@@ -10,18 +10,6 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // -# PINMUX register template -# -# Parameter (given by Python tool) -# - n_mio_periph_in: Number of muxed peripheral inputs -# - n_mio_periph_out: Number of muxed peripheral outputs -# - n_mio_pads: Number of muxed IO pads -# - n_dio_periph_in: Number of dedicated peripheral inputs -# - n_dio_periph_out: Number of dedicated peripheral outputs -# - n_dio_pads: Number of dedicated IO pads -# - n_wkup_detect: Number of wakeup condition detectors -# - wkup_cnt_width: Width of wakeup counters -# { name: "PINMUX", clock_primary: "clk_i", @@ -129,6 +117,12 @@ ] param_list: [ + { name: "AttrDw", + desc: "Pad attribute data width", + type: "int", + default: "10", + local: "true" + }, { name: "NMioPeriphIn", desc: "Number of muxed peripheral inputs", type: "int", @@ -204,30 +198,6 @@ // TODO: Enable these once supported by topgen and the C header generation script. // These parameters are currently located in pinmux_pkg.sv - // // If a bit is set to 1 in this vector, this MIO activates low power - // // behavior when going to sleep. - // { name: "MioPeriphHasSleepMode", - // desc: ''' - // Indicates whether a MIO channel activates low power behavior - // when going to sleep. - // ''' - // type: "logic [NMioPeriphOut-1:0]", - // // TODO: need to generate this via topgen - // default: "'1", - // local: "true" - // }, - // // If a bit is set to 1 in this vector, this DIO activates low power - // // behavior when going to sleep. - // { name: "DioPeriphHasSleepMode", - // desc: ''' - // Indicates whether a DIO channel activates low power behavior - // when going to sleep. - // ''', - // type: "logic [NDioPads-1:0]", - // // TODO: need to generate this via topgen - // default: "'1", - // local: "true" - // }, // // If a bit is set to 1 in this vector, wakeup detectors are connected // // to this DIO. // { name: "DioPeriphHasWkup", @@ -239,7 +209,9 @@ // }, ], registers: [ -# inputs +////////////////////////// +// MIO Inputs // +////////////////////////// { multireg: { name: "MIO_PERIPH_INSEL_REGWEN", desc: "Register write enable for MIO peripheral input selects.", count: "NMioPeriphIn", @@ -281,7 +253,10 @@ ] } }, -# outputs + +////////////////////////// +// MIO Outputs // +////////////////////////// { multireg: { name: "MIO_OUTSEL_REGWEN", desc: "Register write enable for MIO output selects.", count: "NMioPads", @@ -326,20 +301,23 @@ tags: ["excl:CsrNonInitTests:CsrExclWrite"] } }, -# sleep behavior of MIO peripheral outputs - { multireg: { name: "MIO_OUT_SLEEP_REGWEN", - desc: "Register write enable for MIO sleep value configuration.", + +////////////////////////// +// MIO PAD attributes // +////////////////////////// + { multireg: { name: "MIO_PAD_ATTR_REGWEN", + desc: "Register write enable for MIO PAD attributes.", count: "NMioPads", compact: "false", swaccess: "rw0c", hwaccess: "none", - cname: "MIO_OUT_SLEEP_VAL", + cname: "MIO_PAD", fields: [ { bits: "0", name: "EN", desc: ''' Register write enable bit. - If this is cleared to 0, the corresponding MIO_OUT_SLEEP_VAL + If this is cleared to 0, the corresponding !!MIO_PAD_ATTR is not writable anymore. ''', resval: "1", @@ -347,66 +325,61 @@ ] } }, -# TODO: add individual sleep disable bits - { multireg: { name: "MIO_OUT_SLEEP_VAL", - desc: '''Defines sleep behavior of muxed output or inout. Note that - the MIO output will only switch into sleep mode if the the corresponding - !!MIO_OUTSEL is either set to 0-2, or if !!MIO_OUTSEL selects a peripheral - output that can go into sleep. If an always on peripheral is selected with - !!MIO_OUTSEL, the !!MIO_OUT_SLEEP_VAL configuration has no effect. - ''' + { multireg: { name: "MIO_PAD_ATTR", + desc: ''' + Muxed pad attributes. + This register has WARL behavior since not each pad type may support + all attributes. + ''', count: "NMioPads", compact: "false", swaccess: "rw", - hwaccess: "hro", - regwen: "MIO_OUT_SLEEP_REGWEN", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + regwen: "MIO_PAD_ATTR_REGWEN", regwen_multi: "true", - cname: "OUT", + cname: "MIO_PAD", fields: [ - { bits: "1:0", - name: "OUT", - resval: 2, - desc:"Value to drive in deep sleep." - enum: [ - { value: "0", - name: "Tie-Low", - desc: "The pin is driven actively to zero in deep sleep mode." - }, - { value: "1", - name: "Tie-High", - desc: "The pin is driven actively to one in deep sleep mode." - }, - { value: "2", - name: "High-Z", - desc: ''' - The pin is left undriven in deep sleep mode. Note that the actual - driving behavior during deep sleep will then depend on the pull-up/-down - configuration of padctrl. - ''' - }, - { value: "3", - name: "Keep", - desc: "Keep last driven value (including high-Z)." - }, - ] + { bits: "9:0", + name: "ATTR", + desc: '''Bit 0: input/output inversion, + Bit 1: Virtual open drain enable. + Bit 2: Pull enable. + Bit 3: Pull select (0: pull down, 1: pull up). + Bit 4: Keeper enable. + Bit 5: Schmitt trigger enable. + Bit 6: Slew rate (0: slow, 1: fast). + Bit 7/8: Drive strength (00: weakest, 11: strongest). + Bit 9: Reserved. + ''' + resval: 0 } - ] + ], + // these CSRs have WARL behavior and may not + // read back the same value that was written to them. + // further, they have hardware side effects since they drive the + // pad attributes, and hence no random data should be written to them. + tags: ["excl:CsrAllTests:CsrExclWrite"] } }, -# sleep behavior of DIO peripheral outputs - { multireg: { name: "DIO_OUT_SLEEP_REGWEN", - desc: "Register write enable for DIO sleep value configuration.", + +////////////////////////// +// DIO PAD attributes // +////////////////////////// + { multireg: { name: "DIO_PAD_ATTR_REGWEN", + desc: "Register write enable for DIO PAD attributes.", count: "NDioPads", compact: "false", swaccess: "rw0c", hwaccess: "none", - cname: "DIO_OUT_SLEEP_VAL", + cname: "DIO_PAD", fields: [ { bits: "0", name: "EN", desc: ''' Register write enable bit. - If this is cleared to 0, the corresponding DIO_OUT_SLEEP_VAL + If this is cleared to 0, the corresponding !!DIO_PAD_ATTR is not writable anymore. ''', resval: "1", @@ -414,43 +387,147 @@ ] } }, -# TODO: add individual sleep disable bits - { multireg: { name: "DIO_OUT_SLEEP_VAL", - desc: '''Defines sleep behavior of dedicated output or inout. Note this - register has WARL behavior since the sleep value settings are - meaningless for always-on and input-only DIOs. For these DIOs, - this register always reads 0. - ''' + { multireg: { name: "DIO_PAD_ATTR", + desc: ''' + Dedicated pad attributes. + This register has WARL behavior since not each pad type may support + all attributes. + ''', count: "NDioPads", compact: "false", swaccess: "rw", hwaccess: "hrw", hwext: "true", hwqe: "true", - regwen: "DIO_OUT_SLEEP_REGWEN", + regwen: "DIO_PAD_ATTR_REGWEN", + regwen_multi: "true", + cname: "DIO_PAD", + fields: [ + { bits: "9:0", + name: "ATTR", + desc: '''Bit 0: input/output inversion, + Bit 1: Virtual open drain enable. + Bit 2: Pull enable. + Bit 3: Pull select (0: pull down, 1: pull up). + Bit 4: Keeper enable. + Bit 5: Schmitt trigger enable. + Bit 6: Slew rate (0: slow, 1: fast). + Bit 7/8: Drive strength (00: weakest, 11: strongest). + Bit 9: Reserved. + ''' + resval: 0 + } + ], + // these CSRs have WARL behavior and may not + // read back the same value that was written to them. + // further, they have hardware side effects since they drive the + // pad attributes, and hence no random data should be written to them. + tags: ["excl:CsrAllTests:CsrExclWrite"] + } + }, + +////////////////////////// +// MIO PAD sleep mode // +////////////////////////// + { multireg: { name: "MIO_PAD_SLEEP_STATUS", + desc: "Register indicating whether the corresponding pad is in sleep mode.", + count: "NMioPads", + swaccess: "rw0c", + hwaccess: "hrw", + cname: "MIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + This register is set to 1 if the deep sleep mode of the corresponding + pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. + The sleep mode of the corresponding pad will remain active until SW + clears this bit. + ''', + resval: "0", + } + ] + } + }, + { multireg: { name: "MIO_PAD_SLEEP_REGWEN", + desc: "Register write enable for MIO sleep value configuration.", + count: "NMioPads", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "MIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding !!MIO_OUT_SLEEP_MODE + is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "MIO_PAD_SLEEP_EN", + desc: '''Enables the sleep mode of the corresponding muxed pad. + ''' + count: "NMioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "MIO_PAD_SLEEP_REGWEN", regwen_multi: "true", cname: "OUT", fields: [ - { bits: "1:0", - name: "OUT", + { bits: "0", + name: "EN", + resval: 0, + desc: ''' + Deep sleep mode enable. + If this bit is set to 1 the corresponding pad will enable the sleep behavior + specified in !!MIO_PAD_SLEEP_MODE upon deep sleep entry, and the corresponding bit + in !!MIO_PAD_SLEEP_STATUS will be set to 1. + The pad remains in deep sleep mode until the corresponding bit in + !!MIO_PAD_SLEEP_STATUS is cleared by SW. + Note that if an always on peripheral is connected to a specific MIO pad, + the corresponding !!MIO_PAD_SLEEP_EN bit should be set to 0. + ''' + } + ] + } + }, + { multireg: { name: "MIO_PAD_SLEEP_MODE", + desc: '''Defines sleep behavior of the corresponding muxed pad. + ''' + count: "NMioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "MIO_PAD_SLEEP_REGWEN", + regwen_multi: "true", + cname: "OUT", + fields: [ + { bits: "1:0", + name: "OUT", resval: 2, - desc:"Value to drive in deep sleep." + desc: "Value to drive in deep sleep." enum: [ { value: "0", name: "Tie-Low", - desc: "The pin is driven actively to zero in deep sleep mode." + desc: "The pad is driven actively to zero in deep sleep mode." }, { value: "1", name: "Tie-High", - desc: "The pin is driven actively to one in deep sleep mode." + desc: "The pad is driven actively to one in deep sleep mode." }, { value: "2", name: "High-Z", desc: ''' - The pin is left undriven in deep sleep mode. Note that the actual - driving behavior during deep sleep will then depend on the pull-up/-down - configuration of padctrl. - ''' + The pad is left undriven in deep sleep mode. Note that the actual + driving behavior during deep sleep will then depend on the pull-up/-down + configuration of in !!MIO_PAD_ATTR. + ''' }, { value: "3", name: "Keep", @@ -459,12 +536,123 @@ ] } ] - // these CSRs have WARL behavior and may not - // read back the same value that was written to them. - tags: ["excl:CsrAllTests:CsrExclWriteCheck"] } }, -# wakeup detector enables +////////////////////////// +// DIO PAD sleep mode // +////////////////////////// + { multireg: { name: "DIO_PAD_SLEEP_STATUS", + desc: "Register indicating whether the corresponding pad is in sleep mode.", + count: "NDioPads", + swaccess: "rw0c", + hwaccess: "hrw", + cname: "DIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + This register is set to 1 if the deep sleep mode of the corresponding + pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. + The sleep mode of the corresponding pad will remain active until SW + clears this bit. + ''', + resval: "0", + } + ] + } + }, + { multireg: { name: "DIO_PAD_SLEEP_REGWEN", + desc: "Register write enable for DIO sleep value configuration.", + count: "NDioPads", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "DIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding !!DIO_PAD_SLEEP_MODE + is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "DIO_PAD_SLEEP_EN", + desc: '''Enables the sleep mode of the corresponding dedicated pad. + ''' + count: "NDioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "DIO_PAD_SLEEP_REGWEN", + regwen_multi: "true", + cname: "OUT", + fields: [ + { bits: "0", + name: "EN", + resval: 0, + desc: ''' + Deep sleep mode enable. + If this bit is set to 1 the corresponding pad will enable the sleep behavior + specified in !!DIO_PAD_SLEEP_MODE upon deep sleep entry, and the corresponding bit + in !!DIO_PAD_SLEEP_STATUS will be set to 1. + The pad remains in deep sleep mode until the corresponding bit in + !!DIO_PAD_SLEEP_STATUS is cleared by SW. + Note that if an always on peripheral is connected to a specific DIO pad, + the corresponding !!DIO_PAD_SLEEP_EN bit should be set to 0. + ''' + } + ] + } + }, + { multireg: { name: "DIO_PAD_SLEEP_MODE", + desc: '''Defines sleep behavior of the corresponding dedicated pad. + ''' + count: "NDioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "DIO_PAD_SLEEP_REGWEN", + regwen_multi: "true", + cname: "OUT", + fields: [ + { bits: "1:0", + name: "OUT", + resval: 2, + desc: "Value to drive in deep sleep." + enum: [ + { value: "0", + name: "Tie-Low", + desc: "The pad is driven actively to zero in deep sleep mode." + }, + { value: "1", + name: "Tie-High", + desc: "The pad is driven actively to one in deep sleep mode." + }, + { value: "2", + name: "High-Z", + desc: ''' + The pad is left undriven in deep sleep mode. Note that the actual + driving behavior during deep sleep will then depend on the pull-up/-down + configuration of in !!DIO_PAD_ATTR. + ''' + }, + { value: "3", + name: "Keep", + desc: "Keep last driven value (including high-Z)." + }, + ] + } + ] + } + }, +//////////////////////// +// Wakeup detectors // +//////////////////////// { multireg: { name: "WKUP_DETECTOR_REGWEN", desc: "Register write enable for wakeup detectors.", count: "NWkupDetect", @@ -508,7 +696,7 @@ } }, -# wakeup detector config + # wakeup detector config { multireg: { name: "WKUP_DETECTOR", desc: "Configuration of wakeup condition detectors." count: "NWkupDetect", @@ -575,7 +763,6 @@ } }, -# wakeup detector count thresholds { multireg: { name: "WKUP_DETECTOR_CNT_TH", desc: "Counter thresholds for wakeup condition detectors." count: "NWkupDetect", @@ -597,7 +784,6 @@ } }, -# wakeup detector pad selectors { multireg: { name: "WKUP_DETECTOR_PADSEL", desc: "Pad selects for pad wakeup condition detectors." count: "NWkupDetect", @@ -621,7 +807,6 @@ } }, -# wakeup detector cause regs { multireg: { name: "WKUP_CAUSE", desc: "Cause registers for wakeup detectors." count: "NWkupDetect",
diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv index c99b210..1f6ef5e 100644 --- a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv +++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
@@ -7,6 +7,7 @@ package pinmux_reg_pkg; // Param list + parameter int AttrDw = 10; parameter int NMioPeriphIn = 41; parameter int NMioPeriphOut = 45; parameter int NMioPads = 32; @@ -35,13 +36,38 @@ } pinmux_reg2hw_mio_outsel_mreg_t; typedef struct packed { - logic [1:0] q; - } pinmux_reg2hw_mio_out_sleep_val_mreg_t; + logic [9:0] q; + logic qe; + } pinmux_reg2hw_mio_pad_attr_mreg_t; + + typedef struct packed { + logic [9:0] q; + logic qe; + } pinmux_reg2hw_dio_pad_attr_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_mio_pad_sleep_status_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_mio_pad_sleep_en_mreg_t; typedef struct packed { logic [1:0] q; - logic qe; - } pinmux_reg2hw_dio_out_sleep_val_mreg_t; + } pinmux_reg2hw_mio_pad_sleep_mode_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_dio_pad_sleep_status_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_dio_pad_sleep_en_mreg_t; + + typedef struct packed { + logic [1:0] q; + } pinmux_reg2hw_dio_pad_sleep_mode_mreg_t; typedef struct packed { logic q; @@ -74,8 +100,22 @@ typedef struct packed { - logic [1:0] d; - } pinmux_hw2reg_dio_out_sleep_val_mreg_t; + logic [9:0] d; + } pinmux_hw2reg_mio_pad_attr_mreg_t; + + typedef struct packed { + logic [9:0] d; + } pinmux_hw2reg_dio_pad_attr_mreg_t; + + typedef struct packed { + logic d; + logic de; + } pinmux_hw2reg_mio_pad_sleep_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } pinmux_hw2reg_dio_pad_sleep_status_mreg_t; typedef struct packed { logic d; @@ -86,10 +126,16 @@ // Register to internal design logic // /////////////////////////////////////// typedef struct packed { - pinmux_reg2hw_mio_periph_insel_mreg_t [40:0] mio_periph_insel; // [722:477] - pinmux_reg2hw_mio_outsel_mreg_t [31:0] mio_outsel; // [476:285] - pinmux_reg2hw_mio_out_sleep_val_mreg_t [31:0] mio_out_sleep_val; // [284:221] - pinmux_reg2hw_dio_out_sleep_val_mreg_t [14:0] dio_out_sleep_val; // [220:176] + pinmux_reg2hw_mio_periph_insel_mreg_t [40:0] mio_periph_insel; // [1318:1073] + pinmux_reg2hw_mio_outsel_mreg_t [31:0] mio_outsel; // [1072:881] + pinmux_reg2hw_mio_pad_attr_mreg_t [31:0] mio_pad_attr; // [880:529] + pinmux_reg2hw_dio_pad_attr_mreg_t [14:0] dio_pad_attr; // [528:364] + pinmux_reg2hw_mio_pad_sleep_status_mreg_t [31:0] mio_pad_sleep_status; // [363:332] + pinmux_reg2hw_mio_pad_sleep_en_mreg_t [31:0] mio_pad_sleep_en; // [331:300] + pinmux_reg2hw_mio_pad_sleep_mode_mreg_t [31:0] mio_pad_sleep_mode; // [299:236] + pinmux_reg2hw_dio_pad_sleep_status_mreg_t [14:0] dio_pad_sleep_status; // [235:221] + pinmux_reg2hw_dio_pad_sleep_en_mreg_t [14:0] dio_pad_sleep_en; // [220:206] + pinmux_reg2hw_dio_pad_sleep_mode_mreg_t [14:0] dio_pad_sleep_mode; // [205:176] pinmux_reg2hw_wkup_detector_en_mreg_t [7:0] wkup_detector_en; // [175:168] pinmux_reg2hw_wkup_detector_mreg_t [7:0] wkup_detector; // [167:128] pinmux_reg2hw_wkup_detector_cnt_th_mreg_t [7:0] wkup_detector_cnt_th; // [127:64] @@ -101,7 +147,10 @@ // Internal design logic to register // /////////////////////////////////////// typedef struct packed { - pinmux_hw2reg_dio_out_sleep_val_mreg_t [14:0] dio_out_sleep_val; // [37:8] + pinmux_hw2reg_mio_pad_attr_mreg_t [31:0] mio_pad_attr; // [571:252] + pinmux_hw2reg_dio_pad_attr_mreg_t [14:0] dio_pad_attr; // [251:102] + pinmux_hw2reg_mio_pad_sleep_status_mreg_t [31:0] mio_pad_sleep_status; // [101:38] + pinmux_hw2reg_dio_pad_sleep_status_mreg_t [14:0] dio_pad_sleep_status; // [37:8] pinmux_hw2reg_wkup_cause_mreg_t [7:0] wkup_cause; // [7:0] } pinmux_hw2reg_t; @@ -252,141 +301,284 @@ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 11'h 23c; parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 11'h 240; parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 11'h 244; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_0_OFFSET = 11'h 248; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_1_OFFSET = 11'h 24c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_2_OFFSET = 11'h 250; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_3_OFFSET = 11'h 254; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_4_OFFSET = 11'h 258; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_5_OFFSET = 11'h 25c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_6_OFFSET = 11'h 260; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_7_OFFSET = 11'h 264; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_8_OFFSET = 11'h 268; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_9_OFFSET = 11'h 26c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_10_OFFSET = 11'h 270; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_11_OFFSET = 11'h 274; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_12_OFFSET = 11'h 278; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_13_OFFSET = 11'h 27c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_14_OFFSET = 11'h 280; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_15_OFFSET = 11'h 284; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_16_OFFSET = 11'h 288; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_17_OFFSET = 11'h 28c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_18_OFFSET = 11'h 290; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_19_OFFSET = 11'h 294; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_20_OFFSET = 11'h 298; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_21_OFFSET = 11'h 29c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_22_OFFSET = 11'h 2a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_23_OFFSET = 11'h 2a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_24_OFFSET = 11'h 2a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_25_OFFSET = 11'h 2ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_26_OFFSET = 11'h 2b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_27_OFFSET = 11'h 2b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_28_OFFSET = 11'h 2b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_29_OFFSET = 11'h 2bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_30_OFFSET = 11'h 2c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_REGWEN_31_OFFSET = 11'h 2c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_0_OFFSET = 11'h 2c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_1_OFFSET = 11'h 2cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_2_OFFSET = 11'h 2d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_3_OFFSET = 11'h 2d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_4_OFFSET = 11'h 2d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_5_OFFSET = 11'h 2dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_6_OFFSET = 11'h 2e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_7_OFFSET = 11'h 2e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_8_OFFSET = 11'h 2e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_9_OFFSET = 11'h 2ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_10_OFFSET = 11'h 2f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_11_OFFSET = 11'h 2f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_12_OFFSET = 11'h 2f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_13_OFFSET = 11'h 2fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_14_OFFSET = 11'h 300; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_15_OFFSET = 11'h 304; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_16_OFFSET = 11'h 308; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_17_OFFSET = 11'h 30c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_18_OFFSET = 11'h 310; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_19_OFFSET = 11'h 314; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_20_OFFSET = 11'h 318; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_21_OFFSET = 11'h 31c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_22_OFFSET = 11'h 320; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_23_OFFSET = 11'h 324; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_24_OFFSET = 11'h 328; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_25_OFFSET = 11'h 32c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_26_OFFSET = 11'h 330; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_27_OFFSET = 11'h 334; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_28_OFFSET = 11'h 338; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_29_OFFSET = 11'h 33c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_30_OFFSET = 11'h 340; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUT_SLEEP_VAL_31_OFFSET = 11'h 344; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_0_OFFSET = 11'h 348; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_1_OFFSET = 11'h 34c; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_2_OFFSET = 11'h 350; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_3_OFFSET = 11'h 354; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_4_OFFSET = 11'h 358; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_5_OFFSET = 11'h 35c; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_6_OFFSET = 11'h 360; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_7_OFFSET = 11'h 364; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_8_OFFSET = 11'h 368; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_9_OFFSET = 11'h 36c; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_10_OFFSET = 11'h 370; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_11_OFFSET = 11'h 374; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_12_OFFSET = 11'h 378; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_13_OFFSET = 11'h 37c; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_REGWEN_14_OFFSET = 11'h 380; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_0_OFFSET = 11'h 384; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_1_OFFSET = 11'h 388; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_2_OFFSET = 11'h 38c; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_3_OFFSET = 11'h 390; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_4_OFFSET = 11'h 394; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_5_OFFSET = 11'h 398; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_6_OFFSET = 11'h 39c; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_7_OFFSET = 11'h 3a0; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_8_OFFSET = 11'h 3a4; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_9_OFFSET = 11'h 3a8; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_10_OFFSET = 11'h 3ac; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_11_OFFSET = 11'h 3b0; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_12_OFFSET = 11'h 3b4; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_13_OFFSET = 11'h 3b8; - parameter logic [BlockAw-1:0] PINMUX_DIO_OUT_SLEEP_VAL_14_OFFSET = 11'h 3bc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 11'h 3c0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 11'h 3c4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 11'h 3c8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 11'h 3cc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 11'h 3d0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 11'h 3d4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 11'h 3d8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 11'h 3dc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 11'h 3e0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 11'h 3e4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 11'h 3e8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 11'h 3ec; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 11'h 3f0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 11'h 3f4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 11'h 3f8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 11'h 3fc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 11'h 400; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 11'h 404; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 11'h 408; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 11'h 40c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 11'h 410; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 11'h 414; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 11'h 418; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 11'h 41c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 11'h 420; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 11'h 424; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 11'h 428; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 11'h 42c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 11'h 430; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 11'h 434; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 11'h 438; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 11'h 43c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 11'h 440; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 11'h 444; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 11'h 448; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 11'h 44c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 11'h 450; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 11'h 454; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 11'h 458; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 11'h 45c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 11'h 460; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 11'h 248; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 11'h 24c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 11'h 250; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 11'h 254; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 11'h 258; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 11'h 25c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 11'h 260; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 11'h 264; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 11'h 268; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 11'h 26c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 11'h 270; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 11'h 274; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 11'h 278; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 11'h 27c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 11'h 280; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 11'h 284; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 11'h 288; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 11'h 28c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 11'h 290; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 11'h 294; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 11'h 298; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 11'h 29c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 11'h 2a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 11'h 2a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 11'h 2a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 11'h 2ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 11'h 2b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 11'h 2b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 11'h 2b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 11'h 2bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 11'h 2c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 11'h 2c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 11'h 2c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 11'h 2cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 11'h 2d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 11'h 2d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 11'h 2d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 11'h 2dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 11'h 2e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 11'h 2e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 11'h 2e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 11'h 2ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 11'h 2f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 11'h 2f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 11'h 2f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 11'h 2fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 11'h 300; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 11'h 304; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 11'h 308; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 11'h 30c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 11'h 310; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 11'h 314; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 11'h 318; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 11'h 31c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 11'h 320; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 11'h 324; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 11'h 328; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 11'h 32c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 11'h 330; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 11'h 334; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 11'h 338; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 11'h 33c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 11'h 340; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 11'h 344; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 11'h 348; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 11'h 34c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 11'h 350; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 11'h 354; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 11'h 358; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 11'h 35c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 11'h 360; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 11'h 364; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 11'h 368; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 11'h 36c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 11'h 370; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 11'h 374; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 11'h 378; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 11'h 37c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 11'h 380; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 11'h 384; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 11'h 388; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 11'h 38c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 11'h 390; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 11'h 394; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 11'h 398; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 11'h 39c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 11'h 3a0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 11'h 3a4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 11'h 3a8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 11'h 3ac; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 11'h 3b0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 11'h 3b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 11'h 3b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 11'h 3bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_OFFSET = 11'h 3c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 11'h 3c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 11'h 3c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 11'h 3cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 11'h 3d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 11'h 3d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 11'h 3d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 11'h 3dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 11'h 3e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 11'h 3e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 11'h 3e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 11'h 3ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 11'h 3f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 11'h 3f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 11'h 3f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 11'h 3fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 11'h 400; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 11'h 404; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 11'h 408; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 11'h 40c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 11'h 410; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 11'h 414; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 11'h 418; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 11'h 41c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 11'h 420; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 11'h 424; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 11'h 428; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 11'h 42c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 11'h 430; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 11'h 434; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 11'h 438; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 11'h 43c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 11'h 440; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 11'h 444; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 11'h 448; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 11'h 44c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 11'h 450; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 11'h 454; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 11'h 458; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 11'h 45c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 11'h 460; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 11'h 464; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 11'h 468; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 11'h 46c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 11'h 470; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 11'h 474; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 11'h 478; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 11'h 47c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 11'h 480; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 11'h 484; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 11'h 488; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 11'h 48c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 11'h 490; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 11'h 494; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 11'h 498; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 11'h 49c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 11'h 4a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 11'h 4a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 11'h 4a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 11'h 4ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 11'h 4b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 11'h 4b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 11'h 4b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 11'h 4bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 11'h 4c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 11'h 4c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 11'h 4c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 11'h 4cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 11'h 4d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 11'h 4d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 11'h 4d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 11'h 4dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 11'h 4e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 11'h 4e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 11'h 4e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 11'h 4ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 11'h 4f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 11'h 4f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 11'h 4f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 11'h 4fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 11'h 500; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 11'h 504; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 11'h 508; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 11'h 50c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 11'h 510; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 11'h 514; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 11'h 518; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 11'h 51c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 11'h 520; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 11'h 524; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 11'h 528; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 11'h 52c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 11'h 530; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 11'h 534; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 11'h 538; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 11'h 53c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 11'h 540; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET = 11'h 544; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 11'h 548; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 11'h 54c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 11'h 550; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 11'h 554; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 11'h 558; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 11'h 55c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 11'h 560; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 11'h 564; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 11'h 568; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 11'h 56c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 11'h 570; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 11'h 574; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 11'h 578; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 11'h 57c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 11'h 580; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 11'h 584; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 11'h 588; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 11'h 58c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 11'h 590; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 11'h 594; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 11'h 598; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 11'h 59c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 11'h 5a0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 11'h 5a4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 11'h 5a8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 11'h 5ac; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 11'h 5b0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 11'h 5b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 11'h 5b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 11'h 5bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 11'h 5c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 11'h 5c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 11'h 5c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 11'h 5cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 11'h 5d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 11'h 5d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 11'h 5d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 11'h 5dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 11'h 5e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 11'h 5e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 11'h 5e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 11'h 5ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 11'h 5f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 11'h 5f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 11'h 5f8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 11'h 5fc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 11'h 600; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 11'h 604; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 11'h 608; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 11'h 60c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 11'h 610; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 11'h 614; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 11'h 618; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 11'h 61c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 11'h 620; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 11'h 624; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 11'h 628; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 11'h 62c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 11'h 630; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 11'h 634; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 11'h 638; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 11'h 63c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 11'h 640; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 11'h 644; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 11'h 648; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 11'h 64c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 11'h 650; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 11'h 654; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 11'h 658; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 11'h 65c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 11'h 660; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 11'h 664; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 11'h 668; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 11'h 66c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 11'h 670; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 11'h 674; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 11'h 678; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 11'h 67c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 11'h 680; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 11'h 684; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 11'h 688; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 11'h 68c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 11'h 690; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 11'h 694; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 11'h 698; + parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 11'h 69c; // Register Index @@ -537,100 +729,243 @@ PINMUX_MIO_OUTSEL_29, PINMUX_MIO_OUTSEL_30, PINMUX_MIO_OUTSEL_31, - PINMUX_MIO_OUT_SLEEP_REGWEN_0, - PINMUX_MIO_OUT_SLEEP_REGWEN_1, - PINMUX_MIO_OUT_SLEEP_REGWEN_2, - PINMUX_MIO_OUT_SLEEP_REGWEN_3, - PINMUX_MIO_OUT_SLEEP_REGWEN_4, - PINMUX_MIO_OUT_SLEEP_REGWEN_5, - PINMUX_MIO_OUT_SLEEP_REGWEN_6, - PINMUX_MIO_OUT_SLEEP_REGWEN_7, - PINMUX_MIO_OUT_SLEEP_REGWEN_8, - PINMUX_MIO_OUT_SLEEP_REGWEN_9, - PINMUX_MIO_OUT_SLEEP_REGWEN_10, - PINMUX_MIO_OUT_SLEEP_REGWEN_11, - PINMUX_MIO_OUT_SLEEP_REGWEN_12, - PINMUX_MIO_OUT_SLEEP_REGWEN_13, - PINMUX_MIO_OUT_SLEEP_REGWEN_14, - PINMUX_MIO_OUT_SLEEP_REGWEN_15, - PINMUX_MIO_OUT_SLEEP_REGWEN_16, - PINMUX_MIO_OUT_SLEEP_REGWEN_17, - PINMUX_MIO_OUT_SLEEP_REGWEN_18, - PINMUX_MIO_OUT_SLEEP_REGWEN_19, - PINMUX_MIO_OUT_SLEEP_REGWEN_20, - PINMUX_MIO_OUT_SLEEP_REGWEN_21, - PINMUX_MIO_OUT_SLEEP_REGWEN_22, - PINMUX_MIO_OUT_SLEEP_REGWEN_23, - PINMUX_MIO_OUT_SLEEP_REGWEN_24, - PINMUX_MIO_OUT_SLEEP_REGWEN_25, - PINMUX_MIO_OUT_SLEEP_REGWEN_26, - PINMUX_MIO_OUT_SLEEP_REGWEN_27, - PINMUX_MIO_OUT_SLEEP_REGWEN_28, - PINMUX_MIO_OUT_SLEEP_REGWEN_29, - PINMUX_MIO_OUT_SLEEP_REGWEN_30, - PINMUX_MIO_OUT_SLEEP_REGWEN_31, - PINMUX_MIO_OUT_SLEEP_VAL_0, - PINMUX_MIO_OUT_SLEEP_VAL_1, - PINMUX_MIO_OUT_SLEEP_VAL_2, - PINMUX_MIO_OUT_SLEEP_VAL_3, - PINMUX_MIO_OUT_SLEEP_VAL_4, - PINMUX_MIO_OUT_SLEEP_VAL_5, - PINMUX_MIO_OUT_SLEEP_VAL_6, - PINMUX_MIO_OUT_SLEEP_VAL_7, - PINMUX_MIO_OUT_SLEEP_VAL_8, - PINMUX_MIO_OUT_SLEEP_VAL_9, - PINMUX_MIO_OUT_SLEEP_VAL_10, - PINMUX_MIO_OUT_SLEEP_VAL_11, - PINMUX_MIO_OUT_SLEEP_VAL_12, - PINMUX_MIO_OUT_SLEEP_VAL_13, - PINMUX_MIO_OUT_SLEEP_VAL_14, - PINMUX_MIO_OUT_SLEEP_VAL_15, - PINMUX_MIO_OUT_SLEEP_VAL_16, - PINMUX_MIO_OUT_SLEEP_VAL_17, - PINMUX_MIO_OUT_SLEEP_VAL_18, - PINMUX_MIO_OUT_SLEEP_VAL_19, - PINMUX_MIO_OUT_SLEEP_VAL_20, - PINMUX_MIO_OUT_SLEEP_VAL_21, - PINMUX_MIO_OUT_SLEEP_VAL_22, - PINMUX_MIO_OUT_SLEEP_VAL_23, - PINMUX_MIO_OUT_SLEEP_VAL_24, - PINMUX_MIO_OUT_SLEEP_VAL_25, - PINMUX_MIO_OUT_SLEEP_VAL_26, - PINMUX_MIO_OUT_SLEEP_VAL_27, - PINMUX_MIO_OUT_SLEEP_VAL_28, - PINMUX_MIO_OUT_SLEEP_VAL_29, - PINMUX_MIO_OUT_SLEEP_VAL_30, - PINMUX_MIO_OUT_SLEEP_VAL_31, - PINMUX_DIO_OUT_SLEEP_REGWEN_0, - PINMUX_DIO_OUT_SLEEP_REGWEN_1, - PINMUX_DIO_OUT_SLEEP_REGWEN_2, - PINMUX_DIO_OUT_SLEEP_REGWEN_3, - PINMUX_DIO_OUT_SLEEP_REGWEN_4, - PINMUX_DIO_OUT_SLEEP_REGWEN_5, - PINMUX_DIO_OUT_SLEEP_REGWEN_6, - PINMUX_DIO_OUT_SLEEP_REGWEN_7, - PINMUX_DIO_OUT_SLEEP_REGWEN_8, - PINMUX_DIO_OUT_SLEEP_REGWEN_9, - PINMUX_DIO_OUT_SLEEP_REGWEN_10, - PINMUX_DIO_OUT_SLEEP_REGWEN_11, - PINMUX_DIO_OUT_SLEEP_REGWEN_12, - PINMUX_DIO_OUT_SLEEP_REGWEN_13, - PINMUX_DIO_OUT_SLEEP_REGWEN_14, - PINMUX_DIO_OUT_SLEEP_VAL_0, - PINMUX_DIO_OUT_SLEEP_VAL_1, - PINMUX_DIO_OUT_SLEEP_VAL_2, - PINMUX_DIO_OUT_SLEEP_VAL_3, - PINMUX_DIO_OUT_SLEEP_VAL_4, - PINMUX_DIO_OUT_SLEEP_VAL_5, - PINMUX_DIO_OUT_SLEEP_VAL_6, - PINMUX_DIO_OUT_SLEEP_VAL_7, - PINMUX_DIO_OUT_SLEEP_VAL_8, - PINMUX_DIO_OUT_SLEEP_VAL_9, - PINMUX_DIO_OUT_SLEEP_VAL_10, - PINMUX_DIO_OUT_SLEEP_VAL_11, - PINMUX_DIO_OUT_SLEEP_VAL_12, - PINMUX_DIO_OUT_SLEEP_VAL_13, - PINMUX_DIO_OUT_SLEEP_VAL_14, + PINMUX_MIO_PAD_ATTR_REGWEN_0, + PINMUX_MIO_PAD_ATTR_REGWEN_1, + PINMUX_MIO_PAD_ATTR_REGWEN_2, + PINMUX_MIO_PAD_ATTR_REGWEN_3, + PINMUX_MIO_PAD_ATTR_REGWEN_4, + PINMUX_MIO_PAD_ATTR_REGWEN_5, + PINMUX_MIO_PAD_ATTR_REGWEN_6, + PINMUX_MIO_PAD_ATTR_REGWEN_7, + PINMUX_MIO_PAD_ATTR_REGWEN_8, + PINMUX_MIO_PAD_ATTR_REGWEN_9, + PINMUX_MIO_PAD_ATTR_REGWEN_10, + PINMUX_MIO_PAD_ATTR_REGWEN_11, + PINMUX_MIO_PAD_ATTR_REGWEN_12, + PINMUX_MIO_PAD_ATTR_REGWEN_13, + PINMUX_MIO_PAD_ATTR_REGWEN_14, + PINMUX_MIO_PAD_ATTR_REGWEN_15, + PINMUX_MIO_PAD_ATTR_REGWEN_16, + PINMUX_MIO_PAD_ATTR_REGWEN_17, + PINMUX_MIO_PAD_ATTR_REGWEN_18, + PINMUX_MIO_PAD_ATTR_REGWEN_19, + PINMUX_MIO_PAD_ATTR_REGWEN_20, + PINMUX_MIO_PAD_ATTR_REGWEN_21, + PINMUX_MIO_PAD_ATTR_REGWEN_22, + PINMUX_MIO_PAD_ATTR_REGWEN_23, + PINMUX_MIO_PAD_ATTR_REGWEN_24, + PINMUX_MIO_PAD_ATTR_REGWEN_25, + PINMUX_MIO_PAD_ATTR_REGWEN_26, + PINMUX_MIO_PAD_ATTR_REGWEN_27, + PINMUX_MIO_PAD_ATTR_REGWEN_28, + PINMUX_MIO_PAD_ATTR_REGWEN_29, + PINMUX_MIO_PAD_ATTR_REGWEN_30, + PINMUX_MIO_PAD_ATTR_REGWEN_31, + PINMUX_MIO_PAD_ATTR_0, + PINMUX_MIO_PAD_ATTR_1, + PINMUX_MIO_PAD_ATTR_2, + PINMUX_MIO_PAD_ATTR_3, + PINMUX_MIO_PAD_ATTR_4, + PINMUX_MIO_PAD_ATTR_5, + PINMUX_MIO_PAD_ATTR_6, + PINMUX_MIO_PAD_ATTR_7, + PINMUX_MIO_PAD_ATTR_8, + PINMUX_MIO_PAD_ATTR_9, + PINMUX_MIO_PAD_ATTR_10, + PINMUX_MIO_PAD_ATTR_11, + PINMUX_MIO_PAD_ATTR_12, + PINMUX_MIO_PAD_ATTR_13, + PINMUX_MIO_PAD_ATTR_14, + PINMUX_MIO_PAD_ATTR_15, + PINMUX_MIO_PAD_ATTR_16, + PINMUX_MIO_PAD_ATTR_17, + PINMUX_MIO_PAD_ATTR_18, + PINMUX_MIO_PAD_ATTR_19, + PINMUX_MIO_PAD_ATTR_20, + PINMUX_MIO_PAD_ATTR_21, + PINMUX_MIO_PAD_ATTR_22, + PINMUX_MIO_PAD_ATTR_23, + PINMUX_MIO_PAD_ATTR_24, + PINMUX_MIO_PAD_ATTR_25, + PINMUX_MIO_PAD_ATTR_26, + PINMUX_MIO_PAD_ATTR_27, + PINMUX_MIO_PAD_ATTR_28, + PINMUX_MIO_PAD_ATTR_29, + PINMUX_MIO_PAD_ATTR_30, + PINMUX_MIO_PAD_ATTR_31, + PINMUX_DIO_PAD_ATTR_REGWEN_0, + PINMUX_DIO_PAD_ATTR_REGWEN_1, + PINMUX_DIO_PAD_ATTR_REGWEN_2, + PINMUX_DIO_PAD_ATTR_REGWEN_3, + PINMUX_DIO_PAD_ATTR_REGWEN_4, + PINMUX_DIO_PAD_ATTR_REGWEN_5, + PINMUX_DIO_PAD_ATTR_REGWEN_6, + PINMUX_DIO_PAD_ATTR_REGWEN_7, + PINMUX_DIO_PAD_ATTR_REGWEN_8, + PINMUX_DIO_PAD_ATTR_REGWEN_9, + PINMUX_DIO_PAD_ATTR_REGWEN_10, + PINMUX_DIO_PAD_ATTR_REGWEN_11, + PINMUX_DIO_PAD_ATTR_REGWEN_12, + PINMUX_DIO_PAD_ATTR_REGWEN_13, + PINMUX_DIO_PAD_ATTR_REGWEN_14, + PINMUX_DIO_PAD_ATTR_0, + PINMUX_DIO_PAD_ATTR_1, + PINMUX_DIO_PAD_ATTR_2, + PINMUX_DIO_PAD_ATTR_3, + PINMUX_DIO_PAD_ATTR_4, + PINMUX_DIO_PAD_ATTR_5, + PINMUX_DIO_PAD_ATTR_6, + PINMUX_DIO_PAD_ATTR_7, + PINMUX_DIO_PAD_ATTR_8, + PINMUX_DIO_PAD_ATTR_9, + PINMUX_DIO_PAD_ATTR_10, + PINMUX_DIO_PAD_ATTR_11, + PINMUX_DIO_PAD_ATTR_12, + PINMUX_DIO_PAD_ATTR_13, + PINMUX_DIO_PAD_ATTR_14, + PINMUX_MIO_PAD_SLEEP_STATUS, + PINMUX_MIO_PAD_SLEEP_REGWEN_0, + PINMUX_MIO_PAD_SLEEP_REGWEN_1, + PINMUX_MIO_PAD_SLEEP_REGWEN_2, + PINMUX_MIO_PAD_SLEEP_REGWEN_3, + PINMUX_MIO_PAD_SLEEP_REGWEN_4, + PINMUX_MIO_PAD_SLEEP_REGWEN_5, + PINMUX_MIO_PAD_SLEEP_REGWEN_6, + PINMUX_MIO_PAD_SLEEP_REGWEN_7, + PINMUX_MIO_PAD_SLEEP_REGWEN_8, + PINMUX_MIO_PAD_SLEEP_REGWEN_9, + PINMUX_MIO_PAD_SLEEP_REGWEN_10, + PINMUX_MIO_PAD_SLEEP_REGWEN_11, + PINMUX_MIO_PAD_SLEEP_REGWEN_12, + PINMUX_MIO_PAD_SLEEP_REGWEN_13, + PINMUX_MIO_PAD_SLEEP_REGWEN_14, + PINMUX_MIO_PAD_SLEEP_REGWEN_15, + PINMUX_MIO_PAD_SLEEP_REGWEN_16, + PINMUX_MIO_PAD_SLEEP_REGWEN_17, + PINMUX_MIO_PAD_SLEEP_REGWEN_18, + PINMUX_MIO_PAD_SLEEP_REGWEN_19, + PINMUX_MIO_PAD_SLEEP_REGWEN_20, + PINMUX_MIO_PAD_SLEEP_REGWEN_21, + PINMUX_MIO_PAD_SLEEP_REGWEN_22, + PINMUX_MIO_PAD_SLEEP_REGWEN_23, + PINMUX_MIO_PAD_SLEEP_REGWEN_24, + PINMUX_MIO_PAD_SLEEP_REGWEN_25, + PINMUX_MIO_PAD_SLEEP_REGWEN_26, + PINMUX_MIO_PAD_SLEEP_REGWEN_27, + PINMUX_MIO_PAD_SLEEP_REGWEN_28, + PINMUX_MIO_PAD_SLEEP_REGWEN_29, + PINMUX_MIO_PAD_SLEEP_REGWEN_30, + PINMUX_MIO_PAD_SLEEP_REGWEN_31, + PINMUX_MIO_PAD_SLEEP_EN_0, + PINMUX_MIO_PAD_SLEEP_EN_1, + PINMUX_MIO_PAD_SLEEP_EN_2, + PINMUX_MIO_PAD_SLEEP_EN_3, + PINMUX_MIO_PAD_SLEEP_EN_4, + PINMUX_MIO_PAD_SLEEP_EN_5, + PINMUX_MIO_PAD_SLEEP_EN_6, + PINMUX_MIO_PAD_SLEEP_EN_7, + PINMUX_MIO_PAD_SLEEP_EN_8, + PINMUX_MIO_PAD_SLEEP_EN_9, + PINMUX_MIO_PAD_SLEEP_EN_10, + PINMUX_MIO_PAD_SLEEP_EN_11, + PINMUX_MIO_PAD_SLEEP_EN_12, + PINMUX_MIO_PAD_SLEEP_EN_13, + PINMUX_MIO_PAD_SLEEP_EN_14, + PINMUX_MIO_PAD_SLEEP_EN_15, + PINMUX_MIO_PAD_SLEEP_EN_16, + PINMUX_MIO_PAD_SLEEP_EN_17, + PINMUX_MIO_PAD_SLEEP_EN_18, + PINMUX_MIO_PAD_SLEEP_EN_19, + PINMUX_MIO_PAD_SLEEP_EN_20, + PINMUX_MIO_PAD_SLEEP_EN_21, + PINMUX_MIO_PAD_SLEEP_EN_22, + PINMUX_MIO_PAD_SLEEP_EN_23, + PINMUX_MIO_PAD_SLEEP_EN_24, + PINMUX_MIO_PAD_SLEEP_EN_25, + PINMUX_MIO_PAD_SLEEP_EN_26, + PINMUX_MIO_PAD_SLEEP_EN_27, + PINMUX_MIO_PAD_SLEEP_EN_28, + PINMUX_MIO_PAD_SLEEP_EN_29, + PINMUX_MIO_PAD_SLEEP_EN_30, + PINMUX_MIO_PAD_SLEEP_EN_31, + PINMUX_MIO_PAD_SLEEP_MODE_0, + PINMUX_MIO_PAD_SLEEP_MODE_1, + PINMUX_MIO_PAD_SLEEP_MODE_2, + PINMUX_MIO_PAD_SLEEP_MODE_3, + PINMUX_MIO_PAD_SLEEP_MODE_4, + PINMUX_MIO_PAD_SLEEP_MODE_5, + PINMUX_MIO_PAD_SLEEP_MODE_6, + PINMUX_MIO_PAD_SLEEP_MODE_7, + PINMUX_MIO_PAD_SLEEP_MODE_8, + PINMUX_MIO_PAD_SLEEP_MODE_9, + PINMUX_MIO_PAD_SLEEP_MODE_10, + PINMUX_MIO_PAD_SLEEP_MODE_11, + PINMUX_MIO_PAD_SLEEP_MODE_12, + PINMUX_MIO_PAD_SLEEP_MODE_13, + PINMUX_MIO_PAD_SLEEP_MODE_14, + PINMUX_MIO_PAD_SLEEP_MODE_15, + PINMUX_MIO_PAD_SLEEP_MODE_16, + PINMUX_MIO_PAD_SLEEP_MODE_17, + PINMUX_MIO_PAD_SLEEP_MODE_18, + PINMUX_MIO_PAD_SLEEP_MODE_19, + PINMUX_MIO_PAD_SLEEP_MODE_20, + PINMUX_MIO_PAD_SLEEP_MODE_21, + PINMUX_MIO_PAD_SLEEP_MODE_22, + PINMUX_MIO_PAD_SLEEP_MODE_23, + PINMUX_MIO_PAD_SLEEP_MODE_24, + PINMUX_MIO_PAD_SLEEP_MODE_25, + PINMUX_MIO_PAD_SLEEP_MODE_26, + PINMUX_MIO_PAD_SLEEP_MODE_27, + PINMUX_MIO_PAD_SLEEP_MODE_28, + PINMUX_MIO_PAD_SLEEP_MODE_29, + PINMUX_MIO_PAD_SLEEP_MODE_30, + PINMUX_MIO_PAD_SLEEP_MODE_31, + PINMUX_DIO_PAD_SLEEP_STATUS, + PINMUX_DIO_PAD_SLEEP_REGWEN_0, + PINMUX_DIO_PAD_SLEEP_REGWEN_1, + PINMUX_DIO_PAD_SLEEP_REGWEN_2, + PINMUX_DIO_PAD_SLEEP_REGWEN_3, + PINMUX_DIO_PAD_SLEEP_REGWEN_4, + PINMUX_DIO_PAD_SLEEP_REGWEN_5, + PINMUX_DIO_PAD_SLEEP_REGWEN_6, + PINMUX_DIO_PAD_SLEEP_REGWEN_7, + PINMUX_DIO_PAD_SLEEP_REGWEN_8, + PINMUX_DIO_PAD_SLEEP_REGWEN_9, + PINMUX_DIO_PAD_SLEEP_REGWEN_10, + PINMUX_DIO_PAD_SLEEP_REGWEN_11, + PINMUX_DIO_PAD_SLEEP_REGWEN_12, + PINMUX_DIO_PAD_SLEEP_REGWEN_13, + PINMUX_DIO_PAD_SLEEP_REGWEN_14, + PINMUX_DIO_PAD_SLEEP_EN_0, + PINMUX_DIO_PAD_SLEEP_EN_1, + PINMUX_DIO_PAD_SLEEP_EN_2, + PINMUX_DIO_PAD_SLEEP_EN_3, + PINMUX_DIO_PAD_SLEEP_EN_4, + PINMUX_DIO_PAD_SLEEP_EN_5, + PINMUX_DIO_PAD_SLEEP_EN_6, + PINMUX_DIO_PAD_SLEEP_EN_7, + PINMUX_DIO_PAD_SLEEP_EN_8, + PINMUX_DIO_PAD_SLEEP_EN_9, + PINMUX_DIO_PAD_SLEEP_EN_10, + PINMUX_DIO_PAD_SLEEP_EN_11, + PINMUX_DIO_PAD_SLEEP_EN_12, + PINMUX_DIO_PAD_SLEEP_EN_13, + PINMUX_DIO_PAD_SLEEP_EN_14, + PINMUX_DIO_PAD_SLEEP_MODE_0, + PINMUX_DIO_PAD_SLEEP_MODE_1, + PINMUX_DIO_PAD_SLEEP_MODE_2, + PINMUX_DIO_PAD_SLEEP_MODE_3, + PINMUX_DIO_PAD_SLEEP_MODE_4, + PINMUX_DIO_PAD_SLEEP_MODE_5, + PINMUX_DIO_PAD_SLEEP_MODE_6, + PINMUX_DIO_PAD_SLEEP_MODE_7, + PINMUX_DIO_PAD_SLEEP_MODE_8, + PINMUX_DIO_PAD_SLEEP_MODE_9, + PINMUX_DIO_PAD_SLEEP_MODE_10, + PINMUX_DIO_PAD_SLEEP_MODE_11, + PINMUX_DIO_PAD_SLEEP_MODE_12, + PINMUX_DIO_PAD_SLEEP_MODE_13, + PINMUX_DIO_PAD_SLEEP_MODE_14, PINMUX_WKUP_DETECTOR_REGWEN_0, PINMUX_WKUP_DETECTOR_REGWEN_1, PINMUX_WKUP_DETECTOR_REGWEN_2, @@ -675,7 +1010,7 @@ } pinmux_id_e; // Register width information to check illegal writes - parameter logic [3:0] PINMUX_PERMIT [281] = '{ + parameter logic [3:0] PINMUX_PERMIT [424] = '{ 4'b 0001, // index[ 0] PINMUX_MIO_PERIPH_INSEL_REGWEN_0 4'b 0001, // index[ 1] PINMUX_MIO_PERIPH_INSEL_REGWEN_1 4'b 0001, // index[ 2] PINMUX_MIO_PERIPH_INSEL_REGWEN_2 @@ -822,141 +1157,284 @@ 4'b 0001, // index[143] PINMUX_MIO_OUTSEL_29 4'b 0001, // index[144] PINMUX_MIO_OUTSEL_30 4'b 0001, // index[145] PINMUX_MIO_OUTSEL_31 - 4'b 0001, // index[146] PINMUX_MIO_OUT_SLEEP_REGWEN_0 - 4'b 0001, // index[147] PINMUX_MIO_OUT_SLEEP_REGWEN_1 - 4'b 0001, // index[148] PINMUX_MIO_OUT_SLEEP_REGWEN_2 - 4'b 0001, // index[149] PINMUX_MIO_OUT_SLEEP_REGWEN_3 - 4'b 0001, // index[150] PINMUX_MIO_OUT_SLEEP_REGWEN_4 - 4'b 0001, // index[151] PINMUX_MIO_OUT_SLEEP_REGWEN_5 - 4'b 0001, // index[152] PINMUX_MIO_OUT_SLEEP_REGWEN_6 - 4'b 0001, // index[153] PINMUX_MIO_OUT_SLEEP_REGWEN_7 - 4'b 0001, // index[154] PINMUX_MIO_OUT_SLEEP_REGWEN_8 - 4'b 0001, // index[155] PINMUX_MIO_OUT_SLEEP_REGWEN_9 - 4'b 0001, // index[156] PINMUX_MIO_OUT_SLEEP_REGWEN_10 - 4'b 0001, // index[157] PINMUX_MIO_OUT_SLEEP_REGWEN_11 - 4'b 0001, // index[158] PINMUX_MIO_OUT_SLEEP_REGWEN_12 - 4'b 0001, // index[159] PINMUX_MIO_OUT_SLEEP_REGWEN_13 - 4'b 0001, // index[160] PINMUX_MIO_OUT_SLEEP_REGWEN_14 - 4'b 0001, // index[161] PINMUX_MIO_OUT_SLEEP_REGWEN_15 - 4'b 0001, // index[162] PINMUX_MIO_OUT_SLEEP_REGWEN_16 - 4'b 0001, // index[163] PINMUX_MIO_OUT_SLEEP_REGWEN_17 - 4'b 0001, // index[164] PINMUX_MIO_OUT_SLEEP_REGWEN_18 - 4'b 0001, // index[165] PINMUX_MIO_OUT_SLEEP_REGWEN_19 - 4'b 0001, // index[166] PINMUX_MIO_OUT_SLEEP_REGWEN_20 - 4'b 0001, // index[167] PINMUX_MIO_OUT_SLEEP_REGWEN_21 - 4'b 0001, // index[168] PINMUX_MIO_OUT_SLEEP_REGWEN_22 - 4'b 0001, // index[169] PINMUX_MIO_OUT_SLEEP_REGWEN_23 - 4'b 0001, // index[170] PINMUX_MIO_OUT_SLEEP_REGWEN_24 - 4'b 0001, // index[171] PINMUX_MIO_OUT_SLEEP_REGWEN_25 - 4'b 0001, // index[172] PINMUX_MIO_OUT_SLEEP_REGWEN_26 - 4'b 0001, // index[173] PINMUX_MIO_OUT_SLEEP_REGWEN_27 - 4'b 0001, // index[174] PINMUX_MIO_OUT_SLEEP_REGWEN_28 - 4'b 0001, // index[175] PINMUX_MIO_OUT_SLEEP_REGWEN_29 - 4'b 0001, // index[176] PINMUX_MIO_OUT_SLEEP_REGWEN_30 - 4'b 0001, // index[177] PINMUX_MIO_OUT_SLEEP_REGWEN_31 - 4'b 0001, // index[178] PINMUX_MIO_OUT_SLEEP_VAL_0 - 4'b 0001, // index[179] PINMUX_MIO_OUT_SLEEP_VAL_1 - 4'b 0001, // index[180] PINMUX_MIO_OUT_SLEEP_VAL_2 - 4'b 0001, // index[181] PINMUX_MIO_OUT_SLEEP_VAL_3 - 4'b 0001, // index[182] PINMUX_MIO_OUT_SLEEP_VAL_4 - 4'b 0001, // index[183] PINMUX_MIO_OUT_SLEEP_VAL_5 - 4'b 0001, // index[184] PINMUX_MIO_OUT_SLEEP_VAL_6 - 4'b 0001, // index[185] PINMUX_MIO_OUT_SLEEP_VAL_7 - 4'b 0001, // index[186] PINMUX_MIO_OUT_SLEEP_VAL_8 - 4'b 0001, // index[187] PINMUX_MIO_OUT_SLEEP_VAL_9 - 4'b 0001, // index[188] PINMUX_MIO_OUT_SLEEP_VAL_10 - 4'b 0001, // index[189] PINMUX_MIO_OUT_SLEEP_VAL_11 - 4'b 0001, // index[190] PINMUX_MIO_OUT_SLEEP_VAL_12 - 4'b 0001, // index[191] PINMUX_MIO_OUT_SLEEP_VAL_13 - 4'b 0001, // index[192] PINMUX_MIO_OUT_SLEEP_VAL_14 - 4'b 0001, // index[193] PINMUX_MIO_OUT_SLEEP_VAL_15 - 4'b 0001, // index[194] PINMUX_MIO_OUT_SLEEP_VAL_16 - 4'b 0001, // index[195] PINMUX_MIO_OUT_SLEEP_VAL_17 - 4'b 0001, // index[196] PINMUX_MIO_OUT_SLEEP_VAL_18 - 4'b 0001, // index[197] PINMUX_MIO_OUT_SLEEP_VAL_19 - 4'b 0001, // index[198] PINMUX_MIO_OUT_SLEEP_VAL_20 - 4'b 0001, // index[199] PINMUX_MIO_OUT_SLEEP_VAL_21 - 4'b 0001, // index[200] PINMUX_MIO_OUT_SLEEP_VAL_22 - 4'b 0001, // index[201] PINMUX_MIO_OUT_SLEEP_VAL_23 - 4'b 0001, // index[202] PINMUX_MIO_OUT_SLEEP_VAL_24 - 4'b 0001, // index[203] PINMUX_MIO_OUT_SLEEP_VAL_25 - 4'b 0001, // index[204] PINMUX_MIO_OUT_SLEEP_VAL_26 - 4'b 0001, // index[205] PINMUX_MIO_OUT_SLEEP_VAL_27 - 4'b 0001, // index[206] PINMUX_MIO_OUT_SLEEP_VAL_28 - 4'b 0001, // index[207] PINMUX_MIO_OUT_SLEEP_VAL_29 - 4'b 0001, // index[208] PINMUX_MIO_OUT_SLEEP_VAL_30 - 4'b 0001, // index[209] PINMUX_MIO_OUT_SLEEP_VAL_31 - 4'b 0001, // index[210] PINMUX_DIO_OUT_SLEEP_REGWEN_0 - 4'b 0001, // index[211] PINMUX_DIO_OUT_SLEEP_REGWEN_1 - 4'b 0001, // index[212] PINMUX_DIO_OUT_SLEEP_REGWEN_2 - 4'b 0001, // index[213] PINMUX_DIO_OUT_SLEEP_REGWEN_3 - 4'b 0001, // index[214] PINMUX_DIO_OUT_SLEEP_REGWEN_4 - 4'b 0001, // index[215] PINMUX_DIO_OUT_SLEEP_REGWEN_5 - 4'b 0001, // index[216] PINMUX_DIO_OUT_SLEEP_REGWEN_6 - 4'b 0001, // index[217] PINMUX_DIO_OUT_SLEEP_REGWEN_7 - 4'b 0001, // index[218] PINMUX_DIO_OUT_SLEEP_REGWEN_8 - 4'b 0001, // index[219] PINMUX_DIO_OUT_SLEEP_REGWEN_9 - 4'b 0001, // index[220] PINMUX_DIO_OUT_SLEEP_REGWEN_10 - 4'b 0001, // index[221] PINMUX_DIO_OUT_SLEEP_REGWEN_11 - 4'b 0001, // index[222] PINMUX_DIO_OUT_SLEEP_REGWEN_12 - 4'b 0001, // index[223] PINMUX_DIO_OUT_SLEEP_REGWEN_13 - 4'b 0001, // index[224] PINMUX_DIO_OUT_SLEEP_REGWEN_14 - 4'b 0001, // index[225] PINMUX_DIO_OUT_SLEEP_VAL_0 - 4'b 0001, // index[226] PINMUX_DIO_OUT_SLEEP_VAL_1 - 4'b 0001, // index[227] PINMUX_DIO_OUT_SLEEP_VAL_2 - 4'b 0001, // index[228] PINMUX_DIO_OUT_SLEEP_VAL_3 - 4'b 0001, // index[229] PINMUX_DIO_OUT_SLEEP_VAL_4 - 4'b 0001, // index[230] PINMUX_DIO_OUT_SLEEP_VAL_5 - 4'b 0001, // index[231] PINMUX_DIO_OUT_SLEEP_VAL_6 - 4'b 0001, // index[232] PINMUX_DIO_OUT_SLEEP_VAL_7 - 4'b 0001, // index[233] PINMUX_DIO_OUT_SLEEP_VAL_8 - 4'b 0001, // index[234] PINMUX_DIO_OUT_SLEEP_VAL_9 - 4'b 0001, // index[235] PINMUX_DIO_OUT_SLEEP_VAL_10 - 4'b 0001, // index[236] PINMUX_DIO_OUT_SLEEP_VAL_11 - 4'b 0001, // index[237] PINMUX_DIO_OUT_SLEEP_VAL_12 - 4'b 0001, // index[238] PINMUX_DIO_OUT_SLEEP_VAL_13 - 4'b 0001, // index[239] PINMUX_DIO_OUT_SLEEP_VAL_14 - 4'b 0001, // index[240] PINMUX_WKUP_DETECTOR_REGWEN_0 - 4'b 0001, // index[241] PINMUX_WKUP_DETECTOR_REGWEN_1 - 4'b 0001, // index[242] PINMUX_WKUP_DETECTOR_REGWEN_2 - 4'b 0001, // index[243] PINMUX_WKUP_DETECTOR_REGWEN_3 - 4'b 0001, // index[244] PINMUX_WKUP_DETECTOR_REGWEN_4 - 4'b 0001, // index[245] PINMUX_WKUP_DETECTOR_REGWEN_5 - 4'b 0001, // index[246] PINMUX_WKUP_DETECTOR_REGWEN_6 - 4'b 0001, // index[247] PINMUX_WKUP_DETECTOR_REGWEN_7 - 4'b 0001, // index[248] PINMUX_WKUP_DETECTOR_EN_0 - 4'b 0001, // index[249] PINMUX_WKUP_DETECTOR_EN_1 - 4'b 0001, // index[250] PINMUX_WKUP_DETECTOR_EN_2 - 4'b 0001, // index[251] PINMUX_WKUP_DETECTOR_EN_3 - 4'b 0001, // index[252] PINMUX_WKUP_DETECTOR_EN_4 - 4'b 0001, // index[253] PINMUX_WKUP_DETECTOR_EN_5 - 4'b 0001, // index[254] PINMUX_WKUP_DETECTOR_EN_6 - 4'b 0001, // index[255] PINMUX_WKUP_DETECTOR_EN_7 - 4'b 0001, // index[256] PINMUX_WKUP_DETECTOR_0 - 4'b 0001, // index[257] PINMUX_WKUP_DETECTOR_1 - 4'b 0001, // index[258] PINMUX_WKUP_DETECTOR_2 - 4'b 0001, // index[259] PINMUX_WKUP_DETECTOR_3 - 4'b 0001, // index[260] PINMUX_WKUP_DETECTOR_4 - 4'b 0001, // index[261] PINMUX_WKUP_DETECTOR_5 - 4'b 0001, // index[262] PINMUX_WKUP_DETECTOR_6 - 4'b 0001, // index[263] PINMUX_WKUP_DETECTOR_7 - 4'b 0001, // index[264] PINMUX_WKUP_DETECTOR_CNT_TH_0 - 4'b 0001, // index[265] PINMUX_WKUP_DETECTOR_CNT_TH_1 - 4'b 0001, // index[266] PINMUX_WKUP_DETECTOR_CNT_TH_2 - 4'b 0001, // index[267] PINMUX_WKUP_DETECTOR_CNT_TH_3 - 4'b 0001, // index[268] PINMUX_WKUP_DETECTOR_CNT_TH_4 - 4'b 0001, // index[269] PINMUX_WKUP_DETECTOR_CNT_TH_5 - 4'b 0001, // index[270] PINMUX_WKUP_DETECTOR_CNT_TH_6 - 4'b 0001, // index[271] PINMUX_WKUP_DETECTOR_CNT_TH_7 - 4'b 0001, // index[272] PINMUX_WKUP_DETECTOR_PADSEL_0 - 4'b 0001, // index[273] PINMUX_WKUP_DETECTOR_PADSEL_1 - 4'b 0001, // index[274] PINMUX_WKUP_DETECTOR_PADSEL_2 - 4'b 0001, // index[275] PINMUX_WKUP_DETECTOR_PADSEL_3 - 4'b 0001, // index[276] PINMUX_WKUP_DETECTOR_PADSEL_4 - 4'b 0001, // index[277] PINMUX_WKUP_DETECTOR_PADSEL_5 - 4'b 0001, // index[278] PINMUX_WKUP_DETECTOR_PADSEL_6 - 4'b 0001, // index[279] PINMUX_WKUP_DETECTOR_PADSEL_7 - 4'b 0001 // index[280] PINMUX_WKUP_CAUSE + 4'b 0001, // index[146] PINMUX_MIO_PAD_ATTR_REGWEN_0 + 4'b 0001, // index[147] PINMUX_MIO_PAD_ATTR_REGWEN_1 + 4'b 0001, // index[148] PINMUX_MIO_PAD_ATTR_REGWEN_2 + 4'b 0001, // index[149] PINMUX_MIO_PAD_ATTR_REGWEN_3 + 4'b 0001, // index[150] PINMUX_MIO_PAD_ATTR_REGWEN_4 + 4'b 0001, // index[151] PINMUX_MIO_PAD_ATTR_REGWEN_5 + 4'b 0001, // index[152] PINMUX_MIO_PAD_ATTR_REGWEN_6 + 4'b 0001, // index[153] PINMUX_MIO_PAD_ATTR_REGWEN_7 + 4'b 0001, // index[154] PINMUX_MIO_PAD_ATTR_REGWEN_8 + 4'b 0001, // index[155] PINMUX_MIO_PAD_ATTR_REGWEN_9 + 4'b 0001, // index[156] PINMUX_MIO_PAD_ATTR_REGWEN_10 + 4'b 0001, // index[157] PINMUX_MIO_PAD_ATTR_REGWEN_11 + 4'b 0001, // index[158] PINMUX_MIO_PAD_ATTR_REGWEN_12 + 4'b 0001, // index[159] PINMUX_MIO_PAD_ATTR_REGWEN_13 + 4'b 0001, // index[160] PINMUX_MIO_PAD_ATTR_REGWEN_14 + 4'b 0001, // index[161] PINMUX_MIO_PAD_ATTR_REGWEN_15 + 4'b 0001, // index[162] PINMUX_MIO_PAD_ATTR_REGWEN_16 + 4'b 0001, // index[163] PINMUX_MIO_PAD_ATTR_REGWEN_17 + 4'b 0001, // index[164] PINMUX_MIO_PAD_ATTR_REGWEN_18 + 4'b 0001, // index[165] PINMUX_MIO_PAD_ATTR_REGWEN_19 + 4'b 0001, // index[166] PINMUX_MIO_PAD_ATTR_REGWEN_20 + 4'b 0001, // index[167] PINMUX_MIO_PAD_ATTR_REGWEN_21 + 4'b 0001, // index[168] PINMUX_MIO_PAD_ATTR_REGWEN_22 + 4'b 0001, // index[169] PINMUX_MIO_PAD_ATTR_REGWEN_23 + 4'b 0001, // index[170] PINMUX_MIO_PAD_ATTR_REGWEN_24 + 4'b 0001, // index[171] PINMUX_MIO_PAD_ATTR_REGWEN_25 + 4'b 0001, // index[172] PINMUX_MIO_PAD_ATTR_REGWEN_26 + 4'b 0001, // index[173] PINMUX_MIO_PAD_ATTR_REGWEN_27 + 4'b 0001, // index[174] PINMUX_MIO_PAD_ATTR_REGWEN_28 + 4'b 0001, // index[175] PINMUX_MIO_PAD_ATTR_REGWEN_29 + 4'b 0001, // index[176] PINMUX_MIO_PAD_ATTR_REGWEN_30 + 4'b 0001, // index[177] PINMUX_MIO_PAD_ATTR_REGWEN_31 + 4'b 0011, // index[178] PINMUX_MIO_PAD_ATTR_0 + 4'b 0011, // index[179] PINMUX_MIO_PAD_ATTR_1 + 4'b 0011, // index[180] PINMUX_MIO_PAD_ATTR_2 + 4'b 0011, // index[181] PINMUX_MIO_PAD_ATTR_3 + 4'b 0011, // index[182] PINMUX_MIO_PAD_ATTR_4 + 4'b 0011, // index[183] PINMUX_MIO_PAD_ATTR_5 + 4'b 0011, // index[184] PINMUX_MIO_PAD_ATTR_6 + 4'b 0011, // index[185] PINMUX_MIO_PAD_ATTR_7 + 4'b 0011, // index[186] PINMUX_MIO_PAD_ATTR_8 + 4'b 0011, // index[187] PINMUX_MIO_PAD_ATTR_9 + 4'b 0011, // index[188] PINMUX_MIO_PAD_ATTR_10 + 4'b 0011, // index[189] PINMUX_MIO_PAD_ATTR_11 + 4'b 0011, // index[190] PINMUX_MIO_PAD_ATTR_12 + 4'b 0011, // index[191] PINMUX_MIO_PAD_ATTR_13 + 4'b 0011, // index[192] PINMUX_MIO_PAD_ATTR_14 + 4'b 0011, // index[193] PINMUX_MIO_PAD_ATTR_15 + 4'b 0011, // index[194] PINMUX_MIO_PAD_ATTR_16 + 4'b 0011, // index[195] PINMUX_MIO_PAD_ATTR_17 + 4'b 0011, // index[196] PINMUX_MIO_PAD_ATTR_18 + 4'b 0011, // index[197] PINMUX_MIO_PAD_ATTR_19 + 4'b 0011, // index[198] PINMUX_MIO_PAD_ATTR_20 + 4'b 0011, // index[199] PINMUX_MIO_PAD_ATTR_21 + 4'b 0011, // index[200] PINMUX_MIO_PAD_ATTR_22 + 4'b 0011, // index[201] PINMUX_MIO_PAD_ATTR_23 + 4'b 0011, // index[202] PINMUX_MIO_PAD_ATTR_24 + 4'b 0011, // index[203] PINMUX_MIO_PAD_ATTR_25 + 4'b 0011, // index[204] PINMUX_MIO_PAD_ATTR_26 + 4'b 0011, // index[205] PINMUX_MIO_PAD_ATTR_27 + 4'b 0011, // index[206] PINMUX_MIO_PAD_ATTR_28 + 4'b 0011, // index[207] PINMUX_MIO_PAD_ATTR_29 + 4'b 0011, // index[208] PINMUX_MIO_PAD_ATTR_30 + 4'b 0011, // index[209] PINMUX_MIO_PAD_ATTR_31 + 4'b 0001, // index[210] PINMUX_DIO_PAD_ATTR_REGWEN_0 + 4'b 0001, // index[211] PINMUX_DIO_PAD_ATTR_REGWEN_1 + 4'b 0001, // index[212] PINMUX_DIO_PAD_ATTR_REGWEN_2 + 4'b 0001, // index[213] PINMUX_DIO_PAD_ATTR_REGWEN_3 + 4'b 0001, // index[214] PINMUX_DIO_PAD_ATTR_REGWEN_4 + 4'b 0001, // index[215] PINMUX_DIO_PAD_ATTR_REGWEN_5 + 4'b 0001, // index[216] PINMUX_DIO_PAD_ATTR_REGWEN_6 + 4'b 0001, // index[217] PINMUX_DIO_PAD_ATTR_REGWEN_7 + 4'b 0001, // index[218] PINMUX_DIO_PAD_ATTR_REGWEN_8 + 4'b 0001, // index[219] PINMUX_DIO_PAD_ATTR_REGWEN_9 + 4'b 0001, // index[220] PINMUX_DIO_PAD_ATTR_REGWEN_10 + 4'b 0001, // index[221] PINMUX_DIO_PAD_ATTR_REGWEN_11 + 4'b 0001, // index[222] PINMUX_DIO_PAD_ATTR_REGWEN_12 + 4'b 0001, // index[223] PINMUX_DIO_PAD_ATTR_REGWEN_13 + 4'b 0001, // index[224] PINMUX_DIO_PAD_ATTR_REGWEN_14 + 4'b 0011, // index[225] PINMUX_DIO_PAD_ATTR_0 + 4'b 0011, // index[226] PINMUX_DIO_PAD_ATTR_1 + 4'b 0011, // index[227] PINMUX_DIO_PAD_ATTR_2 + 4'b 0011, // index[228] PINMUX_DIO_PAD_ATTR_3 + 4'b 0011, // index[229] PINMUX_DIO_PAD_ATTR_4 + 4'b 0011, // index[230] PINMUX_DIO_PAD_ATTR_5 + 4'b 0011, // index[231] PINMUX_DIO_PAD_ATTR_6 + 4'b 0011, // index[232] PINMUX_DIO_PAD_ATTR_7 + 4'b 0011, // index[233] PINMUX_DIO_PAD_ATTR_8 + 4'b 0011, // index[234] PINMUX_DIO_PAD_ATTR_9 + 4'b 0011, // index[235] PINMUX_DIO_PAD_ATTR_10 + 4'b 0011, // index[236] PINMUX_DIO_PAD_ATTR_11 + 4'b 0011, // index[237] PINMUX_DIO_PAD_ATTR_12 + 4'b 0011, // index[238] PINMUX_DIO_PAD_ATTR_13 + 4'b 0011, // index[239] PINMUX_DIO_PAD_ATTR_14 + 4'b 1111, // index[240] PINMUX_MIO_PAD_SLEEP_STATUS + 4'b 0001, // index[241] PINMUX_MIO_PAD_SLEEP_REGWEN_0 + 4'b 0001, // index[242] PINMUX_MIO_PAD_SLEEP_REGWEN_1 + 4'b 0001, // index[243] PINMUX_MIO_PAD_SLEEP_REGWEN_2 + 4'b 0001, // index[244] PINMUX_MIO_PAD_SLEEP_REGWEN_3 + 4'b 0001, // index[245] PINMUX_MIO_PAD_SLEEP_REGWEN_4 + 4'b 0001, // index[246] PINMUX_MIO_PAD_SLEEP_REGWEN_5 + 4'b 0001, // index[247] PINMUX_MIO_PAD_SLEEP_REGWEN_6 + 4'b 0001, // index[248] PINMUX_MIO_PAD_SLEEP_REGWEN_7 + 4'b 0001, // index[249] PINMUX_MIO_PAD_SLEEP_REGWEN_8 + 4'b 0001, // index[250] PINMUX_MIO_PAD_SLEEP_REGWEN_9 + 4'b 0001, // index[251] PINMUX_MIO_PAD_SLEEP_REGWEN_10 + 4'b 0001, // index[252] PINMUX_MIO_PAD_SLEEP_REGWEN_11 + 4'b 0001, // index[253] PINMUX_MIO_PAD_SLEEP_REGWEN_12 + 4'b 0001, // index[254] PINMUX_MIO_PAD_SLEEP_REGWEN_13 + 4'b 0001, // index[255] PINMUX_MIO_PAD_SLEEP_REGWEN_14 + 4'b 0001, // index[256] PINMUX_MIO_PAD_SLEEP_REGWEN_15 + 4'b 0001, // index[257] PINMUX_MIO_PAD_SLEEP_REGWEN_16 + 4'b 0001, // index[258] PINMUX_MIO_PAD_SLEEP_REGWEN_17 + 4'b 0001, // index[259] PINMUX_MIO_PAD_SLEEP_REGWEN_18 + 4'b 0001, // index[260] PINMUX_MIO_PAD_SLEEP_REGWEN_19 + 4'b 0001, // index[261] PINMUX_MIO_PAD_SLEEP_REGWEN_20 + 4'b 0001, // index[262] PINMUX_MIO_PAD_SLEEP_REGWEN_21 + 4'b 0001, // index[263] PINMUX_MIO_PAD_SLEEP_REGWEN_22 + 4'b 0001, // index[264] PINMUX_MIO_PAD_SLEEP_REGWEN_23 + 4'b 0001, // index[265] PINMUX_MIO_PAD_SLEEP_REGWEN_24 + 4'b 0001, // index[266] PINMUX_MIO_PAD_SLEEP_REGWEN_25 + 4'b 0001, // index[267] PINMUX_MIO_PAD_SLEEP_REGWEN_26 + 4'b 0001, // index[268] PINMUX_MIO_PAD_SLEEP_REGWEN_27 + 4'b 0001, // index[269] PINMUX_MIO_PAD_SLEEP_REGWEN_28 + 4'b 0001, // index[270] PINMUX_MIO_PAD_SLEEP_REGWEN_29 + 4'b 0001, // index[271] PINMUX_MIO_PAD_SLEEP_REGWEN_30 + 4'b 0001, // index[272] PINMUX_MIO_PAD_SLEEP_REGWEN_31 + 4'b 0001, // index[273] PINMUX_MIO_PAD_SLEEP_EN_0 + 4'b 0001, // index[274] PINMUX_MIO_PAD_SLEEP_EN_1 + 4'b 0001, // index[275] PINMUX_MIO_PAD_SLEEP_EN_2 + 4'b 0001, // index[276] PINMUX_MIO_PAD_SLEEP_EN_3 + 4'b 0001, // index[277] PINMUX_MIO_PAD_SLEEP_EN_4 + 4'b 0001, // index[278] PINMUX_MIO_PAD_SLEEP_EN_5 + 4'b 0001, // index[279] PINMUX_MIO_PAD_SLEEP_EN_6 + 4'b 0001, // index[280] PINMUX_MIO_PAD_SLEEP_EN_7 + 4'b 0001, // index[281] PINMUX_MIO_PAD_SLEEP_EN_8 + 4'b 0001, // index[282] PINMUX_MIO_PAD_SLEEP_EN_9 + 4'b 0001, // index[283] PINMUX_MIO_PAD_SLEEP_EN_10 + 4'b 0001, // index[284] PINMUX_MIO_PAD_SLEEP_EN_11 + 4'b 0001, // index[285] PINMUX_MIO_PAD_SLEEP_EN_12 + 4'b 0001, // index[286] PINMUX_MIO_PAD_SLEEP_EN_13 + 4'b 0001, // index[287] PINMUX_MIO_PAD_SLEEP_EN_14 + 4'b 0001, // index[288] PINMUX_MIO_PAD_SLEEP_EN_15 + 4'b 0001, // index[289] PINMUX_MIO_PAD_SLEEP_EN_16 + 4'b 0001, // index[290] PINMUX_MIO_PAD_SLEEP_EN_17 + 4'b 0001, // index[291] PINMUX_MIO_PAD_SLEEP_EN_18 + 4'b 0001, // index[292] PINMUX_MIO_PAD_SLEEP_EN_19 + 4'b 0001, // index[293] PINMUX_MIO_PAD_SLEEP_EN_20 + 4'b 0001, // index[294] PINMUX_MIO_PAD_SLEEP_EN_21 + 4'b 0001, // index[295] PINMUX_MIO_PAD_SLEEP_EN_22 + 4'b 0001, // index[296] PINMUX_MIO_PAD_SLEEP_EN_23 + 4'b 0001, // index[297] PINMUX_MIO_PAD_SLEEP_EN_24 + 4'b 0001, // index[298] PINMUX_MIO_PAD_SLEEP_EN_25 + 4'b 0001, // index[299] PINMUX_MIO_PAD_SLEEP_EN_26 + 4'b 0001, // index[300] PINMUX_MIO_PAD_SLEEP_EN_27 + 4'b 0001, // index[301] PINMUX_MIO_PAD_SLEEP_EN_28 + 4'b 0001, // index[302] PINMUX_MIO_PAD_SLEEP_EN_29 + 4'b 0001, // index[303] PINMUX_MIO_PAD_SLEEP_EN_30 + 4'b 0001, // index[304] PINMUX_MIO_PAD_SLEEP_EN_31 + 4'b 0001, // index[305] PINMUX_MIO_PAD_SLEEP_MODE_0 + 4'b 0001, // index[306] PINMUX_MIO_PAD_SLEEP_MODE_1 + 4'b 0001, // index[307] PINMUX_MIO_PAD_SLEEP_MODE_2 + 4'b 0001, // index[308] PINMUX_MIO_PAD_SLEEP_MODE_3 + 4'b 0001, // index[309] PINMUX_MIO_PAD_SLEEP_MODE_4 + 4'b 0001, // index[310] PINMUX_MIO_PAD_SLEEP_MODE_5 + 4'b 0001, // index[311] PINMUX_MIO_PAD_SLEEP_MODE_6 + 4'b 0001, // index[312] PINMUX_MIO_PAD_SLEEP_MODE_7 + 4'b 0001, // index[313] PINMUX_MIO_PAD_SLEEP_MODE_8 + 4'b 0001, // index[314] PINMUX_MIO_PAD_SLEEP_MODE_9 + 4'b 0001, // index[315] PINMUX_MIO_PAD_SLEEP_MODE_10 + 4'b 0001, // index[316] PINMUX_MIO_PAD_SLEEP_MODE_11 + 4'b 0001, // index[317] PINMUX_MIO_PAD_SLEEP_MODE_12 + 4'b 0001, // index[318] PINMUX_MIO_PAD_SLEEP_MODE_13 + 4'b 0001, // index[319] PINMUX_MIO_PAD_SLEEP_MODE_14 + 4'b 0001, // index[320] PINMUX_MIO_PAD_SLEEP_MODE_15 + 4'b 0001, // index[321] PINMUX_MIO_PAD_SLEEP_MODE_16 + 4'b 0001, // index[322] PINMUX_MIO_PAD_SLEEP_MODE_17 + 4'b 0001, // index[323] PINMUX_MIO_PAD_SLEEP_MODE_18 + 4'b 0001, // index[324] PINMUX_MIO_PAD_SLEEP_MODE_19 + 4'b 0001, // index[325] PINMUX_MIO_PAD_SLEEP_MODE_20 + 4'b 0001, // index[326] PINMUX_MIO_PAD_SLEEP_MODE_21 + 4'b 0001, // index[327] PINMUX_MIO_PAD_SLEEP_MODE_22 + 4'b 0001, // index[328] PINMUX_MIO_PAD_SLEEP_MODE_23 + 4'b 0001, // index[329] PINMUX_MIO_PAD_SLEEP_MODE_24 + 4'b 0001, // index[330] PINMUX_MIO_PAD_SLEEP_MODE_25 + 4'b 0001, // index[331] PINMUX_MIO_PAD_SLEEP_MODE_26 + 4'b 0001, // index[332] PINMUX_MIO_PAD_SLEEP_MODE_27 + 4'b 0001, // index[333] PINMUX_MIO_PAD_SLEEP_MODE_28 + 4'b 0001, // index[334] PINMUX_MIO_PAD_SLEEP_MODE_29 + 4'b 0001, // index[335] PINMUX_MIO_PAD_SLEEP_MODE_30 + 4'b 0001, // index[336] PINMUX_MIO_PAD_SLEEP_MODE_31 + 4'b 0011, // index[337] PINMUX_DIO_PAD_SLEEP_STATUS + 4'b 0001, // index[338] PINMUX_DIO_PAD_SLEEP_REGWEN_0 + 4'b 0001, // index[339] PINMUX_DIO_PAD_SLEEP_REGWEN_1 + 4'b 0001, // index[340] PINMUX_DIO_PAD_SLEEP_REGWEN_2 + 4'b 0001, // index[341] PINMUX_DIO_PAD_SLEEP_REGWEN_3 + 4'b 0001, // index[342] PINMUX_DIO_PAD_SLEEP_REGWEN_4 + 4'b 0001, // index[343] PINMUX_DIO_PAD_SLEEP_REGWEN_5 + 4'b 0001, // index[344] PINMUX_DIO_PAD_SLEEP_REGWEN_6 + 4'b 0001, // index[345] PINMUX_DIO_PAD_SLEEP_REGWEN_7 + 4'b 0001, // index[346] PINMUX_DIO_PAD_SLEEP_REGWEN_8 + 4'b 0001, // index[347] PINMUX_DIO_PAD_SLEEP_REGWEN_9 + 4'b 0001, // index[348] PINMUX_DIO_PAD_SLEEP_REGWEN_10 + 4'b 0001, // index[349] PINMUX_DIO_PAD_SLEEP_REGWEN_11 + 4'b 0001, // index[350] PINMUX_DIO_PAD_SLEEP_REGWEN_12 + 4'b 0001, // index[351] PINMUX_DIO_PAD_SLEEP_REGWEN_13 + 4'b 0001, // index[352] PINMUX_DIO_PAD_SLEEP_REGWEN_14 + 4'b 0001, // index[353] PINMUX_DIO_PAD_SLEEP_EN_0 + 4'b 0001, // index[354] PINMUX_DIO_PAD_SLEEP_EN_1 + 4'b 0001, // index[355] PINMUX_DIO_PAD_SLEEP_EN_2 + 4'b 0001, // index[356] PINMUX_DIO_PAD_SLEEP_EN_3 + 4'b 0001, // index[357] PINMUX_DIO_PAD_SLEEP_EN_4 + 4'b 0001, // index[358] PINMUX_DIO_PAD_SLEEP_EN_5 + 4'b 0001, // index[359] PINMUX_DIO_PAD_SLEEP_EN_6 + 4'b 0001, // index[360] PINMUX_DIO_PAD_SLEEP_EN_7 + 4'b 0001, // index[361] PINMUX_DIO_PAD_SLEEP_EN_8 + 4'b 0001, // index[362] PINMUX_DIO_PAD_SLEEP_EN_9 + 4'b 0001, // index[363] PINMUX_DIO_PAD_SLEEP_EN_10 + 4'b 0001, // index[364] PINMUX_DIO_PAD_SLEEP_EN_11 + 4'b 0001, // index[365] PINMUX_DIO_PAD_SLEEP_EN_12 + 4'b 0001, // index[366] PINMUX_DIO_PAD_SLEEP_EN_13 + 4'b 0001, // index[367] PINMUX_DIO_PAD_SLEEP_EN_14 + 4'b 0001, // index[368] PINMUX_DIO_PAD_SLEEP_MODE_0 + 4'b 0001, // index[369] PINMUX_DIO_PAD_SLEEP_MODE_1 + 4'b 0001, // index[370] PINMUX_DIO_PAD_SLEEP_MODE_2 + 4'b 0001, // index[371] PINMUX_DIO_PAD_SLEEP_MODE_3 + 4'b 0001, // index[372] PINMUX_DIO_PAD_SLEEP_MODE_4 + 4'b 0001, // index[373] PINMUX_DIO_PAD_SLEEP_MODE_5 + 4'b 0001, // index[374] PINMUX_DIO_PAD_SLEEP_MODE_6 + 4'b 0001, // index[375] PINMUX_DIO_PAD_SLEEP_MODE_7 + 4'b 0001, // index[376] PINMUX_DIO_PAD_SLEEP_MODE_8 + 4'b 0001, // index[377] PINMUX_DIO_PAD_SLEEP_MODE_9 + 4'b 0001, // index[378] PINMUX_DIO_PAD_SLEEP_MODE_10 + 4'b 0001, // index[379] PINMUX_DIO_PAD_SLEEP_MODE_11 + 4'b 0001, // index[380] PINMUX_DIO_PAD_SLEEP_MODE_12 + 4'b 0001, // index[381] PINMUX_DIO_PAD_SLEEP_MODE_13 + 4'b 0001, // index[382] PINMUX_DIO_PAD_SLEEP_MODE_14 + 4'b 0001, // index[383] PINMUX_WKUP_DETECTOR_REGWEN_0 + 4'b 0001, // index[384] PINMUX_WKUP_DETECTOR_REGWEN_1 + 4'b 0001, // index[385] PINMUX_WKUP_DETECTOR_REGWEN_2 + 4'b 0001, // index[386] PINMUX_WKUP_DETECTOR_REGWEN_3 + 4'b 0001, // index[387] PINMUX_WKUP_DETECTOR_REGWEN_4 + 4'b 0001, // index[388] PINMUX_WKUP_DETECTOR_REGWEN_5 + 4'b 0001, // index[389] PINMUX_WKUP_DETECTOR_REGWEN_6 + 4'b 0001, // index[390] PINMUX_WKUP_DETECTOR_REGWEN_7 + 4'b 0001, // index[391] PINMUX_WKUP_DETECTOR_EN_0 + 4'b 0001, // index[392] PINMUX_WKUP_DETECTOR_EN_1 + 4'b 0001, // index[393] PINMUX_WKUP_DETECTOR_EN_2 + 4'b 0001, // index[394] PINMUX_WKUP_DETECTOR_EN_3 + 4'b 0001, // index[395] PINMUX_WKUP_DETECTOR_EN_4 + 4'b 0001, // index[396] PINMUX_WKUP_DETECTOR_EN_5 + 4'b 0001, // index[397] PINMUX_WKUP_DETECTOR_EN_6 + 4'b 0001, // index[398] PINMUX_WKUP_DETECTOR_EN_7 + 4'b 0001, // index[399] PINMUX_WKUP_DETECTOR_0 + 4'b 0001, // index[400] PINMUX_WKUP_DETECTOR_1 + 4'b 0001, // index[401] PINMUX_WKUP_DETECTOR_2 + 4'b 0001, // index[402] PINMUX_WKUP_DETECTOR_3 + 4'b 0001, // index[403] PINMUX_WKUP_DETECTOR_4 + 4'b 0001, // index[404] PINMUX_WKUP_DETECTOR_5 + 4'b 0001, // index[405] PINMUX_WKUP_DETECTOR_6 + 4'b 0001, // index[406] PINMUX_WKUP_DETECTOR_7 + 4'b 0001, // index[407] PINMUX_WKUP_DETECTOR_CNT_TH_0 + 4'b 0001, // index[408] PINMUX_WKUP_DETECTOR_CNT_TH_1 + 4'b 0001, // index[409] PINMUX_WKUP_DETECTOR_CNT_TH_2 + 4'b 0001, // index[410] PINMUX_WKUP_DETECTOR_CNT_TH_3 + 4'b 0001, // index[411] PINMUX_WKUP_DETECTOR_CNT_TH_4 + 4'b 0001, // index[412] PINMUX_WKUP_DETECTOR_CNT_TH_5 + 4'b 0001, // index[413] PINMUX_WKUP_DETECTOR_CNT_TH_6 + 4'b 0001, // index[414] PINMUX_WKUP_DETECTOR_CNT_TH_7 + 4'b 0001, // index[415] PINMUX_WKUP_DETECTOR_PADSEL_0 + 4'b 0001, // index[416] PINMUX_WKUP_DETECTOR_PADSEL_1 + 4'b 0001, // index[417] PINMUX_WKUP_DETECTOR_PADSEL_2 + 4'b 0001, // index[418] PINMUX_WKUP_DETECTOR_PADSEL_3 + 4'b 0001, // index[419] PINMUX_WKUP_DETECTOR_PADSEL_4 + 4'b 0001, // index[420] PINMUX_WKUP_DETECTOR_PADSEL_5 + 4'b 0001, // index[421] PINMUX_WKUP_DETECTOR_PADSEL_6 + 4'b 0001, // index[422] PINMUX_WKUP_DETECTOR_PADSEL_7 + 4'b 0001 // index[423] PINMUX_WKUP_CAUSE }; endpackage
diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv index 7a1fd48..cb667a4 100644 --- a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv +++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
@@ -509,303 +509,899 @@ logic [5:0] mio_outsel_31_qs; logic [5:0] mio_outsel_31_wd; logic mio_outsel_31_we; - logic mio_out_sleep_regwen_0_qs; - logic mio_out_sleep_regwen_0_wd; - logic mio_out_sleep_regwen_0_we; - logic mio_out_sleep_regwen_1_qs; - logic mio_out_sleep_regwen_1_wd; - logic mio_out_sleep_regwen_1_we; - logic mio_out_sleep_regwen_2_qs; - logic mio_out_sleep_regwen_2_wd; - logic mio_out_sleep_regwen_2_we; - logic mio_out_sleep_regwen_3_qs; - logic mio_out_sleep_regwen_3_wd; - logic mio_out_sleep_regwen_3_we; - logic mio_out_sleep_regwen_4_qs; - logic mio_out_sleep_regwen_4_wd; - logic mio_out_sleep_regwen_4_we; - logic mio_out_sleep_regwen_5_qs; - logic mio_out_sleep_regwen_5_wd; - logic mio_out_sleep_regwen_5_we; - logic mio_out_sleep_regwen_6_qs; - logic mio_out_sleep_regwen_6_wd; - logic mio_out_sleep_regwen_6_we; - logic mio_out_sleep_regwen_7_qs; - logic mio_out_sleep_regwen_7_wd; - logic mio_out_sleep_regwen_7_we; - logic mio_out_sleep_regwen_8_qs; - logic mio_out_sleep_regwen_8_wd; - logic mio_out_sleep_regwen_8_we; - logic mio_out_sleep_regwen_9_qs; - logic mio_out_sleep_regwen_9_wd; - logic mio_out_sleep_regwen_9_we; - logic mio_out_sleep_regwen_10_qs; - logic mio_out_sleep_regwen_10_wd; - logic mio_out_sleep_regwen_10_we; - logic mio_out_sleep_regwen_11_qs; - logic mio_out_sleep_regwen_11_wd; - logic mio_out_sleep_regwen_11_we; - logic mio_out_sleep_regwen_12_qs; - logic mio_out_sleep_regwen_12_wd; - logic mio_out_sleep_regwen_12_we; - logic mio_out_sleep_regwen_13_qs; - logic mio_out_sleep_regwen_13_wd; - logic mio_out_sleep_regwen_13_we; - logic mio_out_sleep_regwen_14_qs; - logic mio_out_sleep_regwen_14_wd; - logic mio_out_sleep_regwen_14_we; - logic mio_out_sleep_regwen_15_qs; - logic mio_out_sleep_regwen_15_wd; - logic mio_out_sleep_regwen_15_we; - logic mio_out_sleep_regwen_16_qs; - logic mio_out_sleep_regwen_16_wd; - logic mio_out_sleep_regwen_16_we; - logic mio_out_sleep_regwen_17_qs; - logic mio_out_sleep_regwen_17_wd; - logic mio_out_sleep_regwen_17_we; - logic mio_out_sleep_regwen_18_qs; - logic mio_out_sleep_regwen_18_wd; - logic mio_out_sleep_regwen_18_we; - logic mio_out_sleep_regwen_19_qs; - logic mio_out_sleep_regwen_19_wd; - logic mio_out_sleep_regwen_19_we; - logic mio_out_sleep_regwen_20_qs; - logic mio_out_sleep_regwen_20_wd; - logic mio_out_sleep_regwen_20_we; - logic mio_out_sleep_regwen_21_qs; - logic mio_out_sleep_regwen_21_wd; - logic mio_out_sleep_regwen_21_we; - logic mio_out_sleep_regwen_22_qs; - logic mio_out_sleep_regwen_22_wd; - logic mio_out_sleep_regwen_22_we; - logic mio_out_sleep_regwen_23_qs; - logic mio_out_sleep_regwen_23_wd; - logic mio_out_sleep_regwen_23_we; - logic mio_out_sleep_regwen_24_qs; - logic mio_out_sleep_regwen_24_wd; - logic mio_out_sleep_regwen_24_we; - logic mio_out_sleep_regwen_25_qs; - logic mio_out_sleep_regwen_25_wd; - logic mio_out_sleep_regwen_25_we; - logic mio_out_sleep_regwen_26_qs; - logic mio_out_sleep_regwen_26_wd; - logic mio_out_sleep_regwen_26_we; - logic mio_out_sleep_regwen_27_qs; - logic mio_out_sleep_regwen_27_wd; - logic mio_out_sleep_regwen_27_we; - logic mio_out_sleep_regwen_28_qs; - logic mio_out_sleep_regwen_28_wd; - logic mio_out_sleep_regwen_28_we; - logic mio_out_sleep_regwen_29_qs; - logic mio_out_sleep_regwen_29_wd; - logic mio_out_sleep_regwen_29_we; - logic mio_out_sleep_regwen_30_qs; - logic mio_out_sleep_regwen_30_wd; - logic mio_out_sleep_regwen_30_we; - logic mio_out_sleep_regwen_31_qs; - logic mio_out_sleep_regwen_31_wd; - logic mio_out_sleep_regwen_31_we; - logic [1:0] mio_out_sleep_val_0_qs; - logic [1:0] mio_out_sleep_val_0_wd; - logic mio_out_sleep_val_0_we; - logic [1:0] mio_out_sleep_val_1_qs; - logic [1:0] mio_out_sleep_val_1_wd; - logic mio_out_sleep_val_1_we; - logic [1:0] mio_out_sleep_val_2_qs; - logic [1:0] mio_out_sleep_val_2_wd; - logic mio_out_sleep_val_2_we; - logic [1:0] mio_out_sleep_val_3_qs; - logic [1:0] mio_out_sleep_val_3_wd; - logic mio_out_sleep_val_3_we; - logic [1:0] mio_out_sleep_val_4_qs; - logic [1:0] mio_out_sleep_val_4_wd; - logic mio_out_sleep_val_4_we; - logic [1:0] mio_out_sleep_val_5_qs; - logic [1:0] mio_out_sleep_val_5_wd; - logic mio_out_sleep_val_5_we; - logic [1:0] mio_out_sleep_val_6_qs; - logic [1:0] mio_out_sleep_val_6_wd; - logic mio_out_sleep_val_6_we; - logic [1:0] mio_out_sleep_val_7_qs; - logic [1:0] mio_out_sleep_val_7_wd; - logic mio_out_sleep_val_7_we; - logic [1:0] mio_out_sleep_val_8_qs; - logic [1:0] mio_out_sleep_val_8_wd; - logic mio_out_sleep_val_8_we; - logic [1:0] mio_out_sleep_val_9_qs; - logic [1:0] mio_out_sleep_val_9_wd; - logic mio_out_sleep_val_9_we; - logic [1:0] mio_out_sleep_val_10_qs; - logic [1:0] mio_out_sleep_val_10_wd; - logic mio_out_sleep_val_10_we; - logic [1:0] mio_out_sleep_val_11_qs; - logic [1:0] mio_out_sleep_val_11_wd; - logic mio_out_sleep_val_11_we; - logic [1:0] mio_out_sleep_val_12_qs; - logic [1:0] mio_out_sleep_val_12_wd; - logic mio_out_sleep_val_12_we; - logic [1:0] mio_out_sleep_val_13_qs; - logic [1:0] mio_out_sleep_val_13_wd; - logic mio_out_sleep_val_13_we; - logic [1:0] mio_out_sleep_val_14_qs; - logic [1:0] mio_out_sleep_val_14_wd; - logic mio_out_sleep_val_14_we; - logic [1:0] mio_out_sleep_val_15_qs; - logic [1:0] mio_out_sleep_val_15_wd; - logic mio_out_sleep_val_15_we; - logic [1:0] mio_out_sleep_val_16_qs; - logic [1:0] mio_out_sleep_val_16_wd; - logic mio_out_sleep_val_16_we; - logic [1:0] mio_out_sleep_val_17_qs; - logic [1:0] mio_out_sleep_val_17_wd; - logic mio_out_sleep_val_17_we; - logic [1:0] mio_out_sleep_val_18_qs; - logic [1:0] mio_out_sleep_val_18_wd; - logic mio_out_sleep_val_18_we; - logic [1:0] mio_out_sleep_val_19_qs; - logic [1:0] mio_out_sleep_val_19_wd; - logic mio_out_sleep_val_19_we; - logic [1:0] mio_out_sleep_val_20_qs; - logic [1:0] mio_out_sleep_val_20_wd; - logic mio_out_sleep_val_20_we; - logic [1:0] mio_out_sleep_val_21_qs; - logic [1:0] mio_out_sleep_val_21_wd; - logic mio_out_sleep_val_21_we; - logic [1:0] mio_out_sleep_val_22_qs; - logic [1:0] mio_out_sleep_val_22_wd; - logic mio_out_sleep_val_22_we; - logic [1:0] mio_out_sleep_val_23_qs; - logic [1:0] mio_out_sleep_val_23_wd; - logic mio_out_sleep_val_23_we; - logic [1:0] mio_out_sleep_val_24_qs; - logic [1:0] mio_out_sleep_val_24_wd; - logic mio_out_sleep_val_24_we; - logic [1:0] mio_out_sleep_val_25_qs; - logic [1:0] mio_out_sleep_val_25_wd; - logic mio_out_sleep_val_25_we; - logic [1:0] mio_out_sleep_val_26_qs; - logic [1:0] mio_out_sleep_val_26_wd; - logic mio_out_sleep_val_26_we; - logic [1:0] mio_out_sleep_val_27_qs; - logic [1:0] mio_out_sleep_val_27_wd; - logic mio_out_sleep_val_27_we; - logic [1:0] mio_out_sleep_val_28_qs; - logic [1:0] mio_out_sleep_val_28_wd; - logic mio_out_sleep_val_28_we; - logic [1:0] mio_out_sleep_val_29_qs; - logic [1:0] mio_out_sleep_val_29_wd; - logic mio_out_sleep_val_29_we; - logic [1:0] mio_out_sleep_val_30_qs; - logic [1:0] mio_out_sleep_val_30_wd; - logic mio_out_sleep_val_30_we; - logic [1:0] mio_out_sleep_val_31_qs; - logic [1:0] mio_out_sleep_val_31_wd; - logic mio_out_sleep_val_31_we; - logic dio_out_sleep_regwen_0_qs; - logic dio_out_sleep_regwen_0_wd; - logic dio_out_sleep_regwen_0_we; - logic dio_out_sleep_regwen_1_qs; - logic dio_out_sleep_regwen_1_wd; - logic dio_out_sleep_regwen_1_we; - logic dio_out_sleep_regwen_2_qs; - logic dio_out_sleep_regwen_2_wd; - logic dio_out_sleep_regwen_2_we; - logic dio_out_sleep_regwen_3_qs; - logic dio_out_sleep_regwen_3_wd; - logic dio_out_sleep_regwen_3_we; - logic dio_out_sleep_regwen_4_qs; - logic dio_out_sleep_regwen_4_wd; - logic dio_out_sleep_regwen_4_we; - logic dio_out_sleep_regwen_5_qs; - logic dio_out_sleep_regwen_5_wd; - logic dio_out_sleep_regwen_5_we; - logic dio_out_sleep_regwen_6_qs; - logic dio_out_sleep_regwen_6_wd; - logic dio_out_sleep_regwen_6_we; - logic dio_out_sleep_regwen_7_qs; - logic dio_out_sleep_regwen_7_wd; - logic dio_out_sleep_regwen_7_we; - logic dio_out_sleep_regwen_8_qs; - logic dio_out_sleep_regwen_8_wd; - logic dio_out_sleep_regwen_8_we; - logic dio_out_sleep_regwen_9_qs; - logic dio_out_sleep_regwen_9_wd; - logic dio_out_sleep_regwen_9_we; - logic dio_out_sleep_regwen_10_qs; - logic dio_out_sleep_regwen_10_wd; - logic dio_out_sleep_regwen_10_we; - logic dio_out_sleep_regwen_11_qs; - logic dio_out_sleep_regwen_11_wd; - logic dio_out_sleep_regwen_11_we; - logic dio_out_sleep_regwen_12_qs; - logic dio_out_sleep_regwen_12_wd; - logic dio_out_sleep_regwen_12_we; - logic dio_out_sleep_regwen_13_qs; - logic dio_out_sleep_regwen_13_wd; - logic dio_out_sleep_regwen_13_we; - logic dio_out_sleep_regwen_14_qs; - logic dio_out_sleep_regwen_14_wd; - logic dio_out_sleep_regwen_14_we; - logic [1:0] dio_out_sleep_val_0_qs; - logic [1:0] dio_out_sleep_val_0_wd; - logic dio_out_sleep_val_0_we; - logic dio_out_sleep_val_0_re; - logic [1:0] dio_out_sleep_val_1_qs; - logic [1:0] dio_out_sleep_val_1_wd; - logic dio_out_sleep_val_1_we; - logic dio_out_sleep_val_1_re; - logic [1:0] dio_out_sleep_val_2_qs; - logic [1:0] dio_out_sleep_val_2_wd; - logic dio_out_sleep_val_2_we; - logic dio_out_sleep_val_2_re; - logic [1:0] dio_out_sleep_val_3_qs; - logic [1:0] dio_out_sleep_val_3_wd; - logic dio_out_sleep_val_3_we; - logic dio_out_sleep_val_3_re; - logic [1:0] dio_out_sleep_val_4_qs; - logic [1:0] dio_out_sleep_val_4_wd; - logic dio_out_sleep_val_4_we; - logic dio_out_sleep_val_4_re; - logic [1:0] dio_out_sleep_val_5_qs; - logic [1:0] dio_out_sleep_val_5_wd; - logic dio_out_sleep_val_5_we; - logic dio_out_sleep_val_5_re; - logic [1:0] dio_out_sleep_val_6_qs; - logic [1:0] dio_out_sleep_val_6_wd; - logic dio_out_sleep_val_6_we; - logic dio_out_sleep_val_6_re; - logic [1:0] dio_out_sleep_val_7_qs; - logic [1:0] dio_out_sleep_val_7_wd; - logic dio_out_sleep_val_7_we; - logic dio_out_sleep_val_7_re; - logic [1:0] dio_out_sleep_val_8_qs; - logic [1:0] dio_out_sleep_val_8_wd; - logic dio_out_sleep_val_8_we; - logic dio_out_sleep_val_8_re; - logic [1:0] dio_out_sleep_val_9_qs; - logic [1:0] dio_out_sleep_val_9_wd; - logic dio_out_sleep_val_9_we; - logic dio_out_sleep_val_9_re; - logic [1:0] dio_out_sleep_val_10_qs; - logic [1:0] dio_out_sleep_val_10_wd; - logic dio_out_sleep_val_10_we; - logic dio_out_sleep_val_10_re; - logic [1:0] dio_out_sleep_val_11_qs; - logic [1:0] dio_out_sleep_val_11_wd; - logic dio_out_sleep_val_11_we; - logic dio_out_sleep_val_11_re; - logic [1:0] dio_out_sleep_val_12_qs; - logic [1:0] dio_out_sleep_val_12_wd; - logic dio_out_sleep_val_12_we; - logic dio_out_sleep_val_12_re; - logic [1:0] dio_out_sleep_val_13_qs; - logic [1:0] dio_out_sleep_val_13_wd; - logic dio_out_sleep_val_13_we; - logic dio_out_sleep_val_13_re; - logic [1:0] dio_out_sleep_val_14_qs; - logic [1:0] dio_out_sleep_val_14_wd; - logic dio_out_sleep_val_14_we; - logic dio_out_sleep_val_14_re; + logic mio_pad_attr_regwen_0_qs; + logic mio_pad_attr_regwen_0_wd; + logic mio_pad_attr_regwen_0_we; + logic mio_pad_attr_regwen_1_qs; + logic mio_pad_attr_regwen_1_wd; + logic mio_pad_attr_regwen_1_we; + logic mio_pad_attr_regwen_2_qs; + logic mio_pad_attr_regwen_2_wd; + logic mio_pad_attr_regwen_2_we; + logic mio_pad_attr_regwen_3_qs; + logic mio_pad_attr_regwen_3_wd; + logic mio_pad_attr_regwen_3_we; + logic mio_pad_attr_regwen_4_qs; + logic mio_pad_attr_regwen_4_wd; + logic mio_pad_attr_regwen_4_we; + logic mio_pad_attr_regwen_5_qs; + logic mio_pad_attr_regwen_5_wd; + logic mio_pad_attr_regwen_5_we; + logic mio_pad_attr_regwen_6_qs; + logic mio_pad_attr_regwen_6_wd; + logic mio_pad_attr_regwen_6_we; + logic mio_pad_attr_regwen_7_qs; + logic mio_pad_attr_regwen_7_wd; + logic mio_pad_attr_regwen_7_we; + logic mio_pad_attr_regwen_8_qs; + logic mio_pad_attr_regwen_8_wd; + logic mio_pad_attr_regwen_8_we; + logic mio_pad_attr_regwen_9_qs; + logic mio_pad_attr_regwen_9_wd; + logic mio_pad_attr_regwen_9_we; + logic mio_pad_attr_regwen_10_qs; + logic mio_pad_attr_regwen_10_wd; + logic mio_pad_attr_regwen_10_we; + logic mio_pad_attr_regwen_11_qs; + logic mio_pad_attr_regwen_11_wd; + logic mio_pad_attr_regwen_11_we; + logic mio_pad_attr_regwen_12_qs; + logic mio_pad_attr_regwen_12_wd; + logic mio_pad_attr_regwen_12_we; + logic mio_pad_attr_regwen_13_qs; + logic mio_pad_attr_regwen_13_wd; + logic mio_pad_attr_regwen_13_we; + logic mio_pad_attr_regwen_14_qs; + logic mio_pad_attr_regwen_14_wd; + logic mio_pad_attr_regwen_14_we; + logic mio_pad_attr_regwen_15_qs; + logic mio_pad_attr_regwen_15_wd; + logic mio_pad_attr_regwen_15_we; + logic mio_pad_attr_regwen_16_qs; + logic mio_pad_attr_regwen_16_wd; + logic mio_pad_attr_regwen_16_we; + logic mio_pad_attr_regwen_17_qs; + logic mio_pad_attr_regwen_17_wd; + logic mio_pad_attr_regwen_17_we; + logic mio_pad_attr_regwen_18_qs; + logic mio_pad_attr_regwen_18_wd; + logic mio_pad_attr_regwen_18_we; + logic mio_pad_attr_regwen_19_qs; + logic mio_pad_attr_regwen_19_wd; + logic mio_pad_attr_regwen_19_we; + logic mio_pad_attr_regwen_20_qs; + logic mio_pad_attr_regwen_20_wd; + logic mio_pad_attr_regwen_20_we; + logic mio_pad_attr_regwen_21_qs; + logic mio_pad_attr_regwen_21_wd; + logic mio_pad_attr_regwen_21_we; + logic mio_pad_attr_regwen_22_qs; + logic mio_pad_attr_regwen_22_wd; + logic mio_pad_attr_regwen_22_we; + logic mio_pad_attr_regwen_23_qs; + logic mio_pad_attr_regwen_23_wd; + logic mio_pad_attr_regwen_23_we; + logic mio_pad_attr_regwen_24_qs; + logic mio_pad_attr_regwen_24_wd; + logic mio_pad_attr_regwen_24_we; + logic mio_pad_attr_regwen_25_qs; + logic mio_pad_attr_regwen_25_wd; + logic mio_pad_attr_regwen_25_we; + logic mio_pad_attr_regwen_26_qs; + logic mio_pad_attr_regwen_26_wd; + logic mio_pad_attr_regwen_26_we; + logic mio_pad_attr_regwen_27_qs; + logic mio_pad_attr_regwen_27_wd; + logic mio_pad_attr_regwen_27_we; + logic mio_pad_attr_regwen_28_qs; + logic mio_pad_attr_regwen_28_wd; + logic mio_pad_attr_regwen_28_we; + logic mio_pad_attr_regwen_29_qs; + logic mio_pad_attr_regwen_29_wd; + logic mio_pad_attr_regwen_29_we; + logic mio_pad_attr_regwen_30_qs; + logic mio_pad_attr_regwen_30_wd; + logic mio_pad_attr_regwen_30_we; + logic mio_pad_attr_regwen_31_qs; + logic mio_pad_attr_regwen_31_wd; + logic mio_pad_attr_regwen_31_we; + logic [9:0] mio_pad_attr_0_qs; + logic [9:0] mio_pad_attr_0_wd; + logic mio_pad_attr_0_we; + logic mio_pad_attr_0_re; + logic [9:0] mio_pad_attr_1_qs; + logic [9:0] mio_pad_attr_1_wd; + logic mio_pad_attr_1_we; + logic mio_pad_attr_1_re; + logic [9:0] mio_pad_attr_2_qs; + logic [9:0] mio_pad_attr_2_wd; + logic mio_pad_attr_2_we; + logic mio_pad_attr_2_re; + logic [9:0] mio_pad_attr_3_qs; + logic [9:0] mio_pad_attr_3_wd; + logic mio_pad_attr_3_we; + logic mio_pad_attr_3_re; + logic [9:0] mio_pad_attr_4_qs; + logic [9:0] mio_pad_attr_4_wd; + logic mio_pad_attr_4_we; + logic mio_pad_attr_4_re; + logic [9:0] mio_pad_attr_5_qs; + logic [9:0] mio_pad_attr_5_wd; + logic mio_pad_attr_5_we; + logic mio_pad_attr_5_re; + logic [9:0] mio_pad_attr_6_qs; + logic [9:0] mio_pad_attr_6_wd; + logic mio_pad_attr_6_we; + logic mio_pad_attr_6_re; + logic [9:0] mio_pad_attr_7_qs; + logic [9:0] mio_pad_attr_7_wd; + logic mio_pad_attr_7_we; + logic mio_pad_attr_7_re; + logic [9:0] mio_pad_attr_8_qs; + logic [9:0] mio_pad_attr_8_wd; + logic mio_pad_attr_8_we; + logic mio_pad_attr_8_re; + logic [9:0] mio_pad_attr_9_qs; + logic [9:0] mio_pad_attr_9_wd; + logic mio_pad_attr_9_we; + logic mio_pad_attr_9_re; + logic [9:0] mio_pad_attr_10_qs; + logic [9:0] mio_pad_attr_10_wd; + logic mio_pad_attr_10_we; + logic mio_pad_attr_10_re; + logic [9:0] mio_pad_attr_11_qs; + logic [9:0] mio_pad_attr_11_wd; + logic mio_pad_attr_11_we; + logic mio_pad_attr_11_re; + logic [9:0] mio_pad_attr_12_qs; + logic [9:0] mio_pad_attr_12_wd; + logic mio_pad_attr_12_we; + logic mio_pad_attr_12_re; + logic [9:0] mio_pad_attr_13_qs; + logic [9:0] mio_pad_attr_13_wd; + logic mio_pad_attr_13_we; + logic mio_pad_attr_13_re; + logic [9:0] mio_pad_attr_14_qs; + logic [9:0] mio_pad_attr_14_wd; + logic mio_pad_attr_14_we; + logic mio_pad_attr_14_re; + logic [9:0] mio_pad_attr_15_qs; + logic [9:0] mio_pad_attr_15_wd; + logic mio_pad_attr_15_we; + logic mio_pad_attr_15_re; + logic [9:0] mio_pad_attr_16_qs; + logic [9:0] mio_pad_attr_16_wd; + logic mio_pad_attr_16_we; + logic mio_pad_attr_16_re; + logic [9:0] mio_pad_attr_17_qs; + logic [9:0] mio_pad_attr_17_wd; + logic mio_pad_attr_17_we; + logic mio_pad_attr_17_re; + logic [9:0] mio_pad_attr_18_qs; + logic [9:0] mio_pad_attr_18_wd; + logic mio_pad_attr_18_we; + logic mio_pad_attr_18_re; + logic [9:0] mio_pad_attr_19_qs; + logic [9:0] mio_pad_attr_19_wd; + logic mio_pad_attr_19_we; + logic mio_pad_attr_19_re; + logic [9:0] mio_pad_attr_20_qs; + logic [9:0] mio_pad_attr_20_wd; + logic mio_pad_attr_20_we; + logic mio_pad_attr_20_re; + logic [9:0] mio_pad_attr_21_qs; + logic [9:0] mio_pad_attr_21_wd; + logic mio_pad_attr_21_we; + logic mio_pad_attr_21_re; + logic [9:0] mio_pad_attr_22_qs; + logic [9:0] mio_pad_attr_22_wd; + logic mio_pad_attr_22_we; + logic mio_pad_attr_22_re; + logic [9:0] mio_pad_attr_23_qs; + logic [9:0] mio_pad_attr_23_wd; + logic mio_pad_attr_23_we; + logic mio_pad_attr_23_re; + logic [9:0] mio_pad_attr_24_qs; + logic [9:0] mio_pad_attr_24_wd; + logic mio_pad_attr_24_we; + logic mio_pad_attr_24_re; + logic [9:0] mio_pad_attr_25_qs; + logic [9:0] mio_pad_attr_25_wd; + logic mio_pad_attr_25_we; + logic mio_pad_attr_25_re; + logic [9:0] mio_pad_attr_26_qs; + logic [9:0] mio_pad_attr_26_wd; + logic mio_pad_attr_26_we; + logic mio_pad_attr_26_re; + logic [9:0] mio_pad_attr_27_qs; + logic [9:0] mio_pad_attr_27_wd; + logic mio_pad_attr_27_we; + logic mio_pad_attr_27_re; + logic [9:0] mio_pad_attr_28_qs; + logic [9:0] mio_pad_attr_28_wd; + logic mio_pad_attr_28_we; + logic mio_pad_attr_28_re; + logic [9:0] mio_pad_attr_29_qs; + logic [9:0] mio_pad_attr_29_wd; + logic mio_pad_attr_29_we; + logic mio_pad_attr_29_re; + logic [9:0] mio_pad_attr_30_qs; + logic [9:0] mio_pad_attr_30_wd; + logic mio_pad_attr_30_we; + logic mio_pad_attr_30_re; + logic [9:0] mio_pad_attr_31_qs; + logic [9:0] mio_pad_attr_31_wd; + logic mio_pad_attr_31_we; + logic mio_pad_attr_31_re; + logic dio_pad_attr_regwen_0_qs; + logic dio_pad_attr_regwen_0_wd; + logic dio_pad_attr_regwen_0_we; + logic dio_pad_attr_regwen_1_qs; + logic dio_pad_attr_regwen_1_wd; + logic dio_pad_attr_regwen_1_we; + logic dio_pad_attr_regwen_2_qs; + logic dio_pad_attr_regwen_2_wd; + logic dio_pad_attr_regwen_2_we; + logic dio_pad_attr_regwen_3_qs; + logic dio_pad_attr_regwen_3_wd; + logic dio_pad_attr_regwen_3_we; + logic dio_pad_attr_regwen_4_qs; + logic dio_pad_attr_regwen_4_wd; + logic dio_pad_attr_regwen_4_we; + logic dio_pad_attr_regwen_5_qs; + logic dio_pad_attr_regwen_5_wd; + logic dio_pad_attr_regwen_5_we; + logic dio_pad_attr_regwen_6_qs; + logic dio_pad_attr_regwen_6_wd; + logic dio_pad_attr_regwen_6_we; + logic dio_pad_attr_regwen_7_qs; + logic dio_pad_attr_regwen_7_wd; + logic dio_pad_attr_regwen_7_we; + logic dio_pad_attr_regwen_8_qs; + logic dio_pad_attr_regwen_8_wd; + logic dio_pad_attr_regwen_8_we; + logic dio_pad_attr_regwen_9_qs; + logic dio_pad_attr_regwen_9_wd; + logic dio_pad_attr_regwen_9_we; + logic dio_pad_attr_regwen_10_qs; + logic dio_pad_attr_regwen_10_wd; + logic dio_pad_attr_regwen_10_we; + logic dio_pad_attr_regwen_11_qs; + logic dio_pad_attr_regwen_11_wd; + logic dio_pad_attr_regwen_11_we; + logic dio_pad_attr_regwen_12_qs; + logic dio_pad_attr_regwen_12_wd; + logic dio_pad_attr_regwen_12_we; + logic dio_pad_attr_regwen_13_qs; + logic dio_pad_attr_regwen_13_wd; + logic dio_pad_attr_regwen_13_we; + logic dio_pad_attr_regwen_14_qs; + logic dio_pad_attr_regwen_14_wd; + logic dio_pad_attr_regwen_14_we; + logic [9:0] dio_pad_attr_0_qs; + logic [9:0] dio_pad_attr_0_wd; + logic dio_pad_attr_0_we; + logic dio_pad_attr_0_re; + logic [9:0] dio_pad_attr_1_qs; + logic [9:0] dio_pad_attr_1_wd; + logic dio_pad_attr_1_we; + logic dio_pad_attr_1_re; + logic [9:0] dio_pad_attr_2_qs; + logic [9:0] dio_pad_attr_2_wd; + logic dio_pad_attr_2_we; + logic dio_pad_attr_2_re; + logic [9:0] dio_pad_attr_3_qs; + logic [9:0] dio_pad_attr_3_wd; + logic dio_pad_attr_3_we; + logic dio_pad_attr_3_re; + logic [9:0] dio_pad_attr_4_qs; + logic [9:0] dio_pad_attr_4_wd; + logic dio_pad_attr_4_we; + logic dio_pad_attr_4_re; + logic [9:0] dio_pad_attr_5_qs; + logic [9:0] dio_pad_attr_5_wd; + logic dio_pad_attr_5_we; + logic dio_pad_attr_5_re; + logic [9:0] dio_pad_attr_6_qs; + logic [9:0] dio_pad_attr_6_wd; + logic dio_pad_attr_6_we; + logic dio_pad_attr_6_re; + logic [9:0] dio_pad_attr_7_qs; + logic [9:0] dio_pad_attr_7_wd; + logic dio_pad_attr_7_we; + logic dio_pad_attr_7_re; + logic [9:0] dio_pad_attr_8_qs; + logic [9:0] dio_pad_attr_8_wd; + logic dio_pad_attr_8_we; + logic dio_pad_attr_8_re; + logic [9:0] dio_pad_attr_9_qs; + logic [9:0] dio_pad_attr_9_wd; + logic dio_pad_attr_9_we; + logic dio_pad_attr_9_re; + logic [9:0] dio_pad_attr_10_qs; + logic [9:0] dio_pad_attr_10_wd; + logic dio_pad_attr_10_we; + logic dio_pad_attr_10_re; + logic [9:0] dio_pad_attr_11_qs; + logic [9:0] dio_pad_attr_11_wd; + logic dio_pad_attr_11_we; + logic dio_pad_attr_11_re; + logic [9:0] dio_pad_attr_12_qs; + logic [9:0] dio_pad_attr_12_wd; + logic dio_pad_attr_12_we; + logic dio_pad_attr_12_re; + logic [9:0] dio_pad_attr_13_qs; + logic [9:0] dio_pad_attr_13_wd; + logic dio_pad_attr_13_we; + logic dio_pad_attr_13_re; + logic [9:0] dio_pad_attr_14_qs; + logic [9:0] dio_pad_attr_14_wd; + logic dio_pad_attr_14_we; + logic dio_pad_attr_14_re; + logic mio_pad_sleep_status_en_0_qs; + logic mio_pad_sleep_status_en_0_wd; + logic mio_pad_sleep_status_en_0_we; + logic mio_pad_sleep_status_en_1_qs; + logic mio_pad_sleep_status_en_1_wd; + logic mio_pad_sleep_status_en_1_we; + logic mio_pad_sleep_status_en_2_qs; + logic mio_pad_sleep_status_en_2_wd; + logic mio_pad_sleep_status_en_2_we; + logic mio_pad_sleep_status_en_3_qs; + logic mio_pad_sleep_status_en_3_wd; + logic mio_pad_sleep_status_en_3_we; + logic mio_pad_sleep_status_en_4_qs; + logic mio_pad_sleep_status_en_4_wd; + logic mio_pad_sleep_status_en_4_we; + logic mio_pad_sleep_status_en_5_qs; + logic mio_pad_sleep_status_en_5_wd; + logic mio_pad_sleep_status_en_5_we; + logic mio_pad_sleep_status_en_6_qs; + logic mio_pad_sleep_status_en_6_wd; + logic mio_pad_sleep_status_en_6_we; + logic mio_pad_sleep_status_en_7_qs; + logic mio_pad_sleep_status_en_7_wd; + logic mio_pad_sleep_status_en_7_we; + logic mio_pad_sleep_status_en_8_qs; + logic mio_pad_sleep_status_en_8_wd; + logic mio_pad_sleep_status_en_8_we; + logic mio_pad_sleep_status_en_9_qs; + logic mio_pad_sleep_status_en_9_wd; + logic mio_pad_sleep_status_en_9_we; + logic mio_pad_sleep_status_en_10_qs; + logic mio_pad_sleep_status_en_10_wd; + logic mio_pad_sleep_status_en_10_we; + logic mio_pad_sleep_status_en_11_qs; + logic mio_pad_sleep_status_en_11_wd; + logic mio_pad_sleep_status_en_11_we; + logic mio_pad_sleep_status_en_12_qs; + logic mio_pad_sleep_status_en_12_wd; + logic mio_pad_sleep_status_en_12_we; + logic mio_pad_sleep_status_en_13_qs; + logic mio_pad_sleep_status_en_13_wd; + logic mio_pad_sleep_status_en_13_we; + logic mio_pad_sleep_status_en_14_qs; + logic mio_pad_sleep_status_en_14_wd; + logic mio_pad_sleep_status_en_14_we; + logic mio_pad_sleep_status_en_15_qs; + logic mio_pad_sleep_status_en_15_wd; + logic mio_pad_sleep_status_en_15_we; + logic mio_pad_sleep_status_en_16_qs; + logic mio_pad_sleep_status_en_16_wd; + logic mio_pad_sleep_status_en_16_we; + logic mio_pad_sleep_status_en_17_qs; + logic mio_pad_sleep_status_en_17_wd; + logic mio_pad_sleep_status_en_17_we; + logic mio_pad_sleep_status_en_18_qs; + logic mio_pad_sleep_status_en_18_wd; + logic mio_pad_sleep_status_en_18_we; + logic mio_pad_sleep_status_en_19_qs; + logic mio_pad_sleep_status_en_19_wd; + logic mio_pad_sleep_status_en_19_we; + logic mio_pad_sleep_status_en_20_qs; + logic mio_pad_sleep_status_en_20_wd; + logic mio_pad_sleep_status_en_20_we; + logic mio_pad_sleep_status_en_21_qs; + logic mio_pad_sleep_status_en_21_wd; + logic mio_pad_sleep_status_en_21_we; + logic mio_pad_sleep_status_en_22_qs; + logic mio_pad_sleep_status_en_22_wd; + logic mio_pad_sleep_status_en_22_we; + logic mio_pad_sleep_status_en_23_qs; + logic mio_pad_sleep_status_en_23_wd; + logic mio_pad_sleep_status_en_23_we; + logic mio_pad_sleep_status_en_24_qs; + logic mio_pad_sleep_status_en_24_wd; + logic mio_pad_sleep_status_en_24_we; + logic mio_pad_sleep_status_en_25_qs; + logic mio_pad_sleep_status_en_25_wd; + logic mio_pad_sleep_status_en_25_we; + logic mio_pad_sleep_status_en_26_qs; + logic mio_pad_sleep_status_en_26_wd; + logic mio_pad_sleep_status_en_26_we; + logic mio_pad_sleep_status_en_27_qs; + logic mio_pad_sleep_status_en_27_wd; + logic mio_pad_sleep_status_en_27_we; + logic mio_pad_sleep_status_en_28_qs; + logic mio_pad_sleep_status_en_28_wd; + logic mio_pad_sleep_status_en_28_we; + logic mio_pad_sleep_status_en_29_qs; + logic mio_pad_sleep_status_en_29_wd; + logic mio_pad_sleep_status_en_29_we; + logic mio_pad_sleep_status_en_30_qs; + logic mio_pad_sleep_status_en_30_wd; + logic mio_pad_sleep_status_en_30_we; + logic mio_pad_sleep_status_en_31_qs; + logic mio_pad_sleep_status_en_31_wd; + logic mio_pad_sleep_status_en_31_we; + logic mio_pad_sleep_regwen_0_qs; + logic mio_pad_sleep_regwen_0_wd; + logic mio_pad_sleep_regwen_0_we; + logic mio_pad_sleep_regwen_1_qs; + logic mio_pad_sleep_regwen_1_wd; + logic mio_pad_sleep_regwen_1_we; + logic mio_pad_sleep_regwen_2_qs; + logic mio_pad_sleep_regwen_2_wd; + logic mio_pad_sleep_regwen_2_we; + logic mio_pad_sleep_regwen_3_qs; + logic mio_pad_sleep_regwen_3_wd; + logic mio_pad_sleep_regwen_3_we; + logic mio_pad_sleep_regwen_4_qs; + logic mio_pad_sleep_regwen_4_wd; + logic mio_pad_sleep_regwen_4_we; + logic mio_pad_sleep_regwen_5_qs; + logic mio_pad_sleep_regwen_5_wd; + logic mio_pad_sleep_regwen_5_we; + logic mio_pad_sleep_regwen_6_qs; + logic mio_pad_sleep_regwen_6_wd; + logic mio_pad_sleep_regwen_6_we; + logic mio_pad_sleep_regwen_7_qs; + logic mio_pad_sleep_regwen_7_wd; + logic mio_pad_sleep_regwen_7_we; + logic mio_pad_sleep_regwen_8_qs; + logic mio_pad_sleep_regwen_8_wd; + logic mio_pad_sleep_regwen_8_we; + logic mio_pad_sleep_regwen_9_qs; + logic mio_pad_sleep_regwen_9_wd; + logic mio_pad_sleep_regwen_9_we; + logic mio_pad_sleep_regwen_10_qs; + logic mio_pad_sleep_regwen_10_wd; + logic mio_pad_sleep_regwen_10_we; + logic mio_pad_sleep_regwen_11_qs; + logic mio_pad_sleep_regwen_11_wd; + logic mio_pad_sleep_regwen_11_we; + logic mio_pad_sleep_regwen_12_qs; + logic mio_pad_sleep_regwen_12_wd; + logic mio_pad_sleep_regwen_12_we; + logic mio_pad_sleep_regwen_13_qs; + logic mio_pad_sleep_regwen_13_wd; + logic mio_pad_sleep_regwen_13_we; + logic mio_pad_sleep_regwen_14_qs; + logic mio_pad_sleep_regwen_14_wd; + logic mio_pad_sleep_regwen_14_we; + logic mio_pad_sleep_regwen_15_qs; + logic mio_pad_sleep_regwen_15_wd; + logic mio_pad_sleep_regwen_15_we; + logic mio_pad_sleep_regwen_16_qs; + logic mio_pad_sleep_regwen_16_wd; + logic mio_pad_sleep_regwen_16_we; + logic mio_pad_sleep_regwen_17_qs; + logic mio_pad_sleep_regwen_17_wd; + logic mio_pad_sleep_regwen_17_we; + logic mio_pad_sleep_regwen_18_qs; + logic mio_pad_sleep_regwen_18_wd; + logic mio_pad_sleep_regwen_18_we; + logic mio_pad_sleep_regwen_19_qs; + logic mio_pad_sleep_regwen_19_wd; + logic mio_pad_sleep_regwen_19_we; + logic mio_pad_sleep_regwen_20_qs; + logic mio_pad_sleep_regwen_20_wd; + logic mio_pad_sleep_regwen_20_we; + logic mio_pad_sleep_regwen_21_qs; + logic mio_pad_sleep_regwen_21_wd; + logic mio_pad_sleep_regwen_21_we; + logic mio_pad_sleep_regwen_22_qs; + logic mio_pad_sleep_regwen_22_wd; + logic mio_pad_sleep_regwen_22_we; + logic mio_pad_sleep_regwen_23_qs; + logic mio_pad_sleep_regwen_23_wd; + logic mio_pad_sleep_regwen_23_we; + logic mio_pad_sleep_regwen_24_qs; + logic mio_pad_sleep_regwen_24_wd; + logic mio_pad_sleep_regwen_24_we; + logic mio_pad_sleep_regwen_25_qs; + logic mio_pad_sleep_regwen_25_wd; + logic mio_pad_sleep_regwen_25_we; + logic mio_pad_sleep_regwen_26_qs; + logic mio_pad_sleep_regwen_26_wd; + logic mio_pad_sleep_regwen_26_we; + logic mio_pad_sleep_regwen_27_qs; + logic mio_pad_sleep_regwen_27_wd; + logic mio_pad_sleep_regwen_27_we; + logic mio_pad_sleep_regwen_28_qs; + logic mio_pad_sleep_regwen_28_wd; + logic mio_pad_sleep_regwen_28_we; + logic mio_pad_sleep_regwen_29_qs; + logic mio_pad_sleep_regwen_29_wd; + logic mio_pad_sleep_regwen_29_we; + logic mio_pad_sleep_regwen_30_qs; + logic mio_pad_sleep_regwen_30_wd; + logic mio_pad_sleep_regwen_30_we; + logic mio_pad_sleep_regwen_31_qs; + logic mio_pad_sleep_regwen_31_wd; + logic mio_pad_sleep_regwen_31_we; + logic mio_pad_sleep_en_0_qs; + logic mio_pad_sleep_en_0_wd; + logic mio_pad_sleep_en_0_we; + logic mio_pad_sleep_en_1_qs; + logic mio_pad_sleep_en_1_wd; + logic mio_pad_sleep_en_1_we; + logic mio_pad_sleep_en_2_qs; + logic mio_pad_sleep_en_2_wd; + logic mio_pad_sleep_en_2_we; + logic mio_pad_sleep_en_3_qs; + logic mio_pad_sleep_en_3_wd; + logic mio_pad_sleep_en_3_we; + logic mio_pad_sleep_en_4_qs; + logic mio_pad_sleep_en_4_wd; + logic mio_pad_sleep_en_4_we; + logic mio_pad_sleep_en_5_qs; + logic mio_pad_sleep_en_5_wd; + logic mio_pad_sleep_en_5_we; + logic mio_pad_sleep_en_6_qs; + logic mio_pad_sleep_en_6_wd; + logic mio_pad_sleep_en_6_we; + logic mio_pad_sleep_en_7_qs; + logic mio_pad_sleep_en_7_wd; + logic mio_pad_sleep_en_7_we; + logic mio_pad_sleep_en_8_qs; + logic mio_pad_sleep_en_8_wd; + logic mio_pad_sleep_en_8_we; + logic mio_pad_sleep_en_9_qs; + logic mio_pad_sleep_en_9_wd; + logic mio_pad_sleep_en_9_we; + logic mio_pad_sleep_en_10_qs; + logic mio_pad_sleep_en_10_wd; + logic mio_pad_sleep_en_10_we; + logic mio_pad_sleep_en_11_qs; + logic mio_pad_sleep_en_11_wd; + logic mio_pad_sleep_en_11_we; + logic mio_pad_sleep_en_12_qs; + logic mio_pad_sleep_en_12_wd; + logic mio_pad_sleep_en_12_we; + logic mio_pad_sleep_en_13_qs; + logic mio_pad_sleep_en_13_wd; + logic mio_pad_sleep_en_13_we; + logic mio_pad_sleep_en_14_qs; + logic mio_pad_sleep_en_14_wd; + logic mio_pad_sleep_en_14_we; + logic mio_pad_sleep_en_15_qs; + logic mio_pad_sleep_en_15_wd; + logic mio_pad_sleep_en_15_we; + logic mio_pad_sleep_en_16_qs; + logic mio_pad_sleep_en_16_wd; + logic mio_pad_sleep_en_16_we; + logic mio_pad_sleep_en_17_qs; + logic mio_pad_sleep_en_17_wd; + logic mio_pad_sleep_en_17_we; + logic mio_pad_sleep_en_18_qs; + logic mio_pad_sleep_en_18_wd; + logic mio_pad_sleep_en_18_we; + logic mio_pad_sleep_en_19_qs; + logic mio_pad_sleep_en_19_wd; + logic mio_pad_sleep_en_19_we; + logic mio_pad_sleep_en_20_qs; + logic mio_pad_sleep_en_20_wd; + logic mio_pad_sleep_en_20_we; + logic mio_pad_sleep_en_21_qs; + logic mio_pad_sleep_en_21_wd; + logic mio_pad_sleep_en_21_we; + logic mio_pad_sleep_en_22_qs; + logic mio_pad_sleep_en_22_wd; + logic mio_pad_sleep_en_22_we; + logic mio_pad_sleep_en_23_qs; + logic mio_pad_sleep_en_23_wd; + logic mio_pad_sleep_en_23_we; + logic mio_pad_sleep_en_24_qs; + logic mio_pad_sleep_en_24_wd; + logic mio_pad_sleep_en_24_we; + logic mio_pad_sleep_en_25_qs; + logic mio_pad_sleep_en_25_wd; + logic mio_pad_sleep_en_25_we; + logic mio_pad_sleep_en_26_qs; + logic mio_pad_sleep_en_26_wd; + logic mio_pad_sleep_en_26_we; + logic mio_pad_sleep_en_27_qs; + logic mio_pad_sleep_en_27_wd; + logic mio_pad_sleep_en_27_we; + logic mio_pad_sleep_en_28_qs; + logic mio_pad_sleep_en_28_wd; + logic mio_pad_sleep_en_28_we; + logic mio_pad_sleep_en_29_qs; + logic mio_pad_sleep_en_29_wd; + logic mio_pad_sleep_en_29_we; + logic mio_pad_sleep_en_30_qs; + logic mio_pad_sleep_en_30_wd; + logic mio_pad_sleep_en_30_we; + logic mio_pad_sleep_en_31_qs; + logic mio_pad_sleep_en_31_wd; + logic mio_pad_sleep_en_31_we; + logic [1:0] mio_pad_sleep_mode_0_qs; + logic [1:0] mio_pad_sleep_mode_0_wd; + logic mio_pad_sleep_mode_0_we; + logic [1:0] mio_pad_sleep_mode_1_qs; + logic [1:0] mio_pad_sleep_mode_1_wd; + logic mio_pad_sleep_mode_1_we; + logic [1:0] mio_pad_sleep_mode_2_qs; + logic [1:0] mio_pad_sleep_mode_2_wd; + logic mio_pad_sleep_mode_2_we; + logic [1:0] mio_pad_sleep_mode_3_qs; + logic [1:0] mio_pad_sleep_mode_3_wd; + logic mio_pad_sleep_mode_3_we; + logic [1:0] mio_pad_sleep_mode_4_qs; + logic [1:0] mio_pad_sleep_mode_4_wd; + logic mio_pad_sleep_mode_4_we; + logic [1:0] mio_pad_sleep_mode_5_qs; + logic [1:0] mio_pad_sleep_mode_5_wd; + logic mio_pad_sleep_mode_5_we; + logic [1:0] mio_pad_sleep_mode_6_qs; + logic [1:0] mio_pad_sleep_mode_6_wd; + logic mio_pad_sleep_mode_6_we; + logic [1:0] mio_pad_sleep_mode_7_qs; + logic [1:0] mio_pad_sleep_mode_7_wd; + logic mio_pad_sleep_mode_7_we; + logic [1:0] mio_pad_sleep_mode_8_qs; + logic [1:0] mio_pad_sleep_mode_8_wd; + logic mio_pad_sleep_mode_8_we; + logic [1:0] mio_pad_sleep_mode_9_qs; + logic [1:0] mio_pad_sleep_mode_9_wd; + logic mio_pad_sleep_mode_9_we; + logic [1:0] mio_pad_sleep_mode_10_qs; + logic [1:0] mio_pad_sleep_mode_10_wd; + logic mio_pad_sleep_mode_10_we; + logic [1:0] mio_pad_sleep_mode_11_qs; + logic [1:0] mio_pad_sleep_mode_11_wd; + logic mio_pad_sleep_mode_11_we; + logic [1:0] mio_pad_sleep_mode_12_qs; + logic [1:0] mio_pad_sleep_mode_12_wd; + logic mio_pad_sleep_mode_12_we; + logic [1:0] mio_pad_sleep_mode_13_qs; + logic [1:0] mio_pad_sleep_mode_13_wd; + logic mio_pad_sleep_mode_13_we; + logic [1:0] mio_pad_sleep_mode_14_qs; + logic [1:0] mio_pad_sleep_mode_14_wd; + logic mio_pad_sleep_mode_14_we; + logic [1:0] mio_pad_sleep_mode_15_qs; + logic [1:0] mio_pad_sleep_mode_15_wd; + logic mio_pad_sleep_mode_15_we; + logic [1:0] mio_pad_sleep_mode_16_qs; + logic [1:0] mio_pad_sleep_mode_16_wd; + logic mio_pad_sleep_mode_16_we; + logic [1:0] mio_pad_sleep_mode_17_qs; + logic [1:0] mio_pad_sleep_mode_17_wd; + logic mio_pad_sleep_mode_17_we; + logic [1:0] mio_pad_sleep_mode_18_qs; + logic [1:0] mio_pad_sleep_mode_18_wd; + logic mio_pad_sleep_mode_18_we; + logic [1:0] mio_pad_sleep_mode_19_qs; + logic [1:0] mio_pad_sleep_mode_19_wd; + logic mio_pad_sleep_mode_19_we; + logic [1:0] mio_pad_sleep_mode_20_qs; + logic [1:0] mio_pad_sleep_mode_20_wd; + logic mio_pad_sleep_mode_20_we; + logic [1:0] mio_pad_sleep_mode_21_qs; + logic [1:0] mio_pad_sleep_mode_21_wd; + logic mio_pad_sleep_mode_21_we; + logic [1:0] mio_pad_sleep_mode_22_qs; + logic [1:0] mio_pad_sleep_mode_22_wd; + logic mio_pad_sleep_mode_22_we; + logic [1:0] mio_pad_sleep_mode_23_qs; + logic [1:0] mio_pad_sleep_mode_23_wd; + logic mio_pad_sleep_mode_23_we; + logic [1:0] mio_pad_sleep_mode_24_qs; + logic [1:0] mio_pad_sleep_mode_24_wd; + logic mio_pad_sleep_mode_24_we; + logic [1:0] mio_pad_sleep_mode_25_qs; + logic [1:0] mio_pad_sleep_mode_25_wd; + logic mio_pad_sleep_mode_25_we; + logic [1:0] mio_pad_sleep_mode_26_qs; + logic [1:0] mio_pad_sleep_mode_26_wd; + logic mio_pad_sleep_mode_26_we; + logic [1:0] mio_pad_sleep_mode_27_qs; + logic [1:0] mio_pad_sleep_mode_27_wd; + logic mio_pad_sleep_mode_27_we; + logic [1:0] mio_pad_sleep_mode_28_qs; + logic [1:0] mio_pad_sleep_mode_28_wd; + logic mio_pad_sleep_mode_28_we; + logic [1:0] mio_pad_sleep_mode_29_qs; + logic [1:0] mio_pad_sleep_mode_29_wd; + logic mio_pad_sleep_mode_29_we; + logic [1:0] mio_pad_sleep_mode_30_qs; + logic [1:0] mio_pad_sleep_mode_30_wd; + logic mio_pad_sleep_mode_30_we; + logic [1:0] mio_pad_sleep_mode_31_qs; + logic [1:0] mio_pad_sleep_mode_31_wd; + logic mio_pad_sleep_mode_31_we; + logic dio_pad_sleep_status_en_0_qs; + logic dio_pad_sleep_status_en_0_wd; + logic dio_pad_sleep_status_en_0_we; + logic dio_pad_sleep_status_en_1_qs; + logic dio_pad_sleep_status_en_1_wd; + logic dio_pad_sleep_status_en_1_we; + logic dio_pad_sleep_status_en_2_qs; + logic dio_pad_sleep_status_en_2_wd; + logic dio_pad_sleep_status_en_2_we; + logic dio_pad_sleep_status_en_3_qs; + logic dio_pad_sleep_status_en_3_wd; + logic dio_pad_sleep_status_en_3_we; + logic dio_pad_sleep_status_en_4_qs; + logic dio_pad_sleep_status_en_4_wd; + logic dio_pad_sleep_status_en_4_we; + logic dio_pad_sleep_status_en_5_qs; + logic dio_pad_sleep_status_en_5_wd; + logic dio_pad_sleep_status_en_5_we; + logic dio_pad_sleep_status_en_6_qs; + logic dio_pad_sleep_status_en_6_wd; + logic dio_pad_sleep_status_en_6_we; + logic dio_pad_sleep_status_en_7_qs; + logic dio_pad_sleep_status_en_7_wd; + logic dio_pad_sleep_status_en_7_we; + logic dio_pad_sleep_status_en_8_qs; + logic dio_pad_sleep_status_en_8_wd; + logic dio_pad_sleep_status_en_8_we; + logic dio_pad_sleep_status_en_9_qs; + logic dio_pad_sleep_status_en_9_wd; + logic dio_pad_sleep_status_en_9_we; + logic dio_pad_sleep_status_en_10_qs; + logic dio_pad_sleep_status_en_10_wd; + logic dio_pad_sleep_status_en_10_we; + logic dio_pad_sleep_status_en_11_qs; + logic dio_pad_sleep_status_en_11_wd; + logic dio_pad_sleep_status_en_11_we; + logic dio_pad_sleep_status_en_12_qs; + logic dio_pad_sleep_status_en_12_wd; + logic dio_pad_sleep_status_en_12_we; + logic dio_pad_sleep_status_en_13_qs; + logic dio_pad_sleep_status_en_13_wd; + logic dio_pad_sleep_status_en_13_we; + logic dio_pad_sleep_status_en_14_qs; + logic dio_pad_sleep_status_en_14_wd; + logic dio_pad_sleep_status_en_14_we; + logic dio_pad_sleep_regwen_0_qs; + logic dio_pad_sleep_regwen_0_wd; + logic dio_pad_sleep_regwen_0_we; + logic dio_pad_sleep_regwen_1_qs; + logic dio_pad_sleep_regwen_1_wd; + logic dio_pad_sleep_regwen_1_we; + logic dio_pad_sleep_regwen_2_qs; + logic dio_pad_sleep_regwen_2_wd; + logic dio_pad_sleep_regwen_2_we; + logic dio_pad_sleep_regwen_3_qs; + logic dio_pad_sleep_regwen_3_wd; + logic dio_pad_sleep_regwen_3_we; + logic dio_pad_sleep_regwen_4_qs; + logic dio_pad_sleep_regwen_4_wd; + logic dio_pad_sleep_regwen_4_we; + logic dio_pad_sleep_regwen_5_qs; + logic dio_pad_sleep_regwen_5_wd; + logic dio_pad_sleep_regwen_5_we; + logic dio_pad_sleep_regwen_6_qs; + logic dio_pad_sleep_regwen_6_wd; + logic dio_pad_sleep_regwen_6_we; + logic dio_pad_sleep_regwen_7_qs; + logic dio_pad_sleep_regwen_7_wd; + logic dio_pad_sleep_regwen_7_we; + logic dio_pad_sleep_regwen_8_qs; + logic dio_pad_sleep_regwen_8_wd; + logic dio_pad_sleep_regwen_8_we; + logic dio_pad_sleep_regwen_9_qs; + logic dio_pad_sleep_regwen_9_wd; + logic dio_pad_sleep_regwen_9_we; + logic dio_pad_sleep_regwen_10_qs; + logic dio_pad_sleep_regwen_10_wd; + logic dio_pad_sleep_regwen_10_we; + logic dio_pad_sleep_regwen_11_qs; + logic dio_pad_sleep_regwen_11_wd; + logic dio_pad_sleep_regwen_11_we; + logic dio_pad_sleep_regwen_12_qs; + logic dio_pad_sleep_regwen_12_wd; + logic dio_pad_sleep_regwen_12_we; + logic dio_pad_sleep_regwen_13_qs; + logic dio_pad_sleep_regwen_13_wd; + logic dio_pad_sleep_regwen_13_we; + logic dio_pad_sleep_regwen_14_qs; + logic dio_pad_sleep_regwen_14_wd; + logic dio_pad_sleep_regwen_14_we; + logic dio_pad_sleep_en_0_qs; + logic dio_pad_sleep_en_0_wd; + logic dio_pad_sleep_en_0_we; + logic dio_pad_sleep_en_1_qs; + logic dio_pad_sleep_en_1_wd; + logic dio_pad_sleep_en_1_we; + logic dio_pad_sleep_en_2_qs; + logic dio_pad_sleep_en_2_wd; + logic dio_pad_sleep_en_2_we; + logic dio_pad_sleep_en_3_qs; + logic dio_pad_sleep_en_3_wd; + logic dio_pad_sleep_en_3_we; + logic dio_pad_sleep_en_4_qs; + logic dio_pad_sleep_en_4_wd; + logic dio_pad_sleep_en_4_we; + logic dio_pad_sleep_en_5_qs; + logic dio_pad_sleep_en_5_wd; + logic dio_pad_sleep_en_5_we; + logic dio_pad_sleep_en_6_qs; + logic dio_pad_sleep_en_6_wd; + logic dio_pad_sleep_en_6_we; + logic dio_pad_sleep_en_7_qs; + logic dio_pad_sleep_en_7_wd; + logic dio_pad_sleep_en_7_we; + logic dio_pad_sleep_en_8_qs; + logic dio_pad_sleep_en_8_wd; + logic dio_pad_sleep_en_8_we; + logic dio_pad_sleep_en_9_qs; + logic dio_pad_sleep_en_9_wd; + logic dio_pad_sleep_en_9_we; + logic dio_pad_sleep_en_10_qs; + logic dio_pad_sleep_en_10_wd; + logic dio_pad_sleep_en_10_we; + logic dio_pad_sleep_en_11_qs; + logic dio_pad_sleep_en_11_wd; + logic dio_pad_sleep_en_11_we; + logic dio_pad_sleep_en_12_qs; + logic dio_pad_sleep_en_12_wd; + logic dio_pad_sleep_en_12_we; + logic dio_pad_sleep_en_13_qs; + logic dio_pad_sleep_en_13_wd; + logic dio_pad_sleep_en_13_we; + logic dio_pad_sleep_en_14_qs; + logic dio_pad_sleep_en_14_wd; + logic dio_pad_sleep_en_14_we; + logic [1:0] dio_pad_sleep_mode_0_qs; + logic [1:0] dio_pad_sleep_mode_0_wd; + logic dio_pad_sleep_mode_0_we; + logic [1:0] dio_pad_sleep_mode_1_qs; + logic [1:0] dio_pad_sleep_mode_1_wd; + logic dio_pad_sleep_mode_1_we; + logic [1:0] dio_pad_sleep_mode_2_qs; + logic [1:0] dio_pad_sleep_mode_2_wd; + logic dio_pad_sleep_mode_2_we; + logic [1:0] dio_pad_sleep_mode_3_qs; + logic [1:0] dio_pad_sleep_mode_3_wd; + logic dio_pad_sleep_mode_3_we; + logic [1:0] dio_pad_sleep_mode_4_qs; + logic [1:0] dio_pad_sleep_mode_4_wd; + logic dio_pad_sleep_mode_4_we; + logic [1:0] dio_pad_sleep_mode_5_qs; + logic [1:0] dio_pad_sleep_mode_5_wd; + logic dio_pad_sleep_mode_5_we; + logic [1:0] dio_pad_sleep_mode_6_qs; + logic [1:0] dio_pad_sleep_mode_6_wd; + logic dio_pad_sleep_mode_6_we; + logic [1:0] dio_pad_sleep_mode_7_qs; + logic [1:0] dio_pad_sleep_mode_7_wd; + logic dio_pad_sleep_mode_7_we; + logic [1:0] dio_pad_sleep_mode_8_qs; + logic [1:0] dio_pad_sleep_mode_8_wd; + logic dio_pad_sleep_mode_8_we; + logic [1:0] dio_pad_sleep_mode_9_qs; + logic [1:0] dio_pad_sleep_mode_9_wd; + logic dio_pad_sleep_mode_9_we; + logic [1:0] dio_pad_sleep_mode_10_qs; + logic [1:0] dio_pad_sleep_mode_10_wd; + logic dio_pad_sleep_mode_10_we; + logic [1:0] dio_pad_sleep_mode_11_qs; + logic [1:0] dio_pad_sleep_mode_11_wd; + logic dio_pad_sleep_mode_11_we; + logic [1:0] dio_pad_sleep_mode_12_qs; + logic [1:0] dio_pad_sleep_mode_12_wd; + logic dio_pad_sleep_mode_12_we; + logic [1:0] dio_pad_sleep_mode_13_qs; + logic [1:0] dio_pad_sleep_mode_13_wd; + logic dio_pad_sleep_mode_13_we; + logic [1:0] dio_pad_sleep_mode_14_qs; + logic [1:0] dio_pad_sleep_mode_14_wd; + logic dio_pad_sleep_mode_14_we; logic wkup_detector_regwen_0_qs; logic wkup_detector_regwen_0_wd; logic wkup_detector_regwen_0_we; @@ -4959,20 +5555,20 @@ - // Subregister 0 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_0]: V(False) + // Subregister 0 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_0]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_0 ( + ) u_mio_pad_attr_regwen_0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_0_we), - .wd (mio_out_sleep_regwen_0_wd), + .we (mio_pad_attr_regwen_0_we), + .wd (mio_pad_attr_regwen_0_wd), // from internal hardware .de (1'b0), @@ -4983,23 +5579,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_0_qs) + .qs (mio_pad_attr_regwen_0_qs) ); - // Subregister 1 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_1]: V(False) + // Subregister 1 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_1]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_1 ( + ) u_mio_pad_attr_regwen_1 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_1_we), - .wd (mio_out_sleep_regwen_1_wd), + .we (mio_pad_attr_regwen_1_we), + .wd (mio_pad_attr_regwen_1_wd), // from internal hardware .de (1'b0), @@ -5010,23 +5606,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_1_qs) + .qs (mio_pad_attr_regwen_1_qs) ); - // Subregister 2 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_2]: V(False) + // Subregister 2 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_2]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_2 ( + ) u_mio_pad_attr_regwen_2 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_2_we), - .wd (mio_out_sleep_regwen_2_wd), + .we (mio_pad_attr_regwen_2_we), + .wd (mio_pad_attr_regwen_2_wd), // from internal hardware .de (1'b0), @@ -5037,23 +5633,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_2_qs) + .qs (mio_pad_attr_regwen_2_qs) ); - // Subregister 3 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_3]: V(False) + // Subregister 3 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_3]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_3 ( + ) u_mio_pad_attr_regwen_3 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_3_we), - .wd (mio_out_sleep_regwen_3_wd), + .we (mio_pad_attr_regwen_3_we), + .wd (mio_pad_attr_regwen_3_wd), // from internal hardware .de (1'b0), @@ -5064,23 +5660,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_3_qs) + .qs (mio_pad_attr_regwen_3_qs) ); - // Subregister 4 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_4]: V(False) + // Subregister 4 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_4]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_4 ( + ) u_mio_pad_attr_regwen_4 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_4_we), - .wd (mio_out_sleep_regwen_4_wd), + .we (mio_pad_attr_regwen_4_we), + .wd (mio_pad_attr_regwen_4_wd), // from internal hardware .de (1'b0), @@ -5091,23 +5687,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_4_qs) + .qs (mio_pad_attr_regwen_4_qs) ); - // Subregister 5 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_5]: V(False) + // Subregister 5 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_5]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_5 ( + ) u_mio_pad_attr_regwen_5 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_5_we), - .wd (mio_out_sleep_regwen_5_wd), + .we (mio_pad_attr_regwen_5_we), + .wd (mio_pad_attr_regwen_5_wd), // from internal hardware .de (1'b0), @@ -5118,23 +5714,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_5_qs) + .qs (mio_pad_attr_regwen_5_qs) ); - // Subregister 6 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_6]: V(False) + // Subregister 6 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_6]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_6 ( + ) u_mio_pad_attr_regwen_6 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_6_we), - .wd (mio_out_sleep_regwen_6_wd), + .we (mio_pad_attr_regwen_6_we), + .wd (mio_pad_attr_regwen_6_wd), // from internal hardware .de (1'b0), @@ -5145,23 +5741,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_6_qs) + .qs (mio_pad_attr_regwen_6_qs) ); - // Subregister 7 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_7]: V(False) + // Subregister 7 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_7]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_7 ( + ) u_mio_pad_attr_regwen_7 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_7_we), - .wd (mio_out_sleep_regwen_7_wd), + .we (mio_pad_attr_regwen_7_we), + .wd (mio_pad_attr_regwen_7_wd), // from internal hardware .de (1'b0), @@ -5172,23 +5768,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_7_qs) + .qs (mio_pad_attr_regwen_7_qs) ); - // Subregister 8 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_8]: V(False) + // Subregister 8 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_8]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_8 ( + ) u_mio_pad_attr_regwen_8 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_8_we), - .wd (mio_out_sleep_regwen_8_wd), + .we (mio_pad_attr_regwen_8_we), + .wd (mio_pad_attr_regwen_8_wd), // from internal hardware .de (1'b0), @@ -5199,23 +5795,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_8_qs) + .qs (mio_pad_attr_regwen_8_qs) ); - // Subregister 9 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_9]: V(False) + // Subregister 9 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_9]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_9 ( + ) u_mio_pad_attr_regwen_9 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_9_we), - .wd (mio_out_sleep_regwen_9_wd), + .we (mio_pad_attr_regwen_9_we), + .wd (mio_pad_attr_regwen_9_wd), // from internal hardware .de (1'b0), @@ -5226,23 +5822,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_9_qs) + .qs (mio_pad_attr_regwen_9_qs) ); - // Subregister 10 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_10]: V(False) + // Subregister 10 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_10]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_10 ( + ) u_mio_pad_attr_regwen_10 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_10_we), - .wd (mio_out_sleep_regwen_10_wd), + .we (mio_pad_attr_regwen_10_we), + .wd (mio_pad_attr_regwen_10_wd), // from internal hardware .de (1'b0), @@ -5253,23 +5849,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_10_qs) + .qs (mio_pad_attr_regwen_10_qs) ); - // Subregister 11 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_11]: V(False) + // Subregister 11 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_11]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_11 ( + ) u_mio_pad_attr_regwen_11 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_11_we), - .wd (mio_out_sleep_regwen_11_wd), + .we (mio_pad_attr_regwen_11_we), + .wd (mio_pad_attr_regwen_11_wd), // from internal hardware .de (1'b0), @@ -5280,23 +5876,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_11_qs) + .qs (mio_pad_attr_regwen_11_qs) ); - // Subregister 12 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_12]: V(False) + // Subregister 12 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_12]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_12 ( + ) u_mio_pad_attr_regwen_12 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_12_we), - .wd (mio_out_sleep_regwen_12_wd), + .we (mio_pad_attr_regwen_12_we), + .wd (mio_pad_attr_regwen_12_wd), // from internal hardware .de (1'b0), @@ -5307,23 +5903,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_12_qs) + .qs (mio_pad_attr_regwen_12_qs) ); - // Subregister 13 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_13]: V(False) + // Subregister 13 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_13]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_13 ( + ) u_mio_pad_attr_regwen_13 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_13_we), - .wd (mio_out_sleep_regwen_13_wd), + .we (mio_pad_attr_regwen_13_we), + .wd (mio_pad_attr_regwen_13_wd), // from internal hardware .de (1'b0), @@ -5334,23 +5930,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_13_qs) + .qs (mio_pad_attr_regwen_13_qs) ); - // Subregister 14 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_14]: V(False) + // Subregister 14 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_14]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_14 ( + ) u_mio_pad_attr_regwen_14 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_14_we), - .wd (mio_out_sleep_regwen_14_wd), + .we (mio_pad_attr_regwen_14_we), + .wd (mio_pad_attr_regwen_14_wd), // from internal hardware .de (1'b0), @@ -5361,23 +5957,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_14_qs) + .qs (mio_pad_attr_regwen_14_qs) ); - // Subregister 15 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_15]: V(False) + // Subregister 15 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_15]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_15 ( + ) u_mio_pad_attr_regwen_15 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_15_we), - .wd (mio_out_sleep_regwen_15_wd), + .we (mio_pad_attr_regwen_15_we), + .wd (mio_pad_attr_regwen_15_wd), // from internal hardware .de (1'b0), @@ -5388,23 +5984,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_15_qs) + .qs (mio_pad_attr_regwen_15_qs) ); - // Subregister 16 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_16]: V(False) + // Subregister 16 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_16]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_16 ( + ) u_mio_pad_attr_regwen_16 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_16_we), - .wd (mio_out_sleep_regwen_16_wd), + .we (mio_pad_attr_regwen_16_we), + .wd (mio_pad_attr_regwen_16_wd), // from internal hardware .de (1'b0), @@ -5415,23 +6011,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_16_qs) + .qs (mio_pad_attr_regwen_16_qs) ); - // Subregister 17 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_17]: V(False) + // Subregister 17 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_17]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_17 ( + ) u_mio_pad_attr_regwen_17 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_17_we), - .wd (mio_out_sleep_regwen_17_wd), + .we (mio_pad_attr_regwen_17_we), + .wd (mio_pad_attr_regwen_17_wd), // from internal hardware .de (1'b0), @@ -5442,23 +6038,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_17_qs) + .qs (mio_pad_attr_regwen_17_qs) ); - // Subregister 18 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_18]: V(False) + // Subregister 18 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_18]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_18 ( + ) u_mio_pad_attr_regwen_18 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_18_we), - .wd (mio_out_sleep_regwen_18_wd), + .we (mio_pad_attr_regwen_18_we), + .wd (mio_pad_attr_regwen_18_wd), // from internal hardware .de (1'b0), @@ -5469,23 +6065,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_18_qs) + .qs (mio_pad_attr_regwen_18_qs) ); - // Subregister 19 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_19]: V(False) + // Subregister 19 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_19]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_19 ( + ) u_mio_pad_attr_regwen_19 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_19_we), - .wd (mio_out_sleep_regwen_19_wd), + .we (mio_pad_attr_regwen_19_we), + .wd (mio_pad_attr_regwen_19_wd), // from internal hardware .de (1'b0), @@ -5496,23 +6092,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_19_qs) + .qs (mio_pad_attr_regwen_19_qs) ); - // Subregister 20 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_20]: V(False) + // Subregister 20 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_20]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_20 ( + ) u_mio_pad_attr_regwen_20 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_20_we), - .wd (mio_out_sleep_regwen_20_wd), + .we (mio_pad_attr_regwen_20_we), + .wd (mio_pad_attr_regwen_20_wd), // from internal hardware .de (1'b0), @@ -5523,23 +6119,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_20_qs) + .qs (mio_pad_attr_regwen_20_qs) ); - // Subregister 21 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_21]: V(False) + // Subregister 21 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_21]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_21 ( + ) u_mio_pad_attr_regwen_21 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_21_we), - .wd (mio_out_sleep_regwen_21_wd), + .we (mio_pad_attr_regwen_21_we), + .wd (mio_pad_attr_regwen_21_wd), // from internal hardware .de (1'b0), @@ -5550,23 +6146,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_21_qs) + .qs (mio_pad_attr_regwen_21_qs) ); - // Subregister 22 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_22]: V(False) + // Subregister 22 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_22]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_22 ( + ) u_mio_pad_attr_regwen_22 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_22_we), - .wd (mio_out_sleep_regwen_22_wd), + .we (mio_pad_attr_regwen_22_we), + .wd (mio_pad_attr_regwen_22_wd), // from internal hardware .de (1'b0), @@ -5577,23 +6173,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_22_qs) + .qs (mio_pad_attr_regwen_22_qs) ); - // Subregister 23 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_23]: V(False) + // Subregister 23 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_23]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_23 ( + ) u_mio_pad_attr_regwen_23 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_23_we), - .wd (mio_out_sleep_regwen_23_wd), + .we (mio_pad_attr_regwen_23_we), + .wd (mio_pad_attr_regwen_23_wd), // from internal hardware .de (1'b0), @@ -5604,23 +6200,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_23_qs) + .qs (mio_pad_attr_regwen_23_qs) ); - // Subregister 24 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_24]: V(False) + // Subregister 24 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_24]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_24 ( + ) u_mio_pad_attr_regwen_24 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_24_we), - .wd (mio_out_sleep_regwen_24_wd), + .we (mio_pad_attr_regwen_24_we), + .wd (mio_pad_attr_regwen_24_wd), // from internal hardware .de (1'b0), @@ -5631,23 +6227,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_24_qs) + .qs (mio_pad_attr_regwen_24_qs) ); - // Subregister 25 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_25]: V(False) + // Subregister 25 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_25]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_25 ( + ) u_mio_pad_attr_regwen_25 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_25_we), - .wd (mio_out_sleep_regwen_25_wd), + .we (mio_pad_attr_regwen_25_we), + .wd (mio_pad_attr_regwen_25_wd), // from internal hardware .de (1'b0), @@ -5658,23 +6254,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_25_qs) + .qs (mio_pad_attr_regwen_25_qs) ); - // Subregister 26 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_26]: V(False) + // Subregister 26 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_26]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_26 ( + ) u_mio_pad_attr_regwen_26 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_26_we), - .wd (mio_out_sleep_regwen_26_wd), + .we (mio_pad_attr_regwen_26_we), + .wd (mio_pad_attr_regwen_26_wd), // from internal hardware .de (1'b0), @@ -5685,23 +6281,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_26_qs) + .qs (mio_pad_attr_regwen_26_qs) ); - // Subregister 27 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_27]: V(False) + // Subregister 27 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_27]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_27 ( + ) u_mio_pad_attr_regwen_27 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_27_we), - .wd (mio_out_sleep_regwen_27_wd), + .we (mio_pad_attr_regwen_27_we), + .wd (mio_pad_attr_regwen_27_wd), // from internal hardware .de (1'b0), @@ -5712,23 +6308,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_27_qs) + .qs (mio_pad_attr_regwen_27_qs) ); - // Subregister 28 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_28]: V(False) + // Subregister 28 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_28]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_28 ( + ) u_mio_pad_attr_regwen_28 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_28_we), - .wd (mio_out_sleep_regwen_28_wd), + .we (mio_pad_attr_regwen_28_we), + .wd (mio_pad_attr_regwen_28_wd), // from internal hardware .de (1'b0), @@ -5739,23 +6335,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_28_qs) + .qs (mio_pad_attr_regwen_28_qs) ); - // Subregister 29 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_29]: V(False) + // Subregister 29 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_29]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_29 ( + ) u_mio_pad_attr_regwen_29 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_29_we), - .wd (mio_out_sleep_regwen_29_wd), + .we (mio_pad_attr_regwen_29_we), + .wd (mio_pad_attr_regwen_29_wd), // from internal hardware .de (1'b0), @@ -5766,23 +6362,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_29_qs) + .qs (mio_pad_attr_regwen_29_qs) ); - // Subregister 30 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_30]: V(False) + // Subregister 30 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_30]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_30 ( + ) u_mio_pad_attr_regwen_30 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_30_we), - .wd (mio_out_sleep_regwen_30_wd), + .we (mio_pad_attr_regwen_30_we), + .wd (mio_pad_attr_regwen_30_wd), // from internal hardware .de (1'b0), @@ -5793,23 +6389,23 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_30_qs) + .qs (mio_pad_attr_regwen_30_qs) ); - // Subregister 31 of Multireg mio_out_sleep_regwen - // R[mio_out_sleep_regwen_31]: V(False) + // Subregister 31 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_31]: V(False) prim_subreg #( .DW (1), .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_mio_out_sleep_regwen_31 ( + ) u_mio_pad_attr_regwen_31 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (mio_out_sleep_regwen_31_we), - .wd (mio_out_sleep_regwen_31_wd), + .we (mio_pad_attr_regwen_31_we), + .wd (mio_pad_attr_regwen_31_wd), // from internal hardware .de (1'b0), @@ -5820,1537 +6416,6268 @@ .q (), // to register interface (read) - .qs (mio_out_sleep_regwen_31_qs) + .qs (mio_pad_attr_regwen_31_qs) ); - // Subregister 0 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_0]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_0_we & mio_out_sleep_regwen_0_qs), - .wd (mio_out_sleep_val_0_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[0].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_0_qs) - ); - - // Subregister 1 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_1]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_1_we & mio_out_sleep_regwen_1_qs), - .wd (mio_out_sleep_val_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[1].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_1_qs) - ); - - // Subregister 2 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_2]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_2_we & mio_out_sleep_regwen_2_qs), - .wd (mio_out_sleep_val_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[2].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_2_qs) - ); - - // Subregister 3 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_3]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_3_we & mio_out_sleep_regwen_3_qs), - .wd (mio_out_sleep_val_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[3].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_3_qs) - ); - - // Subregister 4 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_4]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_4_we & mio_out_sleep_regwen_4_qs), - .wd (mio_out_sleep_val_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[4].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_4_qs) - ); - - // Subregister 5 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_5]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_5_we & mio_out_sleep_regwen_5_qs), - .wd (mio_out_sleep_val_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[5].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_5_qs) - ); - - // Subregister 6 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_6]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_6_we & mio_out_sleep_regwen_6_qs), - .wd (mio_out_sleep_val_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[6].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_6_qs) - ); - - // Subregister 7 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_7]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_7_we & mio_out_sleep_regwen_7_qs), - .wd (mio_out_sleep_val_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[7].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_7_qs) - ); - - // Subregister 8 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_8]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_8_we & mio_out_sleep_regwen_8_qs), - .wd (mio_out_sleep_val_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[8].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_8_qs) - ); - - // Subregister 9 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_9]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_9_we & mio_out_sleep_regwen_9_qs), - .wd (mio_out_sleep_val_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[9].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_9_qs) - ); - - // Subregister 10 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_10]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_10_we & mio_out_sleep_regwen_10_qs), - .wd (mio_out_sleep_val_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[10].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_10_qs) - ); - - // Subregister 11 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_11]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_11_we & mio_out_sleep_regwen_11_qs), - .wd (mio_out_sleep_val_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[11].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_11_qs) - ); - - // Subregister 12 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_12]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_12_we & mio_out_sleep_regwen_12_qs), - .wd (mio_out_sleep_val_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[12].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_12_qs) - ); - - // Subregister 13 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_13]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_13_we & mio_out_sleep_regwen_13_qs), - .wd (mio_out_sleep_val_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[13].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_13_qs) - ); - - // Subregister 14 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_14]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_14_we & mio_out_sleep_regwen_14_qs), - .wd (mio_out_sleep_val_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[14].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_14_qs) - ); - - // Subregister 15 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_15]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_15_we & mio_out_sleep_regwen_15_qs), - .wd (mio_out_sleep_val_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[15].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_15_qs) - ); - - // Subregister 16 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_16]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_16 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_16_we & mio_out_sleep_regwen_16_qs), - .wd (mio_out_sleep_val_16_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[16].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_16_qs) - ); - - // Subregister 17 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_17]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_17 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_17_we & mio_out_sleep_regwen_17_qs), - .wd (mio_out_sleep_val_17_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[17].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_17_qs) - ); - - // Subregister 18 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_18]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_18 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_18_we & mio_out_sleep_regwen_18_qs), - .wd (mio_out_sleep_val_18_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[18].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_18_qs) - ); - - // Subregister 19 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_19]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_19 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_19_we & mio_out_sleep_regwen_19_qs), - .wd (mio_out_sleep_val_19_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[19].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_19_qs) - ); - - // Subregister 20 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_20]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_20 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_20_we & mio_out_sleep_regwen_20_qs), - .wd (mio_out_sleep_val_20_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[20].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_20_qs) - ); - - // Subregister 21 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_21]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_21 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_21_we & mio_out_sleep_regwen_21_qs), - .wd (mio_out_sleep_val_21_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[21].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_21_qs) - ); - - // Subregister 22 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_22]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_22 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_22_we & mio_out_sleep_regwen_22_qs), - .wd (mio_out_sleep_val_22_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[22].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_22_qs) - ); - - // Subregister 23 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_23]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_23 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_23_we & mio_out_sleep_regwen_23_qs), - .wd (mio_out_sleep_val_23_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[23].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_23_qs) - ); - - // Subregister 24 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_24]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_24 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_24_we & mio_out_sleep_regwen_24_qs), - .wd (mio_out_sleep_val_24_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[24].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_24_qs) - ); - - // Subregister 25 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_25]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_25 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_25_we & mio_out_sleep_regwen_25_qs), - .wd (mio_out_sleep_val_25_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[25].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_25_qs) - ); - - // Subregister 26 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_26]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_26 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_26_we & mio_out_sleep_regwen_26_qs), - .wd (mio_out_sleep_val_26_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[26].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_26_qs) - ); - - // Subregister 27 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_27]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_27 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_27_we & mio_out_sleep_regwen_27_qs), - .wd (mio_out_sleep_val_27_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[27].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_27_qs) - ); - - // Subregister 28 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_28]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_28 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_28_we & mio_out_sleep_regwen_28_qs), - .wd (mio_out_sleep_val_28_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[28].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_28_qs) - ); - - // Subregister 29 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_29]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_29 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_29_we & mio_out_sleep_regwen_29_qs), - .wd (mio_out_sleep_val_29_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[29].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_29_qs) - ); - - // Subregister 30 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_30]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_30 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_30_we & mio_out_sleep_regwen_30_qs), - .wd (mio_out_sleep_val_30_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[30].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_30_qs) - ); - - // Subregister 31 of Multireg mio_out_sleep_val - // R[mio_out_sleep_val_31]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h2) - ) u_mio_out_sleep_val_31 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (mio_out_sleep_val_31_we & mio_out_sleep_regwen_31_qs), - .wd (mio_out_sleep_val_31_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.mio_out_sleep_val[31].q ), - - // to register interface (read) - .qs (mio_out_sleep_val_31_qs) - ); - - - - // Subregister 0 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_0]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_0_we), - .wd (dio_out_sleep_regwen_0_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_0_qs) - ); - - // Subregister 1 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_1]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_1_we), - .wd (dio_out_sleep_regwen_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_1_qs) - ); - - // Subregister 2 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_2]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_2_we), - .wd (dio_out_sleep_regwen_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_2_qs) - ); - - // Subregister 3 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_3]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_3_we), - .wd (dio_out_sleep_regwen_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_3_qs) - ); - - // Subregister 4 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_4]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_4_we), - .wd (dio_out_sleep_regwen_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_4_qs) - ); - - // Subregister 5 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_5]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_5_we), - .wd (dio_out_sleep_regwen_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_5_qs) - ); - - // Subregister 6 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_6]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_6_we), - .wd (dio_out_sleep_regwen_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_6_qs) - ); - - // Subregister 7 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_7]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_7_we), - .wd (dio_out_sleep_regwen_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_7_qs) - ); - - // Subregister 8 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_8]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_8_we), - .wd (dio_out_sleep_regwen_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_8_qs) - ); - - // Subregister 9 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_9]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_9_we), - .wd (dio_out_sleep_regwen_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_9_qs) - ); - - // Subregister 10 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_10]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_10_we), - .wd (dio_out_sleep_regwen_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_10_qs) - ); - - // Subregister 11 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_11]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_11_we), - .wd (dio_out_sleep_regwen_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_11_qs) - ); - - // Subregister 12 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_12]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_12_we), - .wd (dio_out_sleep_regwen_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_12_qs) - ); - - // Subregister 13 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_13]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_13_we), - .wd (dio_out_sleep_regwen_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_13_qs) - ); - - // Subregister 14 of Multireg dio_out_sleep_regwen - // R[dio_out_sleep_regwen_14]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W0C"), - .RESVAL (1'h1) - ) u_dio_out_sleep_regwen_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dio_out_sleep_regwen_14_we), - .wd (dio_out_sleep_regwen_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (dio_out_sleep_regwen_14_qs) - ); - - - - // Subregister 0 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_0]: V(True) + // Subregister 0 of Multireg mio_pad_attr + // R[mio_pad_attr_0]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_0 ( - .re (dio_out_sleep_val_0_re), + .DW (10) + ) u_mio_pad_attr_0 ( + .re (mio_pad_attr_0_re), // qualified with register enable - .we (dio_out_sleep_val_0_we & dio_out_sleep_regwen_0_qs), - .wd (dio_out_sleep_val_0_wd), - .d (hw2reg.dio_out_sleep_val[0].d), + .we (mio_pad_attr_0_we & mio_pad_attr_regwen_0_qs), + .wd (mio_pad_attr_0_wd), + .d (hw2reg.mio_pad_attr[0].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[0].qe), - .q (reg2hw.dio_out_sleep_val[0].q ), - .qs (dio_out_sleep_val_0_qs) + .qe (reg2hw.mio_pad_attr[0].qe), + .q (reg2hw.mio_pad_attr[0].q ), + .qs (mio_pad_attr_0_qs) ); - // Subregister 1 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_1]: V(True) + // Subregister 1 of Multireg mio_pad_attr + // R[mio_pad_attr_1]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_1 ( - .re (dio_out_sleep_val_1_re), + .DW (10) + ) u_mio_pad_attr_1 ( + .re (mio_pad_attr_1_re), // qualified with register enable - .we (dio_out_sleep_val_1_we & dio_out_sleep_regwen_1_qs), - .wd (dio_out_sleep_val_1_wd), - .d (hw2reg.dio_out_sleep_val[1].d), + .we (mio_pad_attr_1_we & mio_pad_attr_regwen_1_qs), + .wd (mio_pad_attr_1_wd), + .d (hw2reg.mio_pad_attr[1].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[1].qe), - .q (reg2hw.dio_out_sleep_val[1].q ), - .qs (dio_out_sleep_val_1_qs) + .qe (reg2hw.mio_pad_attr[1].qe), + .q (reg2hw.mio_pad_attr[1].q ), + .qs (mio_pad_attr_1_qs) ); - // Subregister 2 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_2]: V(True) + // Subregister 2 of Multireg mio_pad_attr + // R[mio_pad_attr_2]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_2 ( - .re (dio_out_sleep_val_2_re), + .DW (10) + ) u_mio_pad_attr_2 ( + .re (mio_pad_attr_2_re), // qualified with register enable - .we (dio_out_sleep_val_2_we & dio_out_sleep_regwen_2_qs), - .wd (dio_out_sleep_val_2_wd), - .d (hw2reg.dio_out_sleep_val[2].d), + .we (mio_pad_attr_2_we & mio_pad_attr_regwen_2_qs), + .wd (mio_pad_attr_2_wd), + .d (hw2reg.mio_pad_attr[2].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[2].qe), - .q (reg2hw.dio_out_sleep_val[2].q ), - .qs (dio_out_sleep_val_2_qs) + .qe (reg2hw.mio_pad_attr[2].qe), + .q (reg2hw.mio_pad_attr[2].q ), + .qs (mio_pad_attr_2_qs) ); - // Subregister 3 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_3]: V(True) + // Subregister 3 of Multireg mio_pad_attr + // R[mio_pad_attr_3]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_3 ( - .re (dio_out_sleep_val_3_re), + .DW (10) + ) u_mio_pad_attr_3 ( + .re (mio_pad_attr_3_re), // qualified with register enable - .we (dio_out_sleep_val_3_we & dio_out_sleep_regwen_3_qs), - .wd (dio_out_sleep_val_3_wd), - .d (hw2reg.dio_out_sleep_val[3].d), + .we (mio_pad_attr_3_we & mio_pad_attr_regwen_3_qs), + .wd (mio_pad_attr_3_wd), + .d (hw2reg.mio_pad_attr[3].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[3].qe), - .q (reg2hw.dio_out_sleep_val[3].q ), - .qs (dio_out_sleep_val_3_qs) + .qe (reg2hw.mio_pad_attr[3].qe), + .q (reg2hw.mio_pad_attr[3].q ), + .qs (mio_pad_attr_3_qs) ); - // Subregister 4 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_4]: V(True) + // Subregister 4 of Multireg mio_pad_attr + // R[mio_pad_attr_4]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_4 ( - .re (dio_out_sleep_val_4_re), + .DW (10) + ) u_mio_pad_attr_4 ( + .re (mio_pad_attr_4_re), // qualified with register enable - .we (dio_out_sleep_val_4_we & dio_out_sleep_regwen_4_qs), - .wd (dio_out_sleep_val_4_wd), - .d (hw2reg.dio_out_sleep_val[4].d), + .we (mio_pad_attr_4_we & mio_pad_attr_regwen_4_qs), + .wd (mio_pad_attr_4_wd), + .d (hw2reg.mio_pad_attr[4].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[4].qe), - .q (reg2hw.dio_out_sleep_val[4].q ), - .qs (dio_out_sleep_val_4_qs) + .qe (reg2hw.mio_pad_attr[4].qe), + .q (reg2hw.mio_pad_attr[4].q ), + .qs (mio_pad_attr_4_qs) ); - // Subregister 5 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_5]: V(True) + // Subregister 5 of Multireg mio_pad_attr + // R[mio_pad_attr_5]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_5 ( - .re (dio_out_sleep_val_5_re), + .DW (10) + ) u_mio_pad_attr_5 ( + .re (mio_pad_attr_5_re), // qualified with register enable - .we (dio_out_sleep_val_5_we & dio_out_sleep_regwen_5_qs), - .wd (dio_out_sleep_val_5_wd), - .d (hw2reg.dio_out_sleep_val[5].d), + .we (mio_pad_attr_5_we & mio_pad_attr_regwen_5_qs), + .wd (mio_pad_attr_5_wd), + .d (hw2reg.mio_pad_attr[5].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[5].qe), - .q (reg2hw.dio_out_sleep_val[5].q ), - .qs (dio_out_sleep_val_5_qs) + .qe (reg2hw.mio_pad_attr[5].qe), + .q (reg2hw.mio_pad_attr[5].q ), + .qs (mio_pad_attr_5_qs) ); - // Subregister 6 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_6]: V(True) + // Subregister 6 of Multireg mio_pad_attr + // R[mio_pad_attr_6]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_6 ( - .re (dio_out_sleep_val_6_re), + .DW (10) + ) u_mio_pad_attr_6 ( + .re (mio_pad_attr_6_re), // qualified with register enable - .we (dio_out_sleep_val_6_we & dio_out_sleep_regwen_6_qs), - .wd (dio_out_sleep_val_6_wd), - .d (hw2reg.dio_out_sleep_val[6].d), + .we (mio_pad_attr_6_we & mio_pad_attr_regwen_6_qs), + .wd (mio_pad_attr_6_wd), + .d (hw2reg.mio_pad_attr[6].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[6].qe), - .q (reg2hw.dio_out_sleep_val[6].q ), - .qs (dio_out_sleep_val_6_qs) + .qe (reg2hw.mio_pad_attr[6].qe), + .q (reg2hw.mio_pad_attr[6].q ), + .qs (mio_pad_attr_6_qs) ); - // Subregister 7 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_7]: V(True) + // Subregister 7 of Multireg mio_pad_attr + // R[mio_pad_attr_7]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_7 ( - .re (dio_out_sleep_val_7_re), + .DW (10) + ) u_mio_pad_attr_7 ( + .re (mio_pad_attr_7_re), // qualified with register enable - .we (dio_out_sleep_val_7_we & dio_out_sleep_regwen_7_qs), - .wd (dio_out_sleep_val_7_wd), - .d (hw2reg.dio_out_sleep_val[7].d), + .we (mio_pad_attr_7_we & mio_pad_attr_regwen_7_qs), + .wd (mio_pad_attr_7_wd), + .d (hw2reg.mio_pad_attr[7].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[7].qe), - .q (reg2hw.dio_out_sleep_val[7].q ), - .qs (dio_out_sleep_val_7_qs) + .qe (reg2hw.mio_pad_attr[7].qe), + .q (reg2hw.mio_pad_attr[7].q ), + .qs (mio_pad_attr_7_qs) ); - // Subregister 8 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_8]: V(True) + // Subregister 8 of Multireg mio_pad_attr + // R[mio_pad_attr_8]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_8 ( - .re (dio_out_sleep_val_8_re), + .DW (10) + ) u_mio_pad_attr_8 ( + .re (mio_pad_attr_8_re), // qualified with register enable - .we (dio_out_sleep_val_8_we & dio_out_sleep_regwen_8_qs), - .wd (dio_out_sleep_val_8_wd), - .d (hw2reg.dio_out_sleep_val[8].d), + .we (mio_pad_attr_8_we & mio_pad_attr_regwen_8_qs), + .wd (mio_pad_attr_8_wd), + .d (hw2reg.mio_pad_attr[8].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[8].qe), - .q (reg2hw.dio_out_sleep_val[8].q ), - .qs (dio_out_sleep_val_8_qs) + .qe (reg2hw.mio_pad_attr[8].qe), + .q (reg2hw.mio_pad_attr[8].q ), + .qs (mio_pad_attr_8_qs) ); - // Subregister 9 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_9]: V(True) + // Subregister 9 of Multireg mio_pad_attr + // R[mio_pad_attr_9]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_9 ( - .re (dio_out_sleep_val_9_re), + .DW (10) + ) u_mio_pad_attr_9 ( + .re (mio_pad_attr_9_re), // qualified with register enable - .we (dio_out_sleep_val_9_we & dio_out_sleep_regwen_9_qs), - .wd (dio_out_sleep_val_9_wd), - .d (hw2reg.dio_out_sleep_val[9].d), + .we (mio_pad_attr_9_we & mio_pad_attr_regwen_9_qs), + .wd (mio_pad_attr_9_wd), + .d (hw2reg.mio_pad_attr[9].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[9].qe), - .q (reg2hw.dio_out_sleep_val[9].q ), - .qs (dio_out_sleep_val_9_qs) + .qe (reg2hw.mio_pad_attr[9].qe), + .q (reg2hw.mio_pad_attr[9].q ), + .qs (mio_pad_attr_9_qs) ); - // Subregister 10 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_10]: V(True) + // Subregister 10 of Multireg mio_pad_attr + // R[mio_pad_attr_10]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_10 ( - .re (dio_out_sleep_val_10_re), + .DW (10) + ) u_mio_pad_attr_10 ( + .re (mio_pad_attr_10_re), // qualified with register enable - .we (dio_out_sleep_val_10_we & dio_out_sleep_regwen_10_qs), - .wd (dio_out_sleep_val_10_wd), - .d (hw2reg.dio_out_sleep_val[10].d), + .we (mio_pad_attr_10_we & mio_pad_attr_regwen_10_qs), + .wd (mio_pad_attr_10_wd), + .d (hw2reg.mio_pad_attr[10].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[10].qe), - .q (reg2hw.dio_out_sleep_val[10].q ), - .qs (dio_out_sleep_val_10_qs) + .qe (reg2hw.mio_pad_attr[10].qe), + .q (reg2hw.mio_pad_attr[10].q ), + .qs (mio_pad_attr_10_qs) ); - // Subregister 11 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_11]: V(True) + // Subregister 11 of Multireg mio_pad_attr + // R[mio_pad_attr_11]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_11 ( - .re (dio_out_sleep_val_11_re), + .DW (10) + ) u_mio_pad_attr_11 ( + .re (mio_pad_attr_11_re), // qualified with register enable - .we (dio_out_sleep_val_11_we & dio_out_sleep_regwen_11_qs), - .wd (dio_out_sleep_val_11_wd), - .d (hw2reg.dio_out_sleep_val[11].d), + .we (mio_pad_attr_11_we & mio_pad_attr_regwen_11_qs), + .wd (mio_pad_attr_11_wd), + .d (hw2reg.mio_pad_attr[11].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[11].qe), - .q (reg2hw.dio_out_sleep_val[11].q ), - .qs (dio_out_sleep_val_11_qs) + .qe (reg2hw.mio_pad_attr[11].qe), + .q (reg2hw.mio_pad_attr[11].q ), + .qs (mio_pad_attr_11_qs) ); - // Subregister 12 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_12]: V(True) + // Subregister 12 of Multireg mio_pad_attr + // R[mio_pad_attr_12]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_12 ( - .re (dio_out_sleep_val_12_re), + .DW (10) + ) u_mio_pad_attr_12 ( + .re (mio_pad_attr_12_re), // qualified with register enable - .we (dio_out_sleep_val_12_we & dio_out_sleep_regwen_12_qs), - .wd (dio_out_sleep_val_12_wd), - .d (hw2reg.dio_out_sleep_val[12].d), + .we (mio_pad_attr_12_we & mio_pad_attr_regwen_12_qs), + .wd (mio_pad_attr_12_wd), + .d (hw2reg.mio_pad_attr[12].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[12].qe), - .q (reg2hw.dio_out_sleep_val[12].q ), - .qs (dio_out_sleep_val_12_qs) + .qe (reg2hw.mio_pad_attr[12].qe), + .q (reg2hw.mio_pad_attr[12].q ), + .qs (mio_pad_attr_12_qs) ); - // Subregister 13 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_13]: V(True) + // Subregister 13 of Multireg mio_pad_attr + // R[mio_pad_attr_13]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_13 ( - .re (dio_out_sleep_val_13_re), + .DW (10) + ) u_mio_pad_attr_13 ( + .re (mio_pad_attr_13_re), // qualified with register enable - .we (dio_out_sleep_val_13_we & dio_out_sleep_regwen_13_qs), - .wd (dio_out_sleep_val_13_wd), - .d (hw2reg.dio_out_sleep_val[13].d), + .we (mio_pad_attr_13_we & mio_pad_attr_regwen_13_qs), + .wd (mio_pad_attr_13_wd), + .d (hw2reg.mio_pad_attr[13].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[13].qe), - .q (reg2hw.dio_out_sleep_val[13].q ), - .qs (dio_out_sleep_val_13_qs) + .qe (reg2hw.mio_pad_attr[13].qe), + .q (reg2hw.mio_pad_attr[13].q ), + .qs (mio_pad_attr_13_qs) ); - // Subregister 14 of Multireg dio_out_sleep_val - // R[dio_out_sleep_val_14]: V(True) + // Subregister 14 of Multireg mio_pad_attr + // R[mio_pad_attr_14]: V(True) prim_subreg_ext #( - .DW (2) - ) u_dio_out_sleep_val_14 ( - .re (dio_out_sleep_val_14_re), + .DW (10) + ) u_mio_pad_attr_14 ( + .re (mio_pad_attr_14_re), // qualified with register enable - .we (dio_out_sleep_val_14_we & dio_out_sleep_regwen_14_qs), - .wd (dio_out_sleep_val_14_wd), - .d (hw2reg.dio_out_sleep_val[14].d), + .we (mio_pad_attr_14_we & mio_pad_attr_regwen_14_qs), + .wd (mio_pad_attr_14_wd), + .d (hw2reg.mio_pad_attr[14].d), .qre (), - .qe (reg2hw.dio_out_sleep_val[14].qe), - .q (reg2hw.dio_out_sleep_val[14].q ), - .qs (dio_out_sleep_val_14_qs) + .qe (reg2hw.mio_pad_attr[14].qe), + .q (reg2hw.mio_pad_attr[14].q ), + .qs (mio_pad_attr_14_qs) + ); + + // Subregister 15 of Multireg mio_pad_attr + // R[mio_pad_attr_15]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_15 ( + .re (mio_pad_attr_15_re), + // qualified with register enable + .we (mio_pad_attr_15_we & mio_pad_attr_regwen_15_qs), + .wd (mio_pad_attr_15_wd), + .d (hw2reg.mio_pad_attr[15].d), + .qre (), + .qe (reg2hw.mio_pad_attr[15].qe), + .q (reg2hw.mio_pad_attr[15].q ), + .qs (mio_pad_attr_15_qs) + ); + + // Subregister 16 of Multireg mio_pad_attr + // R[mio_pad_attr_16]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_16 ( + .re (mio_pad_attr_16_re), + // qualified with register enable + .we (mio_pad_attr_16_we & mio_pad_attr_regwen_16_qs), + .wd (mio_pad_attr_16_wd), + .d (hw2reg.mio_pad_attr[16].d), + .qre (), + .qe (reg2hw.mio_pad_attr[16].qe), + .q (reg2hw.mio_pad_attr[16].q ), + .qs (mio_pad_attr_16_qs) + ); + + // Subregister 17 of Multireg mio_pad_attr + // R[mio_pad_attr_17]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_17 ( + .re (mio_pad_attr_17_re), + // qualified with register enable + .we (mio_pad_attr_17_we & mio_pad_attr_regwen_17_qs), + .wd (mio_pad_attr_17_wd), + .d (hw2reg.mio_pad_attr[17].d), + .qre (), + .qe (reg2hw.mio_pad_attr[17].qe), + .q (reg2hw.mio_pad_attr[17].q ), + .qs (mio_pad_attr_17_qs) + ); + + // Subregister 18 of Multireg mio_pad_attr + // R[mio_pad_attr_18]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_18 ( + .re (mio_pad_attr_18_re), + // qualified with register enable + .we (mio_pad_attr_18_we & mio_pad_attr_regwen_18_qs), + .wd (mio_pad_attr_18_wd), + .d (hw2reg.mio_pad_attr[18].d), + .qre (), + .qe (reg2hw.mio_pad_attr[18].qe), + .q (reg2hw.mio_pad_attr[18].q ), + .qs (mio_pad_attr_18_qs) + ); + + // Subregister 19 of Multireg mio_pad_attr + // R[mio_pad_attr_19]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_19 ( + .re (mio_pad_attr_19_re), + // qualified with register enable + .we (mio_pad_attr_19_we & mio_pad_attr_regwen_19_qs), + .wd (mio_pad_attr_19_wd), + .d (hw2reg.mio_pad_attr[19].d), + .qre (), + .qe (reg2hw.mio_pad_attr[19].qe), + .q (reg2hw.mio_pad_attr[19].q ), + .qs (mio_pad_attr_19_qs) + ); + + // Subregister 20 of Multireg mio_pad_attr + // R[mio_pad_attr_20]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_20 ( + .re (mio_pad_attr_20_re), + // qualified with register enable + .we (mio_pad_attr_20_we & mio_pad_attr_regwen_20_qs), + .wd (mio_pad_attr_20_wd), + .d (hw2reg.mio_pad_attr[20].d), + .qre (), + .qe (reg2hw.mio_pad_attr[20].qe), + .q (reg2hw.mio_pad_attr[20].q ), + .qs (mio_pad_attr_20_qs) + ); + + // Subregister 21 of Multireg mio_pad_attr + // R[mio_pad_attr_21]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_21 ( + .re (mio_pad_attr_21_re), + // qualified with register enable + .we (mio_pad_attr_21_we & mio_pad_attr_regwen_21_qs), + .wd (mio_pad_attr_21_wd), + .d (hw2reg.mio_pad_attr[21].d), + .qre (), + .qe (reg2hw.mio_pad_attr[21].qe), + .q (reg2hw.mio_pad_attr[21].q ), + .qs (mio_pad_attr_21_qs) + ); + + // Subregister 22 of Multireg mio_pad_attr + // R[mio_pad_attr_22]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_22 ( + .re (mio_pad_attr_22_re), + // qualified with register enable + .we (mio_pad_attr_22_we & mio_pad_attr_regwen_22_qs), + .wd (mio_pad_attr_22_wd), + .d (hw2reg.mio_pad_attr[22].d), + .qre (), + .qe (reg2hw.mio_pad_attr[22].qe), + .q (reg2hw.mio_pad_attr[22].q ), + .qs (mio_pad_attr_22_qs) + ); + + // Subregister 23 of Multireg mio_pad_attr + // R[mio_pad_attr_23]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_23 ( + .re (mio_pad_attr_23_re), + // qualified with register enable + .we (mio_pad_attr_23_we & mio_pad_attr_regwen_23_qs), + .wd (mio_pad_attr_23_wd), + .d (hw2reg.mio_pad_attr[23].d), + .qre (), + .qe (reg2hw.mio_pad_attr[23].qe), + .q (reg2hw.mio_pad_attr[23].q ), + .qs (mio_pad_attr_23_qs) + ); + + // Subregister 24 of Multireg mio_pad_attr + // R[mio_pad_attr_24]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_24 ( + .re (mio_pad_attr_24_re), + // qualified with register enable + .we (mio_pad_attr_24_we & mio_pad_attr_regwen_24_qs), + .wd (mio_pad_attr_24_wd), + .d (hw2reg.mio_pad_attr[24].d), + .qre (), + .qe (reg2hw.mio_pad_attr[24].qe), + .q (reg2hw.mio_pad_attr[24].q ), + .qs (mio_pad_attr_24_qs) + ); + + // Subregister 25 of Multireg mio_pad_attr + // R[mio_pad_attr_25]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_25 ( + .re (mio_pad_attr_25_re), + // qualified with register enable + .we (mio_pad_attr_25_we & mio_pad_attr_regwen_25_qs), + .wd (mio_pad_attr_25_wd), + .d (hw2reg.mio_pad_attr[25].d), + .qre (), + .qe (reg2hw.mio_pad_attr[25].qe), + .q (reg2hw.mio_pad_attr[25].q ), + .qs (mio_pad_attr_25_qs) + ); + + // Subregister 26 of Multireg mio_pad_attr + // R[mio_pad_attr_26]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_26 ( + .re (mio_pad_attr_26_re), + // qualified with register enable + .we (mio_pad_attr_26_we & mio_pad_attr_regwen_26_qs), + .wd (mio_pad_attr_26_wd), + .d (hw2reg.mio_pad_attr[26].d), + .qre (), + .qe (reg2hw.mio_pad_attr[26].qe), + .q (reg2hw.mio_pad_attr[26].q ), + .qs (mio_pad_attr_26_qs) + ); + + // Subregister 27 of Multireg mio_pad_attr + // R[mio_pad_attr_27]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_27 ( + .re (mio_pad_attr_27_re), + // qualified with register enable + .we (mio_pad_attr_27_we & mio_pad_attr_regwen_27_qs), + .wd (mio_pad_attr_27_wd), + .d (hw2reg.mio_pad_attr[27].d), + .qre (), + .qe (reg2hw.mio_pad_attr[27].qe), + .q (reg2hw.mio_pad_attr[27].q ), + .qs (mio_pad_attr_27_qs) + ); + + // Subregister 28 of Multireg mio_pad_attr + // R[mio_pad_attr_28]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_28 ( + .re (mio_pad_attr_28_re), + // qualified with register enable + .we (mio_pad_attr_28_we & mio_pad_attr_regwen_28_qs), + .wd (mio_pad_attr_28_wd), + .d (hw2reg.mio_pad_attr[28].d), + .qre (), + .qe (reg2hw.mio_pad_attr[28].qe), + .q (reg2hw.mio_pad_attr[28].q ), + .qs (mio_pad_attr_28_qs) + ); + + // Subregister 29 of Multireg mio_pad_attr + // R[mio_pad_attr_29]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_29 ( + .re (mio_pad_attr_29_re), + // qualified with register enable + .we (mio_pad_attr_29_we & mio_pad_attr_regwen_29_qs), + .wd (mio_pad_attr_29_wd), + .d (hw2reg.mio_pad_attr[29].d), + .qre (), + .qe (reg2hw.mio_pad_attr[29].qe), + .q (reg2hw.mio_pad_attr[29].q ), + .qs (mio_pad_attr_29_qs) + ); + + // Subregister 30 of Multireg mio_pad_attr + // R[mio_pad_attr_30]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_30 ( + .re (mio_pad_attr_30_re), + // qualified with register enable + .we (mio_pad_attr_30_we & mio_pad_attr_regwen_30_qs), + .wd (mio_pad_attr_30_wd), + .d (hw2reg.mio_pad_attr[30].d), + .qre (), + .qe (reg2hw.mio_pad_attr[30].qe), + .q (reg2hw.mio_pad_attr[30].q ), + .qs (mio_pad_attr_30_qs) + ); + + // Subregister 31 of Multireg mio_pad_attr + // R[mio_pad_attr_31]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_mio_pad_attr_31 ( + .re (mio_pad_attr_31_re), + // qualified with register enable + .we (mio_pad_attr_31_we & mio_pad_attr_regwen_31_qs), + .wd (mio_pad_attr_31_wd), + .d (hw2reg.mio_pad_attr[31].d), + .qre (), + .qe (reg2hw.mio_pad_attr[31].qe), + .q (reg2hw.mio_pad_attr[31].q ), + .qs (mio_pad_attr_31_qs) + ); + + + + // Subregister 0 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_0]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_0_we), + .wd (dio_pad_attr_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_0_qs) + ); + + // Subregister 1 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_1]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_1_we), + .wd (dio_pad_attr_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_1_qs) + ); + + // Subregister 2 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_2]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_2_we), + .wd (dio_pad_attr_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_2_qs) + ); + + // Subregister 3 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_3]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_3_we), + .wd (dio_pad_attr_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_3_qs) + ); + + // Subregister 4 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_4]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_4_we), + .wd (dio_pad_attr_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_4_qs) + ); + + // Subregister 5 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_5]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_5_we), + .wd (dio_pad_attr_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_5_qs) + ); + + // Subregister 6 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_6]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_6_we), + .wd (dio_pad_attr_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_6_qs) + ); + + // Subregister 7 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_7]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_7_we), + .wd (dio_pad_attr_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_7_qs) + ); + + // Subregister 8 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_8]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_8_we), + .wd (dio_pad_attr_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_8_qs) + ); + + // Subregister 9 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_9]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_9_we), + .wd (dio_pad_attr_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_9_qs) + ); + + // Subregister 10 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_10]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_10_we), + .wd (dio_pad_attr_regwen_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_10_qs) + ); + + // Subregister 11 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_11]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_11_we), + .wd (dio_pad_attr_regwen_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_11_qs) + ); + + // Subregister 12 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_12]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_12_we), + .wd (dio_pad_attr_regwen_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_12_qs) + ); + + // Subregister 13 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_13]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_13_we), + .wd (dio_pad_attr_regwen_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_13_qs) + ); + + // Subregister 14 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_14]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_attr_regwen_14_we), + .wd (dio_pad_attr_regwen_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_14_qs) + ); + + + + // Subregister 0 of Multireg dio_pad_attr + // R[dio_pad_attr_0]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_0 ( + .re (dio_pad_attr_0_re), + // qualified with register enable + .we (dio_pad_attr_0_we & dio_pad_attr_regwen_0_qs), + .wd (dio_pad_attr_0_wd), + .d (hw2reg.dio_pad_attr[0].d), + .qre (), + .qe (reg2hw.dio_pad_attr[0].qe), + .q (reg2hw.dio_pad_attr[0].q ), + .qs (dio_pad_attr_0_qs) + ); + + // Subregister 1 of Multireg dio_pad_attr + // R[dio_pad_attr_1]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_1 ( + .re (dio_pad_attr_1_re), + // qualified with register enable + .we (dio_pad_attr_1_we & dio_pad_attr_regwen_1_qs), + .wd (dio_pad_attr_1_wd), + .d (hw2reg.dio_pad_attr[1].d), + .qre (), + .qe (reg2hw.dio_pad_attr[1].qe), + .q (reg2hw.dio_pad_attr[1].q ), + .qs (dio_pad_attr_1_qs) + ); + + // Subregister 2 of Multireg dio_pad_attr + // R[dio_pad_attr_2]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_2 ( + .re (dio_pad_attr_2_re), + // qualified with register enable + .we (dio_pad_attr_2_we & dio_pad_attr_regwen_2_qs), + .wd (dio_pad_attr_2_wd), + .d (hw2reg.dio_pad_attr[2].d), + .qre (), + .qe (reg2hw.dio_pad_attr[2].qe), + .q (reg2hw.dio_pad_attr[2].q ), + .qs (dio_pad_attr_2_qs) + ); + + // Subregister 3 of Multireg dio_pad_attr + // R[dio_pad_attr_3]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_3 ( + .re (dio_pad_attr_3_re), + // qualified with register enable + .we (dio_pad_attr_3_we & dio_pad_attr_regwen_3_qs), + .wd (dio_pad_attr_3_wd), + .d (hw2reg.dio_pad_attr[3].d), + .qre (), + .qe (reg2hw.dio_pad_attr[3].qe), + .q (reg2hw.dio_pad_attr[3].q ), + .qs (dio_pad_attr_3_qs) + ); + + // Subregister 4 of Multireg dio_pad_attr + // R[dio_pad_attr_4]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_4 ( + .re (dio_pad_attr_4_re), + // qualified with register enable + .we (dio_pad_attr_4_we & dio_pad_attr_regwen_4_qs), + .wd (dio_pad_attr_4_wd), + .d (hw2reg.dio_pad_attr[4].d), + .qre (), + .qe (reg2hw.dio_pad_attr[4].qe), + .q (reg2hw.dio_pad_attr[4].q ), + .qs (dio_pad_attr_4_qs) + ); + + // Subregister 5 of Multireg dio_pad_attr + // R[dio_pad_attr_5]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_5 ( + .re (dio_pad_attr_5_re), + // qualified with register enable + .we (dio_pad_attr_5_we & dio_pad_attr_regwen_5_qs), + .wd (dio_pad_attr_5_wd), + .d (hw2reg.dio_pad_attr[5].d), + .qre (), + .qe (reg2hw.dio_pad_attr[5].qe), + .q (reg2hw.dio_pad_attr[5].q ), + .qs (dio_pad_attr_5_qs) + ); + + // Subregister 6 of Multireg dio_pad_attr + // R[dio_pad_attr_6]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_6 ( + .re (dio_pad_attr_6_re), + // qualified with register enable + .we (dio_pad_attr_6_we & dio_pad_attr_regwen_6_qs), + .wd (dio_pad_attr_6_wd), + .d (hw2reg.dio_pad_attr[6].d), + .qre (), + .qe (reg2hw.dio_pad_attr[6].qe), + .q (reg2hw.dio_pad_attr[6].q ), + .qs (dio_pad_attr_6_qs) + ); + + // Subregister 7 of Multireg dio_pad_attr + // R[dio_pad_attr_7]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_7 ( + .re (dio_pad_attr_7_re), + // qualified with register enable + .we (dio_pad_attr_7_we & dio_pad_attr_regwen_7_qs), + .wd (dio_pad_attr_7_wd), + .d (hw2reg.dio_pad_attr[7].d), + .qre (), + .qe (reg2hw.dio_pad_attr[7].qe), + .q (reg2hw.dio_pad_attr[7].q ), + .qs (dio_pad_attr_7_qs) + ); + + // Subregister 8 of Multireg dio_pad_attr + // R[dio_pad_attr_8]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_8 ( + .re (dio_pad_attr_8_re), + // qualified with register enable + .we (dio_pad_attr_8_we & dio_pad_attr_regwen_8_qs), + .wd (dio_pad_attr_8_wd), + .d (hw2reg.dio_pad_attr[8].d), + .qre (), + .qe (reg2hw.dio_pad_attr[8].qe), + .q (reg2hw.dio_pad_attr[8].q ), + .qs (dio_pad_attr_8_qs) + ); + + // Subregister 9 of Multireg dio_pad_attr + // R[dio_pad_attr_9]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_9 ( + .re (dio_pad_attr_9_re), + // qualified with register enable + .we (dio_pad_attr_9_we & dio_pad_attr_regwen_9_qs), + .wd (dio_pad_attr_9_wd), + .d (hw2reg.dio_pad_attr[9].d), + .qre (), + .qe (reg2hw.dio_pad_attr[9].qe), + .q (reg2hw.dio_pad_attr[9].q ), + .qs (dio_pad_attr_9_qs) + ); + + // Subregister 10 of Multireg dio_pad_attr + // R[dio_pad_attr_10]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_10 ( + .re (dio_pad_attr_10_re), + // qualified with register enable + .we (dio_pad_attr_10_we & dio_pad_attr_regwen_10_qs), + .wd (dio_pad_attr_10_wd), + .d (hw2reg.dio_pad_attr[10].d), + .qre (), + .qe (reg2hw.dio_pad_attr[10].qe), + .q (reg2hw.dio_pad_attr[10].q ), + .qs (dio_pad_attr_10_qs) + ); + + // Subregister 11 of Multireg dio_pad_attr + // R[dio_pad_attr_11]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_11 ( + .re (dio_pad_attr_11_re), + // qualified with register enable + .we (dio_pad_attr_11_we & dio_pad_attr_regwen_11_qs), + .wd (dio_pad_attr_11_wd), + .d (hw2reg.dio_pad_attr[11].d), + .qre (), + .qe (reg2hw.dio_pad_attr[11].qe), + .q (reg2hw.dio_pad_attr[11].q ), + .qs (dio_pad_attr_11_qs) + ); + + // Subregister 12 of Multireg dio_pad_attr + // R[dio_pad_attr_12]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_12 ( + .re (dio_pad_attr_12_re), + // qualified with register enable + .we (dio_pad_attr_12_we & dio_pad_attr_regwen_12_qs), + .wd (dio_pad_attr_12_wd), + .d (hw2reg.dio_pad_attr[12].d), + .qre (), + .qe (reg2hw.dio_pad_attr[12].qe), + .q (reg2hw.dio_pad_attr[12].q ), + .qs (dio_pad_attr_12_qs) + ); + + // Subregister 13 of Multireg dio_pad_attr + // R[dio_pad_attr_13]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_13 ( + .re (dio_pad_attr_13_re), + // qualified with register enable + .we (dio_pad_attr_13_we & dio_pad_attr_regwen_13_qs), + .wd (dio_pad_attr_13_wd), + .d (hw2reg.dio_pad_attr[13].d), + .qre (), + .qe (reg2hw.dio_pad_attr[13].qe), + .q (reg2hw.dio_pad_attr[13].q ), + .qs (dio_pad_attr_13_qs) + ); + + // Subregister 14 of Multireg dio_pad_attr + // R[dio_pad_attr_14]: V(True) + + prim_subreg_ext #( + .DW (10) + ) u_dio_pad_attr_14 ( + .re (dio_pad_attr_14_re), + // qualified with register enable + .we (dio_pad_attr_14_we & dio_pad_attr_regwen_14_qs), + .wd (dio_pad_attr_14_wd), + .d (hw2reg.dio_pad_attr[14].d), + .qre (), + .qe (reg2hw.dio_pad_attr[14].qe), + .q (reg2hw.dio_pad_attr[14].q ), + .qs (dio_pad_attr_14_qs) + ); + + + + // Subregister 0 of Multireg mio_pad_sleep_status + // R[mio_pad_sleep_status]: V(False) + + // F[en_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_0_we), + .wd (mio_pad_sleep_status_en_0_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[0].de), + .d (hw2reg.mio_pad_sleep_status[0].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[0].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_0_qs) + ); + + + // F[en_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_1_we), + .wd (mio_pad_sleep_status_en_1_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[1].de), + .d (hw2reg.mio_pad_sleep_status[1].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[1].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_1_qs) + ); + + + // F[en_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_2_we), + .wd (mio_pad_sleep_status_en_2_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[2].de), + .d (hw2reg.mio_pad_sleep_status[2].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[2].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_2_qs) + ); + + + // F[en_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_3_we), + .wd (mio_pad_sleep_status_en_3_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[3].de), + .d (hw2reg.mio_pad_sleep_status[3].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[3].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_3_qs) + ); + + + // F[en_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_4_we), + .wd (mio_pad_sleep_status_en_4_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[4].de), + .d (hw2reg.mio_pad_sleep_status[4].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[4].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_4_qs) + ); + + + // F[en_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_5_we), + .wd (mio_pad_sleep_status_en_5_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[5].de), + .d (hw2reg.mio_pad_sleep_status[5].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[5].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_5_qs) + ); + + + // F[en_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_6_we), + .wd (mio_pad_sleep_status_en_6_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[6].de), + .d (hw2reg.mio_pad_sleep_status[6].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[6].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_6_qs) + ); + + + // F[en_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_7_we), + .wd (mio_pad_sleep_status_en_7_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[7].de), + .d (hw2reg.mio_pad_sleep_status[7].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[7].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_7_qs) + ); + + + // F[en_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_8_we), + .wd (mio_pad_sleep_status_en_8_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[8].de), + .d (hw2reg.mio_pad_sleep_status[8].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[8].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_8_qs) + ); + + + // F[en_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_9_we), + .wd (mio_pad_sleep_status_en_9_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[9].de), + .d (hw2reg.mio_pad_sleep_status[9].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[9].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_9_qs) + ); + + + // F[en_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_10_we), + .wd (mio_pad_sleep_status_en_10_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[10].de), + .d (hw2reg.mio_pad_sleep_status[10].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[10].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_10_qs) + ); + + + // F[en_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_11_we), + .wd (mio_pad_sleep_status_en_11_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[11].de), + .d (hw2reg.mio_pad_sleep_status[11].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[11].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_11_qs) + ); + + + // F[en_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_12_we), + .wd (mio_pad_sleep_status_en_12_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[12].de), + .d (hw2reg.mio_pad_sleep_status[12].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[12].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_12_qs) + ); + + + // F[en_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_13_we), + .wd (mio_pad_sleep_status_en_13_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[13].de), + .d (hw2reg.mio_pad_sleep_status[13].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[13].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_13_qs) + ); + + + // F[en_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_14_we), + .wd (mio_pad_sleep_status_en_14_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[14].de), + .d (hw2reg.mio_pad_sleep_status[14].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[14].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_14_qs) + ); + + + // F[en_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_15_we), + .wd (mio_pad_sleep_status_en_15_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[15].de), + .d (hw2reg.mio_pad_sleep_status[15].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[15].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_15_qs) + ); + + + // F[en_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_16_we), + .wd (mio_pad_sleep_status_en_16_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[16].de), + .d (hw2reg.mio_pad_sleep_status[16].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[16].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_16_qs) + ); + + + // F[en_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_17_we), + .wd (mio_pad_sleep_status_en_17_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[17].de), + .d (hw2reg.mio_pad_sleep_status[17].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[17].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_17_qs) + ); + + + // F[en_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_18_we), + .wd (mio_pad_sleep_status_en_18_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[18].de), + .d (hw2reg.mio_pad_sleep_status[18].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[18].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_18_qs) + ); + + + // F[en_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_19_we), + .wd (mio_pad_sleep_status_en_19_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[19].de), + .d (hw2reg.mio_pad_sleep_status[19].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[19].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_19_qs) + ); + + + // F[en_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_20_we), + .wd (mio_pad_sleep_status_en_20_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[20].de), + .d (hw2reg.mio_pad_sleep_status[20].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[20].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_20_qs) + ); + + + // F[en_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_21_we), + .wd (mio_pad_sleep_status_en_21_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[21].de), + .d (hw2reg.mio_pad_sleep_status[21].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[21].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_21_qs) + ); + + + // F[en_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_22_we), + .wd (mio_pad_sleep_status_en_22_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[22].de), + .d (hw2reg.mio_pad_sleep_status[22].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[22].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_22_qs) + ); + + + // F[en_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_23_we), + .wd (mio_pad_sleep_status_en_23_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[23].de), + .d (hw2reg.mio_pad_sleep_status[23].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[23].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_23_qs) + ); + + + // F[en_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_24_we), + .wd (mio_pad_sleep_status_en_24_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[24].de), + .d (hw2reg.mio_pad_sleep_status[24].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[24].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_24_qs) + ); + + + // F[en_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_25_we), + .wd (mio_pad_sleep_status_en_25_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[25].de), + .d (hw2reg.mio_pad_sleep_status[25].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[25].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_25_qs) + ); + + + // F[en_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_26_we), + .wd (mio_pad_sleep_status_en_26_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[26].de), + .d (hw2reg.mio_pad_sleep_status[26].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[26].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_26_qs) + ); + + + // F[en_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_27_we), + .wd (mio_pad_sleep_status_en_27_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[27].de), + .d (hw2reg.mio_pad_sleep_status[27].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[27].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_27_qs) + ); + + + // F[en_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_28_we), + .wd (mio_pad_sleep_status_en_28_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[28].de), + .d (hw2reg.mio_pad_sleep_status[28].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[28].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_28_qs) + ); + + + // F[en_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_29_we), + .wd (mio_pad_sleep_status_en_29_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[29].de), + .d (hw2reg.mio_pad_sleep_status[29].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[29].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_29_qs) + ); + + + // F[en_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_30_we), + .wd (mio_pad_sleep_status_en_30_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[30].de), + .d (hw2reg.mio_pad_sleep_status[30].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[30].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_30_qs) + ); + + + // F[en_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_status_en_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_status_en_31_we), + .wd (mio_pad_sleep_status_en_31_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[31].de), + .d (hw2reg.mio_pad_sleep_status[31].d ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[31].q ), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_31_qs) + ); + + + + + // Subregister 0 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_0]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_0_we), + .wd (mio_pad_sleep_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_0_qs) + ); + + // Subregister 1 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_1]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_1_we), + .wd (mio_pad_sleep_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_1_qs) + ); + + // Subregister 2 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_2]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_2_we), + .wd (mio_pad_sleep_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_2_qs) + ); + + // Subregister 3 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_3]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_3_we), + .wd (mio_pad_sleep_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_3_qs) + ); + + // Subregister 4 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_4]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_4_we), + .wd (mio_pad_sleep_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_4_qs) + ); + + // Subregister 5 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_5]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_5_we), + .wd (mio_pad_sleep_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_5_qs) + ); + + // Subregister 6 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_6]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_6_we), + .wd (mio_pad_sleep_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_6_qs) + ); + + // Subregister 7 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_7]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_7_we), + .wd (mio_pad_sleep_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_7_qs) + ); + + // Subregister 8 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_8]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_8_we), + .wd (mio_pad_sleep_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_8_qs) + ); + + // Subregister 9 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_9]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_9_we), + .wd (mio_pad_sleep_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_9_qs) + ); + + // Subregister 10 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_10]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_10_we), + .wd (mio_pad_sleep_regwen_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_10_qs) + ); + + // Subregister 11 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_11]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_11_we), + .wd (mio_pad_sleep_regwen_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_11_qs) + ); + + // Subregister 12 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_12]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_12_we), + .wd (mio_pad_sleep_regwen_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_12_qs) + ); + + // Subregister 13 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_13]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_13_we), + .wd (mio_pad_sleep_regwen_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_13_qs) + ); + + // Subregister 14 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_14]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_14_we), + .wd (mio_pad_sleep_regwen_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_14_qs) + ); + + // Subregister 15 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_15]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_15_we), + .wd (mio_pad_sleep_regwen_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_15_qs) + ); + + // Subregister 16 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_16]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_16_we), + .wd (mio_pad_sleep_regwen_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_16_qs) + ); + + // Subregister 17 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_17]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_17_we), + .wd (mio_pad_sleep_regwen_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_17_qs) + ); + + // Subregister 18 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_18]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_18_we), + .wd (mio_pad_sleep_regwen_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_18_qs) + ); + + // Subregister 19 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_19]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_19_we), + .wd (mio_pad_sleep_regwen_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_19_qs) + ); + + // Subregister 20 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_20]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_20_we), + .wd (mio_pad_sleep_regwen_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_20_qs) + ); + + // Subregister 21 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_21]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_21_we), + .wd (mio_pad_sleep_regwen_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_21_qs) + ); + + // Subregister 22 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_22]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_22_we), + .wd (mio_pad_sleep_regwen_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_22_qs) + ); + + // Subregister 23 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_23]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_23_we), + .wd (mio_pad_sleep_regwen_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_23_qs) + ); + + // Subregister 24 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_24]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_24_we), + .wd (mio_pad_sleep_regwen_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_24_qs) + ); + + // Subregister 25 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_25]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_25_we), + .wd (mio_pad_sleep_regwen_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_25_qs) + ); + + // Subregister 26 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_26]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_26_we), + .wd (mio_pad_sleep_regwen_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_26_qs) + ); + + // Subregister 27 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_27]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_27_we), + .wd (mio_pad_sleep_regwen_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_27_qs) + ); + + // Subregister 28 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_28]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_28_we), + .wd (mio_pad_sleep_regwen_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_28_qs) + ); + + // Subregister 29 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_29]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_29_we), + .wd (mio_pad_sleep_regwen_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_29_qs) + ); + + // Subregister 30 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_30]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_30_we), + .wd (mio_pad_sleep_regwen_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_30_qs) + ); + + // Subregister 31 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_31]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_mio_pad_sleep_regwen_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (mio_pad_sleep_regwen_31_we), + .wd (mio_pad_sleep_regwen_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_31_qs) + ); + + + + // Subregister 0 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_0]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_0_we & mio_pad_sleep_regwen_0_qs), + .wd (mio_pad_sleep_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[0].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_0_qs) + ); + + // Subregister 1 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_1]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_1_we & mio_pad_sleep_regwen_1_qs), + .wd (mio_pad_sleep_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[1].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_1_qs) + ); + + // Subregister 2 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_2]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_2_we & mio_pad_sleep_regwen_2_qs), + .wd (mio_pad_sleep_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[2].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_2_qs) + ); + + // Subregister 3 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_3]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_3_we & mio_pad_sleep_regwen_3_qs), + .wd (mio_pad_sleep_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[3].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_3_qs) + ); + + // Subregister 4 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_4]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_4_we & mio_pad_sleep_regwen_4_qs), + .wd (mio_pad_sleep_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[4].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_4_qs) + ); + + // Subregister 5 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_5]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_5_we & mio_pad_sleep_regwen_5_qs), + .wd (mio_pad_sleep_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[5].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_5_qs) + ); + + // Subregister 6 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_6]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_6_we & mio_pad_sleep_regwen_6_qs), + .wd (mio_pad_sleep_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[6].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_6_qs) + ); + + // Subregister 7 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_7]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_7_we & mio_pad_sleep_regwen_7_qs), + .wd (mio_pad_sleep_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[7].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_7_qs) + ); + + // Subregister 8 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_8]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_8_we & mio_pad_sleep_regwen_8_qs), + .wd (mio_pad_sleep_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[8].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_8_qs) + ); + + // Subregister 9 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_9]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_9_we & mio_pad_sleep_regwen_9_qs), + .wd (mio_pad_sleep_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[9].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_9_qs) + ); + + // Subregister 10 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_10]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_10_we & mio_pad_sleep_regwen_10_qs), + .wd (mio_pad_sleep_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[10].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_10_qs) + ); + + // Subregister 11 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_11]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_11_we & mio_pad_sleep_regwen_11_qs), + .wd (mio_pad_sleep_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[11].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_11_qs) + ); + + // Subregister 12 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_12]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_12_we & mio_pad_sleep_regwen_12_qs), + .wd (mio_pad_sleep_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[12].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_12_qs) + ); + + // Subregister 13 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_13]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_13_we & mio_pad_sleep_regwen_13_qs), + .wd (mio_pad_sleep_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[13].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_13_qs) + ); + + // Subregister 14 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_14]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_14_we & mio_pad_sleep_regwen_14_qs), + .wd (mio_pad_sleep_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[14].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_14_qs) + ); + + // Subregister 15 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_15]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_15_we & mio_pad_sleep_regwen_15_qs), + .wd (mio_pad_sleep_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[15].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_15_qs) + ); + + // Subregister 16 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_16]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_16_we & mio_pad_sleep_regwen_16_qs), + .wd (mio_pad_sleep_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[16].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_16_qs) + ); + + // Subregister 17 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_17]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_17_we & mio_pad_sleep_regwen_17_qs), + .wd (mio_pad_sleep_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[17].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_17_qs) + ); + + // Subregister 18 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_18]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_18_we & mio_pad_sleep_regwen_18_qs), + .wd (mio_pad_sleep_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[18].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_18_qs) + ); + + // Subregister 19 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_19]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_19_we & mio_pad_sleep_regwen_19_qs), + .wd (mio_pad_sleep_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[19].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_19_qs) + ); + + // Subregister 20 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_20]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_20_we & mio_pad_sleep_regwen_20_qs), + .wd (mio_pad_sleep_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[20].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_20_qs) + ); + + // Subregister 21 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_21]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_21_we & mio_pad_sleep_regwen_21_qs), + .wd (mio_pad_sleep_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[21].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_21_qs) + ); + + // Subregister 22 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_22]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_22_we & mio_pad_sleep_regwen_22_qs), + .wd (mio_pad_sleep_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[22].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_22_qs) + ); + + // Subregister 23 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_23]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_23_we & mio_pad_sleep_regwen_23_qs), + .wd (mio_pad_sleep_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[23].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_23_qs) + ); + + // Subregister 24 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_24]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_24_we & mio_pad_sleep_regwen_24_qs), + .wd (mio_pad_sleep_en_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[24].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_24_qs) + ); + + // Subregister 25 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_25]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_25_we & mio_pad_sleep_regwen_25_qs), + .wd (mio_pad_sleep_en_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[25].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_25_qs) + ); + + // Subregister 26 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_26]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_26_we & mio_pad_sleep_regwen_26_qs), + .wd (mio_pad_sleep_en_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[26].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_26_qs) + ); + + // Subregister 27 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_27]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_27_we & mio_pad_sleep_regwen_27_qs), + .wd (mio_pad_sleep_en_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[27].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_27_qs) + ); + + // Subregister 28 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_28]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_28_we & mio_pad_sleep_regwen_28_qs), + .wd (mio_pad_sleep_en_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[28].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_28_qs) + ); + + // Subregister 29 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_29]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_29_we & mio_pad_sleep_regwen_29_qs), + .wd (mio_pad_sleep_en_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[29].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_29_qs) + ); + + // Subregister 30 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_30]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_30_we & mio_pad_sleep_regwen_30_qs), + .wd (mio_pad_sleep_en_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[30].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_30_qs) + ); + + // Subregister 31 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_31]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_mio_pad_sleep_en_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_en_31_we & mio_pad_sleep_regwen_31_qs), + .wd (mio_pad_sleep_en_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[31].q ), + + // to register interface (read) + .qs (mio_pad_sleep_en_31_qs) + ); + + + + // Subregister 0 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_0]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_0_we & mio_pad_sleep_regwen_0_qs), + .wd (mio_pad_sleep_mode_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[0].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_0_qs) + ); + + // Subregister 1 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_1]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_1_we & mio_pad_sleep_regwen_1_qs), + .wd (mio_pad_sleep_mode_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[1].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_1_qs) + ); + + // Subregister 2 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_2]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_2_we & mio_pad_sleep_regwen_2_qs), + .wd (mio_pad_sleep_mode_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[2].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_2_qs) + ); + + // Subregister 3 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_3]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_3_we & mio_pad_sleep_regwen_3_qs), + .wd (mio_pad_sleep_mode_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[3].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_3_qs) + ); + + // Subregister 4 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_4]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_4_we & mio_pad_sleep_regwen_4_qs), + .wd (mio_pad_sleep_mode_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[4].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_4_qs) + ); + + // Subregister 5 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_5]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_5_we & mio_pad_sleep_regwen_5_qs), + .wd (mio_pad_sleep_mode_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[5].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_5_qs) + ); + + // Subregister 6 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_6]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_6_we & mio_pad_sleep_regwen_6_qs), + .wd (mio_pad_sleep_mode_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[6].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_6_qs) + ); + + // Subregister 7 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_7]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_7_we & mio_pad_sleep_regwen_7_qs), + .wd (mio_pad_sleep_mode_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[7].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_7_qs) + ); + + // Subregister 8 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_8]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_8_we & mio_pad_sleep_regwen_8_qs), + .wd (mio_pad_sleep_mode_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[8].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_8_qs) + ); + + // Subregister 9 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_9]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_9_we & mio_pad_sleep_regwen_9_qs), + .wd (mio_pad_sleep_mode_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[9].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_9_qs) + ); + + // Subregister 10 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_10]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_10_we & mio_pad_sleep_regwen_10_qs), + .wd (mio_pad_sleep_mode_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[10].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_10_qs) + ); + + // Subregister 11 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_11]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_11_we & mio_pad_sleep_regwen_11_qs), + .wd (mio_pad_sleep_mode_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[11].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_11_qs) + ); + + // Subregister 12 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_12]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_12_we & mio_pad_sleep_regwen_12_qs), + .wd (mio_pad_sleep_mode_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[12].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_12_qs) + ); + + // Subregister 13 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_13]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_13_we & mio_pad_sleep_regwen_13_qs), + .wd (mio_pad_sleep_mode_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[13].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_13_qs) + ); + + // Subregister 14 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_14]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_14_we & mio_pad_sleep_regwen_14_qs), + .wd (mio_pad_sleep_mode_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[14].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_14_qs) + ); + + // Subregister 15 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_15]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_15_we & mio_pad_sleep_regwen_15_qs), + .wd (mio_pad_sleep_mode_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[15].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_15_qs) + ); + + // Subregister 16 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_16]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_16_we & mio_pad_sleep_regwen_16_qs), + .wd (mio_pad_sleep_mode_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[16].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_16_qs) + ); + + // Subregister 17 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_17]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_17_we & mio_pad_sleep_regwen_17_qs), + .wd (mio_pad_sleep_mode_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[17].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_17_qs) + ); + + // Subregister 18 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_18]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_18_we & mio_pad_sleep_regwen_18_qs), + .wd (mio_pad_sleep_mode_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[18].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_18_qs) + ); + + // Subregister 19 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_19]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_19_we & mio_pad_sleep_regwen_19_qs), + .wd (mio_pad_sleep_mode_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[19].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_19_qs) + ); + + // Subregister 20 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_20]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_20_we & mio_pad_sleep_regwen_20_qs), + .wd (mio_pad_sleep_mode_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[20].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_20_qs) + ); + + // Subregister 21 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_21]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_21_we & mio_pad_sleep_regwen_21_qs), + .wd (mio_pad_sleep_mode_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[21].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_21_qs) + ); + + // Subregister 22 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_22]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_22_we & mio_pad_sleep_regwen_22_qs), + .wd (mio_pad_sleep_mode_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[22].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_22_qs) + ); + + // Subregister 23 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_23]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_23_we & mio_pad_sleep_regwen_23_qs), + .wd (mio_pad_sleep_mode_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[23].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_23_qs) + ); + + // Subregister 24 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_24]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_24_we & mio_pad_sleep_regwen_24_qs), + .wd (mio_pad_sleep_mode_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[24].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_24_qs) + ); + + // Subregister 25 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_25]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_25_we & mio_pad_sleep_regwen_25_qs), + .wd (mio_pad_sleep_mode_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[25].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_25_qs) + ); + + // Subregister 26 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_26]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_26_we & mio_pad_sleep_regwen_26_qs), + .wd (mio_pad_sleep_mode_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[26].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_26_qs) + ); + + // Subregister 27 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_27]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_27_we & mio_pad_sleep_regwen_27_qs), + .wd (mio_pad_sleep_mode_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[27].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_27_qs) + ); + + // Subregister 28 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_28]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_28_we & mio_pad_sleep_regwen_28_qs), + .wd (mio_pad_sleep_mode_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[28].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_28_qs) + ); + + // Subregister 29 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_29]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_29_we & mio_pad_sleep_regwen_29_qs), + .wd (mio_pad_sleep_mode_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[29].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_29_qs) + ); + + // Subregister 30 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_30]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_30_we & mio_pad_sleep_regwen_30_qs), + .wd (mio_pad_sleep_mode_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[30].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_30_qs) + ); + + // Subregister 31 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_31]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_mio_pad_sleep_mode_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (mio_pad_sleep_mode_31_we & mio_pad_sleep_regwen_31_qs), + .wd (mio_pad_sleep_mode_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[31].q ), + + // to register interface (read) + .qs (mio_pad_sleep_mode_31_qs) + ); + + + + // Subregister 0 of Multireg dio_pad_sleep_status + // R[dio_pad_sleep_status]: V(False) + + // F[en_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_0_we), + .wd (dio_pad_sleep_status_en_0_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[0].de), + .d (hw2reg.dio_pad_sleep_status[0].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[0].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_0_qs) + ); + + + // F[en_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_1_we), + .wd (dio_pad_sleep_status_en_1_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[1].de), + .d (hw2reg.dio_pad_sleep_status[1].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[1].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_1_qs) + ); + + + // F[en_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_2_we), + .wd (dio_pad_sleep_status_en_2_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[2].de), + .d (hw2reg.dio_pad_sleep_status[2].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[2].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_2_qs) + ); + + + // F[en_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_3_we), + .wd (dio_pad_sleep_status_en_3_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[3].de), + .d (hw2reg.dio_pad_sleep_status[3].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[3].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_3_qs) + ); + + + // F[en_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_4_we), + .wd (dio_pad_sleep_status_en_4_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[4].de), + .d (hw2reg.dio_pad_sleep_status[4].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[4].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_4_qs) + ); + + + // F[en_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_5_we), + .wd (dio_pad_sleep_status_en_5_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[5].de), + .d (hw2reg.dio_pad_sleep_status[5].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[5].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_5_qs) + ); + + + // F[en_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_6_we), + .wd (dio_pad_sleep_status_en_6_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[6].de), + .d (hw2reg.dio_pad_sleep_status[6].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[6].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_6_qs) + ); + + + // F[en_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_7_we), + .wd (dio_pad_sleep_status_en_7_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[7].de), + .d (hw2reg.dio_pad_sleep_status[7].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[7].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_7_qs) + ); + + + // F[en_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_8_we), + .wd (dio_pad_sleep_status_en_8_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[8].de), + .d (hw2reg.dio_pad_sleep_status[8].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[8].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_8_qs) + ); + + + // F[en_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_9_we), + .wd (dio_pad_sleep_status_en_9_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[9].de), + .d (hw2reg.dio_pad_sleep_status[9].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[9].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_9_qs) + ); + + + // F[en_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_10_we), + .wd (dio_pad_sleep_status_en_10_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[10].de), + .d (hw2reg.dio_pad_sleep_status[10].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[10].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_10_qs) + ); + + + // F[en_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_11_we), + .wd (dio_pad_sleep_status_en_11_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[11].de), + .d (hw2reg.dio_pad_sleep_status[11].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[11].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_11_qs) + ); + + + // F[en_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_12_we), + .wd (dio_pad_sleep_status_en_12_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[12].de), + .d (hw2reg.dio_pad_sleep_status[12].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[12].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_12_qs) + ); + + + // F[en_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_13_we), + .wd (dio_pad_sleep_status_en_13_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[13].de), + .d (hw2reg.dio_pad_sleep_status[13].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[13].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_13_qs) + ); + + + // F[en_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_status_en_14_we), + .wd (dio_pad_sleep_status_en_14_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[14].de), + .d (hw2reg.dio_pad_sleep_status[14].d ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[14].q ), + + // to register interface (read) + .qs (dio_pad_sleep_status_en_14_qs) + ); + + + + + // Subregister 0 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_0]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_0_we), + .wd (dio_pad_sleep_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_0_qs) + ); + + // Subregister 1 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_1]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_1_we), + .wd (dio_pad_sleep_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_1_qs) + ); + + // Subregister 2 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_2]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_2_we), + .wd (dio_pad_sleep_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_2_qs) + ); + + // Subregister 3 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_3]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_3_we), + .wd (dio_pad_sleep_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_3_qs) + ); + + // Subregister 4 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_4]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_4_we), + .wd (dio_pad_sleep_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_4_qs) + ); + + // Subregister 5 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_5]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_5_we), + .wd (dio_pad_sleep_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_5_qs) + ); + + // Subregister 6 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_6]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_6_we), + .wd (dio_pad_sleep_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_6_qs) + ); + + // Subregister 7 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_7]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_7_we), + .wd (dio_pad_sleep_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_7_qs) + ); + + // Subregister 8 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_8]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_8_we), + .wd (dio_pad_sleep_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_8_qs) + ); + + // Subregister 9 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_9]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_9_we), + .wd (dio_pad_sleep_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_9_qs) + ); + + // Subregister 10 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_10]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_10_we), + .wd (dio_pad_sleep_regwen_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_10_qs) + ); + + // Subregister 11 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_11]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_11_we), + .wd (dio_pad_sleep_regwen_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_11_qs) + ); + + // Subregister 12 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_12]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_12_we), + .wd (dio_pad_sleep_regwen_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_12_qs) + ); + + // Subregister 13 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_13]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_13_we), + .wd (dio_pad_sleep_regwen_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_13_qs) + ); + + // Subregister 14 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_14]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dio_pad_sleep_regwen_14_we), + .wd (dio_pad_sleep_regwen_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_14_qs) + ); + + + + // Subregister 0 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_0]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_0_we & dio_pad_sleep_regwen_0_qs), + .wd (dio_pad_sleep_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[0].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_0_qs) + ); + + // Subregister 1 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_1]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_1_we & dio_pad_sleep_regwen_1_qs), + .wd (dio_pad_sleep_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[1].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_1_qs) + ); + + // Subregister 2 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_2]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_2_we & dio_pad_sleep_regwen_2_qs), + .wd (dio_pad_sleep_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[2].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_2_qs) + ); + + // Subregister 3 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_3]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_3_we & dio_pad_sleep_regwen_3_qs), + .wd (dio_pad_sleep_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[3].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_3_qs) + ); + + // Subregister 4 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_4]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_4_we & dio_pad_sleep_regwen_4_qs), + .wd (dio_pad_sleep_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[4].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_4_qs) + ); + + // Subregister 5 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_5]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_5_we & dio_pad_sleep_regwen_5_qs), + .wd (dio_pad_sleep_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[5].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_5_qs) + ); + + // Subregister 6 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_6]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_6_we & dio_pad_sleep_regwen_6_qs), + .wd (dio_pad_sleep_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[6].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_6_qs) + ); + + // Subregister 7 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_7]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_7_we & dio_pad_sleep_regwen_7_qs), + .wd (dio_pad_sleep_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[7].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_7_qs) + ); + + // Subregister 8 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_8]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_8_we & dio_pad_sleep_regwen_8_qs), + .wd (dio_pad_sleep_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[8].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_8_qs) + ); + + // Subregister 9 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_9]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_9_we & dio_pad_sleep_regwen_9_qs), + .wd (dio_pad_sleep_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[9].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_9_qs) + ); + + // Subregister 10 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_10]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_10_we & dio_pad_sleep_regwen_10_qs), + .wd (dio_pad_sleep_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[10].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_10_qs) + ); + + // Subregister 11 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_11]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_11_we & dio_pad_sleep_regwen_11_qs), + .wd (dio_pad_sleep_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[11].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_11_qs) + ); + + // Subregister 12 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_12]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_12_we & dio_pad_sleep_regwen_12_qs), + .wd (dio_pad_sleep_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[12].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_12_qs) + ); + + // Subregister 13 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_13]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_13_we & dio_pad_sleep_regwen_13_qs), + .wd (dio_pad_sleep_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[13].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_13_qs) + ); + + // Subregister 14 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_14]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_en_14_we & dio_pad_sleep_regwen_14_qs), + .wd (dio_pad_sleep_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[14].q ), + + // to register interface (read) + .qs (dio_pad_sleep_en_14_qs) + ); + + + + // Subregister 0 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_0]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_0_we & dio_pad_sleep_regwen_0_qs), + .wd (dio_pad_sleep_mode_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[0].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_0_qs) + ); + + // Subregister 1 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_1]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_1_we & dio_pad_sleep_regwen_1_qs), + .wd (dio_pad_sleep_mode_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[1].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_1_qs) + ); + + // Subregister 2 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_2]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_2_we & dio_pad_sleep_regwen_2_qs), + .wd (dio_pad_sleep_mode_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[2].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_2_qs) + ); + + // Subregister 3 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_3]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_3_we & dio_pad_sleep_regwen_3_qs), + .wd (dio_pad_sleep_mode_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[3].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_3_qs) + ); + + // Subregister 4 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_4]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_4_we & dio_pad_sleep_regwen_4_qs), + .wd (dio_pad_sleep_mode_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[4].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_4_qs) + ); + + // Subregister 5 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_5]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_5_we & dio_pad_sleep_regwen_5_qs), + .wd (dio_pad_sleep_mode_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[5].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_5_qs) + ); + + // Subregister 6 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_6]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_6_we & dio_pad_sleep_regwen_6_qs), + .wd (dio_pad_sleep_mode_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[6].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_6_qs) + ); + + // Subregister 7 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_7]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_7_we & dio_pad_sleep_regwen_7_qs), + .wd (dio_pad_sleep_mode_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[7].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_7_qs) + ); + + // Subregister 8 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_8]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_8_we & dio_pad_sleep_regwen_8_qs), + .wd (dio_pad_sleep_mode_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[8].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_8_qs) + ); + + // Subregister 9 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_9]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_9_we & dio_pad_sleep_regwen_9_qs), + .wd (dio_pad_sleep_mode_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[9].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_9_qs) + ); + + // Subregister 10 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_10]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_10_we & dio_pad_sleep_regwen_10_qs), + .wd (dio_pad_sleep_mode_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[10].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_10_qs) + ); + + // Subregister 11 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_11]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_11_we & dio_pad_sleep_regwen_11_qs), + .wd (dio_pad_sleep_mode_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[11].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_11_qs) + ); + + // Subregister 12 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_12]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_12_we & dio_pad_sleep_regwen_12_qs), + .wd (dio_pad_sleep_mode_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[12].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_12_qs) + ); + + // Subregister 13 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_13]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_13_we & dio_pad_sleep_regwen_13_qs), + .wd (dio_pad_sleep_mode_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[13].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_13_qs) + ); + + // Subregister 14 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_14]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (dio_pad_sleep_mode_14_we & dio_pad_sleep_regwen_14_qs), + .wd (dio_pad_sleep_mode_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[14].q ), + + // to register interface (read) + .qs (dio_pad_sleep_mode_14_qs) ); @@ -9003,7 +14330,7 @@ - logic [280:0] addr_hit; + logic [423:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET); @@ -9152,141 +14479,284 @@ addr_hit[143] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET); addr_hit[144] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET); addr_hit[145] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET); - addr_hit[146] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_0_OFFSET); - addr_hit[147] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_1_OFFSET); - addr_hit[148] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_2_OFFSET); - addr_hit[149] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_3_OFFSET); - addr_hit[150] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_4_OFFSET); - addr_hit[151] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_5_OFFSET); - addr_hit[152] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_6_OFFSET); - addr_hit[153] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_7_OFFSET); - addr_hit[154] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_8_OFFSET); - addr_hit[155] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_9_OFFSET); - addr_hit[156] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_10_OFFSET); - addr_hit[157] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_11_OFFSET); - addr_hit[158] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_12_OFFSET); - addr_hit[159] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_13_OFFSET); - addr_hit[160] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_14_OFFSET); - addr_hit[161] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_15_OFFSET); - addr_hit[162] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_16_OFFSET); - addr_hit[163] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_17_OFFSET); - addr_hit[164] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_18_OFFSET); - addr_hit[165] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_19_OFFSET); - addr_hit[166] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_20_OFFSET); - addr_hit[167] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_21_OFFSET); - addr_hit[168] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_22_OFFSET); - addr_hit[169] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_23_OFFSET); - addr_hit[170] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_24_OFFSET); - addr_hit[171] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_25_OFFSET); - addr_hit[172] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_26_OFFSET); - addr_hit[173] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_27_OFFSET); - addr_hit[174] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_28_OFFSET); - addr_hit[175] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_29_OFFSET); - addr_hit[176] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_30_OFFSET); - addr_hit[177] = (reg_addr == PINMUX_MIO_OUT_SLEEP_REGWEN_31_OFFSET); - addr_hit[178] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_0_OFFSET); - addr_hit[179] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_1_OFFSET); - addr_hit[180] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_2_OFFSET); - addr_hit[181] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_3_OFFSET); - addr_hit[182] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_4_OFFSET); - addr_hit[183] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_5_OFFSET); - addr_hit[184] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_6_OFFSET); - addr_hit[185] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_7_OFFSET); - addr_hit[186] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_8_OFFSET); - addr_hit[187] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_9_OFFSET); - addr_hit[188] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_10_OFFSET); - addr_hit[189] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_11_OFFSET); - addr_hit[190] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_12_OFFSET); - addr_hit[191] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_13_OFFSET); - addr_hit[192] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_14_OFFSET); - addr_hit[193] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_15_OFFSET); - addr_hit[194] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_16_OFFSET); - addr_hit[195] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_17_OFFSET); - addr_hit[196] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_18_OFFSET); - addr_hit[197] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_19_OFFSET); - addr_hit[198] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_20_OFFSET); - addr_hit[199] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_21_OFFSET); - addr_hit[200] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_22_OFFSET); - addr_hit[201] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_23_OFFSET); - addr_hit[202] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_24_OFFSET); - addr_hit[203] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_25_OFFSET); - addr_hit[204] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_26_OFFSET); - addr_hit[205] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_27_OFFSET); - addr_hit[206] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_28_OFFSET); - addr_hit[207] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_29_OFFSET); - addr_hit[208] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_30_OFFSET); - addr_hit[209] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_31_OFFSET); - addr_hit[210] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_0_OFFSET); - addr_hit[211] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_1_OFFSET); - addr_hit[212] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_2_OFFSET); - addr_hit[213] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_3_OFFSET); - addr_hit[214] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_4_OFFSET); - addr_hit[215] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_5_OFFSET); - addr_hit[216] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_6_OFFSET); - addr_hit[217] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_7_OFFSET); - addr_hit[218] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_8_OFFSET); - addr_hit[219] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_9_OFFSET); - addr_hit[220] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_10_OFFSET); - addr_hit[221] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_11_OFFSET); - addr_hit[222] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_12_OFFSET); - addr_hit[223] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_13_OFFSET); - addr_hit[224] = (reg_addr == PINMUX_DIO_OUT_SLEEP_REGWEN_14_OFFSET); - addr_hit[225] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_0_OFFSET); - addr_hit[226] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_1_OFFSET); - addr_hit[227] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_2_OFFSET); - addr_hit[228] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_3_OFFSET); - addr_hit[229] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_4_OFFSET); - addr_hit[230] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_5_OFFSET); - addr_hit[231] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_6_OFFSET); - addr_hit[232] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_7_OFFSET); - addr_hit[233] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_8_OFFSET); - addr_hit[234] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_9_OFFSET); - addr_hit[235] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_10_OFFSET); - addr_hit[236] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_11_OFFSET); - addr_hit[237] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_12_OFFSET); - addr_hit[238] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_13_OFFSET); - addr_hit[239] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_14_OFFSET); - addr_hit[240] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET); - addr_hit[241] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET); - addr_hit[242] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET); - addr_hit[243] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET); - addr_hit[244] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET); - addr_hit[245] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET); - addr_hit[246] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET); - addr_hit[247] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET); - addr_hit[248] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET); - addr_hit[249] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET); - addr_hit[250] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET); - addr_hit[251] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET); - addr_hit[252] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET); - addr_hit[253] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET); - addr_hit[254] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET); - addr_hit[255] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET); - addr_hit[256] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET); - addr_hit[257] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET); - addr_hit[258] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET); - addr_hit[259] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET); - addr_hit[260] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET); - addr_hit[261] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET); - addr_hit[262] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET); - addr_hit[263] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET); - addr_hit[264] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET); - addr_hit[265] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET); - addr_hit[266] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET); - addr_hit[267] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET); - addr_hit[268] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET); - addr_hit[269] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET); - addr_hit[270] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET); - addr_hit[271] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET); - addr_hit[272] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET); - addr_hit[273] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET); - addr_hit[274] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET); - addr_hit[275] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET); - addr_hit[276] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET); - addr_hit[277] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET); - addr_hit[278] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET); - addr_hit[279] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET); - addr_hit[280] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET); + addr_hit[146] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET); + addr_hit[147] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET); + addr_hit[148] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET); + addr_hit[149] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET); + addr_hit[150] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET); + addr_hit[151] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET); + addr_hit[152] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET); + addr_hit[153] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET); + addr_hit[154] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET); + addr_hit[155] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET); + addr_hit[156] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET); + addr_hit[157] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET); + addr_hit[158] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET); + addr_hit[159] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET); + addr_hit[160] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET); + addr_hit[161] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET); + addr_hit[162] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET); + addr_hit[163] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET); + addr_hit[164] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET); + addr_hit[165] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET); + addr_hit[166] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET); + addr_hit[167] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET); + addr_hit[168] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET); + addr_hit[169] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET); + addr_hit[170] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET); + addr_hit[171] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET); + addr_hit[172] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET); + addr_hit[173] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET); + addr_hit[174] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET); + addr_hit[175] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET); + addr_hit[176] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET); + addr_hit[177] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET); + addr_hit[178] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET); + addr_hit[179] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET); + addr_hit[180] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET); + addr_hit[181] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET); + addr_hit[182] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET); + addr_hit[183] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET); + addr_hit[184] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET); + addr_hit[185] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET); + addr_hit[186] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET); + addr_hit[187] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET); + addr_hit[188] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET); + addr_hit[189] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET); + addr_hit[190] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET); + addr_hit[191] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET); + addr_hit[192] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET); + addr_hit[193] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET); + addr_hit[194] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET); + addr_hit[195] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET); + addr_hit[196] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET); + addr_hit[197] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET); + addr_hit[198] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET); + addr_hit[199] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET); + addr_hit[200] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET); + addr_hit[201] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET); + addr_hit[202] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET); + addr_hit[203] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET); + addr_hit[204] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET); + addr_hit[205] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET); + addr_hit[206] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET); + addr_hit[207] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET); + addr_hit[208] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET); + addr_hit[209] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET); + addr_hit[210] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET); + addr_hit[211] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET); + addr_hit[212] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET); + addr_hit[213] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET); + addr_hit[214] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET); + addr_hit[215] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET); + addr_hit[216] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET); + addr_hit[217] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET); + addr_hit[218] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET); + addr_hit[219] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET); + addr_hit[220] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET); + addr_hit[221] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET); + addr_hit[222] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET); + addr_hit[223] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET); + addr_hit[224] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET); + addr_hit[225] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET); + addr_hit[226] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET); + addr_hit[227] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET); + addr_hit[228] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET); + addr_hit[229] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET); + addr_hit[230] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET); + addr_hit[231] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET); + addr_hit[232] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET); + addr_hit[233] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET); + addr_hit[234] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET); + addr_hit[235] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET); + addr_hit[236] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET); + addr_hit[237] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET); + addr_hit[238] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET); + addr_hit[239] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET); + addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_OFFSET); + addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET); + addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET); + addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET); + addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET); + addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET); + addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET); + addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET); + addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET); + addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET); + addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET); + addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET); + addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET); + addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET); + addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET); + addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET); + addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET); + addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET); + addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET); + addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET); + addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET); + addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET); + addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET); + addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET); + addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET); + addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET); + addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET); + addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET); + addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET); + addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET); + addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET); + addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET); + addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET); + addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET); + addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET); + addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET); + addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET); + addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET); + addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET); + addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET); + addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET); + addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET); + addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET); + addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET); + addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET); + addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET); + addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET); + addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET); + addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET); + addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET); + addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET); + addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET); + addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET); + addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET); + addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET); + addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET); + addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET); + addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET); + addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET); + addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET); + addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET); + addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET); + addr_hit[302] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET); + addr_hit[303] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET); + addr_hit[304] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET); + addr_hit[305] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET); + addr_hit[306] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET); + addr_hit[307] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET); + addr_hit[308] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET); + addr_hit[309] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET); + addr_hit[310] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET); + addr_hit[311] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET); + addr_hit[312] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET); + addr_hit[313] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET); + addr_hit[314] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET); + addr_hit[315] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET); + addr_hit[316] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET); + addr_hit[317] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET); + addr_hit[318] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET); + addr_hit[319] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET); + addr_hit[320] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET); + addr_hit[321] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET); + addr_hit[322] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET); + addr_hit[323] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET); + addr_hit[324] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET); + addr_hit[325] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET); + addr_hit[326] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET); + addr_hit[327] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET); + addr_hit[328] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET); + addr_hit[329] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET); + addr_hit[330] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET); + addr_hit[331] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET); + addr_hit[332] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET); + addr_hit[333] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET); + addr_hit[334] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET); + addr_hit[335] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET); + addr_hit[336] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET); + addr_hit[337] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET); + addr_hit[338] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET); + addr_hit[339] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET); + addr_hit[340] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET); + addr_hit[341] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET); + addr_hit[342] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET); + addr_hit[343] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET); + addr_hit[344] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET); + addr_hit[345] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET); + addr_hit[346] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET); + addr_hit[347] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET); + addr_hit[348] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET); + addr_hit[349] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET); + addr_hit[350] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET); + addr_hit[351] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET); + addr_hit[352] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET); + addr_hit[353] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET); + addr_hit[354] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET); + addr_hit[355] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET); + addr_hit[356] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET); + addr_hit[357] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET); + addr_hit[358] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET); + addr_hit[359] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET); + addr_hit[360] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET); + addr_hit[361] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET); + addr_hit[362] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET); + addr_hit[363] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET); + addr_hit[364] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET); + addr_hit[365] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET); + addr_hit[366] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET); + addr_hit[367] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET); + addr_hit[368] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET); + addr_hit[369] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET); + addr_hit[370] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET); + addr_hit[371] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET); + addr_hit[372] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET); + addr_hit[373] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET); + addr_hit[374] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET); + addr_hit[375] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET); + addr_hit[376] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET); + addr_hit[377] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET); + addr_hit[378] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET); + addr_hit[379] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET); + addr_hit[380] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET); + addr_hit[381] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET); + addr_hit[382] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET); + addr_hit[383] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET); + addr_hit[384] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET); + addr_hit[385] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET); + addr_hit[386] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET); + addr_hit[387] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET); + addr_hit[388] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET); + addr_hit[389] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET); + addr_hit[390] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET); + addr_hit[391] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET); + addr_hit[392] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET); + addr_hit[393] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET); + addr_hit[394] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET); + addr_hit[395] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET); + addr_hit[396] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET); + addr_hit[397] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET); + addr_hit[398] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET); + addr_hit[399] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET); + addr_hit[400] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET); + addr_hit[401] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET); + addr_hit[402] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET); + addr_hit[403] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET); + addr_hit[404] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET); + addr_hit[405] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET); + addr_hit[406] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET); + addr_hit[407] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET); + addr_hit[408] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET); + addr_hit[409] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET); + addr_hit[410] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET); + addr_hit[411] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET); + addr_hit[412] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET); + addr_hit[413] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET); + addr_hit[414] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET); + addr_hit[415] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET); + addr_hit[416] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET); + addr_hit[417] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET); + addr_hit[418] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET); + addr_hit[419] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET); + addr_hit[420] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET); + addr_hit[421] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET); + addr_hit[422] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET); + addr_hit[423] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -9575,6 +15045,149 @@ if (addr_hit[278] && reg_we && (PINMUX_PERMIT[278] != (PINMUX_PERMIT[278] & reg_be))) wr_err = 1'b1 ; if (addr_hit[279] && reg_we && (PINMUX_PERMIT[279] != (PINMUX_PERMIT[279] & reg_be))) wr_err = 1'b1 ; if (addr_hit[280] && reg_we && (PINMUX_PERMIT[280] != (PINMUX_PERMIT[280] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[281] && reg_we && (PINMUX_PERMIT[281] != (PINMUX_PERMIT[281] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[282] && reg_we && (PINMUX_PERMIT[282] != (PINMUX_PERMIT[282] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[283] && reg_we && (PINMUX_PERMIT[283] != (PINMUX_PERMIT[283] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[284] && reg_we && (PINMUX_PERMIT[284] != (PINMUX_PERMIT[284] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[285] && reg_we && (PINMUX_PERMIT[285] != (PINMUX_PERMIT[285] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[286] && reg_we && (PINMUX_PERMIT[286] != (PINMUX_PERMIT[286] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[287] && reg_we && (PINMUX_PERMIT[287] != (PINMUX_PERMIT[287] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[288] && reg_we && (PINMUX_PERMIT[288] != (PINMUX_PERMIT[288] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[289] && reg_we && (PINMUX_PERMIT[289] != (PINMUX_PERMIT[289] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[290] && reg_we && (PINMUX_PERMIT[290] != (PINMUX_PERMIT[290] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[291] && reg_we && (PINMUX_PERMIT[291] != (PINMUX_PERMIT[291] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[292] && reg_we && (PINMUX_PERMIT[292] != (PINMUX_PERMIT[292] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[293] && reg_we && (PINMUX_PERMIT[293] != (PINMUX_PERMIT[293] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[294] && reg_we && (PINMUX_PERMIT[294] != (PINMUX_PERMIT[294] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[295] && reg_we && (PINMUX_PERMIT[295] != (PINMUX_PERMIT[295] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[296] && reg_we && (PINMUX_PERMIT[296] != (PINMUX_PERMIT[296] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[297] && reg_we && (PINMUX_PERMIT[297] != (PINMUX_PERMIT[297] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[298] && reg_we && (PINMUX_PERMIT[298] != (PINMUX_PERMIT[298] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[299] && reg_we && (PINMUX_PERMIT[299] != (PINMUX_PERMIT[299] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[300] && reg_we && (PINMUX_PERMIT[300] != (PINMUX_PERMIT[300] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[301] && reg_we && (PINMUX_PERMIT[301] != (PINMUX_PERMIT[301] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[302] && reg_we && (PINMUX_PERMIT[302] != (PINMUX_PERMIT[302] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[303] && reg_we && (PINMUX_PERMIT[303] != (PINMUX_PERMIT[303] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[304] && reg_we && (PINMUX_PERMIT[304] != (PINMUX_PERMIT[304] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[305] && reg_we && (PINMUX_PERMIT[305] != (PINMUX_PERMIT[305] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[306] && reg_we && (PINMUX_PERMIT[306] != (PINMUX_PERMIT[306] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[307] && reg_we && (PINMUX_PERMIT[307] != (PINMUX_PERMIT[307] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[308] && reg_we && (PINMUX_PERMIT[308] != (PINMUX_PERMIT[308] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[309] && reg_we && (PINMUX_PERMIT[309] != (PINMUX_PERMIT[309] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[310] && reg_we && (PINMUX_PERMIT[310] != (PINMUX_PERMIT[310] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[311] && reg_we && (PINMUX_PERMIT[311] != (PINMUX_PERMIT[311] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[312] && reg_we && (PINMUX_PERMIT[312] != (PINMUX_PERMIT[312] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[313] && reg_we && (PINMUX_PERMIT[313] != (PINMUX_PERMIT[313] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[314] && reg_we && (PINMUX_PERMIT[314] != (PINMUX_PERMIT[314] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[315] && reg_we && (PINMUX_PERMIT[315] != (PINMUX_PERMIT[315] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[316] && reg_we && (PINMUX_PERMIT[316] != (PINMUX_PERMIT[316] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[317] && reg_we && (PINMUX_PERMIT[317] != (PINMUX_PERMIT[317] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[318] && reg_we && (PINMUX_PERMIT[318] != (PINMUX_PERMIT[318] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[319] && reg_we && (PINMUX_PERMIT[319] != (PINMUX_PERMIT[319] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[320] && reg_we && (PINMUX_PERMIT[320] != (PINMUX_PERMIT[320] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[321] && reg_we && (PINMUX_PERMIT[321] != (PINMUX_PERMIT[321] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[322] && reg_we && (PINMUX_PERMIT[322] != (PINMUX_PERMIT[322] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[323] && reg_we && (PINMUX_PERMIT[323] != (PINMUX_PERMIT[323] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[324] && reg_we && (PINMUX_PERMIT[324] != (PINMUX_PERMIT[324] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[325] && reg_we && (PINMUX_PERMIT[325] != (PINMUX_PERMIT[325] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[326] && reg_we && (PINMUX_PERMIT[326] != (PINMUX_PERMIT[326] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[327] && reg_we && (PINMUX_PERMIT[327] != (PINMUX_PERMIT[327] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[328] && reg_we && (PINMUX_PERMIT[328] != (PINMUX_PERMIT[328] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[329] && reg_we && (PINMUX_PERMIT[329] != (PINMUX_PERMIT[329] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[330] && reg_we && (PINMUX_PERMIT[330] != (PINMUX_PERMIT[330] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[331] && reg_we && (PINMUX_PERMIT[331] != (PINMUX_PERMIT[331] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[332] && reg_we && (PINMUX_PERMIT[332] != (PINMUX_PERMIT[332] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[333] && reg_we && (PINMUX_PERMIT[333] != (PINMUX_PERMIT[333] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[334] && reg_we && (PINMUX_PERMIT[334] != (PINMUX_PERMIT[334] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[335] && reg_we && (PINMUX_PERMIT[335] != (PINMUX_PERMIT[335] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[336] && reg_we && (PINMUX_PERMIT[336] != (PINMUX_PERMIT[336] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[337] && reg_we && (PINMUX_PERMIT[337] != (PINMUX_PERMIT[337] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[338] && reg_we && (PINMUX_PERMIT[338] != (PINMUX_PERMIT[338] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[339] && reg_we && (PINMUX_PERMIT[339] != (PINMUX_PERMIT[339] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[340] && reg_we && (PINMUX_PERMIT[340] != (PINMUX_PERMIT[340] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[341] && reg_we && (PINMUX_PERMIT[341] != (PINMUX_PERMIT[341] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[342] && reg_we && (PINMUX_PERMIT[342] != (PINMUX_PERMIT[342] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[343] && reg_we && (PINMUX_PERMIT[343] != (PINMUX_PERMIT[343] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[344] && reg_we && (PINMUX_PERMIT[344] != (PINMUX_PERMIT[344] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[345] && reg_we && (PINMUX_PERMIT[345] != (PINMUX_PERMIT[345] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[346] && reg_we && (PINMUX_PERMIT[346] != (PINMUX_PERMIT[346] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[347] && reg_we && (PINMUX_PERMIT[347] != (PINMUX_PERMIT[347] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[348] && reg_we && (PINMUX_PERMIT[348] != (PINMUX_PERMIT[348] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[349] && reg_we && (PINMUX_PERMIT[349] != (PINMUX_PERMIT[349] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[350] && reg_we && (PINMUX_PERMIT[350] != (PINMUX_PERMIT[350] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[351] && reg_we && (PINMUX_PERMIT[351] != (PINMUX_PERMIT[351] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[352] && reg_we && (PINMUX_PERMIT[352] != (PINMUX_PERMIT[352] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[353] && reg_we && (PINMUX_PERMIT[353] != (PINMUX_PERMIT[353] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[354] && reg_we && (PINMUX_PERMIT[354] != (PINMUX_PERMIT[354] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[355] && reg_we && (PINMUX_PERMIT[355] != (PINMUX_PERMIT[355] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[356] && reg_we && (PINMUX_PERMIT[356] != (PINMUX_PERMIT[356] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[357] && reg_we && (PINMUX_PERMIT[357] != (PINMUX_PERMIT[357] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[358] && reg_we && (PINMUX_PERMIT[358] != (PINMUX_PERMIT[358] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[359] && reg_we && (PINMUX_PERMIT[359] != (PINMUX_PERMIT[359] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[360] && reg_we && (PINMUX_PERMIT[360] != (PINMUX_PERMIT[360] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[361] && reg_we && (PINMUX_PERMIT[361] != (PINMUX_PERMIT[361] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[362] && reg_we && (PINMUX_PERMIT[362] != (PINMUX_PERMIT[362] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[363] && reg_we && (PINMUX_PERMIT[363] != (PINMUX_PERMIT[363] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[364] && reg_we && (PINMUX_PERMIT[364] != (PINMUX_PERMIT[364] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[365] && reg_we && (PINMUX_PERMIT[365] != (PINMUX_PERMIT[365] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[366] && reg_we && (PINMUX_PERMIT[366] != (PINMUX_PERMIT[366] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[367] && reg_we && (PINMUX_PERMIT[367] != (PINMUX_PERMIT[367] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[368] && reg_we && (PINMUX_PERMIT[368] != (PINMUX_PERMIT[368] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[369] && reg_we && (PINMUX_PERMIT[369] != (PINMUX_PERMIT[369] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[370] && reg_we && (PINMUX_PERMIT[370] != (PINMUX_PERMIT[370] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[371] && reg_we && (PINMUX_PERMIT[371] != (PINMUX_PERMIT[371] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[372] && reg_we && (PINMUX_PERMIT[372] != (PINMUX_PERMIT[372] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[373] && reg_we && (PINMUX_PERMIT[373] != (PINMUX_PERMIT[373] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[374] && reg_we && (PINMUX_PERMIT[374] != (PINMUX_PERMIT[374] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[375] && reg_we && (PINMUX_PERMIT[375] != (PINMUX_PERMIT[375] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[376] && reg_we && (PINMUX_PERMIT[376] != (PINMUX_PERMIT[376] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[377] && reg_we && (PINMUX_PERMIT[377] != (PINMUX_PERMIT[377] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[378] && reg_we && (PINMUX_PERMIT[378] != (PINMUX_PERMIT[378] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[379] && reg_we && (PINMUX_PERMIT[379] != (PINMUX_PERMIT[379] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[380] && reg_we && (PINMUX_PERMIT[380] != (PINMUX_PERMIT[380] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[381] && reg_we && (PINMUX_PERMIT[381] != (PINMUX_PERMIT[381] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[382] && reg_we && (PINMUX_PERMIT[382] != (PINMUX_PERMIT[382] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[383] && reg_we && (PINMUX_PERMIT[383] != (PINMUX_PERMIT[383] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[384] && reg_we && (PINMUX_PERMIT[384] != (PINMUX_PERMIT[384] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[385] && reg_we && (PINMUX_PERMIT[385] != (PINMUX_PERMIT[385] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[386] && reg_we && (PINMUX_PERMIT[386] != (PINMUX_PERMIT[386] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[387] && reg_we && (PINMUX_PERMIT[387] != (PINMUX_PERMIT[387] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[388] && reg_we && (PINMUX_PERMIT[388] != (PINMUX_PERMIT[388] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[389] && reg_we && (PINMUX_PERMIT[389] != (PINMUX_PERMIT[389] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[390] && reg_we && (PINMUX_PERMIT[390] != (PINMUX_PERMIT[390] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[391] && reg_we && (PINMUX_PERMIT[391] != (PINMUX_PERMIT[391] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[392] && reg_we && (PINMUX_PERMIT[392] != (PINMUX_PERMIT[392] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[393] && reg_we && (PINMUX_PERMIT[393] != (PINMUX_PERMIT[393] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[394] && reg_we && (PINMUX_PERMIT[394] != (PINMUX_PERMIT[394] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[395] && reg_we && (PINMUX_PERMIT[395] != (PINMUX_PERMIT[395] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[396] && reg_we && (PINMUX_PERMIT[396] != (PINMUX_PERMIT[396] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[397] && reg_we && (PINMUX_PERMIT[397] != (PINMUX_PERMIT[397] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[398] && reg_we && (PINMUX_PERMIT[398] != (PINMUX_PERMIT[398] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[399] && reg_we && (PINMUX_PERMIT[399] != (PINMUX_PERMIT[399] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[400] && reg_we && (PINMUX_PERMIT[400] != (PINMUX_PERMIT[400] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[401] && reg_we && (PINMUX_PERMIT[401] != (PINMUX_PERMIT[401] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[402] && reg_we && (PINMUX_PERMIT[402] != (PINMUX_PERMIT[402] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[403] && reg_we && (PINMUX_PERMIT[403] != (PINMUX_PERMIT[403] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[404] && reg_we && (PINMUX_PERMIT[404] != (PINMUX_PERMIT[404] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[405] && reg_we && (PINMUX_PERMIT[405] != (PINMUX_PERMIT[405] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[406] && reg_we && (PINMUX_PERMIT[406] != (PINMUX_PERMIT[406] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[407] && reg_we && (PINMUX_PERMIT[407] != (PINMUX_PERMIT[407] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[408] && reg_we && (PINMUX_PERMIT[408] != (PINMUX_PERMIT[408] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[409] && reg_we && (PINMUX_PERMIT[409] != (PINMUX_PERMIT[409] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[410] && reg_we && (PINMUX_PERMIT[410] != (PINMUX_PERMIT[410] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[411] && reg_we && (PINMUX_PERMIT[411] != (PINMUX_PERMIT[411] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[412] && reg_we && (PINMUX_PERMIT[412] != (PINMUX_PERMIT[412] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[413] && reg_we && (PINMUX_PERMIT[413] != (PINMUX_PERMIT[413] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[414] && reg_we && (PINMUX_PERMIT[414] != (PINMUX_PERMIT[414] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[415] && reg_we && (PINMUX_PERMIT[415] != (PINMUX_PERMIT[415] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[416] && reg_we && (PINMUX_PERMIT[416] != (PINMUX_PERMIT[416] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[417] && reg_we && (PINMUX_PERMIT[417] != (PINMUX_PERMIT[417] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[418] && reg_we && (PINMUX_PERMIT[418] != (PINMUX_PERMIT[418] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[419] && reg_we && (PINMUX_PERMIT[419] != (PINMUX_PERMIT[419] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[420] && reg_we && (PINMUX_PERMIT[420] != (PINMUX_PERMIT[420] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[421] && reg_we && (PINMUX_PERMIT[421] != (PINMUX_PERMIT[421] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[422] && reg_we && (PINMUX_PERMIT[422] != (PINMUX_PERMIT[422] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[423] && reg_we && (PINMUX_PERMIT[423] != (PINMUX_PERMIT[423] & reg_be))) wr_err = 1'b1 ; end assign mio_periph_insel_regwen_0_we = addr_hit[0] & reg_we & ~wr_err; @@ -10015,502 +15628,1098 @@ assign mio_outsel_31_we = addr_hit[145] & reg_we & ~wr_err; assign mio_outsel_31_wd = reg_wdata[5:0]; - assign mio_out_sleep_regwen_0_we = addr_hit[146] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_0_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_0_we = addr_hit[146] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_0_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_1_we = addr_hit[147] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_1_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_2_we = addr_hit[148] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_2_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_3_we = addr_hit[149] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_3_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_4_we = addr_hit[150] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_4_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_5_we = addr_hit[151] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_5_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_6_we = addr_hit[152] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_6_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_7_we = addr_hit[153] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_7_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_8_we = addr_hit[154] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_8_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_9_we = addr_hit[155] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_9_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_10_we = addr_hit[156] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_10_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_11_we = addr_hit[157] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_11_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_12_we = addr_hit[158] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_12_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_13_we = addr_hit[159] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_13_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_14_we = addr_hit[160] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_14_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_15_we = addr_hit[161] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_15_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_16_we = addr_hit[162] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_16_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_17_we = addr_hit[163] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_17_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_18_we = addr_hit[164] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_18_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_19_we = addr_hit[165] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_19_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_20_we = addr_hit[166] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_20_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_21_we = addr_hit[167] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_21_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_22_we = addr_hit[168] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_22_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_23_we = addr_hit[169] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_23_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_24_we = addr_hit[170] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_24_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_25_we = addr_hit[171] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_25_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_26_we = addr_hit[172] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_26_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_27_we = addr_hit[173] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_27_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_28_we = addr_hit[174] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_28_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_29_we = addr_hit[175] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_29_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_30_we = addr_hit[176] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_30_wd = reg_wdata[0]; + + assign mio_pad_attr_regwen_31_we = addr_hit[177] & reg_we & ~wr_err; + assign mio_pad_attr_regwen_31_wd = reg_wdata[0]; + + assign mio_pad_attr_0_we = addr_hit[178] & reg_we & ~wr_err; + assign mio_pad_attr_0_wd = reg_wdata[9:0]; + assign mio_pad_attr_0_re = addr_hit[178] && reg_re; + + assign mio_pad_attr_1_we = addr_hit[179] & reg_we & ~wr_err; + assign mio_pad_attr_1_wd = reg_wdata[9:0]; + assign mio_pad_attr_1_re = addr_hit[179] && reg_re; + + assign mio_pad_attr_2_we = addr_hit[180] & reg_we & ~wr_err; + assign mio_pad_attr_2_wd = reg_wdata[9:0]; + assign mio_pad_attr_2_re = addr_hit[180] && reg_re; + + assign mio_pad_attr_3_we = addr_hit[181] & reg_we & ~wr_err; + assign mio_pad_attr_3_wd = reg_wdata[9:0]; + assign mio_pad_attr_3_re = addr_hit[181] && reg_re; + + assign mio_pad_attr_4_we = addr_hit[182] & reg_we & ~wr_err; + assign mio_pad_attr_4_wd = reg_wdata[9:0]; + assign mio_pad_attr_4_re = addr_hit[182] && reg_re; + + assign mio_pad_attr_5_we = addr_hit[183] & reg_we & ~wr_err; + assign mio_pad_attr_5_wd = reg_wdata[9:0]; + assign mio_pad_attr_5_re = addr_hit[183] && reg_re; + + assign mio_pad_attr_6_we = addr_hit[184] & reg_we & ~wr_err; + assign mio_pad_attr_6_wd = reg_wdata[9:0]; + assign mio_pad_attr_6_re = addr_hit[184] && reg_re; + + assign mio_pad_attr_7_we = addr_hit[185] & reg_we & ~wr_err; + assign mio_pad_attr_7_wd = reg_wdata[9:0]; + assign mio_pad_attr_7_re = addr_hit[185] && reg_re; + + assign mio_pad_attr_8_we = addr_hit[186] & reg_we & ~wr_err; + assign mio_pad_attr_8_wd = reg_wdata[9:0]; + assign mio_pad_attr_8_re = addr_hit[186] && reg_re; + + assign mio_pad_attr_9_we = addr_hit[187] & reg_we & ~wr_err; + assign mio_pad_attr_9_wd = reg_wdata[9:0]; + assign mio_pad_attr_9_re = addr_hit[187] && reg_re; + + assign mio_pad_attr_10_we = addr_hit[188] & reg_we & ~wr_err; + assign mio_pad_attr_10_wd = reg_wdata[9:0]; + assign mio_pad_attr_10_re = addr_hit[188] && reg_re; + + assign mio_pad_attr_11_we = addr_hit[189] & reg_we & ~wr_err; + assign mio_pad_attr_11_wd = reg_wdata[9:0]; + assign mio_pad_attr_11_re = addr_hit[189] && reg_re; + + assign mio_pad_attr_12_we = addr_hit[190] & reg_we & ~wr_err; + assign mio_pad_attr_12_wd = reg_wdata[9:0]; + assign mio_pad_attr_12_re = addr_hit[190] && reg_re; + + assign mio_pad_attr_13_we = addr_hit[191] & reg_we & ~wr_err; + assign mio_pad_attr_13_wd = reg_wdata[9:0]; + assign mio_pad_attr_13_re = addr_hit[191] && reg_re; + + assign mio_pad_attr_14_we = addr_hit[192] & reg_we & ~wr_err; + assign mio_pad_attr_14_wd = reg_wdata[9:0]; + assign mio_pad_attr_14_re = addr_hit[192] && reg_re; + + assign mio_pad_attr_15_we = addr_hit[193] & reg_we & ~wr_err; + assign mio_pad_attr_15_wd = reg_wdata[9:0]; + assign mio_pad_attr_15_re = addr_hit[193] && reg_re; + + assign mio_pad_attr_16_we = addr_hit[194] & reg_we & ~wr_err; + assign mio_pad_attr_16_wd = reg_wdata[9:0]; + assign mio_pad_attr_16_re = addr_hit[194] && reg_re; + + assign mio_pad_attr_17_we = addr_hit[195] & reg_we & ~wr_err; + assign mio_pad_attr_17_wd = reg_wdata[9:0]; + assign mio_pad_attr_17_re = addr_hit[195] && reg_re; + + assign mio_pad_attr_18_we = addr_hit[196] & reg_we & ~wr_err; + assign mio_pad_attr_18_wd = reg_wdata[9:0]; + assign mio_pad_attr_18_re = addr_hit[196] && reg_re; + + assign mio_pad_attr_19_we = addr_hit[197] & reg_we & ~wr_err; + assign mio_pad_attr_19_wd = reg_wdata[9:0]; + assign mio_pad_attr_19_re = addr_hit[197] && reg_re; + + assign mio_pad_attr_20_we = addr_hit[198] & reg_we & ~wr_err; + assign mio_pad_attr_20_wd = reg_wdata[9:0]; + assign mio_pad_attr_20_re = addr_hit[198] && reg_re; + + assign mio_pad_attr_21_we = addr_hit[199] & reg_we & ~wr_err; + assign mio_pad_attr_21_wd = reg_wdata[9:0]; + assign mio_pad_attr_21_re = addr_hit[199] && reg_re; + + assign mio_pad_attr_22_we = addr_hit[200] & reg_we & ~wr_err; + assign mio_pad_attr_22_wd = reg_wdata[9:0]; + assign mio_pad_attr_22_re = addr_hit[200] && reg_re; + + assign mio_pad_attr_23_we = addr_hit[201] & reg_we & ~wr_err; + assign mio_pad_attr_23_wd = reg_wdata[9:0]; + assign mio_pad_attr_23_re = addr_hit[201] && reg_re; + + assign mio_pad_attr_24_we = addr_hit[202] & reg_we & ~wr_err; + assign mio_pad_attr_24_wd = reg_wdata[9:0]; + assign mio_pad_attr_24_re = addr_hit[202] && reg_re; + + assign mio_pad_attr_25_we = addr_hit[203] & reg_we & ~wr_err; + assign mio_pad_attr_25_wd = reg_wdata[9:0]; + assign mio_pad_attr_25_re = addr_hit[203] && reg_re; + + assign mio_pad_attr_26_we = addr_hit[204] & reg_we & ~wr_err; + assign mio_pad_attr_26_wd = reg_wdata[9:0]; + assign mio_pad_attr_26_re = addr_hit[204] && reg_re; + + assign mio_pad_attr_27_we = addr_hit[205] & reg_we & ~wr_err; + assign mio_pad_attr_27_wd = reg_wdata[9:0]; + assign mio_pad_attr_27_re = addr_hit[205] && reg_re; + + assign mio_pad_attr_28_we = addr_hit[206] & reg_we & ~wr_err; + assign mio_pad_attr_28_wd = reg_wdata[9:0]; + assign mio_pad_attr_28_re = addr_hit[206] && reg_re; + + assign mio_pad_attr_29_we = addr_hit[207] & reg_we & ~wr_err; + assign mio_pad_attr_29_wd = reg_wdata[9:0]; + assign mio_pad_attr_29_re = addr_hit[207] && reg_re; + + assign mio_pad_attr_30_we = addr_hit[208] & reg_we & ~wr_err; + assign mio_pad_attr_30_wd = reg_wdata[9:0]; + assign mio_pad_attr_30_re = addr_hit[208] && reg_re; + + assign mio_pad_attr_31_we = addr_hit[209] & reg_we & ~wr_err; + assign mio_pad_attr_31_wd = reg_wdata[9:0]; + assign mio_pad_attr_31_re = addr_hit[209] && reg_re; + + assign dio_pad_attr_regwen_0_we = addr_hit[210] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_0_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_1_we = addr_hit[211] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_1_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_2_we = addr_hit[212] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_2_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_3_we = addr_hit[213] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_3_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_4_we = addr_hit[214] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_4_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_5_we = addr_hit[215] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_5_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_6_we = addr_hit[216] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_6_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_7_we = addr_hit[217] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_7_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_8_we = addr_hit[218] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_8_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_9_we = addr_hit[219] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_9_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_10_we = addr_hit[220] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_10_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_11_we = addr_hit[221] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_11_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_12_we = addr_hit[222] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_12_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_13_we = addr_hit[223] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_13_wd = reg_wdata[0]; + + assign dio_pad_attr_regwen_14_we = addr_hit[224] & reg_we & ~wr_err; + assign dio_pad_attr_regwen_14_wd = reg_wdata[0]; + + assign dio_pad_attr_0_we = addr_hit[225] & reg_we & ~wr_err; + assign dio_pad_attr_0_wd = reg_wdata[9:0]; + assign dio_pad_attr_0_re = addr_hit[225] && reg_re; + + assign dio_pad_attr_1_we = addr_hit[226] & reg_we & ~wr_err; + assign dio_pad_attr_1_wd = reg_wdata[9:0]; + assign dio_pad_attr_1_re = addr_hit[226] && reg_re; + + assign dio_pad_attr_2_we = addr_hit[227] & reg_we & ~wr_err; + assign dio_pad_attr_2_wd = reg_wdata[9:0]; + assign dio_pad_attr_2_re = addr_hit[227] && reg_re; + + assign dio_pad_attr_3_we = addr_hit[228] & reg_we & ~wr_err; + assign dio_pad_attr_3_wd = reg_wdata[9:0]; + assign dio_pad_attr_3_re = addr_hit[228] && reg_re; + + assign dio_pad_attr_4_we = addr_hit[229] & reg_we & ~wr_err; + assign dio_pad_attr_4_wd = reg_wdata[9:0]; + assign dio_pad_attr_4_re = addr_hit[229] && reg_re; + + assign dio_pad_attr_5_we = addr_hit[230] & reg_we & ~wr_err; + assign dio_pad_attr_5_wd = reg_wdata[9:0]; + assign dio_pad_attr_5_re = addr_hit[230] && reg_re; + + assign dio_pad_attr_6_we = addr_hit[231] & reg_we & ~wr_err; + assign dio_pad_attr_6_wd = reg_wdata[9:0]; + assign dio_pad_attr_6_re = addr_hit[231] && reg_re; + + assign dio_pad_attr_7_we = addr_hit[232] & reg_we & ~wr_err; + assign dio_pad_attr_7_wd = reg_wdata[9:0]; + assign dio_pad_attr_7_re = addr_hit[232] && reg_re; + + assign dio_pad_attr_8_we = addr_hit[233] & reg_we & ~wr_err; + assign dio_pad_attr_8_wd = reg_wdata[9:0]; + assign dio_pad_attr_8_re = addr_hit[233] && reg_re; + + assign dio_pad_attr_9_we = addr_hit[234] & reg_we & ~wr_err; + assign dio_pad_attr_9_wd = reg_wdata[9:0]; + assign dio_pad_attr_9_re = addr_hit[234] && reg_re; + + assign dio_pad_attr_10_we = addr_hit[235] & reg_we & ~wr_err; + assign dio_pad_attr_10_wd = reg_wdata[9:0]; + assign dio_pad_attr_10_re = addr_hit[235] && reg_re; + + assign dio_pad_attr_11_we = addr_hit[236] & reg_we & ~wr_err; + assign dio_pad_attr_11_wd = reg_wdata[9:0]; + assign dio_pad_attr_11_re = addr_hit[236] && reg_re; + + assign dio_pad_attr_12_we = addr_hit[237] & reg_we & ~wr_err; + assign dio_pad_attr_12_wd = reg_wdata[9:0]; + assign dio_pad_attr_12_re = addr_hit[237] && reg_re; + + assign dio_pad_attr_13_we = addr_hit[238] & reg_we & ~wr_err; + assign dio_pad_attr_13_wd = reg_wdata[9:0]; + assign dio_pad_attr_13_re = addr_hit[238] && reg_re; + + assign dio_pad_attr_14_we = addr_hit[239] & reg_we & ~wr_err; + assign dio_pad_attr_14_wd = reg_wdata[9:0]; + assign dio_pad_attr_14_re = addr_hit[239] && reg_re; + + assign mio_pad_sleep_status_en_0_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_0_wd = reg_wdata[0]; + + assign mio_pad_sleep_status_en_1_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_1_wd = reg_wdata[1]; + + assign mio_pad_sleep_status_en_2_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_2_wd = reg_wdata[2]; + + assign mio_pad_sleep_status_en_3_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_3_wd = reg_wdata[3]; + + assign mio_pad_sleep_status_en_4_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_4_wd = reg_wdata[4]; + + assign mio_pad_sleep_status_en_5_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_5_wd = reg_wdata[5]; + + assign mio_pad_sleep_status_en_6_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_6_wd = reg_wdata[6]; + + assign mio_pad_sleep_status_en_7_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_7_wd = reg_wdata[7]; + + assign mio_pad_sleep_status_en_8_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_8_wd = reg_wdata[8]; + + assign mio_pad_sleep_status_en_9_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_9_wd = reg_wdata[9]; + + assign mio_pad_sleep_status_en_10_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_10_wd = reg_wdata[10]; + + assign mio_pad_sleep_status_en_11_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_11_wd = reg_wdata[11]; + + assign mio_pad_sleep_status_en_12_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_12_wd = reg_wdata[12]; + + assign mio_pad_sleep_status_en_13_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_13_wd = reg_wdata[13]; + + assign mio_pad_sleep_status_en_14_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_14_wd = reg_wdata[14]; + + assign mio_pad_sleep_status_en_15_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_15_wd = reg_wdata[15]; + + assign mio_pad_sleep_status_en_16_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_16_wd = reg_wdata[16]; + + assign mio_pad_sleep_status_en_17_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_17_wd = reg_wdata[17]; + + assign mio_pad_sleep_status_en_18_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_18_wd = reg_wdata[18]; + + assign mio_pad_sleep_status_en_19_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_19_wd = reg_wdata[19]; + + assign mio_pad_sleep_status_en_20_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_20_wd = reg_wdata[20]; + + assign mio_pad_sleep_status_en_21_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_21_wd = reg_wdata[21]; + + assign mio_pad_sleep_status_en_22_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_22_wd = reg_wdata[22]; + + assign mio_pad_sleep_status_en_23_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_23_wd = reg_wdata[23]; + + assign mio_pad_sleep_status_en_24_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_24_wd = reg_wdata[24]; + + assign mio_pad_sleep_status_en_25_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_25_wd = reg_wdata[25]; + + assign mio_pad_sleep_status_en_26_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_26_wd = reg_wdata[26]; + + assign mio_pad_sleep_status_en_27_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_27_wd = reg_wdata[27]; + + assign mio_pad_sleep_status_en_28_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_28_wd = reg_wdata[28]; + + assign mio_pad_sleep_status_en_29_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_29_wd = reg_wdata[29]; + + assign mio_pad_sleep_status_en_30_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_30_wd = reg_wdata[30]; + + assign mio_pad_sleep_status_en_31_we = addr_hit[240] & reg_we & ~wr_err; + assign mio_pad_sleep_status_en_31_wd = reg_wdata[31]; + + assign mio_pad_sleep_regwen_0_we = addr_hit[241] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_0_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_1_we = addr_hit[242] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_1_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_2_we = addr_hit[243] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_2_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_3_we = addr_hit[244] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_3_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_4_we = addr_hit[245] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_4_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_5_we = addr_hit[246] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_5_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_6_we = addr_hit[247] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_6_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_7_we = addr_hit[248] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_7_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_8_we = addr_hit[249] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_8_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_9_we = addr_hit[250] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_9_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_10_we = addr_hit[251] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_10_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_11_we = addr_hit[252] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_11_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_12_we = addr_hit[253] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_12_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_13_we = addr_hit[254] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_13_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_14_we = addr_hit[255] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_14_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_15_we = addr_hit[256] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_15_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_16_we = addr_hit[257] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_16_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_17_we = addr_hit[258] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_17_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_18_we = addr_hit[259] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_18_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_19_we = addr_hit[260] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_19_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_20_we = addr_hit[261] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_20_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_21_we = addr_hit[262] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_21_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_22_we = addr_hit[263] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_22_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_23_we = addr_hit[264] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_23_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_24_we = addr_hit[265] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_24_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_25_we = addr_hit[266] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_25_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_26_we = addr_hit[267] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_26_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_27_we = addr_hit[268] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_27_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_28_we = addr_hit[269] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_28_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_29_we = addr_hit[270] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_29_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_30_we = addr_hit[271] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_30_wd = reg_wdata[0]; + + assign mio_pad_sleep_regwen_31_we = addr_hit[272] & reg_we & ~wr_err; + assign mio_pad_sleep_regwen_31_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_0_we = addr_hit[273] & reg_we & ~wr_err; + assign mio_pad_sleep_en_0_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_1_we = addr_hit[274] & reg_we & ~wr_err; + assign mio_pad_sleep_en_1_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_2_we = addr_hit[275] & reg_we & ~wr_err; + assign mio_pad_sleep_en_2_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_3_we = addr_hit[276] & reg_we & ~wr_err; + assign mio_pad_sleep_en_3_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_4_we = addr_hit[277] & reg_we & ~wr_err; + assign mio_pad_sleep_en_4_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_5_we = addr_hit[278] & reg_we & ~wr_err; + assign mio_pad_sleep_en_5_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_6_we = addr_hit[279] & reg_we & ~wr_err; + assign mio_pad_sleep_en_6_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_7_we = addr_hit[280] & reg_we & ~wr_err; + assign mio_pad_sleep_en_7_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_8_we = addr_hit[281] & reg_we & ~wr_err; + assign mio_pad_sleep_en_8_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_9_we = addr_hit[282] & reg_we & ~wr_err; + assign mio_pad_sleep_en_9_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_10_we = addr_hit[283] & reg_we & ~wr_err; + assign mio_pad_sleep_en_10_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_11_we = addr_hit[284] & reg_we & ~wr_err; + assign mio_pad_sleep_en_11_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_12_we = addr_hit[285] & reg_we & ~wr_err; + assign mio_pad_sleep_en_12_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_13_we = addr_hit[286] & reg_we & ~wr_err; + assign mio_pad_sleep_en_13_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_14_we = addr_hit[287] & reg_we & ~wr_err; + assign mio_pad_sleep_en_14_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_15_we = addr_hit[288] & reg_we & ~wr_err; + assign mio_pad_sleep_en_15_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_16_we = addr_hit[289] & reg_we & ~wr_err; + assign mio_pad_sleep_en_16_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_17_we = addr_hit[290] & reg_we & ~wr_err; + assign mio_pad_sleep_en_17_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_18_we = addr_hit[291] & reg_we & ~wr_err; + assign mio_pad_sleep_en_18_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_19_we = addr_hit[292] & reg_we & ~wr_err; + assign mio_pad_sleep_en_19_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_20_we = addr_hit[293] & reg_we & ~wr_err; + assign mio_pad_sleep_en_20_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_21_we = addr_hit[294] & reg_we & ~wr_err; + assign mio_pad_sleep_en_21_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_22_we = addr_hit[295] & reg_we & ~wr_err; + assign mio_pad_sleep_en_22_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_23_we = addr_hit[296] & reg_we & ~wr_err; + assign mio_pad_sleep_en_23_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_24_we = addr_hit[297] & reg_we & ~wr_err; + assign mio_pad_sleep_en_24_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_25_we = addr_hit[298] & reg_we & ~wr_err; + assign mio_pad_sleep_en_25_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_26_we = addr_hit[299] & reg_we & ~wr_err; + assign mio_pad_sleep_en_26_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_27_we = addr_hit[300] & reg_we & ~wr_err; + assign mio_pad_sleep_en_27_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_28_we = addr_hit[301] & reg_we & ~wr_err; + assign mio_pad_sleep_en_28_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_29_we = addr_hit[302] & reg_we & ~wr_err; + assign mio_pad_sleep_en_29_wd = reg_wdata[0]; + + assign mio_pad_sleep_en_30_we = addr_hit[303] & reg_we & ~wr_err; + assign mio_pad_sleep_en_30_wd = reg_wdata[0]; - assign mio_out_sleep_regwen_1_we = addr_hit[147] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_1_wd = reg_wdata[0]; + assign mio_pad_sleep_en_31_we = addr_hit[304] & reg_we & ~wr_err; + assign mio_pad_sleep_en_31_wd = reg_wdata[0]; - assign mio_out_sleep_regwen_2_we = addr_hit[148] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_2_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_0_we = addr_hit[305] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_0_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_3_we = addr_hit[149] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_3_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_1_we = addr_hit[306] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_1_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_4_we = addr_hit[150] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_4_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_2_we = addr_hit[307] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_2_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_5_we = addr_hit[151] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_5_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_3_we = addr_hit[308] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_3_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_6_we = addr_hit[152] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_6_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_4_we = addr_hit[309] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_4_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_7_we = addr_hit[153] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_7_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_5_we = addr_hit[310] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_5_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_8_we = addr_hit[154] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_8_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_6_we = addr_hit[311] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_6_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_9_we = addr_hit[155] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_9_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_7_we = addr_hit[312] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_7_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_10_we = addr_hit[156] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_10_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_8_we = addr_hit[313] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_8_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_11_we = addr_hit[157] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_11_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_9_we = addr_hit[314] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_9_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_12_we = addr_hit[158] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_12_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_10_we = addr_hit[315] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_10_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_13_we = addr_hit[159] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_13_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_11_we = addr_hit[316] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_11_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_14_we = addr_hit[160] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_14_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_12_we = addr_hit[317] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_12_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_15_we = addr_hit[161] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_15_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_13_we = addr_hit[318] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_13_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_16_we = addr_hit[162] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_16_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_14_we = addr_hit[319] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_14_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_17_we = addr_hit[163] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_17_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_15_we = addr_hit[320] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_15_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_18_we = addr_hit[164] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_18_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_16_we = addr_hit[321] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_16_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_19_we = addr_hit[165] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_19_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_17_we = addr_hit[322] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_17_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_20_we = addr_hit[166] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_20_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_18_we = addr_hit[323] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_18_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_21_we = addr_hit[167] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_21_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_19_we = addr_hit[324] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_19_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_22_we = addr_hit[168] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_22_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_20_we = addr_hit[325] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_20_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_23_we = addr_hit[169] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_23_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_21_we = addr_hit[326] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_21_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_24_we = addr_hit[170] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_24_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_22_we = addr_hit[327] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_22_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_25_we = addr_hit[171] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_25_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_23_we = addr_hit[328] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_23_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_26_we = addr_hit[172] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_26_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_24_we = addr_hit[329] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_24_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_27_we = addr_hit[173] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_27_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_25_we = addr_hit[330] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_25_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_28_we = addr_hit[174] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_28_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_26_we = addr_hit[331] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_26_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_29_we = addr_hit[175] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_29_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_27_we = addr_hit[332] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_27_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_30_we = addr_hit[176] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_30_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_28_we = addr_hit[333] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_28_wd = reg_wdata[1:0]; - assign mio_out_sleep_regwen_31_we = addr_hit[177] & reg_we & ~wr_err; - assign mio_out_sleep_regwen_31_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_29_we = addr_hit[334] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_29_wd = reg_wdata[1:0]; - assign mio_out_sleep_val_0_we = addr_hit[178] & reg_we & ~wr_err; - assign mio_out_sleep_val_0_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_30_we = addr_hit[335] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_30_wd = reg_wdata[1:0]; - assign mio_out_sleep_val_1_we = addr_hit[179] & reg_we & ~wr_err; - assign mio_out_sleep_val_1_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_31_we = addr_hit[336] & reg_we & ~wr_err; + assign mio_pad_sleep_mode_31_wd = reg_wdata[1:0]; - assign mio_out_sleep_val_2_we = addr_hit[180] & reg_we & ~wr_err; - assign mio_out_sleep_val_2_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_0_we = addr_hit[337] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_0_wd = reg_wdata[0]; - assign mio_out_sleep_val_3_we = addr_hit[181] & reg_we & ~wr_err; - assign mio_out_sleep_val_3_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_1_we = addr_hit[337] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_1_wd = reg_wdata[1]; - assign mio_out_sleep_val_4_we = addr_hit[182] & reg_we & ~wr_err; - assign mio_out_sleep_val_4_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_2_we = addr_hit[337] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_2_wd = reg_wdata[2]; - assign mio_out_sleep_val_5_we = addr_hit[183] & reg_we & ~wr_err; - assign mio_out_sleep_val_5_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_3_we = addr_hit[337] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_3_wd = reg_wdata[3]; - assign mio_out_sleep_val_6_we = addr_hit[184] & reg_we & ~wr_err; - assign mio_out_sleep_val_6_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_4_we = addr_hit[337] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_4_wd = reg_wdata[4]; - assign mio_out_sleep_val_7_we = addr_hit[185] & reg_we & ~wr_err; - assign mio_out_sleep_val_7_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_5_we = addr_hit[337] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_5_wd = reg_wdata[5]; - assign mio_out_sleep_val_8_we = addr_hit[186] & reg_we & ~wr_err; - assign mio_out_sleep_val_8_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_6_we = addr_hit[337] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_6_wd = reg_wdata[6]; - assign mio_out_sleep_val_9_we = addr_hit[187] & reg_we & ~wr_err; - assign mio_out_sleep_val_9_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_7_we = addr_hit[337] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_7_wd = reg_wdata[7]; - assign mio_out_sleep_val_10_we = addr_hit[188] & reg_we & ~wr_err; - assign mio_out_sleep_val_10_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_8_we = addr_hit[337] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_8_wd = reg_wdata[8]; - assign mio_out_sleep_val_11_we = addr_hit[189] & reg_we & ~wr_err; - assign mio_out_sleep_val_11_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_9_we = addr_hit[337] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_9_wd = reg_wdata[9]; - assign mio_out_sleep_val_12_we = addr_hit[190] & reg_we & ~wr_err; - assign mio_out_sleep_val_12_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_10_we = addr_hit[337] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_10_wd = reg_wdata[10]; - assign mio_out_sleep_val_13_we = addr_hit[191] & reg_we & ~wr_err; - assign mio_out_sleep_val_13_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_11_we = addr_hit[337] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_11_wd = reg_wdata[11]; - assign mio_out_sleep_val_14_we = addr_hit[192] & reg_we & ~wr_err; - assign mio_out_sleep_val_14_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_12_we = addr_hit[337] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_12_wd = reg_wdata[12]; - assign mio_out_sleep_val_15_we = addr_hit[193] & reg_we & ~wr_err; - assign mio_out_sleep_val_15_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_13_we = addr_hit[337] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_13_wd = reg_wdata[13]; - assign mio_out_sleep_val_16_we = addr_hit[194] & reg_we & ~wr_err; - assign mio_out_sleep_val_16_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_en_14_we = addr_hit[337] & reg_we & ~wr_err; + assign dio_pad_sleep_status_en_14_wd = reg_wdata[14]; - assign mio_out_sleep_val_17_we = addr_hit[195] & reg_we & ~wr_err; - assign mio_out_sleep_val_17_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_0_we = addr_hit[338] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_0_wd = reg_wdata[0]; - assign mio_out_sleep_val_18_we = addr_hit[196] & reg_we & ~wr_err; - assign mio_out_sleep_val_18_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_1_we = addr_hit[339] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_1_wd = reg_wdata[0]; - assign mio_out_sleep_val_19_we = addr_hit[197] & reg_we & ~wr_err; - assign mio_out_sleep_val_19_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_2_we = addr_hit[340] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_2_wd = reg_wdata[0]; - assign mio_out_sleep_val_20_we = addr_hit[198] & reg_we & ~wr_err; - assign mio_out_sleep_val_20_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_3_we = addr_hit[341] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_3_wd = reg_wdata[0]; - assign mio_out_sleep_val_21_we = addr_hit[199] & reg_we & ~wr_err; - assign mio_out_sleep_val_21_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_4_we = addr_hit[342] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_4_wd = reg_wdata[0]; - assign mio_out_sleep_val_22_we = addr_hit[200] & reg_we & ~wr_err; - assign mio_out_sleep_val_22_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_5_we = addr_hit[343] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_5_wd = reg_wdata[0]; - assign mio_out_sleep_val_23_we = addr_hit[201] & reg_we & ~wr_err; - assign mio_out_sleep_val_23_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_6_we = addr_hit[344] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_6_wd = reg_wdata[0]; - assign mio_out_sleep_val_24_we = addr_hit[202] & reg_we & ~wr_err; - assign mio_out_sleep_val_24_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_7_we = addr_hit[345] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_7_wd = reg_wdata[0]; - assign mio_out_sleep_val_25_we = addr_hit[203] & reg_we & ~wr_err; - assign mio_out_sleep_val_25_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_8_we = addr_hit[346] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_8_wd = reg_wdata[0]; - assign mio_out_sleep_val_26_we = addr_hit[204] & reg_we & ~wr_err; - assign mio_out_sleep_val_26_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_9_we = addr_hit[347] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_9_wd = reg_wdata[0]; - assign mio_out_sleep_val_27_we = addr_hit[205] & reg_we & ~wr_err; - assign mio_out_sleep_val_27_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_10_we = addr_hit[348] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_10_wd = reg_wdata[0]; - assign mio_out_sleep_val_28_we = addr_hit[206] & reg_we & ~wr_err; - assign mio_out_sleep_val_28_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_11_we = addr_hit[349] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_11_wd = reg_wdata[0]; - assign mio_out_sleep_val_29_we = addr_hit[207] & reg_we & ~wr_err; - assign mio_out_sleep_val_29_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_12_we = addr_hit[350] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_12_wd = reg_wdata[0]; - assign mio_out_sleep_val_30_we = addr_hit[208] & reg_we & ~wr_err; - assign mio_out_sleep_val_30_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_13_we = addr_hit[351] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_13_wd = reg_wdata[0]; - assign mio_out_sleep_val_31_we = addr_hit[209] & reg_we & ~wr_err; - assign mio_out_sleep_val_31_wd = reg_wdata[1:0]; + assign dio_pad_sleep_regwen_14_we = addr_hit[352] & reg_we & ~wr_err; + assign dio_pad_sleep_regwen_14_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_0_we = addr_hit[210] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_0_wd = reg_wdata[0]; + assign dio_pad_sleep_en_0_we = addr_hit[353] & reg_we & ~wr_err; + assign dio_pad_sleep_en_0_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_1_we = addr_hit[211] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_1_wd = reg_wdata[0]; + assign dio_pad_sleep_en_1_we = addr_hit[354] & reg_we & ~wr_err; + assign dio_pad_sleep_en_1_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_2_we = addr_hit[212] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_2_wd = reg_wdata[0]; + assign dio_pad_sleep_en_2_we = addr_hit[355] & reg_we & ~wr_err; + assign dio_pad_sleep_en_2_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_3_we = addr_hit[213] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_3_wd = reg_wdata[0]; + assign dio_pad_sleep_en_3_we = addr_hit[356] & reg_we & ~wr_err; + assign dio_pad_sleep_en_3_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_4_we = addr_hit[214] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_4_wd = reg_wdata[0]; + assign dio_pad_sleep_en_4_we = addr_hit[357] & reg_we & ~wr_err; + assign dio_pad_sleep_en_4_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_5_we = addr_hit[215] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_5_wd = reg_wdata[0]; + assign dio_pad_sleep_en_5_we = addr_hit[358] & reg_we & ~wr_err; + assign dio_pad_sleep_en_5_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_6_we = addr_hit[216] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_6_wd = reg_wdata[0]; + assign dio_pad_sleep_en_6_we = addr_hit[359] & reg_we & ~wr_err; + assign dio_pad_sleep_en_6_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_7_we = addr_hit[217] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_7_wd = reg_wdata[0]; + assign dio_pad_sleep_en_7_we = addr_hit[360] & reg_we & ~wr_err; + assign dio_pad_sleep_en_7_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_8_we = addr_hit[218] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_8_wd = reg_wdata[0]; + assign dio_pad_sleep_en_8_we = addr_hit[361] & reg_we & ~wr_err; + assign dio_pad_sleep_en_8_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_9_we = addr_hit[219] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_9_wd = reg_wdata[0]; + assign dio_pad_sleep_en_9_we = addr_hit[362] & reg_we & ~wr_err; + assign dio_pad_sleep_en_9_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_10_we = addr_hit[220] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_10_wd = reg_wdata[0]; + assign dio_pad_sleep_en_10_we = addr_hit[363] & reg_we & ~wr_err; + assign dio_pad_sleep_en_10_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_11_we = addr_hit[221] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_11_wd = reg_wdata[0]; + assign dio_pad_sleep_en_11_we = addr_hit[364] & reg_we & ~wr_err; + assign dio_pad_sleep_en_11_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_12_we = addr_hit[222] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_12_wd = reg_wdata[0]; + assign dio_pad_sleep_en_12_we = addr_hit[365] & reg_we & ~wr_err; + assign dio_pad_sleep_en_12_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_13_we = addr_hit[223] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_13_wd = reg_wdata[0]; + assign dio_pad_sleep_en_13_we = addr_hit[366] & reg_we & ~wr_err; + assign dio_pad_sleep_en_13_wd = reg_wdata[0]; - assign dio_out_sleep_regwen_14_we = addr_hit[224] & reg_we & ~wr_err; - assign dio_out_sleep_regwen_14_wd = reg_wdata[0]; + assign dio_pad_sleep_en_14_we = addr_hit[367] & reg_we & ~wr_err; + assign dio_pad_sleep_en_14_wd = reg_wdata[0]; - assign dio_out_sleep_val_0_we = addr_hit[225] & reg_we & ~wr_err; - assign dio_out_sleep_val_0_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_0_re = addr_hit[225] && reg_re; + assign dio_pad_sleep_mode_0_we = addr_hit[368] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_0_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_1_we = addr_hit[226] & reg_we & ~wr_err; - assign dio_out_sleep_val_1_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_1_re = addr_hit[226] && reg_re; + assign dio_pad_sleep_mode_1_we = addr_hit[369] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_1_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_2_we = addr_hit[227] & reg_we & ~wr_err; - assign dio_out_sleep_val_2_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_2_re = addr_hit[227] && reg_re; + assign dio_pad_sleep_mode_2_we = addr_hit[370] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_2_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_3_we = addr_hit[228] & reg_we & ~wr_err; - assign dio_out_sleep_val_3_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_3_re = addr_hit[228] && reg_re; + assign dio_pad_sleep_mode_3_we = addr_hit[371] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_3_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_4_we = addr_hit[229] & reg_we & ~wr_err; - assign dio_out_sleep_val_4_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_4_re = addr_hit[229] && reg_re; + assign dio_pad_sleep_mode_4_we = addr_hit[372] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_4_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_5_we = addr_hit[230] & reg_we & ~wr_err; - assign dio_out_sleep_val_5_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_5_re = addr_hit[230] && reg_re; + assign dio_pad_sleep_mode_5_we = addr_hit[373] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_5_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_6_we = addr_hit[231] & reg_we & ~wr_err; - assign dio_out_sleep_val_6_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_6_re = addr_hit[231] && reg_re; + assign dio_pad_sleep_mode_6_we = addr_hit[374] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_6_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_7_we = addr_hit[232] & reg_we & ~wr_err; - assign dio_out_sleep_val_7_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_7_re = addr_hit[232] && reg_re; + assign dio_pad_sleep_mode_7_we = addr_hit[375] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_7_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_8_we = addr_hit[233] & reg_we & ~wr_err; - assign dio_out_sleep_val_8_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_8_re = addr_hit[233] && reg_re; + assign dio_pad_sleep_mode_8_we = addr_hit[376] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_8_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_9_we = addr_hit[234] & reg_we & ~wr_err; - assign dio_out_sleep_val_9_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_9_re = addr_hit[234] && reg_re; + assign dio_pad_sleep_mode_9_we = addr_hit[377] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_9_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_10_we = addr_hit[235] & reg_we & ~wr_err; - assign dio_out_sleep_val_10_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_10_re = addr_hit[235] && reg_re; + assign dio_pad_sleep_mode_10_we = addr_hit[378] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_10_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_11_we = addr_hit[236] & reg_we & ~wr_err; - assign dio_out_sleep_val_11_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_11_re = addr_hit[236] && reg_re; + assign dio_pad_sleep_mode_11_we = addr_hit[379] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_11_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_12_we = addr_hit[237] & reg_we & ~wr_err; - assign dio_out_sleep_val_12_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_12_re = addr_hit[237] && reg_re; + assign dio_pad_sleep_mode_12_we = addr_hit[380] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_12_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_13_we = addr_hit[238] & reg_we & ~wr_err; - assign dio_out_sleep_val_13_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_13_re = addr_hit[238] && reg_re; + assign dio_pad_sleep_mode_13_we = addr_hit[381] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_13_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_14_we = addr_hit[239] & reg_we & ~wr_err; - assign dio_out_sleep_val_14_wd = reg_wdata[1:0]; - assign dio_out_sleep_val_14_re = addr_hit[239] && reg_re; + assign dio_pad_sleep_mode_14_we = addr_hit[382] & reg_we & ~wr_err; + assign dio_pad_sleep_mode_14_wd = reg_wdata[1:0]; - assign wkup_detector_regwen_0_we = addr_hit[240] & reg_we & ~wr_err; + assign wkup_detector_regwen_0_we = addr_hit[383] & reg_we & ~wr_err; assign wkup_detector_regwen_0_wd = reg_wdata[0]; - assign wkup_detector_regwen_1_we = addr_hit[241] & reg_we & ~wr_err; + assign wkup_detector_regwen_1_we = addr_hit[384] & reg_we & ~wr_err; assign wkup_detector_regwen_1_wd = reg_wdata[0]; - assign wkup_detector_regwen_2_we = addr_hit[242] & reg_we & ~wr_err; + assign wkup_detector_regwen_2_we = addr_hit[385] & reg_we & ~wr_err; assign wkup_detector_regwen_2_wd = reg_wdata[0]; - assign wkup_detector_regwen_3_we = addr_hit[243] & reg_we & ~wr_err; + assign wkup_detector_regwen_3_we = addr_hit[386] & reg_we & ~wr_err; assign wkup_detector_regwen_3_wd = reg_wdata[0]; - assign wkup_detector_regwen_4_we = addr_hit[244] & reg_we & ~wr_err; + assign wkup_detector_regwen_4_we = addr_hit[387] & reg_we & ~wr_err; assign wkup_detector_regwen_4_wd = reg_wdata[0]; - assign wkup_detector_regwen_5_we = addr_hit[245] & reg_we & ~wr_err; + assign wkup_detector_regwen_5_we = addr_hit[388] & reg_we & ~wr_err; assign wkup_detector_regwen_5_wd = reg_wdata[0]; - assign wkup_detector_regwen_6_we = addr_hit[246] & reg_we & ~wr_err; + assign wkup_detector_regwen_6_we = addr_hit[389] & reg_we & ~wr_err; assign wkup_detector_regwen_6_wd = reg_wdata[0]; - assign wkup_detector_regwen_7_we = addr_hit[247] & reg_we & ~wr_err; + assign wkup_detector_regwen_7_we = addr_hit[390] & reg_we & ~wr_err; assign wkup_detector_regwen_7_wd = reg_wdata[0]; - assign wkup_detector_en_0_we = addr_hit[248] & reg_we & ~wr_err; + assign wkup_detector_en_0_we = addr_hit[391] & reg_we & ~wr_err; assign wkup_detector_en_0_wd = reg_wdata[0]; - assign wkup_detector_en_1_we = addr_hit[249] & reg_we & ~wr_err; + assign wkup_detector_en_1_we = addr_hit[392] & reg_we & ~wr_err; assign wkup_detector_en_1_wd = reg_wdata[0]; - assign wkup_detector_en_2_we = addr_hit[250] & reg_we & ~wr_err; + assign wkup_detector_en_2_we = addr_hit[393] & reg_we & ~wr_err; assign wkup_detector_en_2_wd = reg_wdata[0]; - assign wkup_detector_en_3_we = addr_hit[251] & reg_we & ~wr_err; + assign wkup_detector_en_3_we = addr_hit[394] & reg_we & ~wr_err; assign wkup_detector_en_3_wd = reg_wdata[0]; - assign wkup_detector_en_4_we = addr_hit[252] & reg_we & ~wr_err; + assign wkup_detector_en_4_we = addr_hit[395] & reg_we & ~wr_err; assign wkup_detector_en_4_wd = reg_wdata[0]; - assign wkup_detector_en_5_we = addr_hit[253] & reg_we & ~wr_err; + assign wkup_detector_en_5_we = addr_hit[396] & reg_we & ~wr_err; assign wkup_detector_en_5_wd = reg_wdata[0]; - assign wkup_detector_en_6_we = addr_hit[254] & reg_we & ~wr_err; + assign wkup_detector_en_6_we = addr_hit[397] & reg_we & ~wr_err; assign wkup_detector_en_6_wd = reg_wdata[0]; - assign wkup_detector_en_7_we = addr_hit[255] & reg_we & ~wr_err; + assign wkup_detector_en_7_we = addr_hit[398] & reg_we & ~wr_err; assign wkup_detector_en_7_wd = reg_wdata[0]; - assign wkup_detector_0_mode_0_we = addr_hit[256] & reg_we & ~wr_err; + assign wkup_detector_0_mode_0_we = addr_hit[399] & reg_we & ~wr_err; assign wkup_detector_0_mode_0_wd = reg_wdata[2:0]; - assign wkup_detector_0_filter_0_we = addr_hit[256] & reg_we & ~wr_err; + assign wkup_detector_0_filter_0_we = addr_hit[399] & reg_we & ~wr_err; assign wkup_detector_0_filter_0_wd = reg_wdata[3]; - assign wkup_detector_0_miodio_0_we = addr_hit[256] & reg_we & ~wr_err; + assign wkup_detector_0_miodio_0_we = addr_hit[399] & reg_we & ~wr_err; assign wkup_detector_0_miodio_0_wd = reg_wdata[4]; - assign wkup_detector_1_mode_1_we = addr_hit[257] & reg_we & ~wr_err; + assign wkup_detector_1_mode_1_we = addr_hit[400] & reg_we & ~wr_err; assign wkup_detector_1_mode_1_wd = reg_wdata[2:0]; - assign wkup_detector_1_filter_1_we = addr_hit[257] & reg_we & ~wr_err; + assign wkup_detector_1_filter_1_we = addr_hit[400] & reg_we & ~wr_err; assign wkup_detector_1_filter_1_wd = reg_wdata[3]; - assign wkup_detector_1_miodio_1_we = addr_hit[257] & reg_we & ~wr_err; + assign wkup_detector_1_miodio_1_we = addr_hit[400] & reg_we & ~wr_err; assign wkup_detector_1_miodio_1_wd = reg_wdata[4]; - assign wkup_detector_2_mode_2_we = addr_hit[258] & reg_we & ~wr_err; + assign wkup_detector_2_mode_2_we = addr_hit[401] & reg_we & ~wr_err; assign wkup_detector_2_mode_2_wd = reg_wdata[2:0]; - assign wkup_detector_2_filter_2_we = addr_hit[258] & reg_we & ~wr_err; + assign wkup_detector_2_filter_2_we = addr_hit[401] & reg_we & ~wr_err; assign wkup_detector_2_filter_2_wd = reg_wdata[3]; - assign wkup_detector_2_miodio_2_we = addr_hit[258] & reg_we & ~wr_err; + assign wkup_detector_2_miodio_2_we = addr_hit[401] & reg_we & ~wr_err; assign wkup_detector_2_miodio_2_wd = reg_wdata[4]; - assign wkup_detector_3_mode_3_we = addr_hit[259] & reg_we & ~wr_err; + assign wkup_detector_3_mode_3_we = addr_hit[402] & reg_we & ~wr_err; assign wkup_detector_3_mode_3_wd = reg_wdata[2:0]; - assign wkup_detector_3_filter_3_we = addr_hit[259] & reg_we & ~wr_err; + assign wkup_detector_3_filter_3_we = addr_hit[402] & reg_we & ~wr_err; assign wkup_detector_3_filter_3_wd = reg_wdata[3]; - assign wkup_detector_3_miodio_3_we = addr_hit[259] & reg_we & ~wr_err; + assign wkup_detector_3_miodio_3_we = addr_hit[402] & reg_we & ~wr_err; assign wkup_detector_3_miodio_3_wd = reg_wdata[4]; - assign wkup_detector_4_mode_4_we = addr_hit[260] & reg_we & ~wr_err; + assign wkup_detector_4_mode_4_we = addr_hit[403] & reg_we & ~wr_err; assign wkup_detector_4_mode_4_wd = reg_wdata[2:0]; - assign wkup_detector_4_filter_4_we = addr_hit[260] & reg_we & ~wr_err; + assign wkup_detector_4_filter_4_we = addr_hit[403] & reg_we & ~wr_err; assign wkup_detector_4_filter_4_wd = reg_wdata[3]; - assign wkup_detector_4_miodio_4_we = addr_hit[260] & reg_we & ~wr_err; + assign wkup_detector_4_miodio_4_we = addr_hit[403] & reg_we & ~wr_err; assign wkup_detector_4_miodio_4_wd = reg_wdata[4]; - assign wkup_detector_5_mode_5_we = addr_hit[261] & reg_we & ~wr_err; + assign wkup_detector_5_mode_5_we = addr_hit[404] & reg_we & ~wr_err; assign wkup_detector_5_mode_5_wd = reg_wdata[2:0]; - assign wkup_detector_5_filter_5_we = addr_hit[261] & reg_we & ~wr_err; + assign wkup_detector_5_filter_5_we = addr_hit[404] & reg_we & ~wr_err; assign wkup_detector_5_filter_5_wd = reg_wdata[3]; - assign wkup_detector_5_miodio_5_we = addr_hit[261] & reg_we & ~wr_err; + assign wkup_detector_5_miodio_5_we = addr_hit[404] & reg_we & ~wr_err; assign wkup_detector_5_miodio_5_wd = reg_wdata[4]; - assign wkup_detector_6_mode_6_we = addr_hit[262] & reg_we & ~wr_err; + assign wkup_detector_6_mode_6_we = addr_hit[405] & reg_we & ~wr_err; assign wkup_detector_6_mode_6_wd = reg_wdata[2:0]; - assign wkup_detector_6_filter_6_we = addr_hit[262] & reg_we & ~wr_err; + assign wkup_detector_6_filter_6_we = addr_hit[405] & reg_we & ~wr_err; assign wkup_detector_6_filter_6_wd = reg_wdata[3]; - assign wkup_detector_6_miodio_6_we = addr_hit[262] & reg_we & ~wr_err; + assign wkup_detector_6_miodio_6_we = addr_hit[405] & reg_we & ~wr_err; assign wkup_detector_6_miodio_6_wd = reg_wdata[4]; - assign wkup_detector_7_mode_7_we = addr_hit[263] & reg_we & ~wr_err; + assign wkup_detector_7_mode_7_we = addr_hit[406] & reg_we & ~wr_err; assign wkup_detector_7_mode_7_wd = reg_wdata[2:0]; - assign wkup_detector_7_filter_7_we = addr_hit[263] & reg_we & ~wr_err; + assign wkup_detector_7_filter_7_we = addr_hit[406] & reg_we & ~wr_err; assign wkup_detector_7_filter_7_wd = reg_wdata[3]; - assign wkup_detector_7_miodio_7_we = addr_hit[263] & reg_we & ~wr_err; + assign wkup_detector_7_miodio_7_we = addr_hit[406] & reg_we & ~wr_err; assign wkup_detector_7_miodio_7_wd = reg_wdata[4]; - assign wkup_detector_cnt_th_0_we = addr_hit[264] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_0_we = addr_hit[407] & reg_we & ~wr_err; assign wkup_detector_cnt_th_0_wd = reg_wdata[7:0]; - assign wkup_detector_cnt_th_1_we = addr_hit[265] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_1_we = addr_hit[408] & reg_we & ~wr_err; assign wkup_detector_cnt_th_1_wd = reg_wdata[7:0]; - assign wkup_detector_cnt_th_2_we = addr_hit[266] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_2_we = addr_hit[409] & reg_we & ~wr_err; assign wkup_detector_cnt_th_2_wd = reg_wdata[7:0]; - assign wkup_detector_cnt_th_3_we = addr_hit[267] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_3_we = addr_hit[410] & reg_we & ~wr_err; assign wkup_detector_cnt_th_3_wd = reg_wdata[7:0]; - assign wkup_detector_cnt_th_4_we = addr_hit[268] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_4_we = addr_hit[411] & reg_we & ~wr_err; assign wkup_detector_cnt_th_4_wd = reg_wdata[7:0]; - assign wkup_detector_cnt_th_5_we = addr_hit[269] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_5_we = addr_hit[412] & reg_we & ~wr_err; assign wkup_detector_cnt_th_5_wd = reg_wdata[7:0]; - assign wkup_detector_cnt_th_6_we = addr_hit[270] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_6_we = addr_hit[413] & reg_we & ~wr_err; assign wkup_detector_cnt_th_6_wd = reg_wdata[7:0]; - assign wkup_detector_cnt_th_7_we = addr_hit[271] & reg_we & ~wr_err; + assign wkup_detector_cnt_th_7_we = addr_hit[414] & reg_we & ~wr_err; assign wkup_detector_cnt_th_7_wd = reg_wdata[7:0]; - assign wkup_detector_padsel_0_we = addr_hit[272] & reg_we & ~wr_err; + assign wkup_detector_padsel_0_we = addr_hit[415] & reg_we & ~wr_err; assign wkup_detector_padsel_0_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_1_we = addr_hit[273] & reg_we & ~wr_err; + assign wkup_detector_padsel_1_we = addr_hit[416] & reg_we & ~wr_err; assign wkup_detector_padsel_1_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_2_we = addr_hit[274] & reg_we & ~wr_err; + assign wkup_detector_padsel_2_we = addr_hit[417] & reg_we & ~wr_err; assign wkup_detector_padsel_2_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_3_we = addr_hit[275] & reg_we & ~wr_err; + assign wkup_detector_padsel_3_we = addr_hit[418] & reg_we & ~wr_err; assign wkup_detector_padsel_3_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_4_we = addr_hit[276] & reg_we & ~wr_err; + assign wkup_detector_padsel_4_we = addr_hit[419] & reg_we & ~wr_err; assign wkup_detector_padsel_4_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_5_we = addr_hit[277] & reg_we & ~wr_err; + assign wkup_detector_padsel_5_we = addr_hit[420] & reg_we & ~wr_err; assign wkup_detector_padsel_5_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_6_we = addr_hit[278] & reg_we & ~wr_err; + assign wkup_detector_padsel_6_we = addr_hit[421] & reg_we & ~wr_err; assign wkup_detector_padsel_6_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_7_we = addr_hit[279] & reg_we & ~wr_err; + assign wkup_detector_padsel_7_we = addr_hit[422] & reg_we & ~wr_err; assign wkup_detector_padsel_7_wd = reg_wdata[5:0]; - assign wkup_cause_cause_0_we = addr_hit[280] & reg_we & ~wr_err; + assign wkup_cause_cause_0_we = addr_hit[423] & reg_we & ~wr_err; assign wkup_cause_cause_0_wd = reg_wdata[0]; - assign wkup_cause_cause_0_re = addr_hit[280] && reg_re; + assign wkup_cause_cause_0_re = addr_hit[423] && reg_re; - assign wkup_cause_cause_1_we = addr_hit[280] & reg_we & ~wr_err; + assign wkup_cause_cause_1_we = addr_hit[423] & reg_we & ~wr_err; assign wkup_cause_cause_1_wd = reg_wdata[1]; - assign wkup_cause_cause_1_re = addr_hit[280] && reg_re; + assign wkup_cause_cause_1_re = addr_hit[423] && reg_re; - assign wkup_cause_cause_2_we = addr_hit[280] & reg_we & ~wr_err; + assign wkup_cause_cause_2_we = addr_hit[423] & reg_we & ~wr_err; assign wkup_cause_cause_2_wd = reg_wdata[2]; - assign wkup_cause_cause_2_re = addr_hit[280] && reg_re; + assign wkup_cause_cause_2_re = addr_hit[423] && reg_re; - assign wkup_cause_cause_3_we = addr_hit[280] & reg_we & ~wr_err; + assign wkup_cause_cause_3_we = addr_hit[423] & reg_we & ~wr_err; assign wkup_cause_cause_3_wd = reg_wdata[3]; - assign wkup_cause_cause_3_re = addr_hit[280] && reg_re; + assign wkup_cause_cause_3_re = addr_hit[423] && reg_re; - assign wkup_cause_cause_4_we = addr_hit[280] & reg_we & ~wr_err; + assign wkup_cause_cause_4_we = addr_hit[423] & reg_we & ~wr_err; assign wkup_cause_cause_4_wd = reg_wdata[4]; - assign wkup_cause_cause_4_re = addr_hit[280] && reg_re; + assign wkup_cause_cause_4_re = addr_hit[423] && reg_re; - assign wkup_cause_cause_5_we = addr_hit[280] & reg_we & ~wr_err; + assign wkup_cause_cause_5_we = addr_hit[423] & reg_we & ~wr_err; assign wkup_cause_cause_5_wd = reg_wdata[5]; - assign wkup_cause_cause_5_re = addr_hit[280] && reg_re; + assign wkup_cause_cause_5_re = addr_hit[423] && reg_re; - assign wkup_cause_cause_6_we = addr_hit[280] & reg_we & ~wr_err; + assign wkup_cause_cause_6_we = addr_hit[423] & reg_we & ~wr_err; assign wkup_cause_cause_6_wd = reg_wdata[6]; - assign wkup_cause_cause_6_re = addr_hit[280] && reg_re; + assign wkup_cause_cause_6_re = addr_hit[423] && reg_re; - assign wkup_cause_cause_7_we = addr_hit[280] & reg_we & ~wr_err; + assign wkup_cause_cause_7_we = addr_hit[423] & reg_we & ~wr_err; assign wkup_cause_cause_7_wd = reg_wdata[7]; - assign wkup_cause_cause_7_re = addr_hit[280] && reg_re; + assign wkup_cause_cause_7_re = addr_hit[423] && reg_re; // Read data return always_comb begin @@ -11101,558 +17310,1175 @@ end addr_hit[146]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_0_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_0_qs; end addr_hit[147]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_1_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_1_qs; end addr_hit[148]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_2_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_2_qs; end addr_hit[149]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_3_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_3_qs; end addr_hit[150]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_4_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_4_qs; end addr_hit[151]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_5_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_5_qs; end addr_hit[152]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_6_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_6_qs; end addr_hit[153]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_7_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_7_qs; end addr_hit[154]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_8_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_8_qs; end addr_hit[155]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_9_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_9_qs; end addr_hit[156]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_10_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_10_qs; end addr_hit[157]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_11_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_11_qs; end addr_hit[158]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_12_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_12_qs; end addr_hit[159]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_13_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_13_qs; end addr_hit[160]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_14_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_14_qs; end addr_hit[161]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_15_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_15_qs; end addr_hit[162]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_16_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_16_qs; end addr_hit[163]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_17_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_17_qs; end addr_hit[164]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_18_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_18_qs; end addr_hit[165]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_19_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_19_qs; end addr_hit[166]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_20_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_20_qs; end addr_hit[167]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_21_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_21_qs; end addr_hit[168]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_22_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_22_qs; end addr_hit[169]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_23_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_23_qs; end addr_hit[170]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_24_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_24_qs; end addr_hit[171]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_25_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_25_qs; end addr_hit[172]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_26_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_26_qs; end addr_hit[173]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_27_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_27_qs; end addr_hit[174]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_28_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_28_qs; end addr_hit[175]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_29_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_29_qs; end addr_hit[176]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_30_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_30_qs; end addr_hit[177]: begin - reg_rdata_next[0] = mio_out_sleep_regwen_31_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_31_qs; end addr_hit[178]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_0_qs; + reg_rdata_next[9:0] = mio_pad_attr_0_qs; end addr_hit[179]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_1_qs; + reg_rdata_next[9:0] = mio_pad_attr_1_qs; end addr_hit[180]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_2_qs; + reg_rdata_next[9:0] = mio_pad_attr_2_qs; end addr_hit[181]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_3_qs; + reg_rdata_next[9:0] = mio_pad_attr_3_qs; end addr_hit[182]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_4_qs; + reg_rdata_next[9:0] = mio_pad_attr_4_qs; end addr_hit[183]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_5_qs; + reg_rdata_next[9:0] = mio_pad_attr_5_qs; end addr_hit[184]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_6_qs; + reg_rdata_next[9:0] = mio_pad_attr_6_qs; end addr_hit[185]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_7_qs; + reg_rdata_next[9:0] = mio_pad_attr_7_qs; end addr_hit[186]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_8_qs; + reg_rdata_next[9:0] = mio_pad_attr_8_qs; end addr_hit[187]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_9_qs; + reg_rdata_next[9:0] = mio_pad_attr_9_qs; end addr_hit[188]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_10_qs; + reg_rdata_next[9:0] = mio_pad_attr_10_qs; end addr_hit[189]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_11_qs; + reg_rdata_next[9:0] = mio_pad_attr_11_qs; end addr_hit[190]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_12_qs; + reg_rdata_next[9:0] = mio_pad_attr_12_qs; end addr_hit[191]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_13_qs; + reg_rdata_next[9:0] = mio_pad_attr_13_qs; end addr_hit[192]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_14_qs; + reg_rdata_next[9:0] = mio_pad_attr_14_qs; end addr_hit[193]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_15_qs; + reg_rdata_next[9:0] = mio_pad_attr_15_qs; end addr_hit[194]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_16_qs; + reg_rdata_next[9:0] = mio_pad_attr_16_qs; end addr_hit[195]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_17_qs; + reg_rdata_next[9:0] = mio_pad_attr_17_qs; end addr_hit[196]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_18_qs; + reg_rdata_next[9:0] = mio_pad_attr_18_qs; end addr_hit[197]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_19_qs; + reg_rdata_next[9:0] = mio_pad_attr_19_qs; end addr_hit[198]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_20_qs; + reg_rdata_next[9:0] = mio_pad_attr_20_qs; end addr_hit[199]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_21_qs; + reg_rdata_next[9:0] = mio_pad_attr_21_qs; end addr_hit[200]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_22_qs; + reg_rdata_next[9:0] = mio_pad_attr_22_qs; end addr_hit[201]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_23_qs; + reg_rdata_next[9:0] = mio_pad_attr_23_qs; end addr_hit[202]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_24_qs; + reg_rdata_next[9:0] = mio_pad_attr_24_qs; end addr_hit[203]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_25_qs; + reg_rdata_next[9:0] = mio_pad_attr_25_qs; end addr_hit[204]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_26_qs; + reg_rdata_next[9:0] = mio_pad_attr_26_qs; end addr_hit[205]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_27_qs; + reg_rdata_next[9:0] = mio_pad_attr_27_qs; end addr_hit[206]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_28_qs; + reg_rdata_next[9:0] = mio_pad_attr_28_qs; end addr_hit[207]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_29_qs; + reg_rdata_next[9:0] = mio_pad_attr_29_qs; end addr_hit[208]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_30_qs; + reg_rdata_next[9:0] = mio_pad_attr_30_qs; end addr_hit[209]: begin - reg_rdata_next[1:0] = mio_out_sleep_val_31_qs; + reg_rdata_next[9:0] = mio_pad_attr_31_qs; end addr_hit[210]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_0_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_0_qs; end addr_hit[211]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_1_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_1_qs; end addr_hit[212]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_2_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_2_qs; end addr_hit[213]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_3_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_3_qs; end addr_hit[214]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_4_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_4_qs; end addr_hit[215]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_5_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_5_qs; end addr_hit[216]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_6_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_6_qs; end addr_hit[217]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_7_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_7_qs; end addr_hit[218]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_8_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_8_qs; end addr_hit[219]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_9_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_9_qs; end addr_hit[220]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_10_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_10_qs; end addr_hit[221]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_11_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_11_qs; end addr_hit[222]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_12_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_12_qs; end addr_hit[223]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_13_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_13_qs; end addr_hit[224]: begin - reg_rdata_next[0] = dio_out_sleep_regwen_14_qs; + reg_rdata_next[0] = dio_pad_attr_regwen_14_qs; end addr_hit[225]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_0_qs; + reg_rdata_next[9:0] = dio_pad_attr_0_qs; end addr_hit[226]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_1_qs; + reg_rdata_next[9:0] = dio_pad_attr_1_qs; end addr_hit[227]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_2_qs; + reg_rdata_next[9:0] = dio_pad_attr_2_qs; end addr_hit[228]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_3_qs; + reg_rdata_next[9:0] = dio_pad_attr_3_qs; end addr_hit[229]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_4_qs; + reg_rdata_next[9:0] = dio_pad_attr_4_qs; end addr_hit[230]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_5_qs; + reg_rdata_next[9:0] = dio_pad_attr_5_qs; end addr_hit[231]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_6_qs; + reg_rdata_next[9:0] = dio_pad_attr_6_qs; end addr_hit[232]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_7_qs; + reg_rdata_next[9:0] = dio_pad_attr_7_qs; end addr_hit[233]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_8_qs; + reg_rdata_next[9:0] = dio_pad_attr_8_qs; end addr_hit[234]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_9_qs; + reg_rdata_next[9:0] = dio_pad_attr_9_qs; end addr_hit[235]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_10_qs; + reg_rdata_next[9:0] = dio_pad_attr_10_qs; end addr_hit[236]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_11_qs; + reg_rdata_next[9:0] = dio_pad_attr_11_qs; end addr_hit[237]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_12_qs; + reg_rdata_next[9:0] = dio_pad_attr_12_qs; end addr_hit[238]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_13_qs; + reg_rdata_next[9:0] = dio_pad_attr_13_qs; end addr_hit[239]: begin - reg_rdata_next[1:0] = dio_out_sleep_val_14_qs; + reg_rdata_next[9:0] = dio_pad_attr_14_qs; end addr_hit[240]: begin - reg_rdata_next[0] = wkup_detector_regwen_0_qs; + reg_rdata_next[0] = mio_pad_sleep_status_en_0_qs; + reg_rdata_next[1] = mio_pad_sleep_status_en_1_qs; + reg_rdata_next[2] = mio_pad_sleep_status_en_2_qs; + reg_rdata_next[3] = mio_pad_sleep_status_en_3_qs; + reg_rdata_next[4] = mio_pad_sleep_status_en_4_qs; + reg_rdata_next[5] = mio_pad_sleep_status_en_5_qs; + reg_rdata_next[6] = mio_pad_sleep_status_en_6_qs; + reg_rdata_next[7] = mio_pad_sleep_status_en_7_qs; + reg_rdata_next[8] = mio_pad_sleep_status_en_8_qs; + reg_rdata_next[9] = mio_pad_sleep_status_en_9_qs; + reg_rdata_next[10] = mio_pad_sleep_status_en_10_qs; + reg_rdata_next[11] = mio_pad_sleep_status_en_11_qs; + reg_rdata_next[12] = mio_pad_sleep_status_en_12_qs; + reg_rdata_next[13] = mio_pad_sleep_status_en_13_qs; + reg_rdata_next[14] = mio_pad_sleep_status_en_14_qs; + reg_rdata_next[15] = mio_pad_sleep_status_en_15_qs; + reg_rdata_next[16] = mio_pad_sleep_status_en_16_qs; + reg_rdata_next[17] = mio_pad_sleep_status_en_17_qs; + reg_rdata_next[18] = mio_pad_sleep_status_en_18_qs; + reg_rdata_next[19] = mio_pad_sleep_status_en_19_qs; + reg_rdata_next[20] = mio_pad_sleep_status_en_20_qs; + reg_rdata_next[21] = mio_pad_sleep_status_en_21_qs; + reg_rdata_next[22] = mio_pad_sleep_status_en_22_qs; + reg_rdata_next[23] = mio_pad_sleep_status_en_23_qs; + reg_rdata_next[24] = mio_pad_sleep_status_en_24_qs; + reg_rdata_next[25] = mio_pad_sleep_status_en_25_qs; + reg_rdata_next[26] = mio_pad_sleep_status_en_26_qs; + reg_rdata_next[27] = mio_pad_sleep_status_en_27_qs; + reg_rdata_next[28] = mio_pad_sleep_status_en_28_qs; + reg_rdata_next[29] = mio_pad_sleep_status_en_29_qs; + reg_rdata_next[30] = mio_pad_sleep_status_en_30_qs; + reg_rdata_next[31] = mio_pad_sleep_status_en_31_qs; end addr_hit[241]: begin - reg_rdata_next[0] = wkup_detector_regwen_1_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_0_qs; end addr_hit[242]: begin - reg_rdata_next[0] = wkup_detector_regwen_2_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_1_qs; end addr_hit[243]: begin - reg_rdata_next[0] = wkup_detector_regwen_3_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_2_qs; end addr_hit[244]: begin - reg_rdata_next[0] = wkup_detector_regwen_4_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_3_qs; end addr_hit[245]: begin - reg_rdata_next[0] = wkup_detector_regwen_5_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_4_qs; end addr_hit[246]: begin - reg_rdata_next[0] = wkup_detector_regwen_6_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_5_qs; end addr_hit[247]: begin - reg_rdata_next[0] = wkup_detector_regwen_7_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_6_qs; end addr_hit[248]: begin - reg_rdata_next[0] = wkup_detector_en_0_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_7_qs; end addr_hit[249]: begin - reg_rdata_next[0] = wkup_detector_en_1_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_8_qs; end addr_hit[250]: begin - reg_rdata_next[0] = wkup_detector_en_2_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_9_qs; end addr_hit[251]: begin - reg_rdata_next[0] = wkup_detector_en_3_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_10_qs; end addr_hit[252]: begin - reg_rdata_next[0] = wkup_detector_en_4_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_11_qs; end addr_hit[253]: begin - reg_rdata_next[0] = wkup_detector_en_5_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_12_qs; end addr_hit[254]: begin - reg_rdata_next[0] = wkup_detector_en_6_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_13_qs; end addr_hit[255]: begin - reg_rdata_next[0] = wkup_detector_en_7_qs; + reg_rdata_next[0] = mio_pad_sleep_regwen_14_qs; end addr_hit[256]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_15_qs; + end + + addr_hit[257]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_16_qs; + end + + addr_hit[258]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_17_qs; + end + + addr_hit[259]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_18_qs; + end + + addr_hit[260]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_19_qs; + end + + addr_hit[261]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_20_qs; + end + + addr_hit[262]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_21_qs; + end + + addr_hit[263]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_22_qs; + end + + addr_hit[264]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_23_qs; + end + + addr_hit[265]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_24_qs; + end + + addr_hit[266]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_25_qs; + end + + addr_hit[267]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_26_qs; + end + + addr_hit[268]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_27_qs; + end + + addr_hit[269]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_28_qs; + end + + addr_hit[270]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_29_qs; + end + + addr_hit[271]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_30_qs; + end + + addr_hit[272]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_31_qs; + end + + addr_hit[273]: begin + reg_rdata_next[0] = mio_pad_sleep_en_0_qs; + end + + addr_hit[274]: begin + reg_rdata_next[0] = mio_pad_sleep_en_1_qs; + end + + addr_hit[275]: begin + reg_rdata_next[0] = mio_pad_sleep_en_2_qs; + end + + addr_hit[276]: begin + reg_rdata_next[0] = mio_pad_sleep_en_3_qs; + end + + addr_hit[277]: begin + reg_rdata_next[0] = mio_pad_sleep_en_4_qs; + end + + addr_hit[278]: begin + reg_rdata_next[0] = mio_pad_sleep_en_5_qs; + end + + addr_hit[279]: begin + reg_rdata_next[0] = mio_pad_sleep_en_6_qs; + end + + addr_hit[280]: begin + reg_rdata_next[0] = mio_pad_sleep_en_7_qs; + end + + addr_hit[281]: begin + reg_rdata_next[0] = mio_pad_sleep_en_8_qs; + end + + addr_hit[282]: begin + reg_rdata_next[0] = mio_pad_sleep_en_9_qs; + end + + addr_hit[283]: begin + reg_rdata_next[0] = mio_pad_sleep_en_10_qs; + end + + addr_hit[284]: begin + reg_rdata_next[0] = mio_pad_sleep_en_11_qs; + end + + addr_hit[285]: begin + reg_rdata_next[0] = mio_pad_sleep_en_12_qs; + end + + addr_hit[286]: begin + reg_rdata_next[0] = mio_pad_sleep_en_13_qs; + end + + addr_hit[287]: begin + reg_rdata_next[0] = mio_pad_sleep_en_14_qs; + end + + addr_hit[288]: begin + reg_rdata_next[0] = mio_pad_sleep_en_15_qs; + end + + addr_hit[289]: begin + reg_rdata_next[0] = mio_pad_sleep_en_16_qs; + end + + addr_hit[290]: begin + reg_rdata_next[0] = mio_pad_sleep_en_17_qs; + end + + addr_hit[291]: begin + reg_rdata_next[0] = mio_pad_sleep_en_18_qs; + end + + addr_hit[292]: begin + reg_rdata_next[0] = mio_pad_sleep_en_19_qs; + end + + addr_hit[293]: begin + reg_rdata_next[0] = mio_pad_sleep_en_20_qs; + end + + addr_hit[294]: begin + reg_rdata_next[0] = mio_pad_sleep_en_21_qs; + end + + addr_hit[295]: begin + reg_rdata_next[0] = mio_pad_sleep_en_22_qs; + end + + addr_hit[296]: begin + reg_rdata_next[0] = mio_pad_sleep_en_23_qs; + end + + addr_hit[297]: begin + reg_rdata_next[0] = mio_pad_sleep_en_24_qs; + end + + addr_hit[298]: begin + reg_rdata_next[0] = mio_pad_sleep_en_25_qs; + end + + addr_hit[299]: begin + reg_rdata_next[0] = mio_pad_sleep_en_26_qs; + end + + addr_hit[300]: begin + reg_rdata_next[0] = mio_pad_sleep_en_27_qs; + end + + addr_hit[301]: begin + reg_rdata_next[0] = mio_pad_sleep_en_28_qs; + end + + addr_hit[302]: begin + reg_rdata_next[0] = mio_pad_sleep_en_29_qs; + end + + addr_hit[303]: begin + reg_rdata_next[0] = mio_pad_sleep_en_30_qs; + end + + addr_hit[304]: begin + reg_rdata_next[0] = mio_pad_sleep_en_31_qs; + end + + addr_hit[305]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_0_qs; + end + + addr_hit[306]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_1_qs; + end + + addr_hit[307]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_2_qs; + end + + addr_hit[308]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_3_qs; + end + + addr_hit[309]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_4_qs; + end + + addr_hit[310]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_5_qs; + end + + addr_hit[311]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_6_qs; + end + + addr_hit[312]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_7_qs; + end + + addr_hit[313]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_8_qs; + end + + addr_hit[314]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_9_qs; + end + + addr_hit[315]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_10_qs; + end + + addr_hit[316]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_11_qs; + end + + addr_hit[317]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_12_qs; + end + + addr_hit[318]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_13_qs; + end + + addr_hit[319]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_14_qs; + end + + addr_hit[320]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_15_qs; + end + + addr_hit[321]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_16_qs; + end + + addr_hit[322]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_17_qs; + end + + addr_hit[323]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_18_qs; + end + + addr_hit[324]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_19_qs; + end + + addr_hit[325]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_20_qs; + end + + addr_hit[326]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_21_qs; + end + + addr_hit[327]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_22_qs; + end + + addr_hit[328]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_23_qs; + end + + addr_hit[329]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_24_qs; + end + + addr_hit[330]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_25_qs; + end + + addr_hit[331]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_26_qs; + end + + addr_hit[332]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_27_qs; + end + + addr_hit[333]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_28_qs; + end + + addr_hit[334]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_29_qs; + end + + addr_hit[335]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_30_qs; + end + + addr_hit[336]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_31_qs; + end + + addr_hit[337]: begin + reg_rdata_next[0] = dio_pad_sleep_status_en_0_qs; + reg_rdata_next[1] = dio_pad_sleep_status_en_1_qs; + reg_rdata_next[2] = dio_pad_sleep_status_en_2_qs; + reg_rdata_next[3] = dio_pad_sleep_status_en_3_qs; + reg_rdata_next[4] = dio_pad_sleep_status_en_4_qs; + reg_rdata_next[5] = dio_pad_sleep_status_en_5_qs; + reg_rdata_next[6] = dio_pad_sleep_status_en_6_qs; + reg_rdata_next[7] = dio_pad_sleep_status_en_7_qs; + reg_rdata_next[8] = dio_pad_sleep_status_en_8_qs; + reg_rdata_next[9] = dio_pad_sleep_status_en_9_qs; + reg_rdata_next[10] = dio_pad_sleep_status_en_10_qs; + reg_rdata_next[11] = dio_pad_sleep_status_en_11_qs; + reg_rdata_next[12] = dio_pad_sleep_status_en_12_qs; + reg_rdata_next[13] = dio_pad_sleep_status_en_13_qs; + reg_rdata_next[14] = dio_pad_sleep_status_en_14_qs; + end + + addr_hit[338]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_0_qs; + end + + addr_hit[339]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_1_qs; + end + + addr_hit[340]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_2_qs; + end + + addr_hit[341]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_3_qs; + end + + addr_hit[342]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_4_qs; + end + + addr_hit[343]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_5_qs; + end + + addr_hit[344]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_6_qs; + end + + addr_hit[345]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_7_qs; + end + + addr_hit[346]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_8_qs; + end + + addr_hit[347]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_9_qs; + end + + addr_hit[348]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_10_qs; + end + + addr_hit[349]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_11_qs; + end + + addr_hit[350]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_12_qs; + end + + addr_hit[351]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_13_qs; + end + + addr_hit[352]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_14_qs; + end + + addr_hit[353]: begin + reg_rdata_next[0] = dio_pad_sleep_en_0_qs; + end + + addr_hit[354]: begin + reg_rdata_next[0] = dio_pad_sleep_en_1_qs; + end + + addr_hit[355]: begin + reg_rdata_next[0] = dio_pad_sleep_en_2_qs; + end + + addr_hit[356]: begin + reg_rdata_next[0] = dio_pad_sleep_en_3_qs; + end + + addr_hit[357]: begin + reg_rdata_next[0] = dio_pad_sleep_en_4_qs; + end + + addr_hit[358]: begin + reg_rdata_next[0] = dio_pad_sleep_en_5_qs; + end + + addr_hit[359]: begin + reg_rdata_next[0] = dio_pad_sleep_en_6_qs; + end + + addr_hit[360]: begin + reg_rdata_next[0] = dio_pad_sleep_en_7_qs; + end + + addr_hit[361]: begin + reg_rdata_next[0] = dio_pad_sleep_en_8_qs; + end + + addr_hit[362]: begin + reg_rdata_next[0] = dio_pad_sleep_en_9_qs; + end + + addr_hit[363]: begin + reg_rdata_next[0] = dio_pad_sleep_en_10_qs; + end + + addr_hit[364]: begin + reg_rdata_next[0] = dio_pad_sleep_en_11_qs; + end + + addr_hit[365]: begin + reg_rdata_next[0] = dio_pad_sleep_en_12_qs; + end + + addr_hit[366]: begin + reg_rdata_next[0] = dio_pad_sleep_en_13_qs; + end + + addr_hit[367]: begin + reg_rdata_next[0] = dio_pad_sleep_en_14_qs; + end + + addr_hit[368]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_0_qs; + end + + addr_hit[369]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_1_qs; + end + + addr_hit[370]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_2_qs; + end + + addr_hit[371]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_3_qs; + end + + addr_hit[372]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_4_qs; + end + + addr_hit[373]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_5_qs; + end + + addr_hit[374]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_6_qs; + end + + addr_hit[375]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_7_qs; + end + + addr_hit[376]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_8_qs; + end + + addr_hit[377]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_9_qs; + end + + addr_hit[378]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_10_qs; + end + + addr_hit[379]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_11_qs; + end + + addr_hit[380]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_12_qs; + end + + addr_hit[381]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_13_qs; + end + + addr_hit[382]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_14_qs; + end + + addr_hit[383]: begin + reg_rdata_next[0] = wkup_detector_regwen_0_qs; + end + + addr_hit[384]: begin + reg_rdata_next[0] = wkup_detector_regwen_1_qs; + end + + addr_hit[385]: begin + reg_rdata_next[0] = wkup_detector_regwen_2_qs; + end + + addr_hit[386]: begin + reg_rdata_next[0] = wkup_detector_regwen_3_qs; + end + + addr_hit[387]: begin + reg_rdata_next[0] = wkup_detector_regwen_4_qs; + end + + addr_hit[388]: begin + reg_rdata_next[0] = wkup_detector_regwen_5_qs; + end + + addr_hit[389]: begin + reg_rdata_next[0] = wkup_detector_regwen_6_qs; + end + + addr_hit[390]: begin + reg_rdata_next[0] = wkup_detector_regwen_7_qs; + end + + addr_hit[391]: begin + reg_rdata_next[0] = wkup_detector_en_0_qs; + end + + addr_hit[392]: begin + reg_rdata_next[0] = wkup_detector_en_1_qs; + end + + addr_hit[393]: begin + reg_rdata_next[0] = wkup_detector_en_2_qs; + end + + addr_hit[394]: begin + reg_rdata_next[0] = wkup_detector_en_3_qs; + end + + addr_hit[395]: begin + reg_rdata_next[0] = wkup_detector_en_4_qs; + end + + addr_hit[396]: begin + reg_rdata_next[0] = wkup_detector_en_5_qs; + end + + addr_hit[397]: begin + reg_rdata_next[0] = wkup_detector_en_6_qs; + end + + addr_hit[398]: begin + reg_rdata_next[0] = wkup_detector_en_7_qs; + end + + addr_hit[399]: begin reg_rdata_next[2:0] = wkup_detector_0_mode_0_qs; reg_rdata_next[3] = wkup_detector_0_filter_0_qs; reg_rdata_next[4] = wkup_detector_0_miodio_0_qs; end - addr_hit[257]: begin + addr_hit[400]: begin reg_rdata_next[2:0] = wkup_detector_1_mode_1_qs; reg_rdata_next[3] = wkup_detector_1_filter_1_qs; reg_rdata_next[4] = wkup_detector_1_miodio_1_qs; end - addr_hit[258]: begin + addr_hit[401]: begin reg_rdata_next[2:0] = wkup_detector_2_mode_2_qs; reg_rdata_next[3] = wkup_detector_2_filter_2_qs; reg_rdata_next[4] = wkup_detector_2_miodio_2_qs; end - addr_hit[259]: begin + addr_hit[402]: begin reg_rdata_next[2:0] = wkup_detector_3_mode_3_qs; reg_rdata_next[3] = wkup_detector_3_filter_3_qs; reg_rdata_next[4] = wkup_detector_3_miodio_3_qs; end - addr_hit[260]: begin + addr_hit[403]: begin reg_rdata_next[2:0] = wkup_detector_4_mode_4_qs; reg_rdata_next[3] = wkup_detector_4_filter_4_qs; reg_rdata_next[4] = wkup_detector_4_miodio_4_qs; end - addr_hit[261]: begin + addr_hit[404]: begin reg_rdata_next[2:0] = wkup_detector_5_mode_5_qs; reg_rdata_next[3] = wkup_detector_5_filter_5_qs; reg_rdata_next[4] = wkup_detector_5_miodio_5_qs; end - addr_hit[262]: begin + addr_hit[405]: begin reg_rdata_next[2:0] = wkup_detector_6_mode_6_qs; reg_rdata_next[3] = wkup_detector_6_filter_6_qs; reg_rdata_next[4] = wkup_detector_6_miodio_6_qs; end - addr_hit[263]: begin + addr_hit[406]: begin reg_rdata_next[2:0] = wkup_detector_7_mode_7_qs; reg_rdata_next[3] = wkup_detector_7_filter_7_qs; reg_rdata_next[4] = wkup_detector_7_miodio_7_qs; end - addr_hit[264]: begin + addr_hit[407]: begin reg_rdata_next[7:0] = wkup_detector_cnt_th_0_qs; end - addr_hit[265]: begin + addr_hit[408]: begin reg_rdata_next[7:0] = wkup_detector_cnt_th_1_qs; end - addr_hit[266]: begin + addr_hit[409]: begin reg_rdata_next[7:0] = wkup_detector_cnt_th_2_qs; end - addr_hit[267]: begin + addr_hit[410]: begin reg_rdata_next[7:0] = wkup_detector_cnt_th_3_qs; end - addr_hit[268]: begin + addr_hit[411]: begin reg_rdata_next[7:0] = wkup_detector_cnt_th_4_qs; end - addr_hit[269]: begin + addr_hit[412]: begin reg_rdata_next[7:0] = wkup_detector_cnt_th_5_qs; end - addr_hit[270]: begin + addr_hit[413]: begin reg_rdata_next[7:0] = wkup_detector_cnt_th_6_qs; end - addr_hit[271]: begin + addr_hit[414]: begin reg_rdata_next[7:0] = wkup_detector_cnt_th_7_qs; end - addr_hit[272]: begin + addr_hit[415]: begin reg_rdata_next[5:0] = wkup_detector_padsel_0_qs; end - addr_hit[273]: begin + addr_hit[416]: begin reg_rdata_next[5:0] = wkup_detector_padsel_1_qs; end - addr_hit[274]: begin + addr_hit[417]: begin reg_rdata_next[5:0] = wkup_detector_padsel_2_qs; end - addr_hit[275]: begin + addr_hit[418]: begin reg_rdata_next[5:0] = wkup_detector_padsel_3_qs; end - addr_hit[276]: begin + addr_hit[419]: begin reg_rdata_next[5:0] = wkup_detector_padsel_4_qs; end - addr_hit[277]: begin + addr_hit[420]: begin reg_rdata_next[5:0] = wkup_detector_padsel_5_qs; end - addr_hit[278]: begin + addr_hit[421]: begin reg_rdata_next[5:0] = wkup_detector_padsel_6_qs; end - addr_hit[279]: begin + addr_hit[422]: begin reg_rdata_next[5:0] = wkup_detector_padsel_7_qs; end - addr_hit[280]: begin + addr_hit[423]: begin reg_rdata_next[0] = wkup_cause_cause_0_qs; reg_rdata_next[1] = wkup_cause_cause_1_qs; reg_rdata_next[2] = wkup_cause_cause_2_qs;
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson index 880c366..2345834 100644 --- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson +++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
@@ -43,7 +43,6 @@ rstmgr_aon clkmgr_aon pinmux_aon - padctrl_aon ram_ret_aon otp_ctrl lc_ctrl @@ -356,24 +355,6 @@ pipeline_byp: "true" } { - name: padctrl_aon - type: device - clock: clk_peri_i - reset: rst_peri_ni - pipeline: "false" - inst_type: padctrl - addr_range: - [ - { - base_addr: 0x40470000 - size_byte: 0x1000 - } - ] - xbar: false - stub: false - pipeline_byp: "true" - } - { name: ram_ret_aon type: device clock: clk_peri_i
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson index 56369d3..8cd2158 100644 --- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson +++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
@@ -117,12 +117,6 @@ } { struct: "tl" type: "req_rsp" - name: "tl_padctrl_aon" - act: "req" - package: "tlul_pkg" - } - { struct: "tl" - type: "req_rsp" name: "tl_ram_ret_aon" act: "req" package: "tlul_pkg"
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv index 90bf821..8006d4d 100644 --- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
@@ -33,7 +33,6 @@ `CONNECT_TL_DEVICE_IF(rstmgr_aon, dut, clk_peri_i, rst_n) `CONNECT_TL_DEVICE_IF(clkmgr_aon, dut, clk_peri_i, rst_n) `CONNECT_TL_DEVICE_IF(pinmux_aon, dut, clk_peri_i, rst_n) -`CONNECT_TL_DEVICE_IF(padctrl_aon, dut, clk_peri_i, rst_n) `CONNECT_TL_DEVICE_IF(ram_ret_aon, dut, clk_peri_i, rst_n) `CONNECT_TL_DEVICE_IF(otp_ctrl, dut, clk_peri_i, rst_n) `CONNECT_TL_DEVICE_IF(lc_ctrl, dut, clk_peri_i, rst_n)
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg index b46d035..6265a2c 100644 --- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg +++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg
@@ -70,10 +70,6 @@ -node tb.dut tl_pinmux_aon_o.a_address[21:19] -node tb.dut tl_pinmux_aon_o.a_address[29:23] -node tb.dut tl_pinmux_aon_o.a_address[31:31] --node tb.dut tl_padctrl_aon_o.a_address[15:12] --node tb.dut tl_padctrl_aon_o.a_address[21:19] --node tb.dut tl_padctrl_aon_o.a_address[29:23] --node tb.dut tl_padctrl_aon_o.a_address[31:31] -node tb.dut tl_ram_ret_aon_o.a_address[20:12] -node tb.dut tl_ram_ret_aon_o.a_address[29:23] -node tb.dut tl_ram_ret_aon_o.a_address[31:31]
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv index cda092a..757aeae 100644 --- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
@@ -55,9 +55,6 @@ '{"pinmux_aon", '{ '{32'h40460000, 32'h40460fff} }}, - '{"padctrl_aon", '{ - '{32'h40470000, 32'h40470fff} - }}, '{"ram_ret_aon", '{ '{32'h40600000, 32'h40600fff} }}, @@ -102,7 +99,6 @@ "rstmgr_aon", "clkmgr_aon", "pinmux_aon", - "padctrl_aon", "ram_ret_aon", "otp_ctrl", "lc_ctrl",
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv index 9001b17..917c029 100644 --- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv +++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
@@ -110,12 +110,6 @@ .h2d (tl_pinmux_aon_o), .d2h (tl_pinmux_aon_i) ); - bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_padctrl_aon ( - .clk_i (clk_peri_i), - .rst_ni (rst_peri_ni), - .h2d (tl_padctrl_aon_o), - .d2h (tl_padctrl_aon_i) - ); bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_ram_ret_aon ( .clk_i (clk_peri_i), .rst_ni (rst_peri_ni),
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv index 2316ed8..c3dfaae 100644 --- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv +++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
@@ -22,7 +22,6 @@ localparam logic [31:0] ADDR_SPACE_RSTMGR_AON = 32'h 40410000; localparam logic [31:0] ADDR_SPACE_CLKMGR_AON = 32'h 40420000; localparam logic [31:0] ADDR_SPACE_PINMUX_AON = 32'h 40460000; - localparam logic [31:0] ADDR_SPACE_PADCTRL_AON = 32'h 40470000; localparam logic [31:0] ADDR_SPACE_RAM_RET_AON = 32'h 40600000; localparam logic [31:0] ADDR_SPACE_OTP_CTRL = 32'h 40130000; localparam logic [31:0] ADDR_SPACE_LC_CTRL = 32'h 40140000; @@ -48,7 +47,6 @@ localparam logic [31:0] ADDR_MASK_RSTMGR_AON = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_CLKMGR_AON = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_PINMUX_AON = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_PADCTRL_AON = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_RAM_RET_AON = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_OTP_CTRL = 32'h 00003fff; localparam logic [31:0] ADDR_MASK_LC_CTRL = 32'h 00000fff; @@ -59,7 +57,7 @@ localparam logic [31:0] ADDR_MASK_AST_WRAPPER = 32'h 00000fff; localparam int N_HOST = 1; - localparam int N_DEVICE = 25; + localparam int N_DEVICE = 24; typedef enum int { TlUart0 = 0, @@ -78,15 +76,14 @@ TlRstmgrAon = 13, TlClkmgrAon = 14, TlPinmuxAon = 15, - TlPadctrlAon = 16, - TlRamRetAon = 17, - TlOtpCtrl = 18, - TlLcCtrl = 19, - TlSensorCtrlAon = 20, - TlAlertHandler = 21, - TlSramCtrlRetAon = 22, - TlNmiGen = 23, - TlAstWrapper = 24 + TlRamRetAon = 16, + TlOtpCtrl = 17, + TlLcCtrl = 18, + TlSensorCtrlAon = 19, + TlAlertHandler = 20, + TlSramCtrlRetAon = 21, + TlNmiGen = 22, + TlAstWrapper = 23 } tl_device_e; typedef enum int {
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv index bbe2334..ce776a4 100644 --- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv +++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
@@ -7,7 +7,7 @@ // // Interconnect // main -// -> s1n_26 +// -> s1n_25 // -> uart0 // -> uart1 // -> uart2 @@ -24,7 +24,6 @@ // -> rstmgr_aon // -> clkmgr_aon // -> pinmux_aon -// -> padctrl_aon // -> ram_ret_aon // -> otp_ctrl // -> lc_ctrl @@ -75,8 +74,6 @@ input tlul_pkg::tl_d2h_t tl_clkmgr_aon_i, output tlul_pkg::tl_h2d_t tl_pinmux_aon_o, input tlul_pkg::tl_d2h_t tl_pinmux_aon_i, - output tlul_pkg::tl_h2d_t tl_padctrl_aon_o, - input tlul_pkg::tl_d2h_t tl_padctrl_aon_i, output tlul_pkg::tl_h2d_t tl_ram_ret_aon_o, input tlul_pkg::tl_d2h_t tl_ram_ret_aon_i, output tlul_pkg::tl_h2d_t tl_otp_ctrl_o, @@ -105,173 +102,167 @@ lc_ctrl_pkg::lc_tx_t unused_scanmode; assign unused_scanmode = scanmode_i; - tl_h2d_t tl_s1n_26_us_h2d ; - tl_d2h_t tl_s1n_26_us_d2h ; + tl_h2d_t tl_s1n_25_us_h2d ; + tl_d2h_t tl_s1n_25_us_d2h ; - tl_h2d_t tl_s1n_26_ds_h2d [25]; - tl_d2h_t tl_s1n_26_ds_d2h [25]; + tl_h2d_t tl_s1n_25_ds_h2d [24]; + tl_d2h_t tl_s1n_25_ds_d2h [24]; // Create steering signal - logic [4:0] dev_sel_s1n_26; + logic [4:0] dev_sel_s1n_25; - assign tl_uart0_o = tl_s1n_26_ds_h2d[0]; - assign tl_s1n_26_ds_d2h[0] = tl_uart0_i; + assign tl_uart0_o = tl_s1n_25_ds_h2d[0]; + assign tl_s1n_25_ds_d2h[0] = tl_uart0_i; - assign tl_uart1_o = tl_s1n_26_ds_h2d[1]; - assign tl_s1n_26_ds_d2h[1] = tl_uart1_i; + assign tl_uart1_o = tl_s1n_25_ds_h2d[1]; + assign tl_s1n_25_ds_d2h[1] = tl_uart1_i; - assign tl_uart2_o = tl_s1n_26_ds_h2d[2]; - assign tl_s1n_26_ds_d2h[2] = tl_uart2_i; + assign tl_uart2_o = tl_s1n_25_ds_h2d[2]; + assign tl_s1n_25_ds_d2h[2] = tl_uart2_i; - assign tl_uart3_o = tl_s1n_26_ds_h2d[3]; - assign tl_s1n_26_ds_d2h[3] = tl_uart3_i; + assign tl_uart3_o = tl_s1n_25_ds_h2d[3]; + assign tl_s1n_25_ds_d2h[3] = tl_uart3_i; - assign tl_i2c0_o = tl_s1n_26_ds_h2d[4]; - assign tl_s1n_26_ds_d2h[4] = tl_i2c0_i; + assign tl_i2c0_o = tl_s1n_25_ds_h2d[4]; + assign tl_s1n_25_ds_d2h[4] = tl_i2c0_i; - assign tl_i2c1_o = tl_s1n_26_ds_h2d[5]; - assign tl_s1n_26_ds_d2h[5] = tl_i2c1_i; + assign tl_i2c1_o = tl_s1n_25_ds_h2d[5]; + assign tl_s1n_25_ds_d2h[5] = tl_i2c1_i; - assign tl_i2c2_o = tl_s1n_26_ds_h2d[6]; - assign tl_s1n_26_ds_d2h[6] = tl_i2c2_i; + assign tl_i2c2_o = tl_s1n_25_ds_h2d[6]; + assign tl_s1n_25_ds_d2h[6] = tl_i2c2_i; - assign tl_pattgen_o = tl_s1n_26_ds_h2d[7]; - assign tl_s1n_26_ds_d2h[7] = tl_pattgen_i; + assign tl_pattgen_o = tl_s1n_25_ds_h2d[7]; + assign tl_s1n_25_ds_d2h[7] = tl_pattgen_i; - assign tl_gpio_o = tl_s1n_26_ds_h2d[8]; - assign tl_s1n_26_ds_d2h[8] = tl_gpio_i; + assign tl_gpio_o = tl_s1n_25_ds_h2d[8]; + assign tl_s1n_25_ds_d2h[8] = tl_gpio_i; - assign tl_spi_device_o = tl_s1n_26_ds_h2d[9]; - assign tl_s1n_26_ds_d2h[9] = tl_spi_device_i; + assign tl_spi_device_o = tl_s1n_25_ds_h2d[9]; + assign tl_s1n_25_ds_d2h[9] = tl_spi_device_i; - assign tl_rv_timer_o = tl_s1n_26_ds_h2d[10]; - assign tl_s1n_26_ds_d2h[10] = tl_rv_timer_i; + assign tl_rv_timer_o = tl_s1n_25_ds_h2d[10]; + assign tl_s1n_25_ds_d2h[10] = tl_rv_timer_i; - assign tl_usbdev_o = tl_s1n_26_ds_h2d[11]; - assign tl_s1n_26_ds_d2h[11] = tl_usbdev_i; + assign tl_usbdev_o = tl_s1n_25_ds_h2d[11]; + assign tl_s1n_25_ds_d2h[11] = tl_usbdev_i; - assign tl_pwrmgr_aon_o = tl_s1n_26_ds_h2d[12]; - assign tl_s1n_26_ds_d2h[12] = tl_pwrmgr_aon_i; + assign tl_pwrmgr_aon_o = tl_s1n_25_ds_h2d[12]; + assign tl_s1n_25_ds_d2h[12] = tl_pwrmgr_aon_i; - assign tl_rstmgr_aon_o = tl_s1n_26_ds_h2d[13]; - assign tl_s1n_26_ds_d2h[13] = tl_rstmgr_aon_i; + assign tl_rstmgr_aon_o = tl_s1n_25_ds_h2d[13]; + assign tl_s1n_25_ds_d2h[13] = tl_rstmgr_aon_i; - assign tl_clkmgr_aon_o = tl_s1n_26_ds_h2d[14]; - assign tl_s1n_26_ds_d2h[14] = tl_clkmgr_aon_i; + assign tl_clkmgr_aon_o = tl_s1n_25_ds_h2d[14]; + assign tl_s1n_25_ds_d2h[14] = tl_clkmgr_aon_i; - assign tl_pinmux_aon_o = tl_s1n_26_ds_h2d[15]; - assign tl_s1n_26_ds_d2h[15] = tl_pinmux_aon_i; + assign tl_pinmux_aon_o = tl_s1n_25_ds_h2d[15]; + assign tl_s1n_25_ds_d2h[15] = tl_pinmux_aon_i; - assign tl_padctrl_aon_o = tl_s1n_26_ds_h2d[16]; - assign tl_s1n_26_ds_d2h[16] = tl_padctrl_aon_i; + assign tl_ram_ret_aon_o = tl_s1n_25_ds_h2d[16]; + assign tl_s1n_25_ds_d2h[16] = tl_ram_ret_aon_i; - assign tl_ram_ret_aon_o = tl_s1n_26_ds_h2d[17]; - assign tl_s1n_26_ds_d2h[17] = tl_ram_ret_aon_i; + assign tl_otp_ctrl_o = tl_s1n_25_ds_h2d[17]; + assign tl_s1n_25_ds_d2h[17] = tl_otp_ctrl_i; - assign tl_otp_ctrl_o = tl_s1n_26_ds_h2d[18]; - assign tl_s1n_26_ds_d2h[18] = tl_otp_ctrl_i; + assign tl_lc_ctrl_o = tl_s1n_25_ds_h2d[18]; + assign tl_s1n_25_ds_d2h[18] = tl_lc_ctrl_i; - assign tl_lc_ctrl_o = tl_s1n_26_ds_h2d[19]; - assign tl_s1n_26_ds_d2h[19] = tl_lc_ctrl_i; + assign tl_sensor_ctrl_aon_o = tl_s1n_25_ds_h2d[19]; + assign tl_s1n_25_ds_d2h[19] = tl_sensor_ctrl_aon_i; - assign tl_sensor_ctrl_aon_o = tl_s1n_26_ds_h2d[20]; - assign tl_s1n_26_ds_d2h[20] = tl_sensor_ctrl_aon_i; + assign tl_alert_handler_o = tl_s1n_25_ds_h2d[20]; + assign tl_s1n_25_ds_d2h[20] = tl_alert_handler_i; - assign tl_alert_handler_o = tl_s1n_26_ds_h2d[21]; - assign tl_s1n_26_ds_d2h[21] = tl_alert_handler_i; + assign tl_nmi_gen_o = tl_s1n_25_ds_h2d[21]; + assign tl_s1n_25_ds_d2h[21] = tl_nmi_gen_i; - assign tl_nmi_gen_o = tl_s1n_26_ds_h2d[22]; - assign tl_s1n_26_ds_d2h[22] = tl_nmi_gen_i; + assign tl_ast_wrapper_o = tl_s1n_25_ds_h2d[22]; + assign tl_s1n_25_ds_d2h[22] = tl_ast_wrapper_i; - assign tl_ast_wrapper_o = tl_s1n_26_ds_h2d[23]; - assign tl_s1n_26_ds_d2h[23] = tl_ast_wrapper_i; + assign tl_sram_ctrl_ret_aon_o = tl_s1n_25_ds_h2d[23]; + assign tl_s1n_25_ds_d2h[23] = tl_sram_ctrl_ret_aon_i; - assign tl_sram_ctrl_ret_aon_o = tl_s1n_26_ds_h2d[24]; - assign tl_s1n_26_ds_d2h[24] = tl_sram_ctrl_ret_aon_i; - - assign tl_s1n_26_us_h2d = tl_main_i; - assign tl_main_o = tl_s1n_26_us_d2h; + assign tl_s1n_25_us_h2d = tl_main_i; + assign tl_main_o = tl_s1n_25_us_d2h; always_comb begin // default steering to generate error response if address is not within the range - dev_sel_s1n_26 = 5'd25; - if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin - dev_sel_s1n_26 = 5'd0; + dev_sel_s1n_25 = 5'd24; + if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin + dev_sel_s1n_25 = 5'd0; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_UART1)) == ADDR_SPACE_UART1) begin - dev_sel_s1n_26 = 5'd1; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_UART1)) == ADDR_SPACE_UART1) begin + dev_sel_s1n_25 = 5'd1; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_UART2)) == ADDR_SPACE_UART2) begin - dev_sel_s1n_26 = 5'd2; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_UART2)) == ADDR_SPACE_UART2) begin + dev_sel_s1n_25 = 5'd2; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_UART3)) == ADDR_SPACE_UART3) begin - dev_sel_s1n_26 = 5'd3; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_UART3)) == ADDR_SPACE_UART3) begin + dev_sel_s1n_25 = 5'd3; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_I2C0)) == ADDR_SPACE_I2C0) begin - dev_sel_s1n_26 = 5'd4; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_I2C0)) == ADDR_SPACE_I2C0) begin + dev_sel_s1n_25 = 5'd4; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_I2C1)) == ADDR_SPACE_I2C1) begin - dev_sel_s1n_26 = 5'd5; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_I2C1)) == ADDR_SPACE_I2C1) begin + dev_sel_s1n_25 = 5'd5; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_I2C2)) == ADDR_SPACE_I2C2) begin - dev_sel_s1n_26 = 5'd6; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_I2C2)) == ADDR_SPACE_I2C2) begin + dev_sel_s1n_25 = 5'd6; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_PATTGEN)) == ADDR_SPACE_PATTGEN) begin - dev_sel_s1n_26 = 5'd7; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_PATTGEN)) == ADDR_SPACE_PATTGEN) begin + dev_sel_s1n_25 = 5'd7; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin - dev_sel_s1n_26 = 5'd8; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin + dev_sel_s1n_25 = 5'd8; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin - dev_sel_s1n_26 = 5'd9; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin + dev_sel_s1n_25 = 5'd9; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin - dev_sel_s1n_26 = 5'd10; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin + dev_sel_s1n_25 = 5'd10; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin - dev_sel_s1n_26 = 5'd11; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin + dev_sel_s1n_25 = 5'd11; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_PWRMGR_AON)) == ADDR_SPACE_PWRMGR_AON) begin - dev_sel_s1n_26 = 5'd12; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_PWRMGR_AON)) == ADDR_SPACE_PWRMGR_AON) begin + dev_sel_s1n_25 = 5'd12; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_RSTMGR_AON)) == ADDR_SPACE_RSTMGR_AON) begin - dev_sel_s1n_26 = 5'd13; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_RSTMGR_AON)) == ADDR_SPACE_RSTMGR_AON) begin + dev_sel_s1n_25 = 5'd13; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_CLKMGR_AON)) == ADDR_SPACE_CLKMGR_AON) begin - dev_sel_s1n_26 = 5'd14; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_CLKMGR_AON)) == ADDR_SPACE_CLKMGR_AON) begin + dev_sel_s1n_25 = 5'd14; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_PINMUX_AON)) == ADDR_SPACE_PINMUX_AON) begin - dev_sel_s1n_26 = 5'd15; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_PINMUX_AON)) == ADDR_SPACE_PINMUX_AON) begin + dev_sel_s1n_25 = 5'd15; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_PADCTRL_AON)) == ADDR_SPACE_PADCTRL_AON) begin - dev_sel_s1n_26 = 5'd16; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_RAM_RET_AON)) == ADDR_SPACE_RAM_RET_AON) begin + dev_sel_s1n_25 = 5'd16; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_RAM_RET_AON)) == ADDR_SPACE_RAM_RET_AON) begin - dev_sel_s1n_26 = 5'd17; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_OTP_CTRL)) == ADDR_SPACE_OTP_CTRL) begin + dev_sel_s1n_25 = 5'd17; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_OTP_CTRL)) == ADDR_SPACE_OTP_CTRL) begin - dev_sel_s1n_26 = 5'd18; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_LC_CTRL)) == ADDR_SPACE_LC_CTRL) begin + dev_sel_s1n_25 = 5'd18; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_LC_CTRL)) == ADDR_SPACE_LC_CTRL) begin - dev_sel_s1n_26 = 5'd19; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_SENSOR_CTRL_AON)) == ADDR_SPACE_SENSOR_CTRL_AON) begin + dev_sel_s1n_25 = 5'd19; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_SENSOR_CTRL_AON)) == ADDR_SPACE_SENSOR_CTRL_AON) begin - dev_sel_s1n_26 = 5'd20; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin + dev_sel_s1n_25 = 5'd20; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin - dev_sel_s1n_26 = 5'd21; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin + dev_sel_s1n_25 = 5'd21; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin - dev_sel_s1n_26 = 5'd22; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_AST_WRAPPER)) == ADDR_SPACE_AST_WRAPPER) begin + dev_sel_s1n_25 = 5'd22; - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_AST_WRAPPER)) == ADDR_SPACE_AST_WRAPPER) begin - dev_sel_s1n_26 = 5'd23; - - end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_RET_AON)) == ADDR_SPACE_SRAM_CTRL_RET_AON) begin - dev_sel_s1n_26 = 5'd24; + end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_RET_AON)) == ADDR_SPACE_SRAM_CTRL_RET_AON) begin + dev_sel_s1n_25 = 5'd23; end end @@ -280,17 +271,17 @@ tlul_socket_1n #( .HReqDepth (4'h0), .HRspDepth (4'h0), - .DReqDepth (100'h0), - .DRspDepth (100'h0), - .N (25) - ) u_s1n_26 ( + .DReqDepth (96'h0), + .DRspDepth (96'h0), + .N (24) + ) u_s1n_25 ( .clk_i (clk_peri_i), .rst_ni (rst_peri_ni), - .tl_h_i (tl_s1n_26_us_h2d), - .tl_h_o (tl_s1n_26_us_d2h), - .tl_d_o (tl_s1n_26_ds_h2d), - .tl_d_i (tl_s1n_26_ds_d2h), - .dev_select_i (dev_sel_s1n_26) + .tl_h_i (tl_s1n_25_us_h2d), + .tl_h_o (tl_s1n_25_us_d2h), + .tl_d_o (tl_s1n_25_ds_h2d), + .tl_d_i (tl_s1n_25_ds_d2h), + .dev_select_i (dev_sel_s1n_25) ); endmodule
diff --git a/hw/top_earlgrey/lint/top_earlgrey_fpv_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_fpv_lint_cfgs.hjson index bdd2c9b..b297443 100644 --- a/hw/top_earlgrey/lint/top_earlgrey_fpv_lint_cfgs.hjson +++ b/hw/top_earlgrey/lint/top_earlgrey_fpv_lint_cfgs.hjson
@@ -71,12 +71,6 @@ rel_path: "hw/ip/prim/fpv/lint/{tool}" } { - name: padctrl_fpv - fusesoc_core: lowrisc:fpv:padctrl_fpv - import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] - rel_path: "hw/ip/padctrl/fpv/lint/{tool}" - } - { name: pinmux_fpv fusesoc_core: lowrisc:fpv:pinmux_fpv import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
diff --git a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson index 6b5a706..23ba63b 100644 --- a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson +++ b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson
@@ -116,11 +116,6 @@ } ] }, - { name: padctrl - fusesoc_core: lowrisc:ip:padctrl - import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] - rel_path: "hw/ip/padctrl/lint/{tool}" - }, { name: pinmux fusesoc_core: lowrisc:ip:pinmux import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index cc23ef4..7b0bb3d 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -47,10 +47,10 @@ output logic [14:0] dio_oe_o, // pad attributes to padring - output logic[padctrl_reg_pkg::NMioPads-1:0] - [padctrl_reg_pkg::AttrDw-1:0] mio_attr_o, - output logic[padctrl_reg_pkg::NDioPads-1:0] - [padctrl_reg_pkg::AttrDw-1:0] dio_attr_o, + output logic[pinmux_reg_pkg::NMioPads-1:0] + [pinmux_reg_pkg::AttrDw-1:0] mio_attr_o, + output logic[pinmux_reg_pkg::NDioPads-1:0] + [pinmux_reg_pkg::AttrDw-1:0] dio_attr_o, // Inter-module Signal External type @@ -200,7 +200,6 @@ // rstmgr_aon // clkmgr_aon // pinmux_aon - // padctrl_aon // sensor_ctrl_aon // sram_ctrl_ret_aon // flash_ctrl @@ -508,8 +507,6 @@ tlul_pkg::tl_d2h_t clkmgr_aon_tl_rsp; tlul_pkg::tl_h2d_t pinmux_aon_tl_req; tlul_pkg::tl_d2h_t pinmux_aon_tl_rsp; - tlul_pkg::tl_h2d_t padctrl_aon_tl_req; - tlul_pkg::tl_d2h_t padctrl_aon_tl_rsp; tlul_pkg::tl_h2d_t ram_ret_aon_tl_req; tlul_pkg::tl_d2h_t ram_ret_aon_tl_rsp; tlul_pkg::tl_h2d_t otp_ctrl_tl_req; @@ -1553,6 +1550,7 @@ .periph_to_mio_oe_i (mio_d2p_en ), .mio_to_periph_o (mio_p2d ), + .mio_attr_o, .mio_out_o, .mio_oe_o, .mio_in_i, @@ -1561,10 +1559,12 @@ .periph_to_dio_oe_i (dio_d2p_en ), .dio_to_periph_o (dio_p2d ), + .dio_attr_o, .dio_out_o, .dio_oe_o, .dio_in_i, + // Clock and reset connections .clk_i (clkmgr_aon_clocks.clk_io_div4_secure), .clk_aon_i (clkmgr_aon_clocks.clk_aon_secure), @@ -1572,20 +1572,6 @@ .rst_aon_ni (rstmgr_aon_resets.rst_sys_aon_n[rstmgr_pkg::DomainAonSel]) ); - padctrl u_padctrl_aon ( - - // Inter-module signals - .tl_i(padctrl_aon_tl_req), - .tl_o(padctrl_aon_tl_rsp), - - .mio_attr_o, - .dio_attr_o, - - // Clock and reset connections - .clk_i (clkmgr_aon_clocks.clk_io_div4_secure), - .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]) - ); - sensor_ctrl u_sensor_ctrl_aon ( // [4]: recov_as @@ -2264,10 +2250,6 @@ .tl_pinmux_aon_o(pinmux_aon_tl_req), .tl_pinmux_aon_i(pinmux_aon_tl_rsp), - // port: tl_padctrl_aon - .tl_padctrl_aon_o(padctrl_aon_tl_req), - .tl_padctrl_aon_i(padctrl_aon_tl_rsp), - // port: tl_ram_ret_aon .tl_ram_ret_aon_o(ram_ret_aon_tl_req), .tl_ram_ret_aon_i(ram_ret_aon_tl_rsp),
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv index a96c360..46a5b25 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
@@ -212,16 +212,6 @@ parameter int unsigned TOP_EARLGREY_PINMUX_AON_SIZE_BYTES = 32'h1000; /** - * Peripheral base address for padctrl_aon in top earlgrey. - */ - parameter int unsigned TOP_EARLGREY_PADCTRL_AON_BASE_ADDR = 32'h40470000; - - /** - * Peripheral size in bytes for padctrl_aon in top earlgrey. - */ - parameter int unsigned TOP_EARLGREY_PADCTRL_AON_SIZE_BYTES = 32'h1000; - - /** * Peripheral base address for sensor_ctrl_aon in top earlgrey. */ parameter int unsigned TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR = 32'h40500000;
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv b/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv index a4ac9bb..eba7264 100644 --- a/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv +++ b/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv
@@ -52,14 +52,14 @@ ////////////////////// logic clk_main, clk_usb_48mhz, rst_n; - logic [padctrl_reg_pkg::NMioPads-1:0][padctrl_reg_pkg::AttrDw-1:0] mio_attr; - logic [padctrl_reg_pkg::NDioPads-1:0][padctrl_reg_pkg::AttrDw-1:0] dio_attr; - logic [padctrl_reg_pkg::NMioPads-1:0] mio_out_core, mio_out_padring; - logic [padctrl_reg_pkg::NMioPads-1:0] mio_oe_core, mio_oe_padring; - logic [padctrl_reg_pkg::NMioPads-1:0] mio_in_core, mio_in_padring; - logic [padctrl_reg_pkg::NDioPads-1:0] dio_out_core, dio_out_padring; - logic [padctrl_reg_pkg::NDioPads-1:0] dio_oe_core, dio_oe_padring; - logic [padctrl_reg_pkg::NDioPads-1:0] dio_in_core, dio_in_padring; + logic [pinmux_reg_pkg::NMioPads-1:0][pinmux_reg_pkg::AttrDw-1:0] mio_attr; + logic [pinmux_reg_pkg::NDioPads-1:0][pinmux_reg_pkg::AttrDw-1:0] dio_attr; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_out_core, mio_out_padring; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe_core, mio_oe_padring; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_in_core, mio_in_padring; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_out_core, dio_out_padring; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe_core, dio_oe_padring; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_in_core, dio_in_padring; padring #( // MIOs 31:20 are currently not
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv index 4c8f123..7a4918b 100644 --- a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv +++ b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
@@ -51,14 +51,14 @@ ////////////////////// logic clk, clk_usb_48mhz, rst_n; - logic [padctrl_reg_pkg::NMioPads-1:0][padctrl_reg_pkg::AttrDw-1:0] mio_attr; - logic [padctrl_reg_pkg::NDioPads-1:0][padctrl_reg_pkg::AttrDw-1:0] dio_attr; - logic [padctrl_reg_pkg::NMioPads-1:0] mio_out_core, mio_out_padring; - logic [padctrl_reg_pkg::NMioPads-1:0] mio_oe_core, mio_oe_padring; - logic [padctrl_reg_pkg::NMioPads-1:0] mio_in_core, mio_in_padring; - logic [padctrl_reg_pkg::NDioPads-1:0] dio_out_core, dio_out_padring; - logic [padctrl_reg_pkg::NDioPads-1:0] dio_oe_core, dio_oe_padring; - logic [padctrl_reg_pkg::NDioPads-1:0] dio_in_core, dio_in_padring; + logic [pinmux_reg_pkg::NMioPads-1:0][pinmux_reg_pkg::AttrDw-1:0] mio_attr; + logic [pinmux_reg_pkg::NDioPads-1:0][pinmux_reg_pkg::AttrDw-1:0] dio_attr; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_out_core, mio_out_padring; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe_core, mio_oe_padring; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_in_core, mio_in_padring; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_out_core, dio_out_padring; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe_core, dio_oe_padring; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_in_core, dio_in_padring; // unused pad signals. need to hook these wires up since lint does not like module ports that are // tied to 1'bz. @@ -146,13 +146,13 @@ logic jtag_trst_n, jtag_srst_n; logic jtag_tck, jtag_tms, jtag_tdi, jtag_tdo; - localparam int NumIOs = padctrl_reg_pkg::NMioPads + - padctrl_reg_pkg::NDioPads; + localparam int NumIOs = pinmux_reg_pkg::NMioPads + + pinmux_reg_pkg::NDioPads; // This specifies the tie-off values of the muxed MIO/DIOs // when the JTAG is active. SPI CSB is active low. localparam logic [NumIOs-1:0] TieOffValues =NumIOs'(1'b1 << ( - padctrl_reg_pkg::NMioPads + top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceCsb)); + pinmux_reg_pkg::NMioPads + top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceCsb)); // TODO: this is a temporary solution. JTAG will eventually be selected and // qualified inside the pinmux, based on strap and lifecycle state. @@ -163,15 +163,15 @@ .TieOffValues ( TieOffValues ), .JtagEnIdx ( 16 ), // MIO 16 .JtagEnPolarity ( 1 ), - .TckIdx ( padctrl_reg_pkg::NMioPads + + .TckIdx ( pinmux_reg_pkg::NMioPads + top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSck ), - .TmsIdx ( padctrl_reg_pkg::NMioPads + + .TmsIdx ( pinmux_reg_pkg::NMioPads + top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceCsb ), .TrstIdx ( 18 ), // MIO 18 .SrstIdx ( 19 ), // MIO 19 - .TdiIdx ( padctrl_reg_pkg::NMioPads + + .TdiIdx ( pinmux_reg_pkg::NMioPads + top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSdi ), - .TdoIdx ( padctrl_reg_pkg::NMioPads + + .TdoIdx ( pinmux_reg_pkg::NMioPads + top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSdo ) ) jtag_mux ( // To JTAG inside core
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv index e90ef06..fcc1463 100644 --- a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv +++ b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
@@ -73,14 +73,14 @@ logic clk_main, clk_usb_48mhz, rst_n; - logic [padctrl_reg_pkg::NMioPads-1:0][padctrl_reg_pkg::AttrDw-1:0] mio_attr; - logic [padctrl_reg_pkg::NDioPads-1:0][padctrl_reg_pkg::AttrDw-1:0] dio_attr; - logic [padctrl_reg_pkg::NMioPads-1:0] mio_out_core, mio_out_padring; - logic [padctrl_reg_pkg::NMioPads-1:0] mio_oe_core, mio_oe_padring; - logic [padctrl_reg_pkg::NMioPads-1:0] mio_in_core, mio_in_padring; - logic [padctrl_reg_pkg::NDioPads-1:0] dio_out_core, dio_out_umux, dio_out_padring; - logic [padctrl_reg_pkg::NDioPads-1:0] dio_oe_core, dio_oe_umux, dio_oe_padring; - logic [padctrl_reg_pkg::NDioPads-1:0] dio_in_core, dio_in_umux, dio_in_padring; + logic [pinmux_reg_pkg::NMioPads-1:0][pinmux_reg_pkg::AttrDw-1:0] mio_attr; + logic [pinmux_reg_pkg::NDioPads-1:0][pinmux_reg_pkg::AttrDw-1:0] dio_attr; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_out_core, mio_out_padring; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe_core, mio_oe_padring; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_in_core, mio_in_padring; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_out_core, dio_out_umux, dio_out_padring; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe_core, dio_oe_umux, dio_oe_padring; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_in_core, dio_in_umux, dio_in_padring; padring #( // MIOs 23:20 are currently not @@ -168,13 +168,13 @@ logic jtag_trst_n, jtag_srst_n; logic jtag_tck, jtag_tck_buf, jtag_tms, jtag_tdi, jtag_tdo; - localparam int NumIOs = padctrl_reg_pkg::NMioPads + - padctrl_reg_pkg::NDioPads; + localparam int NumIOs = pinmux_reg_pkg::NMioPads + + pinmux_reg_pkg::NDioPads; // This specifies the tie-off values of the muxed MIO/DIOs // when the JTAG is active. SPI CSB is active low. localparam logic [NumIOs-1:0] TieOffValues = NumIOs'(1'b1 << ( - padctrl_reg_pkg::NMioPads + top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceCsb)); + pinmux_reg_pkg::NMioPads + top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceCsb)); // TODO: this is a temporary solution. JTAG will eventually be selected and // qualified inside the pinmux, based on strap and lifecycle state. @@ -185,15 +185,15 @@ .TieOffValues ( TieOffValues ), .JtagEnIdx ( 16 ), // MIO 16 .JtagEnPolarity ( 1 ), - .TckIdx ( padctrl_reg_pkg::NMioPads + + .TckIdx ( pinmux_reg_pkg::NMioPads + top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSck ), - .TmsIdx ( padctrl_reg_pkg::NMioPads + + .TmsIdx ( pinmux_reg_pkg::NMioPads + top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceCsb ), .TrstIdx ( 18 ), // MIO 18 .SrstIdx ( 19 ), // MIO 19 - .TdiIdx ( padctrl_reg_pkg::NMioPads + + .TdiIdx ( pinmux_reg_pkg::NMioPads + top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSdi ), - .TdoIdx ( padctrl_reg_pkg::NMioPads + + .TdoIdx ( pinmux_reg_pkg::NMioPads + top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSdo ) ) jtag_mux ( // To JTAG inside core @@ -282,7 +282,7 @@ logic use_uphy; assign use_uphy = mio_in_padring[2]; - for (genvar i = 0; i < padctrl_reg_pkg::NDioPads; i++) begin : gen_dio + for (genvar i = 0; i < pinmux_reg_pkg::NDioPads; i++) begin : gen_dio if (i == DioIdxUsbDn0) begin assign dio_out_umux[i] = undo_swap ? dio_out_core[DioIdxUsbDp0] : dio_out_core[DioIdxUsbDn0];
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h index afcd203..9b2e33c 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -386,24 +386,6 @@ #define TOP_EARLGREY_PINMUX_AON_SIZE_BYTES 0x1000u /** - * Peripheral base address for padctrl_aon in top earlgrey. - * - * This should be used with #mmio_region_from_addr to access the memory-mapped - * registers associated with the peripheral (usually via a DIF). - */ -#define TOP_EARLGREY_PADCTRL_AON_BASE_ADDR 0x40470000u - -/** - * Peripheral size for padctrl_aon in top earlgrey. - * - * This is the size (in bytes) of the peripheral's reserved memory area. All - * memory-mapped registers associated with this peripheral should have an - * address between #TOP_EARLGREY_PADCTRL_AON_BASE_ADDR and - * `TOP_EARLGREY_PADCTRL_AON_BASE_ADDR + TOP_EARLGREY_PADCTRL_AON_SIZE_BYTES`. - */ -#define TOP_EARLGREY_PADCTRL_AON_SIZE_BYTES 0x1000u - -/** * Peripheral base address for sensor_ctrl_aon in top earlgrey. * * This should be used with #mmio_region_from_addr to access the memory-mapped
diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core index e0539a9..8d285d9 100644 --- a/hw/top_earlgrey/top_earlgrey.core +++ b/hw/top_earlgrey/top_earlgrey.core
@@ -14,9 +14,7 @@ - lowrisc:ip:rv_dm - lowrisc:top_earlgrey:rv_plic - lowrisc:top_earlgrey:pinmux_reg - - lowrisc:top_earlgrey:padctrl_reg - lowrisc:ip:pinmux_component - - lowrisc:ip:padctrl_component - lowrisc:ip:rv_timer - lowrisc:ip:tlul - lowrisc:ip:spi_device
diff --git a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson index 2efac41..24a436d 100644 --- a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson +++ b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
@@ -318,17 +318,6 @@ base_addr: "0x40460000", generated: "true" }, - // see comment regarding pinmux above - { name: "padctrl", - type: "padctrl", - clock: "main", - clock_srcs: {clk_i: "main"}, - clock_group: "secure", - reset_connections: {rst_ni: "sys"}, - domain: "Aon", - base_addr: "0x40470000", - generated: "true" - }, { name: "usbdev", type: "usbdev", clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon", clk_usb_48mhz_i: "usb"},
diff --git a/hw/top_englishbreakfast/data/xbar_main.hjson b/hw/top_englishbreakfast/data/xbar_main.hjson index aed1ff3..70b080a 100644 --- a/hw/top_englishbreakfast/data/xbar_main.hjson +++ b/hw/top_englishbreakfast/data/xbar_main.hjson
@@ -100,17 +100,6 @@ }], pipeline_byp: "false" }, - { name: "padctrl", - type: "device", - clock: "clk_main_i", - reset: "rst_fixed_ni", - inst_type: "padctrl", - addr_range: [{ - base_addr: "0x40160000", - size_byte: "0x1000", - }], - pipeline_byp: "false" - }, { name: "sram_ctrl_main", type: "device", clock: "clk_main_i", @@ -122,9 +111,9 @@ corei: ["rom", "debug_mem", "ram_main", "eflash"], cored: ["rom", "debug_mem", "ram_main", "eflash", "peri", "flash_ctrl", "aes", - "hmac", "rv_plic", "pinmux", "padctrl", "sram_ctrl_main"], + "hmac", "rv_plic", "pinmux", "sram_ctrl_main"], dm_sba: ["rom", "ram_main", "eflash", "peri", "flash_ctrl", "aes", - "hmac", "rv_plic", "pinmux", "padctrl", "sram_ctrl_main"], + "hmac", "rv_plic", "pinmux", "sram_ctrl_main"], }, }
diff --git a/hw/top_englishbreakfast/rtl/top_englishbreakfast_cw305.sv b/hw/top_englishbreakfast/rtl/top_englishbreakfast_cw305.sv index c336081..f111413 100644 --- a/hw/top_englishbreakfast/rtl/top_englishbreakfast_cw305.sv +++ b/hw/top_englishbreakfast/rtl/top_englishbreakfast_cw305.sv
@@ -58,14 +58,14 @@ logic clk_main, clk_usb_48mhz, rst_n; - logic [padctrl_reg_pkg::NMioPads-1:0][padctrl_reg_pkg::AttrDw-1:0] mio_attr; - logic [padctrl_reg_pkg::NDioPads-1:0][padctrl_reg_pkg::AttrDw-1:0] dio_attr; - logic [padctrl_reg_pkg::NMioPads-1:0] mio_out_core, mio_out_padring; - logic [padctrl_reg_pkg::NMioPads-1:0] mio_oe_core, mio_oe_padring; - logic [padctrl_reg_pkg::NMioPads-1:0] mio_in_core, mio_in_padring; - logic [padctrl_reg_pkg::NDioPads-1:0] dio_out_core, dio_out_padring; - logic [padctrl_reg_pkg::NDioPads-1:0] dio_oe_core, dio_oe_padring; - logic [padctrl_reg_pkg::NDioPads-1:0] dio_in_core, dio_in_padring; + logic [pinmux_reg_pkg::NMioPads-1:0][pinmux_reg_pkg::AttrDw-1:0] mio_attr; + logic [pinmux_reg_pkg::NDioPads-1:0][pinmux_reg_pkg::AttrDw-1:0] dio_attr; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_out_core, mio_out_padring; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe_core, mio_oe_padring; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_in_core, mio_in_padring; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_out_core, dio_out_padring; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe_core, dio_oe_padring; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_in_core, dio_in_padring; padring #( // MIOs 31:20 are currently not @@ -145,13 +145,13 @@ logic jtag_trst_n, jtag_srst_n; logic jtag_tck, jtag_tck_buf, jtag_tms, jtag_tdi, jtag_tdo; - localparam int NumIOs = padctrl_reg_pkg::NMioPads + - padctrl_reg_pkg::NDioPads; + localparam int NumIOs = pinmux_reg_pkg::NMioPads + + pinmux_reg_pkg::NDioPads; // This specifies the tie-off values of the muxed MIO/DIOs // when the JTAG is active. SPI CSB is active low. localparam logic [NumIOs-1:0] TieOffValues = NumIOs'(1'b1 << ( - padctrl_reg_pkg::NMioPads + top_englishbreakfast_pkg::TopEnglishbreakfastDioPinSpiDeviceCsb)); + pinmux_reg_pkg::NMioPads + top_englishbreakfast_pkg::TopEnglishbreakfastDioPinSpiDeviceCsb)); // TODO: this is a temporary solution. JTAG will eventually be selected and // qualified inside the pinmux, based on strap and lifecycle state. @@ -162,15 +162,15 @@ .TieOffValues ( TieOffValues ), .JtagEnIdx ( 16 ), // MIO 16 .JtagEnPolarity ( 1 ), - .TckIdx ( padctrl_reg_pkg::NMioPads + + .TckIdx ( pinmux_reg_pkg::NMioPads + top_englishbreakfast_pkg::TopEnglishbreakfastDioPinSpiDeviceSck ), - .TmsIdx ( padctrl_reg_pkg::NMioPads + + .TmsIdx ( pinmux_reg_pkg::NMioPads + top_englishbreakfast_pkg::TopEnglishbreakfastDioPinSpiDeviceCsb ), .TrstIdx ( 18 ), // MIO 18 .SrstIdx ( 19 ), // MIO 19 - .TdiIdx ( padctrl_reg_pkg::NMioPads + + .TdiIdx ( pinmux_reg_pkg::NMioPads + top_englishbreakfast_pkg::TopEnglishbreakfastDioPinSpiDeviceSdi ), - .TdoIdx ( padctrl_reg_pkg::NMioPads + + .TdoIdx ( pinmux_reg_pkg::NMioPads + top_englishbreakfast_pkg::TopEnglishbreakfastDioPinSpiDeviceSdo ) ) jtag_mux ( // To JTAG inside core @@ -305,9 +305,9 @@ // GPIO15 is used as capture trigger. localparam int MioIdxTrigger = 15; - logic [padctrl_reg_pkg::NMioPads-1:0] mio_out; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_out; - for (genvar i = 0; i < padctrl_reg_pkg::NMioPads; i++) begin : gen_mio_out + for (genvar i = 0; i < pinmux_reg_pkg::NMioPads; i++) begin : gen_mio_out if (i == MioIdxTrigger) begin // To obtain a more precise capture trigger for side-channel analysis, we only forward the // software-controlled capture trigger when the AES module is actually busy (performing
diff --git a/hw/top_englishbreakfast/top_englishbreakfast.core b/hw/top_englishbreakfast/top_englishbreakfast.core index 946b8ec..f937a26 100644 --- a/hw/top_englishbreakfast/top_englishbreakfast.core +++ b/hw/top_englishbreakfast/top_englishbreakfast.core
@@ -27,7 +27,6 @@ - lowrisc:ip:gpio - lowrisc:ip:rv_plic_component - lowrisc:ip:pinmux_component - - lowrisc:ip:padctrl_component - lowrisc:ip:rv_timer - lowrisc:ip:spi_device - lowrisc:ip:aes
diff --git a/util/build_docs.py b/util/build_docs.py index 253bf9a..477361f 100755 --- a/util/build_docs.py +++ b/util/build_docs.py
@@ -70,7 +70,6 @@ "hw/ip/nmi_gen/data/nmi_gen.hjson", "hw/ip/otbn/data/otbn.hjson", "hw/ip/otp_ctrl/data/otp_ctrl.hjson", - "hw/ip/padctrl/data/padctrl.hjson", "hw/ip/pattgen/data/pattgen.hjson", "hw/ip/pwm/data/pwm.hjson", "hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson", @@ -105,7 +104,6 @@ "hw/ip/keymgr/data/keymgr_testplan.hjson", "hw/ip/lc_ctrl/data/lc_ctrl_testplan.hjson", "hw/ip/otp_ctrl/data/otp_ctrl_testplan.hjson", - "hw/ip/padctrl/data/padctrl_fpv_testplan.hjson", "hw/ip/pattgen/data/pattgen_testplan.hjson", "hw/ip/pinmux/data/pinmux_fpv_testplan.hjson", "hw/ip/rv_plic/data/rv_plic_fpv_testplan.hjson",
diff --git a/util/syn_yosys.sh b/util/syn_yosys.sh index b3c9ec1..14a6fb5 100755 --- a/util/syn_yosys.sh +++ b/util/syn_yosys.sh
@@ -79,7 +79,6 @@ "aes" "hmac" "pinmux" - "padctrl" "alert_handler" "pwrmgr" "rstmgr"
diff --git a/util/topgen-fusesoc.py b/util/topgen-fusesoc.py index c864032..ba2936b 100644 --- a/util/topgen-fusesoc.py +++ b/util/topgen-fusesoc.py
@@ -90,7 +90,7 @@ # example, flash_ctrl depends on topgen but also on pwrmgr_pkg which depends on # pwrmgr_reg_pkg generated by topgen. if reg_only: - for ip in ['alert_handler', 'clkmgr', 'flash_ctrl', 'padctrl', 'pinmux', 'pwrmgr', + for ip in ['alert_handler', 'clkmgr', 'flash_ctrl', 'pinmux', 'pwrmgr', 'rstmgr', 'rv_plic']: core_filepath = os.path.abspath('generated-%s.core' % ip) name = 'lowrisc:ip:%s_reggen' % ip,
diff --git a/util/topgen.py b/util/topgen.py index 25ea189..0bd4783 100755 --- a/util/topgen.py +++ b/util/topgen.py
@@ -330,7 +330,7 @@ return bit_pos -def generate_pinmux_and_padctrl(top, out_path): +def generate_pinmux(top, out_path): topname = top["name"] # MIO Pads n_mio_pads = top["pinmux"]["num_mio"] @@ -390,6 +390,9 @@ n_dio_periph_out = num_dio_inouts + num_dio_outputs n_dio_pads = num_dio_inouts + num_dio_inputs + num_dio_outputs + # TODO: derive this value + attr_dw = 10 + if n_dio_pads <= 0: # TODO: add support for no DIO case log.error("Topgen does currently not support generation of a top " + @@ -412,6 +415,7 @@ log.info("num_dio_inputs: %d" % num_dio_inputs) log.info("num_dio_outputs: %d" % num_dio_outputs) log.info("num_dio_inouts: %d" % num_dio_inouts) + log.info("attr_dw: %d" % attr_dw) log.info("num_wkup_detect: %d" % num_wkup_detect) log.info("wkup_cnt_width: %d" % wkup_cnt_width) log.info("This translates to:") @@ -460,6 +464,7 @@ n_dio_periph_in=n_dio_pads, n_dio_periph_out=n_dio_pads, n_dio_pads=n_dio_pads, + attr_dw=attr_dw, n_wkup_detect=num_wkup_detect, wkup_cnt_width=wkup_cnt_width, usb_start_pos=usb_start_pos, @@ -486,48 +491,6 @@ validate.validate(hjson_obj) gen_rtl.gen_rtl(hjson_obj, str(rtl_path)) - # Target path - # rtl: padctrl_reg_pkg.sv & padctrl_reg_top.sv - # data: padctrl.hjson - rtl_path = out_path / 'ip/padctrl/rtl/autogen' - rtl_path.mkdir(parents=True, exist_ok=True) - data_path = out_path / 'ip/padctrl/data/autogen' - data_path.mkdir(parents=True, exist_ok=True) - - # Template path - tpl_path = Path( - __file__).resolve().parent / '../hw/ip/padctrl/data/padctrl.hjson.tpl' - - # Generate register package and RTLs - gencmd = ("// util/topgen.py -t hw/top_{topname}/data/top_{topname}.hjson " - "-o hw/top_{topname}/\n\n".format(topname=topname)) - - hjson_gen_path = data_path / "padctrl.hjson" - - out = StringIO() - with tpl_path.open(mode='r', encoding='UTF-8') as fin: - hjson_tpl = Template(fin.read()) - try: - out = hjson_tpl.render(n_mio_pads=n_mio_pads, - n_dio_pads=n_dio_pads, - attr_dw=10) - except: # noqa: E722 - log.error(exceptions.text_error_template().render()) - log.info("PADCTRL HJSON: %s" % out) - - if out == "": - log.error("Cannot generate padctrl HJSON") - return - - with hjson_gen_path.open(mode='w', encoding='UTF-8') as fout: - fout.write(genhdr + gencmd + out) - - hjson_obj = hjson.loads(out, - use_decimal=True, - object_pairs_hook=validate.checking_dict) - validate.validate(hjson_obj) - gen_rtl.gen_rtl(hjson_obj, str(rtl_path)) - def generate_clkmgr(top, cfg_path, out_path): @@ -1036,7 +999,7 @@ sys.exit() # Generate Pinmux - generate_pinmux_and_padctrl(completecfg, out_path) + generate_pinmux(completecfg, out_path) # Generate Pwrmgr generate_pwrmgr(completecfg, out_path)
