| commit | 436fa6c8f4af2fb59f3fd17dbb691a410849ba6c | [log] [tgz] |
|---|---|---|
| author | Eunchan Kim <eunchan@opentitan.org> | Tue Dec 15 11:43:23 2020 -0800 |
| committer | Eunchan Kim <eunchan@opentitan.org> | Tue Dec 15 14:12:33 2020 -0800 |
| tree | dce431b03b2ab550ed7e55d7ae58c30c86d888ce | |
| parent | 5e6032a1f878d15e30d0ec06ca019f3754ff3a4c [diff] |
[kmac] Latch the output data from state
Problem:
The software reads unknown data or all-zero from state window.
The `tlram_rdata` is connected to tlram_rdata_endian. the latter is a
muxed signal from the internal Keccak state registers. The mux selection
signal is the input TL-UL address.
As the address only valid when the request is asserted, the selection
signal becomes unknown or incorrect value when the state module returns
the read data.
This commit is to fix the bug by latching the tlram_rdata. There's
another solution to latch the address selectino only when it is valid.
The latter consumes less registers as address bit width is smaller than
the return data but creates a little bit more ambiguous logic so that
drops the readability.
The issue is reported by @udinator
Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
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