)]}'
{
  "commit": "436fa6c8f4af2fb59f3fd17dbb691a410849ba6c",
  "tree": "dce431b03b2ab550ed7e55d7ae58c30c86d888ce",
  "parents": [
    "5e6032a1f878d15e30d0ec06ca019f3754ff3a4c"
  ],
  "author": {
    "name": "Eunchan Kim",
    "email": "eunchan@opentitan.org",
    "time": "Tue Dec 15 11:43:23 2020 -0800"
  },
  "committer": {
    "name": "Eunchan Kim",
    "email": "eunchan@opentitan.org",
    "time": "Tue Dec 15 14:12:33 2020 -0800"
  },
  "message": "[kmac] Latch the output data from state\n\nProblem:\n\n    The software reads unknown data or all-zero from state window.\n\nThe `tlram_rdata` is connected to tlram_rdata_endian. the latter is a\nmuxed signal from the internal Keccak state registers. The mux selection\nsignal is the input TL-UL address.\n\nAs the address only valid when the request is asserted, the selection\nsignal becomes unknown or incorrect value when the state module returns\nthe read data.\n\nThis commit is to fix the bug by latching the tlram_rdata. There\u0027s\nanother solution to latch the address selectino only when it is valid.\nThe latter consumes less registers as address bit width is smaller than\nthe return data but creates a little bit more ambiguous logic so that\ndrops the readability.\n\nThe issue is reported by @udinator\n\nSigned-off-by: Eunchan Kim \u003ceunchan@opentitan.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c8f00b527361f47b658ec36e2f2cfbeca5d36894",
      "old_mode": 33188,
      "old_path": "hw/ip/kmac/rtl/kmac_staterd.sv",
      "new_id": "4cb11d6d069ca5a28b7b25236af1d153c418900f",
      "new_mode": 33188,
      "new_path": "hw/ip/kmac/rtl/kmac_staterd.sv"
    }
  ]
}