| commit | 413baea7b42b04d8575f9b389dd25595f6300af9 | [log] [tgz] |
|---|---|---|
| author | Udi Jonnalagadda <udij@google.com> | Thu Jan 07 12:15:19 2021 -0800 |
| committer | udinator <udij@google.com> | Fri Jan 08 14:55:47 2021 -0800 |
| tree | 044f345c8167e8421ddf0c9691ec9c9e01c626ae | |
| parent | c9176cb07c7854bc77e1ca1ff346b01a4a785290 [diff] |
[sram/dv] initial SRAM testbench This PR adds the auto-generated testbench files produced by uvmdvgen, and instantiates all of the necessary interfaces. Note that `tb.sv` hooks up 3 separate modules as the DUT, this is due to how the SRAM controller interfaces to the SRAM memory scrambling module itself. Also note that, similar to KMAC, two different variants of the SRAM are being tested: one with a depth of `2**10` and one with a depth of `2**14`, to mimic the Main and Retention SRAMs instantiated at the top level. This PR gets the SRAM testbench into a compile-able state, with no tests or additional runtime functionality implemented. Signed-off-by: Udi Jonnalagadda <udij@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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