tree 044f345c8167e8421ddf0c9691ec9c9e01c626ae
parent c9176cb07c7854bc77e1ca1ff346b01a4a785290
author Udi Jonnalagadda <udij@google.com> 1610050519 -0800
committer udinator <udij@google.com> 1610146547 -0800

[sram/dv] initial SRAM testbench

This PR adds the auto-generated testbench files produced by uvmdvgen,
and instantiates all of the necessary interfaces.

Note that `tb.sv` hooks up 3 separate modules as the DUT, this is due to
how the SRAM controller interfaces to the SRAM memory scrambling module
itself.

Also note that, similar to KMAC, two different variants of the SRAM are
being tested: one with a depth of `2**10` and one with a depth of
`2**14`, to mimic the Main and Retention SRAMs instantiated at the top
level.

This PR gets the SRAM testbench into a compile-able state, with no tests
or additional runtime functionality implemented.

Signed-off-by: Udi Jonnalagadda <udij@google.com>