hw/vendor/patches/pulp_riscv_dbg/0007-lint-cleanup-Break-long-lines-and-make-literal-lengt.patch

From 4b293663f9e4353cf58077c6a6f7107e3210915d Mon Sep 17 00:00:00 2001
From: Michael Schaffner <msf@google.com>
Date: Thu, 17 Oct 2019 18:35:46 -0700
Subject: [PATCH 7/9] [lint/cleanup] Break long lines and make literal lengths
 explicit

Overly long lines and unsized literals generate several lint warnings, and this
commit fixes these.
---
 src/dm_csrs.sv      |  6 ++---
 src/dm_pkg.sv       | 56 +++++++++++++++++++++++++++++++++------------
 src/dm_sba.sv       | 12 +++++-----
 src/dmi_jtag_tap.sv |  8 +++----
 4 files changed, 55 insertions(+), 27 deletions(-)

diff --git a/src/dm_csrs.sv b/src/dm_csrs.sv
index 54cbc1a..cac7509 100644
--- a/src/dm_csrs.sv
+++ b/src/dm_csrs.sv
@@ -520,11 +520,11 @@ module dm_csrs #(
     sbcs_d.sbbusy               = sbbusy_i;
     sbcs_d.sbasize              = BusWidth;
     sbcs_d.sbaccess128          = 1'b0;
-    sbcs_d.sbaccess64           = BusWidth == 64;
-    sbcs_d.sbaccess32           = BusWidth == 32;
+    sbcs_d.sbaccess64           = logic'(BusWidth == 32'd64);
+    sbcs_d.sbaccess32           = logic'(BusWidth == 32'd32);
     sbcs_d.sbaccess16           = 1'b0;
     sbcs_d.sbaccess8            = 1'b0;
-    sbcs_d.sbaccess             = BusWidth == 64 ? 2'd3 : 2'd2;
+    sbcs_d.sbaccess             = (BusWidth == 32'd64) ? 2'd3 : 2'd2;
   end
 
   // output multiplexer
diff --git a/src/dm_pkg.sv b/src/dm_pkg.sv
index 341e9ab..de75c3e 100644
--- a/src/dm_pkg.sv
+++ b/src/dm_pkg.sv
@@ -302,69 +302,97 @@ package dm;
 
 
   // Instruction Generation Helpers
-  function automatic logic [31:0] jal (logic[4:0] rd, logic [20:0] imm);
+  function automatic logic [31:0] jal (logic [4:0]  rd,
+                                       logic [20:0] imm);
     // OpCode Jal
     return {imm[20], imm[10:1], imm[11], imm[19:12], rd, 7'h6f};
   endfunction
 
-  function automatic logic [31:0] jalr (logic[4:0] rd, logic[4:0] rs1, logic [11:0] offset);
+  function automatic logic [31:0] jalr (logic [4:0]  rd,
+                                        logic [4:0]  rs1,
+                                        logic [11:0] offset);
     // OpCode Jal
     return {offset[11:0], rs1, 3'b0, rd, 7'h67};
   endfunction
 
-  function automatic logic [31:0] andi (logic[4:0] rd, logic[4:0] rs1, logic [11:0] imm);
+  function automatic logic [31:0] andi (logic [4:0]  rd,
+                                        logic [4:0]  rs1,
+                                        logic [11:0] imm);
     // OpCode andi
     return {imm[11:0], rs1, 3'h7, rd, 7'h13};
   endfunction
 
-  function automatic logic [31:0] slli (logic[4:0] rd, logic[4:0] rs1, logic [5:0] shamt);
+  function automatic logic [31:0] slli (logic [4:0] rd,
+                                        logic [4:0] rs1,
+                                        logic [5:0] shamt);
     // OpCode slli
     return {6'b0, shamt[5:0], rs1, 3'h1, rd, 7'h13};
   endfunction
 
-  function automatic logic [31:0] srli (logic[4:0] rd, logic[4:0] rs1, logic [5:0] shamt);
+  function automatic logic [31:0] srli (logic [4:0] rd,
+                                        logic [4:0] rs1,
+                                        logic [5:0] shamt);
     // OpCode srli
     return {6'b0, shamt[5:0], rs1, 3'h5, rd, 7'h13};
   endfunction
 
-  function automatic logic [31:0] load (logic [2:0] size, logic[4:0] dest, logic[4:0] base, logic [11:0] offset);
+  function automatic logic [31:0] load (logic [2:0]  size,
+                                        logic [4:0]  dest,
+                                        logic [4:0]  base,
+                                        logic [11:0] offset);
     // OpCode Load
     return {offset[11:0], base, size, dest, 7'h03};
   endfunction
 
-  function automatic logic [31:0] auipc (logic[4:0] rd, logic [20:0] imm);
+  function automatic logic [31:0] auipc (logic [4:0]  rd,
+                                         logic [20:0] imm);
     // OpCode Auipc
     return {imm[20], imm[10:1], imm[11], imm[19:12], rd, 7'h17};
   endfunction
 
-  function automatic logic [31:0] store (logic [2:0] size, logic[4:0] src, logic[4:0] base, logic [11:0] offset);
+  function automatic logic [31:0] store (logic [2:0]  size,
+                                         logic [4:0]  src,
+                                         logic [4:0]  base,
+                                         logic [11:0] offset);
     // OpCode Store
     return {offset[11:5], src, base, size, offset[4:0], 7'h23};
   endfunction
 
-  function automatic logic [31:0] float_load (logic [2:0] size, logic[4:0] dest, logic[4:0] base, logic [11:0] offset);
+  function automatic logic [31:0] float_load (logic [2:0]  size,
+                                              logic [4:0]  dest,
+                                              logic [4:0]  base,
+                                              logic [11:0] offset);
     // OpCode Load
     return {offset[11:0], base, size, dest, 7'b00_001_11};
   endfunction
 
-  function automatic logic [31:0] float_store (logic [2:0] size, logic[4:0] src, logic[4:0] base, logic [11:0] offset);
+  function automatic logic [31:0] float_store (logic [2:0]  size,
+                                               logic [4:0]  src,
+                                               logic [4:0]  base,
+                                               logic [11:0] offset);
     // OpCode Store
     return {offset[11:5], src, base, size, offset[4:0], 7'b01_001_11};
   endfunction
 
-  function automatic logic [31:0] csrw (csr_reg_t csr, logic[4:0] rs1);
+  function automatic logic [31:0] csrw (csr_reg_t   csr,
+                                        logic [4:0] rs1);
     // CSRRW, rd, OpCode System
     return {csr, rs1, 3'h1, 5'h0, 7'h73};
   endfunction
 
-  function automatic logic [31:0] csrr (csr_reg_t csr, logic [4:0] dest);
+  function automatic logic [31:0] csrr (csr_reg_t   csr,
+                                        logic [4:0] dest);
     // rs1, CSRRS, rd, OpCode System
     return {csr, 5'h0, 3'h2, dest, 7'h73};
   endfunction
 
-  function automatic logic [31:0] branch(logic [4:0] src2, logic [4:0] src1, logic [2:0] funct3, logic [11:0] offset);
+  function automatic logic [31:0] branch(logic [4:0]  src2,
+                                         logic [4:0]  src1,
+                                         logic [2:0]  funct3,
+                                         logic [11:0] offset);
     // OpCode Branch
-    return {offset[11], offset[9:4], src2, src1, funct3, offset[3:0], offset[10], 7'b11_000_11};
+    return {offset[11], offset[9:4], src2, src1, funct3,
+        offset[3:0], offset[10], 7'b11_000_11};
   endfunction
 
   function automatic logic [31:0] ebreak ();
diff --git a/src/dm_sba.sv b/src/dm_sba.sv
index 9fb445e..fa08d3f 100644
--- a/src/dm_sba.sv
+++ b/src/dm_sba.sv
@@ -96,16 +96,16 @@ module dm_sba #(
         // generate byte enable mask
         case (sbaccess_i)
           3'b000: begin
-            if (BusWidth == 64) be[ sbaddress_i[2:0]] = '1;
-            else                be[ sbaddress_i[1:0]] = '1;
+            if (BusWidth == 32'd64) be[ sbaddress_i[2:0]] = '1;
+            else                    be[ sbaddress_i[1:0]] = '1;
           end
           3'b001: begin
-            if (BusWidth == 64) be[{sbaddress_i[2:1], 1'b0} +: 2] = '1;
-            else                be[{sbaddress_i[1:1], 1'b0} +: 2] = '1;
+            if (BusWidth == 32'd64) be[{sbaddress_i[2:1], 1'b0} +: 2] = '1;
+            else                    be[{sbaddress_i[1:1], 1'b0} +: 2] = '1;
           end
           3'b010: begin
-            if (BusWidth == 64) be[{sbaddress_i[2:2], 2'b0} +: 4] = '1;
-            else                be = '1;
+            if (BusWidth == 32'd64) be[{sbaddress_i[2:2], 2'b0} +: 4] = '1;
+            else                    be = '1;
           end
           3'b011: be = '1;
           default:;
diff --git a/src/dmi_jtag_tap.sv b/src/dmi_jtag_tap.sv
index a6fd191..f8b282a 100644
--- a/src/dmi_jtag_tap.sv
+++ b/src/dmi_jtag_tap.sv
@@ -102,7 +102,7 @@ module dmi_jtag_tap #(
 
     // capture IR register
     if (capture_ir) begin
-      jtag_ir_shift_d =  'b0101;
+      jtag_ir_shift_d =  IrLength'(4'b0101);
     end
 
     // update IR register
@@ -155,10 +155,10 @@ module dmi_jtag_tap #(
                       dmihardreset : 1'b0,
                       dmireset     : 1'b0,
                       zero0        : '0,
-                      idle         : 'd1, // 1: Enter Run-Test/Idle and leave it immediately
+                      idle         : 3'd1, // 1: Enter Run-Test/Idle and leave it immediately
                       dmistat      : dmi_error_i, // 0: No error, 1: Op failed, 2: too fast
-                      abits        : 'd7, // The size of address in dmi
-                      version      : 'd1  // Version described in spec version 0.13 (and later?)
+                      abits        : 6'd7, // The size of address in dmi
+                      version      : 4'd1  // Version described in spec version 0.13 (and later?)
                     };
       end
     end
-- 
2.23.0.866.gb869b98d4c-goog