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opensecura / 3p / lowrisc / opentitan / 39ebbfebdeaf9fe85a375a87add422356f2bdbb6 / . / hw / top_earlgrey / data / autogen / top_earlgrey.gen.hjson
blob: d994ee09d05608e1e7ba3eb2e602bed11969f31a [file] [log] [blame]
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
//
// util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson \
// -o hw/top_earlgrey/ \
// --hjson-only \
// --rnd_cnst_seed 4881560218908238235
{
name: earlgrey
type: top
rnd_cnst_seed: 4881560218908238235
datawidth: "32"
power:
{
domains:
[
Aon
"0"
]
default: "0"
}
clocks:
{
hier_paths:
{
top: clkmgr_aon_clocks.
ext: ""
lpg: clkmgr_aon_cg_en.
}
srcs:
[
{
name: main
aon: no
freq: "100000000"
ref: false
}
{
name: io
aon: no
freq: "96000000"
ref: false
}
{
name: usb
aon: no
freq: "48000000"
ref: false
}
{
name: aon
aon: yes
freq: "200000"
ref: true
}
]
derived_srcs:
[
{
name: io_div2
aon: no
freq: "48000000"
ref: false
div: "2"
src: io
}
{
name: io_div4
aon: no
freq: "24000000"
ref: false
div: "4"
src: io
}
]
groups:
[
{
name: ast
src: ext
sw_cg: no
unique: no
clocks:
{
clk_main_i: main
clk_io_i: io
clk_usb_i: usb
clk_aon_i: aon
}
}
{
name: powerup
src: top
sw_cg: no
unique: no
clocks:
{
clk_io_div4_powerup: io_div4
clk_aon_powerup: aon
clk_main_powerup: main
clk_io_powerup: io
clk_usb_powerup: usb
clk_io_div2_powerup: io_div2
}
}
{
name: trans
src: top
sw_cg: hint
unique: yes
clocks:
{
clk_main_aes: main
clk_main_hmac: main
clk_main_kmac: main
clk_main_otbn: main
}
}
{
name: infra
src: top
sw_cg: no
unique: no
clocks:
{
clk_io_div4_infra: io_div4
clk_main_infra: main
clk_usb_infra: usb
clk_io_infra: io
clk_io_div2_infra: io_div2
}
}
{
name: secure
src: top
sw_cg: no
unique: no
clocks:
{
clk_io_div4_secure: io_div4
clk_main_secure: main
clk_aon_secure: aon
}
}
{
name: peri
src: top
sw_cg: yes
unique: no
clocks:
{
clk_io_div4_peri: io_div4
clk_io_div2_peri: io_div2
clk_io_peri: io
clk_usb_peri: usb
clk_aon_peri: aon
}
}
{
name: timers
src: top
sw_cg: no
unique: no
clocks:
{
clk_io_div4_timers: io_div4
clk_aon_timers: aon
}
}
]
}
resets:
{
hier_paths:
{
top: rstmgr_aon_resets.
ext: ""
lpg: rstmgr_aon_rst_en.
}
nodes:
[
{
name: por_aon
gen: false
type: top
domains:
[
"0"
Aon
]
shadowed: false
sw: false
path: rstmgr_aon_resets.rst_por_aon_n
clock: aon
}
{
name: lc_src
gen: false
type: int
domains: []
shadowed: false
sw: false
path: ""
clock: io_div4
}
{
name: sys_src
gen: false
type: int
domains: []
shadowed: false
sw: false
path: ""
clock: io_div4
}
{
name: por
gen: true
type: top
domains:
[
Aon
]
shadowed: false
sw: false
path: rstmgr_aon_resets.rst_por_n
parent: por_aon
clock: main
}
{
name: por_io
gen: true
type: top
domains:
[
Aon
]
shadowed: false
sw: false
path: rstmgr_aon_resets.rst_por_io_n
parent: por_aon
clock: io
}
{
name: por_io_div2
gen: true
type: top
domains:
[
Aon
]
shadowed: false
sw: false
path: rstmgr_aon_resets.rst_por_io_div2_n
parent: por_aon
clock: io_div2
}
{
name: por_io_div4
gen: true
type: top
domains:
[
Aon
]
shadowed: false
sw: false
path: rstmgr_aon_resets.rst_por_io_div4_n
parent: por_aon
clock: io_div4
}
{
name: por_usb
gen: true
type: top
domains:
[
Aon
]
shadowed: false
sw: false
path: rstmgr_aon_resets.rst_por_usb_n
parent: por_aon
clock: usb
}
{
name: lc
gen: true
type: top
domains:
[
"0"
Aon
]
shadowed: true
sw: false
path: rstmgr_aon_resets.rst_lc_n
parent: lc_src
clock: main
}
{
name: lc_aon
gen: true
type: top
domains:
[
Aon
]
shadowed: false
sw: false
path: rstmgr_aon_resets.rst_lc_aon_n
parent: lc_src
clock: aon
}
{
name: lc_io
gen: true
type: top
domains:
[
Aon
"0"
]
shadowed: false
sw: false
path: rstmgr_aon_resets.rst_lc_io_n
parent: lc_src
clock: io
}
{
name: lc_io_div2
gen: true
type: top
domains:
[
Aon
"0"
]
shadowed: false
sw: false
path: rstmgr_aon_resets.rst_lc_io_div2_n
parent: lc_src
clock: io_div2
}
{
name: lc_io_div4
gen: true
type: top
domains:
[
"0"
Aon
]
shadowed: true
sw: false
path: rstmgr_aon_resets.rst_lc_io_div4_n
parent: lc_src
clock: io_div4
}
{
name: lc_usb
gen: true
type: top
domains:
[
Aon
"0"
]
shadowed: false
sw: false
path: rstmgr_aon_resets.rst_lc_usb_n
parent: lc_src
clock: usb
}
{
name: sys
gen: true
type: top
domains:
[
"0"
]
shadowed: false
sw: false
path: rstmgr_aon_resets.rst_sys_n
parent: sys_src
clock: main
}
{
name: sys_io_div4
gen: true
type: top
domains:
[
Aon
]
shadowed: false
sw: false
path: rstmgr_aon_resets.rst_sys_io_div4_n
parent: sys_src
clock: io_div4
}
{
name: spi_device
gen: true
type: top
domains:
[
"0"
]
shadowed: false
sw: true
path: rstmgr_aon_resets.rst_spi_device_n
parent: lc_src
clock: io_div4
}
{
name: spi_host0
gen: true
type: top
domains:
[
"0"
]
shadowed: false
sw: true
path: rstmgr_aon_resets.rst_spi_host0_n
parent: lc_src
clock: io
}
{
name: spi_host1
gen: true
type: top
domains:
[
"0"
]
shadowed: false
sw: true
path: rstmgr_aon_resets.rst_spi_host1_n
parent: lc_src
clock: io_div2
}
{
name: usb
gen: true
type: top
domains:
[
"0"
]
shadowed: false
sw: true
path: rstmgr_aon_resets.rst_usb_n
parent: lc_src
clock: usb
}
{
name: usb_aon
gen: true
type: top
domains:
[
"0"
]
shadowed: false
sw: true
path: rstmgr_aon_resets.rst_usb_aon_n
parent: lc_src
clock: aon
}
{
name: i2c0
gen: true
type: top
domains:
[
"0"
]
shadowed: false
sw: true
path: rstmgr_aon_resets.rst_i2c0_n
parent: lc_src
clock: io_div4
}
{
name: i2c1
gen: true
type: top
domains:
[
"0"
]
shadowed: false
sw: true
path: rstmgr_aon_resets.rst_i2c1_n
parent: lc_src
clock: io_div4
}
{
name: i2c2
gen: true
type: top
domains:
[
"0"
]
shadowed: false
sw: true
path: rstmgr_aon_resets.rst_i2c2_n
parent: lc_src
clock: io_div4
}
]
}
num_cores: "1"
module:
[
{
name: uart0
type: uart
clock_srcs:
{
clk_i: io_div4
}
clock_group: peri
reset_connections:
{
rst_ni:
{
name: lc_io_div4
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain:
[
"0"
]
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: uart0
default: ""
end_idx: -1
top_signame: uart0_tl
index: -1
}
]
base_addrs:
{
null: 0x40000000
}
}
{
name: uart1
type: uart
clock_srcs:
{
clk_i: io_div4
}
clock_group: peri
reset_connections:
{
rst_ni:
{
name: lc_io_div4
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain:
[
"0"
]
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: uart1
default: ""
end_idx: -1
top_signame: uart1_tl
index: -1
}
]
base_addrs:
{
null: 0x40010000
}
}
{
name: uart2
type: uart
clock_srcs:
{
clk_i: io_div4
}
clock_group: peri
reset_connections:
{
rst_ni:
{
name: lc_io_div4
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain:
[
"0"
]
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: uart2
default: ""
end_idx: -1
top_signame: uart2_tl
index: -1
}
]
base_addrs:
{
null: 0x40020000
}
}
{
name: uart3
type: uart
clock_srcs:
{
clk_i: io_div4
}
clock_group: peri
reset_connections:
{
rst_ni:
{
name: lc_io_div4
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain:
[
"0"
]
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: uart3
default: ""
end_idx: -1
top_signame: uart3_tl
index: -1
}
]
base_addrs:
{
null: 0x40030000
}
}
{
name: gpio
type: gpio
clock_srcs:
{
clk_i: io_div4
}
clock_group: peri
reset_connections:
{
rst_ni:
{
name: lc_io_div4
domain: "0"
}
}
param_decl:
{
GpioAsyncOn: "1"
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain:
[
"0"
]
memory: {}
param_list:
[
{
name: GpioAsyncOn
desc: Instantiates 2-flop synchronizers on all GPIO inputs if set to 1.
type: bit
default: "1"
expose: "true"
name_top: GpioGpioAsyncOn
}
]
inter_signal_list:
[
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: gpio
default: ""
end_idx: -1
top_signame: gpio_tl
index: -1
}
]
base_addrs:
{
null: 0x40040000
}
}
{
name: spi_device
type: spi_device
clock_srcs:
{
clk_i: io_div4
scan_clk_i: io_div2
}
clock_group: peri
reset_connections:
{
rst_ni:
{
name: spi_device
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
scan_clk_i: clkmgr_aon_clocks.clk_io_div2_peri
}
domain:
[
"0"
]
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: ram_cfg
struct: ram_2p_cfg
package: prim_ram_2p_pkg
type: uni
act: rcv
width: 1
inst_name: spi_device
default: ""
top_signame: ast_ram_2p_cfg
index: -1
}
{
name: passthrough
struct: passthrough
package: spi_device_pkg
type: req_rsp
act: req
width: 1
inst_name: spi_device
default: ""
end_idx: -1
top_signame: spi_device_passthrough
index: -1
}
{
name: mbist_en
struct: logic
type: uni
act: rcv
width: 1
inst_name: spi_device
index: -1
}
{
name: sck_monitor
struct: logic
type: uni
act: req
width: 1
inst_name: spi_device
default: ""
package: ""
external: true
top_signame: sck_monitor
conn_type: false
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: spi_device
default: ""
end_idx: -1
top_signame: spi_device_tl
index: -1
}
]
base_addrs:
{
null: 0x40050000
}
}
{
name: i2c0
type: i2c
clock_srcs:
{
clk_i: io_div4
}
clock_group: peri
reset_connections:
{
rst_ni:
{
name: i2c0
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain:
[
"0"
]
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: i2c0
default: ""
end_idx: -1
top_signame: i2c0_tl
index: -1
}
]
base_addrs:
{
null: 0x40080000
}
}
{
name: i2c1
type: i2c
clock_srcs:
{
clk_i: io_div4
}
clock_group: peri
reset_connections:
{
rst_ni:
{
name: i2c1
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain:
[
"0"
]
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: i2c1
default: ""
end_idx: -1
top_signame: i2c1_tl
index: -1
}
]
base_addrs:
{
null: 0x40090000
}
}
{
name: i2c2
type: i2c
clock_srcs:
{
clk_i: io_div4
}
clock_group: peri
reset_connections:
{
rst_ni:
{
name: i2c2
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain:
[
"0"
]
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: i2c2
default: ""
end_idx: -1
top_signame: i2c2_tl
index: -1
}
]
base_addrs:
{
null: 0x400A0000
}
}
{
name: pattgen
type: pattgen
clock_srcs:
{
clk_i: io_div4
}
clock_group: peri
reset_connections:
{
rst_ni:
{
name: lc_io_div4
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain:
[
"0"
]
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: pattgen
default: ""
end_idx: -1
top_signame: pattgen_tl
index: -1
}
]
base_addrs:
{
null: 0x400E0000
}
}
{
name: rv_timer
type: rv_timer
clock_srcs:
{
clk_i: io_div4
}
clock_group: timers
reset_connections:
{
rst_ni:
{
name: lc_io_div4
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_timers
}
domain:
[
"0"
]
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: rv_timer
default: ""
end_idx: -1
top_signame: rv_timer_tl
index: -1
}
]
base_addrs:
{
null: 0x40100000
}
}
{
name: otp_ctrl
type: otp_ctrl
clock_srcs:
{
clk_i: io_div4
clk_edn_i: main
}
clock_group: secure
reset_connections:
{
rst_ni:
{
name: lc_io_div4
domain: "0"
}
rst_edn_ni:
{
name: lc
domain: "0"
}
}
base_addrs:
{
core: 0x40130000
prim: 0x40132000
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_secure
clk_edn_i: clkmgr_aon_clocks.clk_main_secure
}
domain:
[
"0"
]
param_decl: {}
memory: {}
param_list:
[
{
name: MemInitFile
desc: VMEM file to initialize the OTP macro.
type: ""
default: '''""'''
expose: "true"
name_top: OtpCtrlMemInitFile
}
{
name: RndCnstLfsrSeed
desc: Compile-time random bits for initial LFSR seed
type: otp_ctrl_pkg::lfsr_seed_t
randcount: 40
randtype: data
name_top: RndCnstOtpCtrlLfsrSeed
default: 0xcb0157a3ac
randwidth: 40
}
{
name: RndCnstLfsrPerm
desc: Compile-time random permutation for LFSR output
type: otp_ctrl_pkg::lfsr_perm_t
randcount: 40
randtype: perm
name_top: RndCnstOtpCtrlLfsrPerm
default: 0x3946df8032263d64e474a1a110541e61a55770d0a33110222592c19479d2
randwidth: 240
}
{
name: RndCnstScrmblKeyInit
desc: Compile-time random permutation for scrambling key/nonce register reset value
type: otp_ctrl_pkg::scrmbl_key_init_t
randcount: 256
randtype: data
name_top: RndCnstOtpCtrlScrmblKeyInit
default: 0x605fefe9977b00b6fdc21d577a172d047dcf0eebbdd268afd4e2506df1d0603f
randwidth: 256
}
]
inter_signal_list:
[
{
name: otp_ext_voltage_h
struct: ""
type: io
act: none
width: 1
default: "'0"
inst_name: otp_ctrl
package: ""
external: true
top_signame: otp_ext_voltage_h
conn_type: false
index: -1
}
{
name: otp_ast_pwr_seq
desc: Power sequencing signals to AST (VDD domain).
struct: otp_ast_req
package: otp_ctrl_pkg
type: uni
act: req
width: 1
default: "'0"
inst_name: otp_ctrl
external: true
top_signame: otp_ctrl_otp_ast_pwr_seq
conn_type: false
index: -1
}
{
name: otp_ast_pwr_seq_h
desc: Power sequencing signals coming from AST (VCC domain).
struct: otp_ast_rsp
package: otp_ctrl_pkg
type: uni
act: rcv
width: 1
default: "'0"
inst_name: otp_ctrl
external: true
top_signame: otp_ctrl_otp_ast_pwr_seq_h
conn_type: false
index: -1
}
{
name: edn
desc: Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation.
struct: edn
package: edn_pkg
type: req_rsp
act: req
width: 1
inst_name: otp_ctrl
default: ""
top_signame: edn0_edn
index: 1
}
{
name: pwr_otp
desc: Initialization request/acknowledge from/to power manager.
struct: pwr_otp
package: pwrmgr_pkg
type: req_rsp
act: rsp
width: 1
default: "'0"
inst_name: otp_ctrl
top_signame: pwrmgr_aon_pwr_otp
index: -1
}
{
name: lc_otp_vendor_test
desc: Vendor test control signals from/to the life cycle TAP.
struct: lc_otp_vendor_test
package: otp_ctrl_pkg
type: req_rsp
act: rsp
width: 1
default: "'0"
inst_name: otp_ctrl
top_signame: lc_ctrl_lc_otp_vendor_test
index: -1
}
{
name: lc_otp_program
desc: Life cycle state transition interface.
struct: lc_otp_program
package: otp_ctrl_pkg
type: req_rsp
act: rsp
width: 1
default: "'0"
inst_name: otp_ctrl
top_signame: lc_ctrl_lc_otp_program
index: -1
}
{
name: otp_lc_data
desc:
'''
Life cycle state output holding the current life cycle state,
the value of the transition counter and the tokens needed for life cycle transitions.
'''
struct: otp_lc_data
package: otp_ctrl_pkg
type: uni
act: req
width: 1
default: "'0"
inst_name: otp_ctrl
end_idx: -1
top_type: broadcast
top_signame: otp_ctrl_otp_lc_data
index: -1
}
{
name: lc_escalate_en
desc:
'''
Life cycle escalation enable coming from life cycle controller.
This signal moves all FSMs within OTP into the error state.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: otp_ctrl
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: lc_creator_seed_sw_rw_en
desc:
'''
Provision enable qualifier coming from life cycle controller.
This signal enables SW read / write access to the RMA_TOKEN and CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: otp_ctrl
top_signame: lc_ctrl_lc_creator_seed_sw_rw_en
index: -1
}
{
name: lc_seed_hw_rd_en
desc:
'''
Seed read enable coming from life cycle controller.
This signal enables HW read access to the CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: otp_ctrl
top_signame: lc_ctrl_lc_seed_hw_rd_en
index: -1
}
{
name: lc_dft_en
desc:
'''
Test enable qualifier coming from from life cycle controller.
This signals enables the TL-UL access port to the proprietary OTP IP.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: otp_ctrl
top_signame: lc_ctrl_lc_dft_en
index: -1
}
{
name: lc_check_byp_en
desc:
'''
Life cycle partition check bypass signal.
This signal causes the life cycle partition to bypass consistency checks during life cycle state transitions in order to prevent spurious consistency check failures.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: otp_ctrl
top_signame: lc_ctrl_lc_check_byp_en
index: -1
}
{
name: otp_keymgr_key
desc: Key output to the key manager holding CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1.
struct: otp_keymgr_key
package: otp_ctrl_pkg
type: uni
act: req
width: 1
default: "'0"
inst_name: otp_ctrl
end_idx: -1
top_type: broadcast
top_signame: otp_ctrl_otp_keymgr_key
index: -1
}
{
name: flash_otp_key
desc: Key derivation interface for FLASH scrambling.
struct: flash_otp_key
package: otp_ctrl_pkg
type: req_rsp
act: rsp
width: 1
default: "'0"
inst_name: otp_ctrl
top_signame: flash_ctrl_otp
index: -1
}
{
name: sram_otp_key
desc: Array with key derivation interfaces for SRAM scrambling devices.
struct: sram_otp_key
package: otp_ctrl_pkg
type: req_rsp
act: rsp
width: 3
default: "'0"
inst_name: otp_ctrl
end_idx: -1
top_type: one-to-N
top_signame: otp_ctrl_sram_otp_key
index: -1
}
{
name: otbn_otp_key
desc: Key derivation interface for OTBN scrambling devices.
struct: otbn_otp_key
package: otp_ctrl_pkg
type: req_rsp
act: rsp
width: 1
default: "'0"
inst_name: otp_ctrl
end_idx: -1
top_signame: otp_ctrl_otbn_otp_key
index: -1
}
{
name: otp_hw_cfg
desc: Output of the HW_CFG partition.
struct: otp_hw_cfg
package: otp_ctrl_part_pkg
type: uni
act: req
width: 1
default: "'0"
inst_name: otp_ctrl
top_signame: otp_ctrl_otp_hw_cfg
index: -1
}
{
name: obs_ctrl
desc: AST observability control signals.
struct: ast_obs_ctrl
package: ast_pkg
type: uni
act: rcv
width: 1
inst_name: otp_ctrl
default: ""
top_signame: ast_obs_ctrl
index: -1
}
{
name: otp_obs
desc: AST observability bus.
struct: logic
type: uni
act: req
width: 8
inst_name: otp_ctrl
default: ""
package: ""
external: true
top_signame: otp_obs
conn_type: false
index: -1
}
{
name: core_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: otp_ctrl
default: ""
end_idx: -1
top_signame: otp_ctrl_core_tl
index: -1
}
{
name: prim_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: otp_ctrl
default: ""
end_idx: -1
top_signame: otp_ctrl_prim_tl
index: -1
}
]
}
{
name: lc_ctrl
type: lc_ctrl
clock_srcs:
{
clk_i: io_div4
clk_kmac_i: main
}
clock_group: secure
reset_connections:
{
rst_ni:
{
name: lc_io_div4
domain: "0"
}
rst_kmac_ni:
{
name: lc
domain: "0"
}
}
param_decl:
{
ChipGen: 16'h 0000
ChipRev: 16'h 0000
IdcodeValue: jtag_id_pkg::JTAG_IDCODE
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_secure
clk_kmac_i: clkmgr_aon_clocks.clk_main_secure
}
domain:
[
"0"
]
memory: {}
param_list:
[
{
name: RndCnstLcKeymgrDivInvalid
desc: Compile-time random bits for lc state group diversification value
type: lc_ctrl_pkg::lc_keymgr_div_t
randcount: 128
randtype: data
name_top: RndCnstLcCtrlLcKeymgrDivInvalid
default: 0x9cd62f178adc74d53d8ad0b600e7a1dd
randwidth: 128
}
{
name: RndCnstLcKeymgrDivTestDevRma
desc: Compile-time random bits for lc state group diversification value
type: lc_ctrl_pkg::lc_keymgr_div_t
randcount: 128
randtype: data
name_top: RndCnstLcCtrlLcKeymgrDivTestDevRma
default: 0x2f1a43c03dd4ff9b887ab7521ca6cbd8
randwidth: 128
}
{
name: RndCnstLcKeymgrDivProduction
desc: Compile-time random bits for lc state group diversification value
type: lc_ctrl_pkg::lc_keymgr_div_t
randcount: 128
randtype: data
name_top: RndCnstLcCtrlLcKeymgrDivProduction
default: 0xd7107bab98b075743f7aeba81e1c4ec8
randwidth: 128
}
{
name: RndCnstInvalidTokens
desc: Compile-time random bits used for invalid tokens in the token mux
type: lc_ctrl_pkg::lc_token_mux_t
randcount: 1024
randtype: data
name_top: RndCnstLcCtrlInvalidTokens
default: 0xebdeee2911062e039f8c7e1afa78a1d42886cc89ae759cf865b22a5f28de2eca36afc2e8a402302cbdcf2b4819afaa0a11cb68371eef174d98315696c49a8ef53c96f11e4f43ffd421e456b4d6a9d1d2ab4a836f1545ebf50ff87bc3fe8473a3b8a698eb44c3b5821fc5bae3e1bd59723b69b2d7b5330424c30845eb1f7a5eef
randwidth: 1024
}
{
name: ChipGen
desc: Chip generation number.
type: logic [15:0]
default: 16'h 0000
expose: "true"
name_top: LcCtrlChipGen
}
{
name: ChipRev
desc: Chip revision number.
type: logic [15:0]
default: 16'h 0000
expose: "true"
name_top: LcCtrlChipRev
}
{
name: IdcodeValue
desc: JTAG ID code.
type: logic [31:0]
default: jtag_id_pkg::JTAG_IDCODE
expose: "true"
name_top: LcCtrlIdcodeValue
}
]
inter_signal_list:
[
{
name: jtag
struct: jtag
package: jtag_pkg
type: req_rsp
act: rsp
width: 1
inst_name: lc_ctrl
default: ""
top_signame: pinmux_aon_lc_jtag
index: -1
}
{
name: esc_scrap_state0_tx
struct: esc_tx
package: prim_esc_pkg
type: uni
act: rcv
width: 1
inst_name: lc_ctrl
default: ""
top_signame: alert_handler_esc_tx
index: 1
}
{
name: esc_scrap_state0_rx
struct: esc_rx
package: prim_esc_pkg
type: uni
act: req
width: 1
inst_name: lc_ctrl
default: ""
top_signame: alert_handler_esc_rx
index: 1
}
{
name: esc_scrap_state1_tx
struct: esc_tx
package: prim_esc_pkg
type: uni
act: rcv
width: 1
inst_name: lc_ctrl
default: ""
top_signame: alert_handler_esc_tx
index: 2
}
{
name: esc_scrap_state1_rx
struct: esc_rx
package: prim_esc_pkg
type: uni
act: req
width: 1
inst_name: lc_ctrl
default: ""
top_signame: alert_handler_esc_rx
index: 2
}
{
name: pwr_lc
struct: pwr_lc
package: pwrmgr_pkg
type: req_rsp
act: rsp
width: 1
inst_name: lc_ctrl
default: ""
top_signame: pwrmgr_aon_pwr_lc
index: -1
}
{
name: lc_otp_vendor_test
struct: lc_otp_vendor_test
package: otp_ctrl_pkg
type: req_rsp
act: req
width: 1
default: "'0"
inst_name: lc_ctrl
end_idx: -1
top_signame: lc_ctrl_lc_otp_vendor_test
index: -1
}
{
name: otp_lc_data
struct: otp_lc_data
package: otp_ctrl_pkg
type: uni
act: rcv
width: 1
default: otp_ctrl_pkg::OTP_LC_DATA_DEFAULT
inst_name: lc_ctrl
top_signame: otp_ctrl_otp_lc_data
index: -1
}
{
name: lc_otp_program
struct: lc_otp_program
package: otp_ctrl_pkg
type: req_rsp
act: req
width: 1
default: "'0"
inst_name: lc_ctrl
end_idx: -1
top_signame: lc_ctrl_lc_otp_program
index: -1
}
{
name: kmac_data
struct: app
package: kmac_pkg
type: req_rsp
act: req
width: 1
default: "'0"
inst_name: lc_ctrl
top_signame: kmac_app
index: 1
}
{
name: lc_dft_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_dft_en
index: -1
}
{
name: lc_nvm_debug_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_nvm_debug_en
index: -1
}
{
name: lc_hw_debug_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
name: lc_cpu_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_cpu_en
index: -1
}
{
name: lc_keymgr_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_keymgr_en
index: -1
}
{
name: lc_escalate_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: lc_clk_byp_req
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_clk_byp_req
index: -1
}
{
name: lc_clk_byp_ack
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_clk_byp_ack
index: -1
}
{
name: lc_flash_rma_req
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_flash_rma_req
index: -1
}
{
name: lc_flash_rma_seed
struct: lc_flash_rma_seed
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: "'0"
inst_name: lc_ctrl
top_signame: flash_ctrl_rma_seed
index: -1
}
{
name: lc_flash_rma_ack
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
top_signame: otbn_lc_rma_ack
index: -1
}
{
name: lc_check_byp_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_check_byp_en
index: -1
}
{
name: lc_creator_seed_sw_rw_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_creator_seed_sw_rw_en
index: -1
}
{
name: lc_owner_seed_sw_rw_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_owner_seed_sw_rw_en
index: -1
}
{
name: lc_iso_part_sw_rd_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_iso_part_sw_rd_en
index: -1
}
{
name: lc_iso_part_sw_wr_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_iso_part_sw_wr_en
index: -1
}
{
name: lc_seed_hw_rd_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_seed_hw_rd_en
index: -1
}
{
name: lc_keymgr_div
struct: lc_keymgr_div
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: "'0"
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_keymgr_div
index: -1
}
{
name: otp_device_id
struct: otp_device_id
package: otp_ctrl_pkg
type: uni
act: rcv
width: 1
default: "'0"
inst_name: lc_ctrl
top_signame: lc_ctrl_otp_device_id
index: -1
}
{
name: otp_manuf_state
struct: otp_manuf_state
package: otp_ctrl_pkg
type: uni
act: rcv
width: 1
default: "'0"
inst_name: lc_ctrl
top_signame: lc_ctrl_otp_manuf_state
index: -1
}
{
name: hw_rev
struct: lc_hw_rev
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: "'0"
inst_name: lc_ctrl
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: lc_ctrl
default: ""
end_idx: -1
top_signame: lc_ctrl_tl
index: -1
}
]
base_addrs:
{
null: 0x40140000
}
}
{
name: alert_handler
type: alert_handler
clock_srcs:
{
clk_i: io_div4
clk_edn_i: main
}
clock_group: secure
reset_connections:
{
rst_ni:
{
name: lc_io_div4
domain: "0"
}
rst_edn_ni:
{
name: lc
domain: "0"
}
}
attr: ipgen
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_secure
clk_edn_i: clkmgr_aon_clocks.clk_main_secure
}
domain:
[
"0"
]
param_decl: {}
memory: {}
param_list:
[
{
name: RndCnstLfsrSeed
desc: Compile-time random bits for initial LFSR seed
type: alert_pkg::lfsr_seed_t
randcount: 32
randtype: data
name_top: RndCnstAlertHandlerLfsrSeed
default: 0x762a1f91
randwidth: 32
}
{
name: RndCnstLfsrPerm
desc: Compile-time random permutation for LFSR output
type: alert_pkg::lfsr_perm_t
randcount: 32
randtype: perm
name_top: RndCnstAlertHandlerLfsrPerm
default: 0x375ed89d2a1d32862f7a7785f940950cc1cbdb05
randwidth: 160
}
]
inter_signal_list:
[
{
name: crashdump
struct: alert_crashdump
package: alert_pkg
type: uni
act: req
width: 1
inst_name: alert_handler
default: ""
end_idx: -1
top_type: broadcast
top_signame: alert_handler_crashdump
index: -1
}
{
name: edn
struct: edn
package: edn_pkg
type: req_rsp
act: req
width: 1
inst_name: alert_handler
default: ""
top_signame: edn0_edn
index: 4
}
{
name: esc_rx
struct: esc_rx
package: prim_esc_pkg
type: uni
act: rcv
width: 4
inst_name: alert_handler
default: ""
end_idx: -1
top_type: one-to-N
top_signame: alert_handler_esc_rx
index: -1
}
{
name: esc_tx
struct: esc_tx
package: prim_esc_pkg
type: uni
act: req
width: 4
inst_name: alert_handler
default: ""
end_idx: -1
top_type: one-to-N
top_signame: alert_handler_esc_tx
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: alert_handler
default: ""
end_idx: -1
top_signame: alert_handler_tl
index: -1
}
]
base_addrs:
{
null: 0x40150000
}
}
{
name: spi_host0
type: spi_host
clock_srcs:
{
clk_i: io
}
clock_group: peri
reset_connections:
{
rst_ni:
{
name: spi_host0
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_peri
}
domain:
[
"0"
]
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: passthrough
struct: passthrough
package: spi_device_pkg
type: req_rsp
act: rsp
width: 1
inst_name: spi_host0
default: ""
top_signame: spi_device_passthrough
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: spi_host0
default: ""
end_idx: -1
top_signame: spi_host0_tl
index: -1
}
]
base_addrs:
{
null: 0x40300000
}
}
{
name: spi_host1
type: spi_host
clock_srcs:
{
clk_i: io_div2
}
clock_group: peri
reset_connections:
{
rst_ni:
{
name: spi_host1
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div2_peri
}
domain:
[
"0"
]
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: passthrough
struct: passthrough
package: spi_device_pkg
type: req_rsp
act: rsp
width: 1
inst_name: spi_host1
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: spi_host1
default: ""
end_idx: -1
top_signame: spi_host1_tl
index: -1
}
]
base_addrs:
{
null: 0x40310000
}
}
{
name: usbdev
type: usbdev
clock_srcs:
{
clk_i: usb
clk_aon_i: aon
}
clock_group: peri
reset_connections:
{
rst_ni:
{
name: usb
domain: "0"
}
rst_aon_ni:
{
name: usb_aon
domain: "0"
}
}
param_decl:
{
RcvrWakeTimeUs: "100"
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_usb_peri
clk_aon_i: clkmgr_aon_clocks.clk_aon_peri
}
domain:
[
"0"
]
memory: {}
param_list:
[
{
name: Stub
desc: Stub out the core of entropy_src logic
type: bit
default: "0"
expose: "true"
name_top: UsbdevStub
}
{
name: RcvrWakeTimeUs
desc: Maximum number of microseconds for the differential receiver to become operational
type: int
default: "100"
expose: "true"
name_top: UsbdevRcvrWakeTimeUs
}
]
inter_signal_list:
[
{
name: usb_rx_d
desc: USB RX data from an external differential receiver, if available
struct: logic
type: uni
act: rcv
width: 1
inst_name: usbdev
default: ""
package: ""
external: true
top_signame: usbdev_usb_rx_d
conn_type: false
index: -1
}
{
name: usb_tx_d
desc: USB transmit data value (not used if usb_tx_se0 is set)
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
external: true
top_signame: usbdev_usb_tx_d
conn_type: false
index: -1
}
{
name: usb_tx_se0
desc: Force transmission of a USB single-ended zero (i.e. both D+ and D- are low) regardless of usb_tx_d
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
external: true
top_signame: usbdev_usb_tx_se0
conn_type: false
index: -1
}
{
name: usb_tx_use_d_se0
desc: Use the usb_tx_d and usb_tx_se0 TX interface, instead of usb_dp_o and usb_dn_o
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
external: true
top_signame: usbdev_usb_tx_use_d_se0
conn_type: false
index: -1
}
{
name: usb_dp_pullup
desc: USB D+ pullup control
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_dp_pullup
index: -1
}
{
name: usb_dn_pullup
desc: USB D- pullup control
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_dn_pullup
index: -1
}
{
name: usb_rx_enable
desc: USB differential receiver enable
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
external: true
top_signame: usbdev_usb_rx_enable
conn_type: false
index: -1
}
{
name: usb_ref_val
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
external: true
top_signame: usbdev_usb_ref_val
conn_type: false
index: -1
}
{
name: usb_ref_pulse
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
external: true
top_signame: usbdev_usb_ref_pulse
conn_type: false
index: -1
}
{
name: usb_aon_suspend_req
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_aon_suspend_req
index: -1
}
{
name: usb_aon_wake_ack
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_aon_wake_ack
index: -1
}
{
name: usb_aon_bus_reset
struct: logic
type: uni
act: rcv
width: 1
inst_name: usbdev
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_aon_bus_reset
index: -1
}
{
name: usb_aon_sense_lost
struct: logic
type: uni
act: rcv
width: 1
inst_name: usbdev
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_aon_sense_lost
index: -1
}
{
name: usb_aon_wake_detect_active
struct: logic
type: uni
act: rcv
width: 1
inst_name: usbdev
default: ""
package: ""
top_signame: pinmux_aon_usbdev_wake_detect_active
index: -1
}
{
name: ram_cfg
struct: ram_2p_cfg
package: prim_ram_2p_pkg
type: uni
act: rcv
width: 1
inst_name: usbdev
default: ""
top_signame: ast_ram_2p_cfg
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: usbdev
default: ""
end_idx: -1
top_signame: usbdev_tl
index: -1
}
]
base_addrs:
{
null: 0x40320000
}
}
{
name: pwrmgr_aon
type: pwrmgr
clock_group: powerup
clock_srcs:
{
clk_i: io_div4
clk_slow_i: aon
clk_lc_i: io_div4
clk_esc_i:
{
clock: io_div4
group: secure
}
}
reset_connections:
{
rst_ni:
{
name: por_io_div4
domain: Aon
}
rst_main_ni:
{
name: por_aon
domain: "0"
}
rst_lc_ni:
{
name: lc_io_div4
domain: Aon
}
rst_esc_ni:
{
name: lc_io_div4
domain: Aon
}
rst_slow_ni:
{
name: por_aon
domain: Aon
}
}
domain:
[
Aon
"0"
]
attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_powerup
clk_slow_i: clkmgr_aon_clocks.clk_aon_powerup
clk_lc_i: clkmgr_aon_clocks.clk_io_div4_powerup
clk_esc_i: clkmgr_aon_clocks.clk_io_div4_secure
}
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: pwr_ast
struct: pwr_ast
package: pwrmgr_pkg
type: req_rsp
act: req
width: 1
inst_name: pwrmgr_aon
default: ""
external: true
top_signame: pwrmgr_ast
conn_type: false
index: -1
}
{
name: pwr_rst
struct: pwr_rst
package: pwrmgr_pkg
type: req_rsp
act: req
width: 1
inst_name: pwrmgr_aon
default: ""
end_idx: -1
top_signame: pwrmgr_aon_pwr_rst
index: -1
}
{
name: pwr_clk
struct: pwr_clk
package: pwrmgr_pkg
type: req_rsp
act: req
width: 1
inst_name: pwrmgr_aon
default: ""
end_idx: -1
top_signame: pwrmgr_aon_pwr_clk
index: -1
}
{
name: pwr_otp
struct: pwr_otp
package: pwrmgr_pkg
type: req_rsp
act: req
width: 1
inst_name: pwrmgr_aon
default: ""
end_idx: -1
top_signame: pwrmgr_aon_pwr_otp
index: -1
}
{
name: pwr_lc
struct: pwr_lc
package: pwrmgr_pkg
type: req_rsp
act: req
width: 1
inst_name: pwrmgr_aon
default: ""
end_idx: -1
top_signame: pwrmgr_aon_pwr_lc
index: -1
}
{
name: pwr_flash
struct: pwr_flash
package: pwrmgr_pkg
type: uni
act: rcv
width: 1
inst_name: pwrmgr_aon
default: ""
end_idx: -1
top_type: broadcast
top_signame: pwrmgr_aon_pwr_flash
index: -1
}
{
name: esc_rst_tx
struct: esc_tx
package: prim_esc_pkg
type: uni
act: rcv
width: 1
inst_name: pwrmgr_aon
default: ""
top_signame: alert_handler_esc_tx
index: 3
}
{
name: esc_rst_rx
struct: esc_rx
package: prim_esc_pkg
type: uni
act: req
width: 1
inst_name: pwrmgr_aon
default: ""
top_signame: alert_handler_esc_rx
index: 3
}
{
name: pwr_cpu
struct: pwr_cpu
package: pwrmgr_pkg
type: uni
act: rcv
width: 1
inst_name: pwrmgr_aon
default: ""
top_signame: rv_core_ibex_pwrmgr
index: -1
}
{
name: wakeups
struct: logic
type: uni
act: rcv
width: 6
inst_name: pwrmgr_aon
default: ""
package: ""
end_idx: -1
top_type: one-to-N
top_signame: pwrmgr_aon_wakeups
index: -1
}
{
name: rstreqs
struct: logic
type: uni
act: rcv
width: 2
inst_name: pwrmgr_aon
default: ""
package: ""
end_idx: -1
top_type: one-to-N
top_signame: pwrmgr_aon_rstreqs
index: -1
}
{
name: ndmreset_req
struct: logic
type: uni
act: rcv
width: 1
inst_name: pwrmgr_aon
default: ""
package: ""
top_signame: rv_dm_ndmreset_req
index: -1
}
{
name: strap
struct: logic
type: uni
act: req
width: 1
inst_name: pwrmgr_aon
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: pwrmgr_aon_strap
index: -1
}
{
name: low_power
struct: logic
type: uni
act: req
width: 1
inst_name: pwrmgr_aon
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: pwrmgr_aon_low_power
index: -1
}
{
name: rom_ctrl
struct: pwrmgr_data
package: rom_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: pwrmgr_aon
default: ""
top_signame: rom_ctrl_pwrmgr_data
index: -1
}
{
name: fetch_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
inst_name: pwrmgr_aon
default: ""
end_idx: -1
top_type: broadcast
top_signame: pwrmgr_aon_fetch_en
index: -1
}
{
name: lc_dft_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: pwrmgr_aon
default: ""
top_signame: lc_ctrl_lc_dft_en
index: -1
}
{
name: lc_hw_debug_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: pwrmgr_aon
default: ""
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
name: sw_rst_req
struct: mubi4
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
inst_name: pwrmgr_aon
default: ""
top_signame: rstmgr_aon_sw_rst_req
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: pwrmgr_aon
default: ""
end_idx: -1
top_signame: pwrmgr_aon_tl
index: -1
}
]
base_addrs:
{
null: 0x40400000
}
}
{
name: rstmgr_aon
type: rstmgr
clock_srcs:
{
clk_i:
{
clock: io_div4
group: powerup
}
clk_por_i: io_div4
clk_aon_i: aon
clk_main_i: main
clk_io_i: io
clk_usb_i: usb
clk_io_div2_i: io_div2
clk_io_div4_i: io_div4
}
clock_group: powerup
reset_connections:
{
rst_ni:
{
name: lc_io_div4
domain: Aon
}
rst_por_ni:
{
name: por_io_div4
domain: Aon
}
}
domain:
[
Aon
"0"
]
attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_powerup
clk_por_i: clkmgr_aon_clocks.clk_io_div4_powerup
clk_aon_i: clkmgr_aon_clocks.clk_aon_powerup
clk_main_i: clkmgr_aon_clocks.clk_main_powerup
clk_io_i: clkmgr_aon_clocks.clk_io_powerup
clk_usb_i: clkmgr_aon_clocks.clk_usb_powerup
clk_io_div2_i: clkmgr_aon_clocks.clk_io_div2_powerup
clk_io_div4_i: clkmgr_aon_clocks.clk_io_div4_powerup
}
param_decl: {}
memory: {}
param_list:
[
{
name: SecCheck
desc:
'''
When 1, enable rstmgr reset consistency checks.
When 0, there are no consistency checks.
'''
type: bit
default: 1'b1
expose: "true"
name_top: SecRstmgrAonCheck
}
{
name: SecMaxSyncDelay
desc: The maximum synchronization delay for parent / child reset checks.
type: int
default: "2"
expose: "true"
name_top: SecRstmgrAonMaxSyncDelay
}
]
inter_signal_list:
[
{
name: por_n
desc:
'''
Root power on reset signals from ast.
There is one root reset signal for each core power domain.
'''
struct: logic
type: uni
act: rcv
width: 2
inst_name: rstmgr_aon
default: ""
package: ""
external: true
top_signame: por_n
conn_type: false
index: -1
}
{
name: pwr
desc:
'''
Reset request signals from power manager.
Power manager can request for specific domains of the lc/sys reset tree to assert.
'''
struct: pwr_rst
type: req_rsp
act: rsp
width: 1
inst_name: rstmgr_aon
default: ""
package: pwrmgr_pkg
top_signame: pwrmgr_aon_pwr_rst
index: -1
}
{
name: resets
desc: Leaf resets fed to the system.
struct: rstmgr_out
package: rstmgr_pkg
type: uni
act: req
width: 1
inst_name: rstmgr_aon
default: ""
top_signame: rstmgr_aon_resets
index: -1
}
{
name: rst_en
desc: Low-power-group outputs used by alert handler.
struct: rstmgr_rst_en
package: rstmgr_pkg
type: uni
act: req
width: 1
inst_name: rstmgr_aon
default: ""
top_signame: rstmgr_aon_rst_en
index: -1
}
{
name: alert_dump
desc: Alert handler crash dump information.
struct: alert_crashdump
package: alert_pkg
type: uni
act: rcv
width: 1
inst_name: rstmgr_aon
default: ""
top_signame: alert_handler_crashdump
index: -1
}
{
name: cpu_dump
desc: Main processing element crash dump information.
struct: cpu_crash_dump
package: rv_core_ibex_pkg
type: uni
act: rcv
width: 1
inst_name: rstmgr_aon
default: ""
top_signame: rv_core_ibex_crash_dump
index: -1
}
{
name: sw_rst_req
desc: Software requested system reset to pwrmgr.
struct: mubi4
package: prim_mubi_pkg
type: uni
act: req
width: 1
inst_name: rstmgr_aon
default: ""
end_idx: -1
top_type: broadcast
top_signame: rstmgr_aon_sw_rst_req
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: rstmgr_aon
default: ""
end_idx: -1
top_signame: rstmgr_aon_tl
index: -1
}
]
base_addrs:
{
null: 0x40410000
}
}
{
name: clkmgr_aon
type: clkmgr
clock_srcs:
{
clk_i: io_div4
clk_main_i:
{
group: ast
clock: main
}
clk_io_i:
{
group: ast
clock: io
}
clk_usb_i:
{
group: ast
clock: usb
}
clk_aon_i:
{
group: ast
clock: aon
}
}
clock_group: powerup
reset_connections:
{
rst_ni:
{
name: lc_io_div4
domain: Aon
}
rst_aon_ni:
{
name: lc_aon
domain: Aon
}
rst_io_ni:
{
name: lc_io
domain: Aon
}
rst_io_div2_ni:
{
name: lc_io_div2
domain: Aon
}
rst_io_div4_ni:
{
name: lc_io_div4
domain: Aon
}
rst_main_ni:
{
name: lc
domain: Aon
}
rst_usb_ni:
{
name: lc_usb
domain: Aon
}
rst_root_ni:
{
name: por_io_div4
domain: Aon
}
rst_root_io_ni:
{
name: por_io
domain: Aon
}
rst_root_io_div2_ni:
{
name: por_io_div2
domain: Aon
}
rst_root_io_div4_ni:
{
name: por_io_div4
domain: Aon
}
rst_root_main_ni:
{
name: por
domain: Aon
}
rst_root_usb_ni:
{
name: por_usb
domain: Aon
}
}
domain:
[
Aon
]
attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_powerup
clk_main_i: clk_main_i
clk_io_i: clk_io_i
clk_usb_i: clk_usb_i
clk_aon_i: clk_aon_i
}
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: clocks
struct: clkmgr_out
package: clkmgr_pkg
type: uni
act: req
width: 1
inst_name: clkmgr_aon
default: ""
top_signame: clkmgr_aon_clocks
index: -1
}
{
name: cg_en
struct: clkmgr_cg_en
package: clkmgr_pkg
type: uni
act: req
width: 1
inst_name: clkmgr_aon
default: ""
top_signame: clkmgr_aon_cg_en
index: -1
}
{
name: lc_hw_debug_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: clkmgr_aon
default: ""
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
name: io_clk_byp_req
struct: mubi4
package: prim_mubi_pkg
type: uni
act: req
width: 1
inst_name: clkmgr_aon
default: ""
external: true
top_signame: io_clk_byp_req
conn_type: false
index: -1
}
{
name: io_clk_byp_ack
struct: mubi4
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
inst_name: clkmgr_aon
default: ""
external: true
top_signame: io_clk_byp_ack
conn_type: false
index: -1
}
{
name: all_clk_byp_req
struct: mubi4
package: prim_mubi_pkg
type: uni
act: req
width: 1
inst_name: clkmgr_aon
default: ""
external: true
top_signame: all_clk_byp_req
conn_type: false
index: -1
}
{
name: all_clk_byp_ack
struct: mubi4
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
inst_name: clkmgr_aon
default: ""
external: true
top_signame: all_clk_byp_ack
conn_type: false
index: -1
}
{
name: hi_speed_sel
struct: mubi4
package: prim_mubi_pkg
type: uni
act: req
width: 1
inst_name: clkmgr_aon
default: ""
external: true
top_signame: hi_speed_sel
conn_type: false
index: -1
}
{
name: div_step_down_req
struct: mubi4
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
inst_name: clkmgr_aon
default: ""
external: true
top_signame: div_step_down_req
conn_type: false
index: -1
}
{
name: lc_clk_byp_req
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: clkmgr_aon
default: ""
top_signame: lc_ctrl_lc_clk_byp_req
index: -1
}
{
name: lc_clk_byp_ack
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
inst_name: clkmgr_aon
default: ""
top_signame: lc_ctrl_lc_clk_byp_ack
index: -1
}
{
name: jitter_en
struct: mubi4
package: prim_mubi_pkg
type: uni
act: req
width: 1
inst_name: clkmgr_aon
default: ""
external: true
top_signame: clk_main_jitter_en
conn_type: false
index: -1
}
{
name: pwr
struct: pwr_clk
type: req_rsp
act: rsp
width: 1
inst_name: clkmgr_aon
default: ""
package: pwrmgr_pkg
top_signame: pwrmgr_aon_pwr_clk
index: -1
}
{
name: idle
struct: mubi4
package: prim_mubi_pkg
type: uni
act: rcv
width: 4
inst_name: clkmgr_aon
default: ""
end_idx: -1
top_type: one-to-N
top_signame: clkmgr_aon_idle
index: -1
}
{
name: calib_rdy
desc: Indicates clocks are calibrated and frequencies accurate
struct: mubi4
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
default: prim_mubi_pkg::MuBi4True
inst_name: clkmgr_aon
external: true
top_signame: calib_rdy
conn_type: false
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: clkmgr_aon
default: ""
end_idx: -1
top_signame: clkmgr_aon_tl
index: -1
}
]
base_addrs:
{
null: 0x40420000
}
}
{
name: sysrst_ctrl_aon
type: sysrst_ctrl
clock_srcs:
{
clk_i: io_div4
clk_aon_i: aon
}
clock_group: secure
reset_connections:
{
rst_ni:
{
name: lc_io_div4
domain: Aon
}
rst_aon_ni:
{
name: lc_aon
domain: Aon
}
}
domain:
[
Aon
]
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_secure
clk_aon_i: clkmgr_aon_clocks.clk_aon_secure
}
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: wkup_req
struct: logic
type: uni
act: req
width: 1
inst_name: sysrst_ctrl_aon
default: ""
package: ""
top_signame: pwrmgr_aon_wakeups
index: 0
}
{
name: rst_req
struct: logic
type: uni
act: req
width: 1
inst_name: sysrst_ctrl_aon
default: ""
package: ""
top_signame: pwrmgr_aon_rstreqs
index: 0
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: sysrst_ctrl_aon
default: ""
end_idx: -1
top_signame: sysrst_ctrl_aon_tl
index: -1
}
]
base_addrs:
{
null: 0x40430000
}
}
{
name: adc_ctrl_aon
type: adc_ctrl
clock_srcs:
{
clk_i: io_div4
clk_aon_i: aon
}
clock_group: peri
reset_connections:
{
rst_ni:
{
name: lc_io_div4
domain: Aon
}
rst_aon_ni:
{
name: lc_aon
domain: Aon
}
}
domain:
[
Aon
]
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
clk_aon_i: clkmgr_aon_clocks.clk_aon_peri
}
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: adc
struct: adc_ast
package: ast_pkg
type: req_rsp
act: req
width: 1
inst_name: adc_ctrl_aon
default: ""
external: true
top_signame: adc
conn_type: false
index: -1
}
{
name: wkup_req
struct: logic
type: uni
act: req
width: 1
inst_name: adc_ctrl_aon
default: ""
package: ""
top_signame: pwrmgr_aon_wakeups
index: 1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: adc_ctrl_aon
default: ""
end_idx: -1
top_signame: adc_ctrl_aon_tl
index: -1
}
]
base_addrs:
{
null: 0x40440000
}
}
{
name: pwm_aon
type: pwm
clock_srcs:
{
clk_i: io_div4
clk_core_i: aon
}
clock_group: peri
reset_connections:
{
rst_ni:
{
name: lc_io_div4
domain: Aon
}
rst_core_ni:
{
name: lc_aon
domain: Aon
}
}
domain:
[
Aon
]
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
clk_core_i: clkmgr_aon_clocks.clk_aon_peri
}
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: pwm_aon
default: ""
end_idx: -1
top_signame: pwm_aon_tl
index: -1
}
]
base_addrs:
{
null: 0x40450000
}
}
{
name: pinmux_aon
type: pinmux
clock_srcs:
{
clk_i: io_div4
clk_aon_i: aon
}
clock_group: powerup
reset_connections:
{
rst_ni:
{
name: lc_io_div4
domain: Aon
}
rst_aon_ni:
{
name: lc_aon
domain: Aon
}
rst_sys_ni:
{
name: sys_io_div4
domain: Aon
}
}
domain:
[
Aon
]
attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_powerup
clk_aon_i: clkmgr_aon_clocks.clk_aon_powerup
}
param_decl: {}
memory: {}
param_list:
[
{
name: TargetCfg
desc: Target specific pinmux configuration.
type: pinmux_pkg::target_cfg_t
default: pinmux_pkg::DefaultTargetCfg
expose: "true"
name_top: PinmuxAonTargetCfg
}
]
inter_signal_list:
[
{
name: lc_hw_debug_en
desc: Debug enable qualifier coming from life cycle controller, used for HW strap qualification.
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: pinmux_aon
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
name: lc_dft_en
desc: Test enable qualifier coming from life cycle controller, used for HW strap qualification.
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: pinmux_aon
top_signame: lc_ctrl_lc_dft_en
index: -1
}
{
name: lc_escalate_en
desc:
'''
Escalation enable signal coming from life cycle controller, used for invalidating
the latched lc_hw_debug_en state inside the strap sampling logic.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: pinmux_aon
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: lc_check_byp_en
desc:
'''
Check bypass enable signal coming from life cycle controller, used for invalidating
the latched lc_hw_debug_en state inside the strap sampling logic. This signal is asserted
whenever the life cycle controller performs a life cycle transition. Its main use is
to skip any background checks inside the life cycle partition of the OTP controller while
a life cycle transition is in progress.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: pinmux_aon
top_signame: lc_ctrl_lc_check_byp_en
index: -1
}
{
name: pinmux_hw_debug_en
desc:
'''
This is the latched version of lc_hw_debug_en_i. We use it exclusively to gate the JTAG
signals and TAP side of the RV_DM so that RV_DM can remain live during an NDM reset cycle.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: pinmux_aon
end_idx: -1
top_type: broadcast
top_signame: pinmux_aon_pinmux_hw_debug_en
index: -1
}
{
name: lc_jtag
desc: Qualified JTAG signals for life cycle controller TAP.
struct: jtag
package: jtag_pkg
type: req_rsp
act: req
width: 1
inst_name: pinmux_aon
default: ""
end_idx: -1
top_signame: pinmux_aon_lc_jtag
index: -1
}
{
name: rv_jtag
desc: Qualified JTAG signals for RISC-V processor TAP.
struct: jtag
package: jtag_pkg
type: req_rsp
act: req
width: 1
inst_name: pinmux_aon
default: ""
end_idx: -1
top_signame: pinmux_aon_rv_jtag
index: -1
}
{
name: dft_jtag
desc: Qualified JTAG signals for DFT TAP.
struct: jtag
package: jtag_pkg
type: req_rsp
act: req
width: 1
inst_name: pinmux_aon
default: ""
top_signame: pinmux_aon_dft_jtag
index: -1
}
{
name: dft_strap_test
desc: Sampled DFT strap values, going to the DFT TAP.
struct: dft_strap_test_req
package: pinmux_pkg
type: uni
act: req
width: 1
default: "'0"
inst_name: pinmux_aon
external: true
top_signame: dft_strap_test
conn_type: false
index: -1
}
{
name: dft_hold_tap_sel
desc: TAP selection hold indication, asserted by the DFT TAP during boundary scan.
struct: logic
type: uni
act: rcv
width: 1
default: "'0"
inst_name: pinmux_aon
package: ""
external: true
top_signame: dft_hold_tap_sel
conn_type: false
index: -1
}
{
name: sleep_en
desc: Level signal that is asserted when the power manager enters sleep.
struct: logic
type: uni
act: rcv
width: 1
default: 1'b0
inst_name: pinmux_aon
package: ""
top_signame: pwrmgr_aon_low_power
index: -1
}
{
name: strap_en
desc: This signal is pulsed high by the power manager after reset in order to sample the HW straps.
struct: logic
type: uni
act: rcv
width: 1
default: 1'b0
inst_name: pinmux_aon
package: ""
top_signame: pwrmgr_aon_strap
index: -1
}
{
name: pin_wkup_req
desc: Wakeup request from wakeup detectors, to the power manager, running on the AON clock.
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: pinmux_aon
package: ""
top_signame: pwrmgr_aon_wakeups
index: 2
}
{
name: usbdev_dppullup_en
desc: Pullup enable signal coming from the USB IP.
struct: logic
type: uni
act: rcv
width: 1
inst_name: pinmux_aon
default: ""
package: ""
top_signame: usbdev_usb_dp_pullup
index: -1
}
{
name: usbdev_dnpullup_en
desc: Pullup enable signal coming from the USB IP.
struct: logic
type: uni
act: rcv
width: 1
inst_name: pinmux_aon
default: ""
package: ""
top_signame: usbdev_usb_dn_pullup
index: -1
}
{
name: usb_dppullup_en
desc: " Pullup enable signal going to USB PHY, needs to be maintained in low-power mode."
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: pinmux_aon
package: ""
external: true
top_signame: usb_dp_pullup_en
conn_type: false
index: -1
}
{
name: usb_dnpullup_en
desc: Pullup enable signal going to USB PHY, needs to be maintained in low-power mode.
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: pinmux_aon
package: ""
external: true
top_signame: usb_dn_pullup_en
conn_type: false
index: -1
}
{
name: usb_wkup_req
desc: Wakeup request from USB wakeup detector, going to the power manager, running on the AON clock.
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: pinmux_aon
package: ""
top_signame: pwrmgr_aon_wakeups
index: 3
}
{
name: usbdev_suspend_req
desc: Indicates whether USB is in suspended state, coming from the USB device.
struct: logic
type: uni
act: rcv
width: 1
inst_name: pinmux_aon
default: ""
package: ""
top_signame: usbdev_usb_aon_suspend_req
index: -1
}
{
name: usbdev_wake_ack
desc: Acknowledges the USB wakeup request, coming from the USB device.
struct: logic
type: uni
act: rcv
width: 1
inst_name: pinmux_aon
default: ""
package: ""
top_signame: usbdev_usb_aon_wake_ack
index: -1
}
{
name: usbdev_bus_reset
desc: Event signal that indicates what happened while monitoring.
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: pinmux_aon
package: ""
top_signame: usbdev_usb_aon_bus_reset
index: -1
}
{
name: usbdev_sense_lost
desc: Event signal that indicates what happened while monitoring.
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: pinmux_aon
package: ""
top_signame: usbdev_usb_aon_sense_lost
index: -1
}
{
name: usbdev_wake_detect_active
desc: State debug information.
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: pinmux_aon
package: ""
end_idx: -1
top_type: broadcast
top_signame: pinmux_aon_usbdev_wake_detect_active
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: pinmux_aon
default: ""
end_idx: -1
top_signame: pinmux_aon_tl
index: -1
}
]
base_addrs:
{
null: 0x40460000
}
}
{
name: aon_timer_aon
type: aon_timer
clock_srcs:
{
clk_i: io_div4
clk_aon_i: aon
}
clock_group: timers
reset_connections:
{
rst_ni:
{
name: lc_io_div4
domain: Aon
}
rst_aon_ni:
{
name: lc_aon
domain: Aon
}
}
domain:
[
Aon
]
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_timers
clk_aon_i: clkmgr_aon_clocks.clk_aon_timers
}
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: nmi_wdog_timer_bark
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: aon_timer_aon
package: ""
end_idx: -1
top_type: broadcast
top_signame: aon_timer_aon_nmi_wdog_timer_bark
index: -1
}
{
name: wkup_req
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: aon_timer_aon
package: ""
top_signame: pwrmgr_aon_wakeups
index: 4
}
{
name: aon_timer_rst_req
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: aon_timer_aon
package: ""
top_signame: pwrmgr_aon_rstreqs
index: 1
}
{
name: lc_escalate_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: aon_timer_aon
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: sleep_mode
struct: logic
type: uni
act: rcv
width: 1
inst_name: aon_timer_aon
default: ""
package: ""
top_signame: pwrmgr_aon_low_power
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: aon_timer_aon
default: ""
end_idx: -1
top_signame: aon_timer_aon_tl
index: -1
}
]
base_addrs:
{
null: 0x40470000
}
}
{
name: ast
type: ast
clock_srcs:
{
clk_ast_tlul_i:
{
clock: io_div4
group: infra
}
clk_ast_adc_i:
{
clock: aon
group: peri
}
clk_ast_alert_i:
{
clock: io_div4
group: secure
}
clk_ast_es_i:
{
clock: main
group: secure
}
clk_ast_rng_i:
{
clock: main
group: secure
}
clk_ast_usb_i:
{
clock: usb
group: peri
}
}
clock_group: secure
reset_connections:
{
rst_ast_tlul_ni:
{
name: lc_io_div4
domain: "0"
}
rst_ast_adc_ni:
{
name: lc_aon
domain: Aon
}
rst_ast_alert_ni:
{
name: lc_io_div4
domain: "0"
}
rst_ast_es_ni:
{
name: lc
domain: "0"
}
rst_ast_rng_ni:
{
name: lc
domain: "0"
}
rst_ast_usb_ni:
{
name: usb
domain: "0"
}
}
domain:
[
Aon
"0"
]
attr: reggen_only
clock_connections:
{
clk_ast_tlul_i: clkmgr_aon_clocks.clk_io_div4_infra
clk_ast_adc_i: clkmgr_aon_clocks.clk_aon_peri
clk_ast_alert_i: clkmgr_aon_clocks.clk_io_div4_secure
clk_ast_es_i: clkmgr_aon_clocks.clk_main_secure
clk_ast_rng_i: clkmgr_aon_clocks.clk_main_secure
clk_ast_usb_i: clkmgr_aon_clocks.clk_usb_peri
}
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: ast
index: -1
}
]
base_addrs:
{
null: 0x40480000
}
}
{
name: sensor_ctrl
type: sensor_ctrl
clock_srcs:
{
clk_i: io_div4
clk_aon_i: aon
}
clock_group: secure
reset_connections:
{
rst_ni:
{
name: lc_io_div4
domain: Aon
}
rst_aon_ni:
{
name: lc_aon
domain: Aon
}
}
domain:
[
Aon
]
attr: reggen_top
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_secure
clk_aon_i: clkmgr_aon_clocks.clk_aon_secure
}
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: ast_alert
struct: ast_alert
package: ast_pkg
type: req_rsp
act: rsp
width: 1
inst_name: sensor_ctrl
default: ""
external: true
top_signame: sensor_ctrl_ast_alert
conn_type: false
index: -1
}
{
name: ast_status
struct: ast_status
package: ast_pkg
type: uni
act: rcv
width: 1
inst_name: sensor_ctrl
default: ""
external: true
top_signame: sensor_ctrl_ast_status
conn_type: false
index: -1
}
{
name: ast_init_done
struct: mubi4
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
default: prim_mubi_pkg::MuBi4True
inst_name: sensor_ctrl
external: true
top_signame: ast_init_done
conn_type: false
index: -1
}
{
name: ast2pinmux
struct: logic
type: uni
act: rcv
width: 9
inst_name: sensor_ctrl
default: ""
package: ""
external: true
top_signame: ast2pinmux
conn_type: false
index: -1
}
{
name: wkup_req
struct: logic
type: uni
act: req
width: 1
inst_name: sensor_ctrl
default: ""
package: ""
top_signame: pwrmgr_aon_wakeups
index: 5
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: sensor_ctrl
default: ""
end_idx: -1
top_signame: sensor_ctrl_tl
index: -1
}
]
base_addrs:
{
null: 0x40490000
}
}
{
name: sram_ctrl_ret_aon
type: sram_ctrl
clock_srcs:
{
clk_i: io_div4
clk_otp_i: io_div4
}
clock_group: infra
reset_connections:
{
rst_ni:
{
name: lc_io_div4
domain: Aon
}
rst_otp_ni:
{
name: lc_io_div4
domain: Aon
}
}
domain:
[
Aon
]
param_decl:
{
InstrExec: "0"
}
base_addrs:
{
regs: 0x40500000
ram: 0x40600000
}
memory:
{
ram:
{
label: ram_ret_aon
swaccess: rw
data_intg_passthru: "true"
exec: True
byte_write: True
size: 0x1000
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_infra
clk_otp_i: clkmgr_aon_clocks.clk_io_div4_infra
}
param_list:
[
{
name: RndCnstSramKey
desc: Compile-time random reset value for SRAM scrambling key.
type: otp_ctrl_pkg::sram_key_t
randcount: 128
randtype: data
name_top: RndCnstSramCtrlRetAonSramKey
default: 0x3925a2b2b291a98470716274c976b810
randwidth: 128
}
{
name: RndCnstSramNonce
desc: Compile-time random reset value for SRAM scrambling nonce.
type: otp_ctrl_pkg::sram_nonce_t
randcount: 128
randtype: data
name_top: RndCnstSramCtrlRetAonSramNonce
default: 0x6dd974cc66d7f9c8518eefb75ac6b952
randwidth: 128
}
{
name: RndCnstLfsrSeed
desc: Compile-time random bits for initial LFSR seed
type: sram_ctrl_pkg::lfsr_seed_t
randcount: 32
randtype: data
name_top: RndCnstSramCtrlRetAonLfsrSeed
default: 0x8242ce57
randwidth: 32
}
{
name: RndCnstLfsrPerm
desc: Compile-time random permutation for LFSR output
type: sram_ctrl_pkg::lfsr_perm_t
randcount: 32
randtype: perm
name_top: RndCnstSramCtrlRetAonLfsrPerm
default: 0x9eb0a8f524a38f50a165833821df3607bef3365b
randwidth: 160
}
{
name: MemSizeRam
desc: Memory size of the RAM (in bytes).
type: int
name_top: MemSizeSramCtrlRetAonRam
default: 4096
}
{
name: InstrExec
desc: Support execution from SRAM
type: bit
default: "0"
expose: "true"
name_top: SramCtrlRetAonInstrExec
}
]
inter_signal_list:
[
{
name: sram_otp_key
struct: sram_otp_key
package: otp_ctrl_pkg
type: req_rsp
act: req
width: 1
inst_name: sram_ctrl_ret_aon
default: ""
top_signame: otp_ctrl_sram_otp_key
index: 1
}
{
name: cfg
struct: ram_1p_cfg
package: prim_ram_1p_pkg
type: uni
act: rcv
width: 1
default: "'0"
inst_name: sram_ctrl_ret_aon
top_signame: ast_ram_1p_cfg
index: -1
}
{
name: lc_escalate_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: sram_ctrl_ret_aon
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: lc_hw_debug_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: sram_ctrl_ret_aon
index: -1
}
{
name: otp_en_sram_ifetch
struct: mubi8
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
default: prim_mubi_pkg::MuBi8False
inst_name: sram_ctrl_ret_aon
index: -1
}
{
name: regs_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: sram_ctrl_ret_aon
default: ""
end_idx: -1
top_signame: sram_ctrl_ret_aon_regs_tl
index: -1
}
{
name: ram_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: sram_ctrl_ret_aon
default: ""
end_idx: -1
top_signame: sram_ctrl_ret_aon_ram_tl
index: -1
}
]
}
{
name: flash_ctrl
type: flash_ctrl
clock_srcs:
{
clk_i: main
clk_otp_i: io_div4
}
clock_group: infra
reset_connections:
{
rst_ni:
{
name: lc
domain: "0"
}
rst_otp_ni:
{
name: lc_io_div4
domain: "0"
}
}
base_addrs:
{
core: 0x41000000
prim: 0x41008000
mem: 0x20000000
}
param_decl:
{
ProgFifoDepth: "4"
}
memory:
{
mem:
{
label: eflash
swaccess: ro
data_intg_passthru: "true"
exec: True
byte_write: False
config:
{
banks: 2
pages_per_bank: 256
program_resolution: 8
pgm_resolution_bytes: 64
bytes_per_page: 2048
bytes_per_bank: 524288
size: 0x100000
}
size: 0x100000
}
}
attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_infra
clk_otp_i: clkmgr_aon_clocks.clk_io_div4_infra
}
domain:
[
"0"
]
param_list:
[
{
name: RndCnstAddrKey
desc: Compile-time random bits for default address key
type: flash_ctrl_pkg::flash_key_t
randcount: 128
randtype: data
name_top: RndCnstFlashCtrlAddrKey
default: 0x4b9e2fc1918d324c4cfb1a95698ea1eb
randwidth: 128
}
{
name: RndCnstDataKey
desc: Compile-time random bits for default data key
type: flash_ctrl_pkg::flash_key_t
randcount: 128
randtype: data
name_top: RndCnstFlashCtrlDataKey
default: 0x7868f849707838f547a2c2a64a91a9d7
randwidth: 128
}
{
name: RndCnstAllSeeds
desc: Compile-time random bits for default seeds
type: flash_ctrl_pkg::all_seeds_t
randcount: 512
randtype: data
name_top: RndCnstFlashCtrlAllSeeds
default: 0x3429d8d73dedb65d2b0751b90255ccde50a2c9ab31cafb75c007285a0ae495e2f5f51fd2acf212901174c9576a112cea79b52282399833da888c02546e72eb6
randwidth: 512
}
{
name: RndCnstLfsrSeed
desc: Compile-time random bits for initial LFSR seed
type: flash_ctrl_pkg::lfsr_seed_t
randcount: 32
randtype: data
name_top: RndCnstFlashCtrlLfsrSeed
default: 0xf09a26a1
randwidth: 32
}
{
name: RndCnstLfsrPerm
desc: Compile-time random permutation for LFSR output
type: flash_ctrl_pkg::lfsr_perm_t
randcount: 32
randtype: perm
name_top: RndCnstFlashCtrlLfsrPerm
default: 0x8d51f3779ea635794ce550b2476e096bc165846c
randwidth: 160
}
{
name: SecScrambleEn
desc: Compile-time option to enable flash scrambling
type: bit
default: "1"
expose: "true"
name_top: SecFlashCtrlScrambleEn
}
{
name: ProgFifoDepth
desc: Depth of program fifo
type: int
default: "4"
expose: "true"
name_top: FlashCtrlProgFifoDepth
}
{
name: RdFifoDepth
desc: Depth of read fifo
type: int
default: "16"
expose: "true"
name_top: FlashCtrlRdFifoDepth
}
]
inter_signal_list:
[
{
name: otp
struct: flash_otp_key
package: otp_ctrl_pkg
type: req_rsp
act: req
width: 1
inst_name: flash_ctrl
default: ""
end_idx: -1
top_signame: flash_ctrl_otp
index: -1
}
{
name: lc_nvm_debug_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
top_signame: lc_ctrl_lc_nvm_debug_en
index: -1
}
{
name: flash_bist_enable
struct: mubi4
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
external: true
top_signame: flash_bist_enable
conn_type: false
index: -1
}
{
name: flash_power_down_h
struct: logic
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
package: ""
external: true
top_signame: flash_power_down_h
conn_type: false
index: -1
}
{
name: flash_power_ready_h
struct: logic
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
package: ""
external: true
top_signame: flash_power_ready_h
conn_type: false
index: -1
}
{
name: flash_test_mode_a
struct: ""
type: io
act: none
width: 2
inst_name: flash_ctrl
default: ""
package: ""
external: true
top_signame: flash_test_mode_a
conn_type: false
index: -1
}
{
name: flash_test_voltage_h
struct: ""
type: io
act: none
width: 1
inst_name: flash_ctrl
default: ""
package: ""
external: true
top_signame: flash_test_voltage_h
conn_type: false
index: -1
}
{
name: lc_creator_seed_sw_rw_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
top_signame: lc_ctrl_lc_creator_seed_sw_rw_en
index: -1
}
{
name: lc_owner_seed_sw_rw_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
top_signame: lc_ctrl_lc_owner_seed_sw_rw_en
index: -1
}
{
name: lc_iso_part_sw_rd_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
top_signame: lc_ctrl_lc_iso_part_sw_rd_en
index: -1
}
{
name: lc_iso_part_sw_wr_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
top_signame: lc_ctrl_lc_iso_part_sw_wr_en
index: -1
}
{
name: lc_seed_hw_rd_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
top_signame: lc_ctrl_lc_seed_hw_rd_en
index: -1
}
{
name: lc_escalate_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: rma_req
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
top_signame: lc_ctrl_lc_flash_rma_req
index: -1
}
{
name: rma_ack
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
inst_name: flash_ctrl
default: ""
end_idx: -1
top_type: broadcast
top_signame: flash_ctrl_rma_ack
index: -1
}
{
name: rma_seed
struct: lc_flash_rma_seed
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
end_idx: -1
top_type: broadcast
top_signame: flash_ctrl_rma_seed
index: -1
}
{
name: pwrmgr
struct: pwr_flash
package: pwrmgr_pkg
type: uni
act: req
width: 1
inst_name: flash_ctrl
default: ""
top_signame: pwrmgr_aon_pwr_flash
index: -1
}
{
name: keymgr
struct: keymgr_flash
package: flash_ctrl_pkg
type: uni
act: req
width: 1
inst_name: flash_ctrl
default: ""
end_idx: -1
top_type: broadcast
top_signame: flash_ctrl_keymgr
index: -1
}
{
name: obs_ctrl
struct: ast_obs_ctrl
package: ast_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
top_signame: ast_obs_ctrl
index: -1
}
{
name: fla_obs
struct: logic
type: uni
act: req
width: 8
inst_name: flash_ctrl
default: ""
package: ""
external: true
top_signame: flash_obs
conn_type: false
index: -1
}
{
name: core_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: flash_ctrl
default: ""
end_idx: -1
top_signame: flash_ctrl_core_tl
index: -1
}
{
name: prim_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: flash_ctrl
default: ""
end_idx: -1
top_signame: flash_ctrl_prim_tl
index: -1
}
{
name: mem_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: flash_ctrl
default: ""
end_idx: -1
top_signame: flash_ctrl_mem_tl
index: -1
}
]
}
{
name: rv_dm
type: rv_dm
clock_srcs:
{
clk_i: main
}
clock_group: infra
reset_connections:
{
rst_ni:
{
name: sys
domain: "0"
}
}
param_decl:
{
IdcodeValue: jtag_id_pkg::JTAG_IDCODE
}
base_addrs:
{
mem: 0x00010000
regs: 0x41200000
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_infra
}
domain:
[
"0"
]
memory: {}
param_list:
[
{
name: IdcodeValue
desc: RISC-V debug module JTAG ID code.
type: logic [31:0]
default: jtag_id_pkg::JTAG_IDCODE
expose: "true"
name_top: RvDmIdcodeValue
}
]
inter_signal_list:
[
{
name: jtag
desc: JTAG signals for the RISC-V TAP.
struct: jtag
package: jtag_pkg
type: req_rsp
act: rsp
width: 1
inst_name: rv_dm
default: ""
top_signame: pinmux_aon_rv_jtag
index: -1
}
{
name: lc_hw_debug_en
desc:
'''
Multibit life cycle hardware debug enable signal coming from life cycle controller,
asserted when the hardware debug mechanisms are enabled in the system.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: rv_dm
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
name: pinmux_hw_debug_en
desc:
'''
Multibit life cycle hardware debug enable signal coming from pinmux.
This is a latched version of the lc_hw_debug_en signal and is only used to
gate the JTAG / TAP side of the RV_DM. It is used to keep a debug session live
while the rest of the system undergoes an NDM reset.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: rv_dm
top_signame: pinmux_aon_pinmux_hw_debug_en
index: -1
}
{
name: unavailable
desc:
'''
This signal indicates to the debug module that the main processor is not available
for debug (e.g. due to a low-power state).
'''
struct: logic
type: uni
act: rcv
width: 1
default: 1'b0
inst_name: rv_dm
index: -1
}
{
name: ndmreset_req
desc: Non-debug module reset request going to the system reset infrastructure.
struct: logic
type: uni
act: req
width: 1
inst_name: rv_dm
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: rv_dm_ndmreset_req
index: -1
}
{
name: dmactive
desc:
'''
This signal indicates whether the debug module is active and can be used to prevent
power down of the core and bus-attached peripherals.
'''
struct: logic
type: uni
act: req
width: 1
inst_name: rv_dm
index: -1
}
{
name: debug_req
desc: This is the debug request interrupt going to the main processor.
struct: logic [rv_dm_reg_pkg::NrHarts-1:0]
type: uni
act: req
width: 1
inst_name: rv_dm
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: rv_dm_debug_req
index: -1
}
{
name: sba_tl_h
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: rv_dm
default: ""
top_signame: main_tl_rv_dm__sba
index: -1
}
{
name: regs_tl_d
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: rv_dm
default: ""
end_idx: -1
top_signame: rv_dm_regs_tl_d
index: -1
}
{
name: mem_tl_d
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: rv_dm
default: ""
end_idx: -1
top_signame: rv_dm_mem_tl_d
index: -1
}
]
}
{
name: rv_plic
type: rv_plic
clock_srcs:
{
clk_i: main
}
clock_group: secure
reset_connections:
{
rst_ni:
{
name: lc
domain: "0"
}
}
attr: ipgen
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_secure
}
domain:
[
"0"
]
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: irq
struct: logic
type: uni
act: req
width: 1
inst_name: rv_plic
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: rv_plic_irq
index: -1
}
{
name: irq_id
struct: logic
type: uni
act: req
width: 1
inst_name: rv_plic
index: -1
}
{
name: msip
struct: logic
type: uni
act: req
width: 1
inst_name: rv_plic
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: rv_plic_msip
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: rv_plic
default: ""
end_idx: -1
top_signame: rv_plic_tl
index: -1
}
]
base_addrs:
{
null: 0x48000000
}
}
{
name: aes
type: aes
clock_srcs:
{
clk_i: main
clk_edn_i: main
}
clock_group: trans
reset_connections:
{
rst_ni:
{
name: lc
domain: "0"
}
rst_edn_ni:
{
name: lc
domain: "0"
}
}
param_decl:
{
SecMasking: "1"
SecSBoxImpl: aes_pkg::SBoxImplDom
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_aes
clk_edn_i: clkmgr_aon_clocks.clk_main_aes
}
domain:
[
"0"
]
memory: {}
param_list:
[
{
name: AES192Enable
desc: Disable (0) or enable (1) support for 192-bit key lengths (AES-192).
type: bit
default: 1'b1
expose: "false"
name_top: AesAES192Enable
}
{
name: SecMasking
desc:
'''
Disable (0) or enable (1) first-order masking of the AES cipher core.
Masking requires the use of a masked S-Box, see SecSBoxImpl parameter.
'''
type: bit
default: "1"
expose: "true"
name_top: SecAesMasking
}
{
name: SecSBoxImpl
desc: Selection of the S-Box implementation. See aes_pkg.sv.
type: aes_pkg::sbox_impl_e
default: aes_pkg::SBoxImplDom
expose: "true"
name_top: SecAesSBoxImpl
}
{
name: SecStartTriggerDelay
desc:
'''
Manual start trigger delay, useful for SCA measurements.
A value of e.g. 40 allows the processor to go into sleep before AES starts operation.
'''
type: int unsigned
default: "0"
expose: "true"
name_top: SecAesStartTriggerDelay
}
{
name: SecAllowForcingMasks
desc:
'''
Forbid (0) or allow (1) forcing the masking PRNG output to a constant value via FORCE_MASKS bit in the Auxiliary Control Register.
Useful for SCA measurements.
Meaningful only if masking is enabled.
'''
type: bit
default: 1'b0
expose: "true"
name_top: SecAesAllowForcingMasks
}
{
name: SecSkipPRNGReseeding
desc:
'''
Perform (0) or skip (1) PRNG reseeding requests, useful for SCA measurements only.
The current SCA setup doesn't provide sufficient resources to implement the infrastructure required for PRNG reseeding (CSRNG, EDN).
To enable SCA resistance evaluations, we need to skip reseeding requests on the SCA platform.
'''
type: bit
default: 1'b0
expose: "true"
name_top: SecAesSkipPRNGReseeding
}
{
name: RndCnstClearingLfsrSeed
desc: Default seed of the PRNG used for register clearing.
type: aes_pkg::clearing_lfsr_seed_t
randcount: 64
randtype: data
name_top: RndCnstAesClearingLfsrSeed
default: 0x690709f09e8597d2
randwidth: 64
}
{
name: RndCnstClearingLfsrPerm
desc: Permutation applied to the LFSR of the PRNG used for clearing.
type: aes_pkg::clearing_lfsr_perm_t
randcount: 64
randtype: perm
name_top: RndCnstAesClearingLfsrPerm
default: 0x18c918667bfd0701c2e7c825ad6c542918c8e8bbaa737b5fcfb7a8a6cd054048bf9b54a14cff8e69dc8de000f65c955b
randwidth: 384
}
{
name: RndCnstClearingSharePerm
desc: Permutation applied to the clearing PRNG output for clearing the second share of registers.
type: aes_pkg::clearing_lfsr_perm_t
randcount: 64
randtype: perm
name_top: RndCnstAesClearingSharePerm
default: 0xf8633cfde5afa6b507549420eaed688c110a9306b63992ea71787dc9f634cc30916f7b484a6e3195d37bb2788f153e40
randwidth: 384
}
{
name: RndCnstMaskingLfsrSeed
desc: Default seed of the PRNG used for masking.
type: aes_pkg::masking_lfsr_seed_t
randcount: 160
randtype: data
name_top: RndCnstAesMaskingLfsrSeed
default: 0xebdb78aae822f2f444df087b34854b57fa1b481b
randwidth: 160
}
{
name: RndCnstMaskingLfsrPerm
desc: Permutation applied to the concatenated LFSRs of the PRNG used for masking.
type: aes_pkg::masking_lfsr_perm_t
randcount: 160
randtype: perm
name_top: RndCnstAesMaskingLfsrPerm
default: 0x35211013031815808909584f6726255d0417556d9e2a227341642e826136760c4e9b0616931f514c8d0b793d6642813037878800200249502b68999d0a6f864d4a94193f54293a1a637746852833577d1c3239749c0f2c05318340271e705e1b758e453e7b52906a8c8a98485b11122f622d083b569a9153781d92238f6e385f47957f964b847e247a72606597597c3c075a43716c0e5c69340d8b446b14019f
randwidth: 1280
}
]
inter_signal_list:
[
{
name: idle
struct: mubi4
package: prim_mubi_pkg
type: uni
act: req
width: 1
inst_name: aes
default: ""
top_signame: clkmgr_aon_idle
index: 0
}
{
name: lc_escalate_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: aes
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: edn
struct: edn
package: edn_pkg
type: req_rsp
act: req
width: 1
inst_name: aes
default: ""
top_signame: edn0_edn
index: 5
}
{
name: keymgr_key
struct: hw_key_req
package: keymgr_pkg
type: uni
act: rcv
width: 1
inst_name: aes
default: ""
top_signame: keymgr_aes_key
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: aes
default: ""
end_idx: -1
top_signame: aes_tl
index: -1
}
]
base_addrs:
{
null: 0x41100000
}
}
{
name: hmac
type: hmac
clock_srcs:
{
clk_i: main
}
clock_group: trans
reset_connections:
{
rst_ni:
{
name: lc
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_hmac
}
domain:
[
"0"
]
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: idle
struct: mubi4
package: prim_mubi_pkg
type: uni
act: req
width: 1
inst_name: hmac
default: ""
top_signame: clkmgr_aon_idle
index: 1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: hmac
default: ""
end_idx: -1
top_signame: hmac_tl
index: -1
}
]
base_addrs:
{
null: 0x41110000
}
}
{
name: kmac
type: kmac
param_decl:
{
EnMasking: "1"
}
clock_srcs:
{
clk_i: main
clk_edn_i: main
}
clock_group: trans
reset_connections:
{
rst_ni:
{
name: lc
domain: "0"
}
rst_edn_ni:
{
name: lc
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_kmac
clk_edn_i: clkmgr_aon_clocks.clk_main_kmac
}
domain:
[
"0"
]
memory: {}
param_list:
[
{
name: EnMasking
desc: Disable(0) or enable(1) first-order masking of Keccak round.
type: bit
default: "1"
expose: "true"
name_top: KmacEnMasking
}
{
name: SwKeyMasked
desc:
'''
Disable(0) or enable(1) software key masking in case masking is disabled (EnMasking == 0).
If masking is enabled, this parameter has no effect.
Mainly useful for software interface compatibility between the masked and unmasked design.
Mostly relevant for SCA measurements.
'''
type: bit
default: "0"
expose: "true"
name_top: KmacSwKeyMasked
}
{
name: SecCmdDelay
desc:
'''
Command delay, useful for SCA measurements only.
A value of e.g. 40 allows the processor to go into sleep before KMAC starts operation.
If a value greater than 0 is chosen, software can pass two commands in series.
The second command is buffered internally and will be presented to the hardware SecCmdDelay number of cycles after the first one.
'''
type: int
default: "0"
expose: "true"
name_top: SecKmacCmdDelay
}
{
name: SecIdleAcceptSwMsg
desc:
'''
If enabled (1), software writes to the message FIFO before having received a START command are not ignored.
Disabled (0) by default.
Useful for SCA measurements only.
'''
type: bit
default: "0"
expose: "true"
name_top: SecKmacIdleAcceptSwMsg
}
{
name: RndCnstLfsrSeed
desc: Compile-time random data for LFSR default seed
type: kmac_pkg::lfsr_seed_t
randcount: 800
randtype: data
name_top: RndCnstKmacLfsrSeed
default: 0x48f16180909826998ace3628c0cf0e58b70885718609fa79565dcba540aded8c8d5560af97340ea929aae07c399bb65d74bd1ff16f2816902bbe7ed54814f7451c011afbb712b66e42c1910358162e3fb2368ebde95c97fa3b0e8f6629a16e94d4e43991
randwidth: 800
}
{
name: RndCnstLfsrPerm
desc: Compile-time random permutation for LFSR output
type: kmac_pkg::lfsr_perm_t
randcount: 800
randtype: perm
name_top: RndCnstKmacLfsrPerm
default: 0xc116f8ec1bb4a423187784925add5d7f1736506f13c55ab6ab1a707510497a2a30aaf41d15e7b06a0605324a931e4ca206b335f126dc42059684f991522e8483099360995db9a76186a6cb55a44a6637901577fc4838501b71f8534b27ec9c6bcf3c31aebca3a810266d601089e99c92c7cc3ebd711a50368d938c71d234e9e5644c636ee1ae0b88ce78281d70e775fc1eb389ebc09f7c1d1ad4052b89680d1411ee2b68c35e576b91112650c8fe9c0e5371c1b16e89371e5b48e6017a5460a5833a78af684c4e029c1d62fa5a2c4c98468f60c209967aa8276072c090c3b20f1bac18044271bc55a5ca5265ddf621b06b5613d0acc0ee0090a6904d29992b4c87f7d1d9359deb948ab2482591dab12ea3b060a14f1b144a43de23a17587c94bb0118c6ff38a63605c998b171151d0ca38bdc3c3e1c0184cf029215b1a78e4a25014b29e3042e5679ebb4d62b791c625e5f4787b4b68a4d2d0866a29ada8ac86d280510cd399d2297148cbaca4c39bd37c136ec356e1171b8b7460fa8800950e886c8f79d43a5b6fa97589879f779682aba5ec58fd5c4d5afa47b36c1ab24fb0ed461ee313949320a8572862240823846b223d9f50263d66411455e1fe6fdef874801a2682100c5d1f92fccc3a8e56da4a2f6dd3c22d052c286d92148a11f66aa345732d530fd9c00e3c3e696b9dcd4344033698a6e877f4b355633006cc172649bdedc74eba68c1236d33c91531c9d0e221820d9219ddc0a45781a0a9e15a7cad53dc8142fb841300d1a693269c3dcb46a51ac4070b2923987a612245aa5cafdcc89af34f53c6664b068ddb5a2e054bb26e8e0f59f47d0eb7c31762a11c5937e82fadaba4a98b4182d37190ad21a8582383e7c7c6172e81f9ee6e21646754649547336e35619128d0aa1daa4a418549c5a3d9e17dafe1952245969112227a93679a00065dc9b103bf4ef30a4e6fa1cb854c7add0a552fb98954e9db6cd96bbeb9b1f081e00d5954a175630105f5ed3b7d71e08509685f249300a00d09b6d94b946c695bb5706c06a866273bb55f134d19fcb95399b46ebc1d53f2408b09417ae066551504203018da29406c02e5919e0eb185bc41d789d9e3a57c8cb1410e8921d29c54e0244e4c611c0de816ae97986afc6459a2c5681db48357e738b02f1d3104af12d58415a4712d138cfe70570b3e0c8f96e2d4104989a0ba28aa5a55f47c0a47e221ac2ae2544d628148fb29e3c2d6b59c02819412e1ee5dc72545193fea567542369473b4d8638274a22f162db6a8c0aa8b48b2499230a188deba56073dbc94d00b61c2668b63f0a99e4540002b750f584e8368e67b5c064cc98a31313b8d4a46a628efc63214c371f7282854af8b797a41cc562995038a5c14128aa7e03ef942af63ecc4
randwidth: 8000
}
{
name: RndCnstLfsrFwdPerm
desc: Compile-time random permutation for forwarding LFSR state
type: kmac_pkg::lfsr_fwd_perm_t
randcount: 32
randtype: perm
name_top: RndCnstKmacLfsrFwdPerm
default: 0x6c52bada026047a34f972e09207688729fbcf8ff
randwidth: 160
}
{
name: RndCnstMsgPerm
desc: Compile-time random permutation for LFSR Message output
type: kmac_pkg::msg_perm_t
randcount: 64
randtype: perm
name_top: RndCnstKmacMsgPerm
default: 0xe16cb1a4455785bd0dc24673fd21eadfe99c19f0e0090daf78e949158b4c20f8ee8944fb00a9fa45d07d2f5a3cb2b6b9
randwidth: 384
}
]
inter_signal_list:
[
{
name: keymgr_key
struct: hw_key_req
package: keymgr_pkg
type: uni
act: rcv
width: 1
inst_name: kmac
default: ""
top_signame: keymgr_kmac_key
index: -1
}
{
name: app
struct: app
package: kmac_pkg
type: req_rsp
act: rsp
width: 3
inst_name: kmac
default: ""
end_idx: -1
top_type: one-to-N
top_signame: kmac_app
index: -1
}
{
name: entropy
struct: edn
package: edn_pkg
type: req_rsp
act: req
width: 1
inst_name: kmac
default: ""
top_signame: edn0_edn
index: 3
}
{
name: idle
struct: mubi4
package: prim_mubi_pkg
type: uni
act: req
width: 1
inst_name: kmac
default: ""
top_signame: clkmgr_aon_idle
index: 2
}
{
name: en_masking
struct: logic
type: uni
act: req
width: 1
inst_name: kmac
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: kmac_en_masking
index: -1
}
{
name: lc_escalate_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: kmac
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: kmac
default: ""
end_idx: -1
top_signame: kmac_tl
index: -1
}
]
base_addrs:
{
null: 0x41120000
}
}
{
name: otbn
type: otbn
clock_srcs:
{
clk_i:
{
clock: main
group: trans
}
clk_edn_i:
{
clock: main
group: secure
}
clk_otp_i:
{
clock: io_div4
group: secure
}
}
clock_group: trans
reset_connections:
{
rst_ni:
{
name: lc
domain: "0"
}
rst_edn_ni:
{
name: lc
domain: "0"
}
rst_otp_ni:
{
name: lc_io_div4
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_otbn
clk_edn_i: clkmgr_aon_clocks.clk_main_secure
clk_otp_i: clkmgr_aon_clocks.clk_io_div4_secure
}
domain:
[
"0"
]
param_decl: {}
memory: {}
param_list:
[
{
name: Stub
desc: Stub out the core of Otbn logic
type: bit
default: "0"
expose: "true"
name_top: OtbnStub
}
{
name: RegFile
desc: Selection of the register file implementation. See otbn_pkg.sv.
type: otbn_pkg::regfile_e
default: otbn_pkg::RegFileFF
expose: "true"
name_top: OtbnRegFile
}
{
name: RndCnstUrndPrngSeed
desc: Default seed of the PRNG used for URND.
type: otbn_pkg::urnd_prng_seed_t
randcount: 256
randtype: data
name_top: RndCnstOtbnUrndPrngSeed
default: 0x173b021751142eb30b9482bd8e7d31d3e1a2619d66ef6cb916fd6c864a510aed
randwidth: 256
}
{
name: SecMuteUrnd
desc:
'''
If enabled (1), URND is advanced only when data is needed.
Disabled (0) by default.
Useful for SCA measurements only.
'''
type: bit
default: "0"
expose: "true"
name_top: SecOtbnMuteUrnd
}
{
name: SecSkipUrndReseedAtStart
desc:
'''
If enabled (1), URND reseed is skipped at the start of an operation.
Disabled (0) by default.
Useful for SCA measurements only.
'''
type: bit
default: "0"
expose: "true"
name_top: SecOtbnSkipUrndReseedAtStart
}
{
name: RndCnstOtbnKey
desc: Compile-time random reset value for IMem/DMem scrambling key.
type: otp_ctrl_pkg::otbn_key_t
randcount: 128
randtype: data
name_top: RndCnstOtbnOtbnKey
default: 0x83d2d2e24871c35e3aeabae77182cdef
randwidth: 128
}
{
name: RndCnstOtbnNonce
desc: Compile-time random reset value for IMem/DMem scrambling nonce.
type: otp_ctrl_pkg::otbn_nonce_t
randcount: 64
randtype: data
name_top: RndCnstOtbnOtbnNonce
default: 0xf9f77516f1177315
randwidth: 64
}
]
inter_signal_list:
[
{
name: otbn_otp_key
struct: otbn_otp_key
package: otp_ctrl_pkg
type: req_rsp
act: req
width: 1
default: "'0"
inst_name: otbn
top_signame: otp_ctrl_otbn_otp_key
index: -1
}
{
name: edn_rnd
struct: edn
package: edn_pkg
type: req_rsp
act: req
width: 1
inst_name: otbn
default: ""
top_signame: edn1_edn
index: 0
}
{
name: edn_urnd
struct: edn
package: edn_pkg
type: req_rsp
act: req
width: 1
inst_name: otbn
default: ""
top_signame: edn0_edn
index: 6
}
{
name: idle
struct: mubi4
package: prim_mubi_pkg
type: uni
act: req
width: 1
inst_name: otbn
default: ""
top_signame: clkmgr_aon_idle
index: 3
}
{
name: ram_cfg
struct: ram_1p_cfg
package: prim_ram_1p_pkg
type: uni
act: rcv
width: 1
inst_name: otbn
default: ""
top_signame: ast_ram_1p_cfg
index: -1
}
{
name: lc_escalate_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: otbn
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: lc_rma_req
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: otbn
top_signame: flash_ctrl_rma_ack
index: -1
}
{
name: lc_rma_ack
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: otbn
end_idx: -1
top_type: broadcast
top_signame: otbn_lc_rma_ack
index: -1
}
{
name: keymgr_key
struct: otbn_key_req
package: keymgr_pkg
type: uni
act: rcv
width: 1
inst_name: otbn
default: ""
top_signame: keymgr_otbn_key
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: otbn
default: ""
end_idx: -1
top_signame: otbn_tl
index: -1
}
]
base_addrs:
{
null: 0x41130000
}
}
{
name: keymgr
type: keymgr
clock_srcs:
{
clk_i: main
clk_edn_i: main
}
clock_group: secure
reset_connections:
{
rst_ni:
{
name: lc
domain: "0"
}
rst_edn_ni:
{
name: lc
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_secure
clk_edn_i: clkmgr_aon_clocks.clk_main_secure
}
domain:
[
"0"
]
param_decl: {}
memory: {}
param_list:
[
{
name: KmacEnMasking
desc: Flag indicating with kmac masking is enabled
type: bit
default: "1"
expose: "true"
name_top: KeymgrKmacEnMasking
}
{
name: RndCnstLfsrSeed
desc: Compile-time random bits for initial LFSR seed
type: keymgr_pkg::lfsr_seed_t
randcount: 64
randtype: data
name_top: RndCnstKeymgrLfsrSeed
default: 0x733affa732f4c491
randwidth: 64
}
{
name: RndCnstLfsrPerm
desc: Compile-time random permutation for LFSR output
type: keymgr_pkg::lfsr_perm_t
randcount: 64
randtype: perm
name_top: RndCnstKeymgrLfsrPerm
default: 0x2c629940f4ed827c37884c63aa6a4e7455ec93c21bb87712ed5d4ca1e274c8ddb953f0fe03a46f598ac1e1a09fcfd865
randwidth: 384
}
{
name: RndCnstRandPerm
desc: Compile-time random permutation for entropy used in share overriding
type: keymgr_pkg::rand_perm_t
randcount: 32
randtype: perm
name_top: RndCnstKeymgrRandPerm
default: 0x5216c347ed2de7aa0bd0c6ebd905eeb73203a483
randwidth: 160
}
{
name: RndCnstRevisionSeed
desc: Compile-time random bits for revision seed
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrRevisionSeed
default: 0x414c190ad0a09d144ffc0c0fea081cef945b641f096b9f3e9a494ba35fcfef0d
randwidth: 256
}
{
name: RndCnstCreatorIdentitySeed
desc: Compile-time random bits for creator identity seed
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrCreatorIdentitySeed
default: 0xfb223e8ab704f249ee3fa822276c45e588ed40cf52c8fae2d054a71149771822
randwidth: 256
}
{
name: RndCnstOwnerIntIdentitySeed
desc: Compile-time random bits for owner intermediate identity seed
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrOwnerIntIdentitySeed
default: 0x2ec37360e23d4dda559adabcf099937febbf048fac328ba1bdee0caca987be4a
randwidth: 256
}
{
name: RndCnstOwnerIdentitySeed
desc: Compile-time random bits for owner identity seed
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrOwnerIdentitySeed
default: 0x4abf486b16740b20bc32b13ff07a13ff21ce605e0ac019858f73d707cd0ec1d3
randwidth: 256
}
{
name: RndCnstSoftOutputSeed
desc: Compile-time random bits for software generation seed
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrSoftOutputSeed
default: 0x3daaef20e285fa658fdd1b426c037151b16c8d444c444f396f4479cb795cf94b
randwidth: 256
}
{
name: RndCnstHardOutputSeed
desc: Compile-time random bits for hardware generation seed
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrHardOutputSeed
default: 0x9e409d18381bd5d56821e2985e47997105c4900f255574675985b210e1a968e4
randwidth: 256
}
{
name: RndCnstAesSeed
desc: Compile-time random bits for generation seed when aes destination selected
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrAesSeed
default: 0x5e5b35e460fdaf1ff382ab0195e33689d99bcebf2b79b6839264edf4de2b39f3
randwidth: 256
}
{
name: RndCnstKmacSeed
desc: Compile-time random bits for generation seed when kmac destination selected
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrKmacSeed
default: 0x94059891a38bd1d16c763bbd90347e58152d7fca9938036525aaa3f89e3de8f1
randwidth: 256
}
{
name: RndCnstOtbnSeed
desc: Compile-time random bits for generation seed when otbn destination selected
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrOtbnSeed
default: 0x278645e11d7cac76310205e19cd3f2ed294a279f3c6d0649a905cc9b10a67a16
randwidth: 256
}
{
name: RndCnstCdi
desc: Compile-time random bits for generation seed when no CDI is selected
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrCdi
default: 0x161fed72416dfd293de3a18a8837b0dd4cb694dd540451d769d28e1d9e76007b
randwidth: 256
}
{
name: RndCnstNoneSeed
desc: Compile-time random bits for generation seed when no destination selected
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrNoneSeed
default: 0x7a9e0f6e3d591a7fd8c7ba264af78f28aee0d28e4d638d95d1806e870336cd96
randwidth: 256
}
]
inter_signal_list:
[
{
name: edn
struct: edn
package: edn_pkg
type: req_rsp
act: req
width: 1
inst_name: keymgr
default: ""
top_signame: edn0_edn
index: 0
}
{
name: aes_key
struct: hw_key_req
package: keymgr_pkg
type: uni
act: req
width: 1
inst_name: keymgr
default: ""
end_idx: -1
top_type: broadcast
top_signame: keymgr_aes_key
index: -1
}
{
name: kmac_key
struct: hw_key_req
package: keymgr_pkg
type: uni
act: req
width: 1
inst_name: keymgr
default: ""
end_idx: -1
top_type: broadcast
top_signame: keymgr_kmac_key
index: -1
}
{
name: otbn_key
struct: otbn_key_req
package: keymgr_pkg
type: uni
act: req
width: 1
inst_name: keymgr
default: ""
end_idx: -1
top_type: broadcast
top_signame: keymgr_otbn_key
index: -1
}
{
name: kmac_data
struct: app
package: kmac_pkg
type: req_rsp
act: req
width: 1
inst_name: keymgr
default: ""
top_signame: kmac_app
index: 0
}
{
name: otp_key
struct: otp_keymgr_key
package: otp_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: keymgr
default: ""
top_signame: otp_ctrl_otp_keymgr_key
index: -1
}
{
name: otp_device_id
struct: otp_device_id
package: otp_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: keymgr
default: ""
top_signame: keymgr_otp_device_id
index: -1
}
{
name: flash
struct: keymgr_flash
package: flash_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: keymgr
default: ""
top_signame: flash_ctrl_keymgr
index: -1
}
{
name: lc_keymgr_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::On
inst_name: keymgr
top_signame: lc_ctrl_lc_keymgr_en
index: -1
}
{
name: lc_keymgr_div
struct: lc_keymgr_div
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: keymgr
default: ""
top_signame: lc_ctrl_lc_keymgr_div
index: -1
}
{
name: rom_digest
struct: keymgr_data
package: rom_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: keymgr
default: ""
top_signame: rom_ctrl_keymgr_data
index: -1
}
{
name: kmac_en_masking
struct: logic
type: uni
act: rcv
width: 1
inst_name: keymgr
default: ""
package: ""
top_signame: kmac_en_masking
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: keymgr
default: ""
end_idx: -1
top_signame: keymgr_tl
index: -1
}
]
base_addrs:
{
null: 0x41140000
}
}
{
name: csrng
type: csrng
clock_srcs:
{
clk_i: main
}
clock_group: secure
reset_connections:
{
rst_ni:
{
name: lc
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_secure
}
domain:
[
"0"
]
param_decl: {}
memory: {}
param_list:
[
{
name: RndCnstCsKeymgrDivNonProduction
desc: Compile-time random bits for csrng state group diversification value
type: csrng_pkg::cs_keymgr_div_t
randcount: 384
randtype: data
name_top: RndCnstCsrngCsKeymgrDivNonProduction
default: 0x1d2049f332011cab7d512b69b6b766dc84760801c9aae19e8a6dd42f94a9a15fa77f118b21ba52c5d59d755f58d2d862
randwidth: 384
}
{
name: RndCnstCsKeymgrDivProduction
desc: Compile-time random bits for csrng state group diversification value
type: csrng_pkg::cs_keymgr_div_t
randcount: 384
randtype: data
name_top: RndCnstCsrngCsKeymgrDivProduction
default: 0x44d2dc258ca12cc70b776b16dd95013b9569bd77059093ed3ce77aea86ffd82cb1cdee3fcd6039c7c04024965b7c1e1c
randwidth: 384
}
{
name: SBoxImpl
desc: Selection of the S-Box implementation. See aes_pkg.sv.
type: aes_pkg::sbox_impl_e
default: aes_pkg::SBoxImplCanright
expose: "true"
name_top: CsrngSBoxImpl
}
]
inter_signal_list:
[
{
name: csrng_cmd
struct: csrng
package: csrng_pkg
type: req_rsp
act: rsp
width: 2
inst_name: csrng
default: ""
end_idx: -1
top_type: one-to-N
top_signame: csrng_csrng_cmd
index: -1
}
{
name: entropy_src_hw_if
struct: entropy_src_hw_if
package: entropy_src_pkg
type: req_rsp
act: req
width: 1
inst_name: csrng
default: ""
end_idx: -1
top_signame: csrng_entropy_src_hw_if
index: -1
}
{
name: cs_aes_halt
struct: cs_aes_halt
package: entropy_src_pkg
type: req_rsp
act: rsp
width: 1
inst_name: csrng
default: ""
end_idx: -1
top_signame: csrng_cs_aes_halt
index: -1
}
{
name: otp_en_csrng_sw_app_read
struct: mubi8
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
inst_name: csrng
default: ""
top_signame: csrng_otp_en_csrng_sw_app_read
index: -1
}
{
name: lc_hw_debug_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: csrng
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: csrng
default: ""
end_idx: -1
top_signame: csrng_tl
index: -1
}
]
base_addrs:
{
null: 0x41150000
}
}
{
name: entropy_src
type: entropy_src
clock_srcs:
{
clk_i: main
}
clock_group: secure
reset_connections:
{
rst_ni:
{
name: lc
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_secure
}
domain:
[
"0"
]
param_decl: {}
memory: {}
param_list:
[
{
name: Stub
desc: Stub out the core of entropy_src logic
type: bit
default: "0"
expose: "true"
name_top: EntropySrcStub
}
]
inter_signal_list:
[
{
name: entropy_src_hw_if
struct: entropy_src_hw_if
package: entropy_src_pkg
type: req_rsp
act: rsp
width: 1
inst_name: entropy_src
default: ""
top_signame: csrng_entropy_src_hw_if
index: -1
}
{
name: cs_aes_halt
struct: cs_aes_halt
package: entropy_src_pkg
type: req_rsp
act: req
width: 1
inst_name: entropy_src
default: ""
top_signame: csrng_cs_aes_halt
index: -1
}
{
name: entropy_src_rng
struct: entropy_src_rng
package: entropy_src_pkg
type: req_rsp
act: req
width: 1
inst_name: entropy_src
default: ""
external: true
top_signame: es_rng
conn_type: false
index: -1
}
{
name: entropy_src_xht
struct: entropy_src_xht
package: entropy_src_pkg
type: req_rsp
act: req
width: 1
inst_name: entropy_src
index: -1
}
{
name: otp_en_entropy_src_fw_read
struct: mubi8
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
inst_name: entropy_src
default: ""
top_signame: entropy_src_otp_en_entropy_src_fw_read
index: -1
}
{
name: otp_en_entropy_src_fw_over
struct: mubi8
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
inst_name: entropy_src
default: ""
top_signame: entropy_src_otp_en_entropy_src_fw_over
index: -1
}
{
name: rng_fips
struct: logic
type: uni
act: req
width: 1
inst_name: entropy_src
default: ""
package: ""
external: true
top_signame: es_rng_fips
conn_type: false
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: entropy_src
default: ""
end_idx: -1
top_signame: entropy_src_tl
index: -1
}
]
base_addrs:
{
null: 0x41160000
}
}
{
name: edn0
type: edn
clock_srcs:
{
clk_i: main
}
clock_group: secure
reset_connections:
{
rst_ni:
{
name: lc
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_secure
}
domain:
[
"0"
]
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: csrng_cmd
desc: EDN supports a signal CSRNG application interface.
struct: csrng
package: csrng_pkg
type: req_rsp
act: req
width: 1
inst_name: edn0
default: ""
top_signame: csrng_csrng_cmd
index: 0
}
{
name: edn
desc:
'''
The collection of peripheral ports supported by edn. The width (4)
indicates the number of peripheral ports on a single instance.
Due to limitations in the parametrization of top-level interconnects
this value is not currently parameterizable. However, the number
of peripheral ports may change in a future revision.
'''
struct: edn
package: edn_pkg
type: req_rsp
act: rsp
width: 8
default: "'0"
inst_name: edn0
end_idx: -1
top_type: one-to-N
top_signame: edn0_edn
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: edn0
default: ""
end_idx: -1
top_signame: edn0_tl
index: -1
}
]
base_addrs:
{
null: 0x41170000
}
}
{
name: edn1
type: edn
clock_srcs:
{
clk_i: main
}
clock_group: secure
reset_connections:
{
rst_ni:
{
name: lc
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_secure
}
domain:
[
"0"
]
param_decl: {}
param_list: []
inter_signal_list:
[
{
name: csrng_cmd
desc: EDN supports a signal CSRNG application interface.
struct: csrng
package: csrng_pkg
type: req_rsp
act: req
width: 1
inst_name: edn1
default: ""
top_signame: csrng_csrng_cmd
index: 1
}
{
name: edn
desc:
'''
The collection of peripheral ports supported by edn. The width (4)
indicates the number of peripheral ports on a single instance.
Due to limitations in the parametrization of top-level interconnects
this value is not currently parameterizable. However, the number
of peripheral ports may change in a future revision.
'''
struct: edn
package: edn_pkg
type: req_rsp
act: rsp
width: 8
default: "'0"
inst_name: edn1
end_idx: 1
top_type: partial-one-to-N
top_signame: edn1_edn
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: edn1
default: ""
end_idx: -1
top_signame: edn1_tl
index: -1
}
]
base_addrs:
{
null: 0x41180000
}
}
{
name: sram_ctrl_main
type: sram_ctrl
clock_srcs:
{
clk_i: main
clk_otp_i: io_div4
}
clock_group: infra
reset_connections:
{
rst_ni:
{
name: lc
domain: "0"
}
rst_otp_ni:
{
name: lc_io_div4
domain: "0"
}
}
param_decl:
{
InstrExec: "1"
}
base_addrs:
{
regs: 0x411C0000
ram: 0x10000000
}
memory:
{
ram:
{
label: ram_main
swaccess: rw
data_intg_passthru: "true"
exec: True
byte_write: True
size: 0x20000
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_infra
clk_otp_i: clkmgr_aon_clocks.clk_io_div4_infra
}
domain:
[
"0"
]
param_list:
[
{
name: RndCnstSramKey
desc: Compile-time random reset value for SRAM scrambling key.
type: otp_ctrl_pkg::sram_key_t
randcount: 128
randtype: data
name_top: RndCnstSramCtrlMainSramKey
default: 0x7548a9bf5956e7482848de7d401512a
randwidth: 128
}
{
name: RndCnstSramNonce
desc: Compile-time random reset value for SRAM scrambling nonce.
type: otp_ctrl_pkg::sram_nonce_t
randcount: 128
randtype: data
name_top: RndCnstSramCtrlMainSramNonce
default: 0x2573043a8e0ad9b156d761ad532f38f0
randwidth: 128
}
{
name: RndCnstLfsrSeed
desc: Compile-time random bits for initial LFSR seed
type: sram_ctrl_pkg::lfsr_seed_t
randcount: 32
randtype: data
name_top: RndCnstSramCtrlMainLfsrSeed
default: 0x767aff4b
randwidth: 32
}
{
name: RndCnstLfsrPerm
desc: Compile-time random permutation for LFSR output
type: sram_ctrl_pkg::lfsr_perm_t
randcount: 32
randtype: perm
name_top: RndCnstSramCtrlMainLfsrPerm
default: 0x6cd8e17015d40914d8a70990bff7799628f1f957
randwidth: 160
}
{
name: MemSizeRam
desc: Memory size of the RAM (in bytes).
type: int
name_top: MemSizeSramCtrlMainRam
default: 131072
}
{
name: InstrExec
desc: Support execution from SRAM
type: bit
default: "1"
expose: "true"
name_top: SramCtrlMainInstrExec
}
]
inter_signal_list:
[
{
name: sram_otp_key
struct: sram_otp_key
package: otp_ctrl_pkg
type: req_rsp
act: req
width: 1
inst_name: sram_ctrl_main
default: ""
top_signame: otp_ctrl_sram_otp_key
index: 0
}
{
name: cfg
struct: ram_1p_cfg
package: prim_ram_1p_pkg
type: uni
act: rcv
width: 1
default: "'0"
inst_name: sram_ctrl_main
top_signame: ast_ram_1p_cfg
index: -1
}
{
name: lc_escalate_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: sram_ctrl_main
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: lc_hw_debug_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: sram_ctrl_main
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
name: otp_en_sram_ifetch
struct: mubi8
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
default: prim_mubi_pkg::MuBi8False
inst_name: sram_ctrl_main
top_signame: sram_ctrl_main_otp_en_sram_ifetch
index: -1
}
{
name: regs_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: sram_ctrl_main
default: ""
end_idx: -1
top_signame: sram_ctrl_main_regs_tl
index: -1
}
{
name: ram_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: sram_ctrl_main
default: ""
end_idx: -1
top_signame: sram_ctrl_main_ram_tl
index: -1
}
]
}
{
name: rom_ctrl
type: rom_ctrl
clock_srcs:
{
clk_i: main
}
clock_group: infra
reset_connections:
{
rst_ni:
{
name: lc
domain: "0"
}
}
base_addrs:
{
rom: 0x00008000
regs: 0x411e0000
}
memory:
{
rom:
{
label: rom
swaccess: ro
data_intg_passthru: True
exec: True
byte_write: False
size: 0x8000
}
}
param_decl:
{
SecDisableScrambling: 1'b0
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_infra
}
domain:
[
"0"
]
param_list:
[
{
name: BootRomInitFile
desc: Contents of ROM
type: ""
default: '''""'''
expose: "true"
name_top: RomCtrlBootRomInitFile
}
{
name: RndCnstScrNonce
desc: Fixed nonce used for address / data scrambling
type: bit [63:0]
randcount: 64
randtype: data
name_top: RndCnstRomCtrlScrNonce
default: 0x755cf00bd7432c3f
randwidth: 64
}
{
name: RndCnstScrKey
desc: Randomised constant used as a scrambling key for ROM data
type: bit [127:0]
randcount: 128
randtype: data
name_top: RndCnstRomCtrlScrKey
default: 0x8cd4e7eff1b9ec59ce812447c5714595
randwidth: 128
}
{
name: SecDisableScrambling
desc:
'''
Disable scrambling and checking in rom_ctrl, turning the block into a
simple ROM wrapper. This isn't intended for real chips, but is useful
for small FPGA targets where there's not space for the PRINCE
primitives.
'''
type: bit
default: 1'b0
expose: "true"
name_top: SecRomCtrlDisableScrambling
}
]
inter_signal_list:
[
{
name: rom_cfg
struct: rom_cfg
package: prim_rom_pkg
type: uni
act: rcv
width: 1
inst_name: rom_ctrl
default: ""
top_signame: ast_rom_cfg
index: -1
}
{
name: pwrmgr_data
struct: pwrmgr_data
package: rom_ctrl_pkg
type: uni
act: req
width: 1
inst_name: rom_ctrl
default: ""
end_idx: -1
top_type: broadcast
top_signame: rom_ctrl_pwrmgr_data
index: -1
}
{
name: keymgr_data
struct: keymgr_data
package: rom_ctrl_pkg
type: uni
act: req
width: 1
inst_name: rom_ctrl
default: ""
end_idx: -1
top_type: broadcast
top_signame: rom_ctrl_keymgr_data
index: -1
}
{
name: kmac_data
struct: app
package: kmac_pkg
type: req_rsp
act: req
width: 1
inst_name: rom_ctrl
default: ""
top_signame: kmac_app
index: 2
}
{
name: regs_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: rom_ctrl
default: ""
end_idx: -1
top_signame: rom_ctrl_regs_tl
index: -1
}
{
name: rom_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: rom_ctrl
default: ""
end_idx: -1
top_signame: rom_ctrl_rom_tl
index: -1
}
]
}
{
name: rv_core_ibex
type: rv_core_ibex
param_decl:
{
PMPEnable: "1"
PMPGranularity: "0"
PMPNumRegions: "16"
MHPMCounterNum: "10"
MHPMCounterWidth: "32"
RV32E: "0"
RV32M: ibex_pkg::RV32MSingleCycle
RV32B: ibex_pkg::RV32BOTEarlGrey
RegFile: ibex_pkg::RegFileFF
BranchTargetALU: "1"
WritebackStage: "1"
ICache: "1"
ICacheECC: "1"
ICacheScramble: "1"
BranchPredictor: "0"
DbgTriggerEn: "1"
DbgHwBreakNum: "4"
SecureIbex: "1"
DmHaltAddr: tl_main_pkg::ADDR_SPACE_RV_DM__MEM + dm::HaltAddress[31:0]
DmExceptionAddr: tl_main_pkg::ADDR_SPACE_RV_DM__MEM + dm::ExceptionAddress[31:0]
PipeLine: "0"
}
clock_srcs:
{
clk_i: main
clk_edn_i: main
clk_esc_i:
{
clock: io_div4
group: secure
}
clk_otp_i:
{
clock: io_div4
group: secure
}
}
clock_group: infra
reset_connections:
{
rst_ni:
{
name: lc
domain: "0"
}
rst_edn_ni:
{
name: lc
domain: "0"
}
rst_esc_ni:
{
name: lc_io_div4
domain: "0"
}
rst_otp_ni:
{
name: lc_io_div4
domain: "0"
}
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_infra
clk_edn_i: clkmgr_aon_clocks.clk_main_infra
clk_esc_i: clkmgr_aon_clocks.clk_io_div4_secure
clk_otp_i: clkmgr_aon_clocks.clk_io_div4_secure
}
domain:
[
"0"
]
memory: {}
param_list:
[
{
name: RndCnstLfsrSeed
desc: Default seed of the PRNG used for random instructions.
type: ibex_pkg::lfsr_seed_t
randcount: 32
randtype: data
name_top: RndCnstRvCoreIbexLfsrSeed
default: 0xf17463db
randwidth: 32
}
{
name: RndCnstLfsrPerm
desc: Permutation applied to the LFSR of the PRNG used for random instructions.
type: ibex_pkg::lfsr_perm_t
randcount: 32
randtype: perm
name_top: RndCnstRvCoreIbexLfsrPerm
default: 0x7d3352c576e13e90efc895c136094776203e9b4d
randwidth: 160
}
{
name: RndCnstIbexKeyDefault
desc: Default icache scrambling key
type: logic [ibex_pkg::SCRAMBLE_KEY_W-1:0]
randcount: 128
randtype: data
name_top: RndCnstRvCoreIbexIbexKeyDefault
default: 0xc10d8dd7f82d15844e53a6af23823858
randwidth: 128
}
{
name: RndCnstIbexNonceDefault
desc: Default icache scrambling nonce
type: logic [ibex_pkg::SCRAMBLE_NONCE_W-1:0]
randcount: 64
randtype: data
name_top: RndCnstRvCoreIbexIbexNonceDefault
default: 0x2f4520c32d5e0d6d
randwidth: 64
}
{
name: PMPEnable
desc: Enable PMP
type: bit
default: "1"
expose: "true"
name_top: RvCoreIbexPMPEnable
}
{
name: PMPGranularity
desc: PMP Granularity
type: int unsigned
default: "0"
expose: "true"
name_top: RvCoreIbexPMPGranularity
}
{
name: PMPNumRegions
desc: PMP number of regions
type: int unsigned
default: "16"
expose: "true"
name_top: RvCoreIbexPMPNumRegions
}
{
name: MHPMCounterNum
desc: "Number of the MHPM counter "
type: int unsigned
default: "10"
expose: "true"
name_top: RvCoreIbexMHPMCounterNum
}
{
name: MHPMCounterWidth
desc: "Width of the MHPM Counter "
type: int unsigned
default: "32"
expose: "true"
name_top: RvCoreIbexMHPMCounterWidth
}
{
name: RV32E
desc: RV32E
type: bit
default: "0"
expose: "true"
name_top: RvCoreIbexRV32E
}
{
name: RV32M
desc: RV32M
type: ibex_pkg::rv32m_e
default: ibex_pkg::RV32MSingleCycle
expose: "true"
name_top: RvCoreIbexRV32M
}
{
name: RV32B
desc: RV32B
type: ibex_pkg::rv32b_e
default: ibex_pkg::RV32BOTEarlGrey
expose: "true"
name_top: RvCoreIbexRV32B
}
{
name: RegFile
desc: Reg file
type: ibex_pkg::regfile_e
default: ibex_pkg::RegFileFF
expose: "true"
name_top: RvCoreIbexRegFile
}
{
name: BranchTargetALU
desc: Branch target ALU
type: bit
default: "1"
expose: "true"
name_top: RvCoreIbexBranchTargetALU
}
{
name: WritebackStage
desc: Write back stage
type: bit
default: "1"
expose: "true"
name_top: RvCoreIbexWritebackStage
}
{
name: ICache
desc: Instruction cache
type: bit
default: "1"
expose: "true"
name_top: RvCoreIbexICache
}
{
name: ICacheECC
desc: Instruction cache ECC
type: bit
default: "1"
expose: "true"
name_top: RvCoreIbexICacheECC
}
{
name: ICacheScramble
desc: Scramble instruction cach
type: bit
default: "1"
expose: "true"
name_top: RvCoreIbexICacheScramble
}
{
name: BranchPredictor
desc: Branch predictor
type: bit
default: "0"
expose: "true"
name_top: RvCoreIbexBranchPredictor
}
{
name: DbgTriggerEn
desc: Enable degug trigger
type: bit
default: "1"
expose: "true"
name_top: RvCoreIbexDbgTriggerEn
}
{
name: DbgHwBreakNum
desc: Number of debug hardware break
type: int
default: "4"
expose: "true"
name_top: RvCoreIbexDbgHwBreakNum
}
{
name: SecureIbex
desc: "Width of the MHPM Counter "
type: bit
default: "1"
expose: "true"
name_top: RvCoreIbexSecureIbex
}
{
name: DmHaltAddr
desc: Halt address
type: int unsigned
default: tl_main_pkg::ADDR_SPACE_RV_DM__MEM + dm::HaltAddress[31:0]
expose: "true"
name_top: RvCoreIbexDmHaltAddr
}
{
name: DmExceptionAddr
desc: Exception address
type: int unsigned
default: tl_main_pkg::ADDR_SPACE_RV_DM__MEM + dm::ExceptionAddress[31:0]
expose: "true"
name_top: RvCoreIbexDmExceptionAddr
}
{
name: PipeLine
desc: Pipe line
type: bit
default: "0"
expose: "true"
name_top: RvCoreIbexPipeLine
}
]
inter_signal_list:
[
{
name: rst_cpu_n
struct: logic
type: uni
act: req
width: 1
inst_name: rv_core_ibex
index: -1
}
{
name: ram_cfg
struct: ram_1p_cfg
package: prim_ram_1p_pkg
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: ast_ram_1p_cfg
index: -1
}
{
name: hart_id
struct: logic
type: uni
act: rcv
width: 32
inst_name: rv_core_ibex
default: ""
package: ""
top_signame: rv_core_ibex_hart_id
index: -1
}
{
name: boot_addr
struct: logic
type: uni
act: rcv
width: 32
inst_name: rv_core_ibex
default: ""
package: ""
top_signame: rv_core_ibex_boot_addr
index: -1
}
{
name: irq_software
struct: logic
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
package: ""
top_signame: rv_plic_msip
index: -1
}
{
name: irq_timer
struct: logic
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
package: ""
top_signame: rv_core_ibex_irq_timer
index: -1
}
{
name: irq_external
struct: logic
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
package: ""
top_signame: rv_plic_irq
index: -1
}
{
name: esc_tx
struct: esc_tx
package: prim_esc_pkg
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: alert_handler_esc_tx
index: 0
}
{
name: esc_rx
struct: esc_rx
package: prim_esc_pkg
type: uni
act: req
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: alert_handler_esc_rx
index: 0
}
{
name: debug_req
struct: logic
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
package: ""
top_signame: rv_dm_debug_req
index: -1
}
{
name: crash_dump
struct: cpu_crash_dump
package: rv_core_ibex_pkg
type: uni
act: req
width: 1
inst_name: rv_core_ibex
default: ""
end_idx: -1
top_type: broadcast
top_signame: rv_core_ibex_crash_dump
index: -1
}
{
name: lc_cpu_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: lc_ctrl_lc_cpu_en
index: -1
}
{
name: pwrmgr_cpu_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: pwrmgr_aon_fetch_en
index: -1
}
{
name: pwrmgr
struct: pwr_cpu
package: pwrmgr_pkg
type: uni
act: req
width: 1
inst_name: rv_core_ibex
default: ""
end_idx: -1
top_type: broadcast
top_signame: rv_core_ibex_pwrmgr
index: -1
}
{
name: nmi_wdog
struct: logic
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
package: ""
top_signame: aon_timer_aon_nmi_wdog_timer_bark
index: -1
}
{
name: edn
struct: edn
package: edn_pkg
type: req_rsp
act: req
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: edn0_edn
index: 7
}
{
name: icache_otp_key
struct: sram_otp_key
package: otp_ctrl_pkg
type: req_rsp
act: req
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: otp_ctrl_sram_otp_key
index: 2
}
{
name: fpga_info
struct: logic
type: uni
act: rcv
width: 32
inst_name: rv_core_ibex
default: ""
package: ""
external: true
top_signame: fpga_info
conn_type: false
index: -1
}
{
name: corei_tl_h
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: main_tl_rv_core_ibex__corei
index: -1
}
{
name: cored_tl_h
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: main_tl_rv_core_ibex__cored
index: -1
}
{
name: cfg_tl_d
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: rv_core_ibex
default: ""
end_idx: -1
top_signame: rv_core_ibex_cfg_tl_d
index: -1
}
]
base_addrs:
{
cfg: 0x411F0000
}
}
]
memory: []
port:
[
{
name: ast
inter_signal_list:
[
{
struct: edn
type: req_rsp
name: edn
act: rsp
package: edn_pkg
inst_name: ast
width: 1
default: ""
top_signame: edn0_edn
index: 2
external: true
conn_type: true
}
{
struct: lc_tx
type: uni
name: lc_dft_en
act: req
package: lc_ctrl_pkg
inst_name: ast
width: 1
default: ""
top_signame: lc_ctrl_lc_dft_en
index: -1
external: true
conn_type: true
}
{
struct: ram_1p_cfg
package: prim_ram_1p_pkg
type: uni
name: ram_1p_cfg
act: rcv
inst_name: ast
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: ast_ram_1p_cfg
index: -1
external: true
conn_type: true
}
{
struct: ram_2p_cfg
package: prim_ram_2p_pkg
type: uni
name: ram_2p_cfg
act: rcv
inst_name: ast
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: ast_ram_2p_cfg
index: -1
external: true
conn_type: true
}
{
struct: rom_cfg
package: prim_rom_pkg
type: uni
name: rom_cfg
act: rcv
inst_name: ast
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: ast_rom_cfg
index: -1
external: true
conn_type: true
}
{
struct: ast_obs_ctrl
type: uni
name: obs_ctrl
act: rcv
package: ast_pkg
inst_name: ast
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: ast_obs_ctrl
index: -1
external: true
conn_type: true
}
]
}
]
inter_module:
{
connect:
{
ast.obs_ctrl:
[
flash_ctrl.obs_ctrl
otp_ctrl.obs_ctrl
]
ast.ram_1p_cfg:
[
otbn.ram_cfg
sram_ctrl_main.cfg
sram_ctrl_ret_aon.cfg
rv_core_ibex.ram_cfg
]
ast.ram_2p_cfg:
[
spi_device.ram_cfg
usbdev.ram_cfg
]
ast.rom_cfg:
[
rom_ctrl.rom_cfg
]
alert_handler.crashdump:
[
rstmgr_aon.alert_dump
]
alert_handler.esc_rx:
[
rv_core_ibex.esc_rx
lc_ctrl.esc_scrap_state0_rx
lc_ctrl.esc_scrap_state1_rx
pwrmgr_aon.esc_rst_rx
]
alert_handler.esc_tx:
[
rv_core_ibex.esc_tx
lc_ctrl.esc_scrap_state0_tx
lc_ctrl.esc_scrap_state1_tx
pwrmgr_aon.esc_rst_tx
]
aon_timer_aon.nmi_wdog_timer_bark:
[
rv_core_ibex.nmi_wdog
]
csrng.csrng_cmd:
[
edn0.csrng_cmd
edn1.csrng_cmd
]
csrng.entropy_src_hw_if:
[
entropy_src.entropy_src_hw_if
]
csrng.cs_aes_halt:
[
entropy_src.cs_aes_halt
]
flash_ctrl.keymgr:
[
keymgr.flash
]
flash_ctrl.otp:
[
otp_ctrl.flash_otp_key
]
flash_ctrl.rma_seed:
[
lc_ctrl.lc_flash_rma_seed
]
otp_ctrl.sram_otp_key:
[
sram_ctrl_main.sram_otp_key
sram_ctrl_ret_aon.sram_otp_key
rv_core_ibex.icache_otp_key
]
pwrmgr_aon.pwr_flash:
[
flash_ctrl.pwrmgr
]
pwrmgr_aon.pwr_rst:
[
rstmgr_aon.pwr
]
pwrmgr_aon.pwr_clk:
[
clkmgr_aon.pwr
]
pwrmgr_aon.pwr_otp:
[
otp_ctrl.pwr_otp
]
pwrmgr_aon.pwr_lc:
[
lc_ctrl.pwr_lc
]
pwrmgr_aon.strap:
[
pinmux_aon.strap_en
]
pwrmgr_aon.low_power:
[
pinmux_aon.sleep_en
aon_timer_aon.sleep_mode
]
pwrmgr_aon.fetch_en:
[
rv_core_ibex.pwrmgr_cpu_en
]
rom_ctrl.pwrmgr_data:
[
pwrmgr_aon.rom_ctrl
]
rom_ctrl.keymgr_data:
[
keymgr.rom_digest
]
lc_ctrl.lc_flash_rma_req:
[
flash_ctrl.rma_req
]
flash_ctrl.rma_ack:
[
otbn.lc_rma_req
]
otbn.lc_rma_ack:
[
lc_ctrl.lc_flash_rma_ack
]
usbdev.usb_dp_pullup:
[
pinmux_aon.usbdev_dppullup_en
]
usbdev.usb_dn_pullup:
[
pinmux_aon.usbdev_dnpullup_en
]
usbdev.usb_aon_suspend_req:
[
pinmux_aon.usbdev_suspend_req
]
usbdev.usb_aon_wake_ack:
[
pinmux_aon.usbdev_wake_ack
]
usbdev.usb_aon_bus_reset:
[
pinmux_aon.usbdev_bus_reset
]
usbdev.usb_aon_sense_lost:
[
pinmux_aon.usbdev_sense_lost
]
pinmux_aon.usbdev_wake_detect_active:
[
usbdev.usb_aon_wake_detect_active
]
edn0.edn:
[
keymgr.edn
otp_ctrl.edn
ast.edn
kmac.entropy
alert_handler.edn
aes.edn
otbn.edn_urnd
rv_core_ibex.edn
]
edn1.edn:
[
otbn.edn_rnd
]
otp_ctrl.otbn_otp_key:
[
otbn.otbn_otp_key
]
otp_ctrl.otp_keymgr_key:
[
keymgr.otp_key
]
keymgr.aes_key:
[
aes.keymgr_key
]
keymgr.kmac_key:
[
kmac.keymgr_key
]
keymgr.otbn_key:
[
otbn.keymgr_key
]
kmac.app:
[
keymgr.kmac_data
lc_ctrl.kmac_data
rom_ctrl.kmac_data
]
kmac.en_masking:
[
keymgr.kmac_en_masking
]
clkmgr_aon.idle:
[
aes.idle
hmac.idle
kmac.idle
otbn.idle
]
pinmux_aon.lc_jtag:
[
lc_ctrl.jtag
]
pinmux_aon.rv_jtag:
[
rv_dm.jtag
]
pinmux_aon.pinmux_hw_debug_en:
[
rv_dm.pinmux_hw_debug_en
]
otp_ctrl.otp_lc_data:
[
lc_ctrl.otp_lc_data
]
lc_ctrl.lc_otp_program:
[
otp_ctrl.lc_otp_program
]
lc_ctrl.lc_otp_vendor_test:
[
otp_ctrl.lc_otp_vendor_test
]
lc_ctrl.lc_keymgr_div:
[
keymgr.lc_keymgr_div
]
lc_ctrl.lc_dft_en:
[
otp_ctrl.lc_dft_en
pinmux_aon.lc_dft_en
ast.lc_dft_en
pwrmgr_aon.lc_dft_en
]
lc_ctrl.lc_nvm_debug_en:
[
flash_ctrl.lc_nvm_debug_en
]
lc_ctrl.lc_hw_debug_en:
[
sram_ctrl_main.lc_hw_debug_en
pinmux_aon.lc_hw_debug_en
csrng.lc_hw_debug_en
rv_dm.lc_hw_debug_en
clkmgr_aon.lc_hw_debug_en
pwrmgr_aon.lc_hw_debug_en
]
lc_ctrl.lc_cpu_en:
[
rv_core_ibex.lc_cpu_en
]
lc_ctrl.lc_keymgr_en:
[
keymgr.lc_keymgr_en
]
lc_ctrl.lc_escalate_en:
[
aes.lc_escalate_en
kmac.lc_escalate_en
otbn.lc_escalate_en
otp_ctrl.lc_escalate_en
sram_ctrl_main.lc_escalate_en
sram_ctrl_ret_aon.lc_escalate_en
aon_timer_aon.lc_escalate_en
flash_ctrl.lc_escalate_en
pinmux_aon.lc_escalate_en
]
lc_ctrl.lc_check_byp_en:
[
otp_ctrl.lc_check_byp_en
pinmux_aon.lc_check_byp_en
]
lc_ctrl.lc_clk_byp_req:
[
clkmgr_aon.lc_clk_byp_req
]
lc_ctrl.lc_clk_byp_ack:
[
clkmgr_aon.lc_clk_byp_ack
]
lc_ctrl.lc_creator_seed_sw_rw_en:
[
otp_ctrl.lc_creator_seed_sw_rw_en
flash_ctrl.lc_creator_seed_sw_rw_en
]
lc_ctrl.lc_owner_seed_sw_rw_en:
[
flash_ctrl.lc_owner_seed_sw_rw_en
]
lc_ctrl.lc_iso_part_sw_rd_en:
[
flash_ctrl.lc_iso_part_sw_rd_en
]
lc_ctrl.lc_iso_part_sw_wr_en:
[
flash_ctrl.lc_iso_part_sw_wr_en
]
lc_ctrl.lc_seed_hw_rd_en:
[
otp_ctrl.lc_seed_hw_rd_en
flash_ctrl.lc_seed_hw_rd_en
]
rv_plic.msip:
[
rv_core_ibex.irq_software
]
rv_plic.irq:
[
rv_core_ibex.irq_external
]
rv_dm.debug_req:
[
rv_core_ibex.debug_req
]
rv_core_ibex.crash_dump:
[
rstmgr_aon.cpu_dump
]
rv_core_ibex.pwrmgr:
[
pwrmgr_aon.pwr_cpu
]
spi_device.passthrough:
[
spi_host0.passthrough
]
rv_dm.ndmreset_req:
[
pwrmgr_aon.ndmreset_req
]
rstmgr_aon.sw_rst_req:
[
pwrmgr_aon.sw_rst_req
]
pwrmgr_aon.wakeups:
[
sysrst_ctrl_aon.wkup_req
adc_ctrl_aon.wkup_req
pinmux_aon.pin_wkup_req
pinmux_aon.usb_wkup_req
aon_timer_aon.wkup_req
sensor_ctrl.wkup_req
]
pwrmgr_aon.rstreqs:
[
sysrst_ctrl_aon.rst_req
aon_timer_aon.aon_timer_rst_req
]
main.tl_rv_core_ibex__corei:
[
rv_core_ibex.corei_tl_h
]
main.tl_rv_core_ibex__cored:
[
rv_core_ibex.cored_tl_h
]
main.tl_rv_dm__sba:
[
rv_dm.sba_tl_h
]
rv_dm.regs_tl_d:
[
main.tl_rv_dm__regs
]
rv_dm.mem_tl_d:
[
main.tl_rv_dm__mem
]
rom_ctrl.rom_tl:
[
main.tl_rom_ctrl__rom
]
rom_ctrl.regs_tl:
[
main.tl_rom_ctrl__regs
]
main.tl_peri:
[
peri.tl_main
]
spi_host0.tl:
[
main.tl_spi_host0
]
spi_host1.tl:
[
main.tl_spi_host1
]
usbdev.tl:
[
main.tl_usbdev
]
flash_ctrl.core_tl:
[
main.tl_flash_ctrl__core
]
flash_ctrl.prim_tl:
[
main.tl_flash_ctrl__prim
]
flash_ctrl.mem_tl:
[
main.tl_flash_ctrl__mem
]
hmac.tl:
[
main.tl_hmac
]
kmac.tl:
[
main.tl_kmac
]
aes.tl:
[
main.tl_aes
]
entropy_src.tl:
[
main.tl_entropy_src
]
csrng.tl:
[
main.tl_csrng
]
edn0.tl:
[
main.tl_edn0
]
edn1.tl:
[
main.tl_edn1
]
rv_plic.tl:
[
main.tl_rv_plic
]
otbn.tl:
[
main.tl_otbn
]
keymgr.tl:
[
main.tl_keymgr
]
rv_core_ibex.cfg_tl_d:
[
main.tl_rv_core_ibex__cfg
]
sram_ctrl_main.regs_tl:
[
main.tl_sram_ctrl_main__regs
]
sram_ctrl_main.ram_tl:
[
main.tl_sram_ctrl_main__ram
]
uart0.tl:
[
peri.tl_uart0
]
uart1.tl:
[
peri.tl_uart1
]
uart2.tl:
[
peri.tl_uart2
]
uart3.tl:
[
peri.tl_uart3
]
i2c0.tl:
[
peri.tl_i2c0
]
i2c1.tl:
[
peri.tl_i2c1
]
i2c2.tl:
[
peri.tl_i2c2
]
pattgen.tl:
[
peri.tl_pattgen
]
pwm_aon.tl:
[
peri.tl_pwm_aon
]
gpio.tl:
[
peri.tl_gpio
]
spi_device.tl:
[
peri.tl_spi_device
]
rv_timer.tl:
[
peri.tl_rv_timer
]
pwrmgr_aon.tl:
[
peri.tl_pwrmgr_aon
]
rstmgr_aon.tl:
[
peri.tl_rstmgr_aon
]
clkmgr_aon.tl:
[
peri.tl_clkmgr_aon
]
pinmux_aon.tl:
[
peri.tl_pinmux_aon
]
otp_ctrl.core_tl:
[
peri.tl_otp_ctrl__core
]
otp_ctrl.prim_tl:
[
peri.tl_otp_ctrl__prim
]
lc_ctrl.tl:
[
peri.tl_lc_ctrl
]
sensor_ctrl.tl:
[
peri.tl_sensor_ctrl
]
alert_handler.tl:
[
peri.tl_alert_handler
]
sram_ctrl_ret_aon.regs_tl:
[
peri.tl_sram_ctrl_ret_aon__regs
]
sram_ctrl_ret_aon.ram_tl:
[
peri.tl_sram_ctrl_ret_aon__ram
]
aon_timer_aon.tl:
[
peri.tl_aon_timer_aon
]
sysrst_ctrl_aon.tl:
[
peri.tl_sysrst_ctrl_aon
]
adc_ctrl_aon.tl:
[
peri.tl_adc_ctrl_aon
]
}
top:
[
clkmgr_aon.clocks
clkmgr_aon.cg_en
rstmgr_aon.resets
rstmgr_aon.rst_en
rv_core_ibex.irq_timer
rv_core_ibex.hart_id
rv_core_ibex.boot_addr
pinmux_aon.dft_jtag
otp_ctrl.otp_hw_cfg
csrng.otp_en_csrng_sw_app_read
entropy_src.otp_en_entropy_src_fw_read
entropy_src.otp_en_entropy_src_fw_over
lc_ctrl.otp_device_id
lc_ctrl.otp_manuf_state
keymgr.otp_device_id
sram_ctrl_main.otp_en_sram_ifetch
]
external:
{
adc_ctrl_aon.adc: adc
ast.edn: ""
ast.lc_dft_en: ""
ast.obs_ctrl: obs_ctrl
ast.ram_1p_cfg: ram_1p_cfg
ast.ram_2p_cfg: ram_2p_cfg
ast.rom_cfg: rom_cfg
clkmgr_aon.jitter_en: clk_main_jitter_en
clkmgr_aon.io_clk_byp_req: io_clk_byp_req
clkmgr_aon.io_clk_byp_ack: io_clk_byp_ack
clkmgr_aon.all_clk_byp_req: all_clk_byp_req
clkmgr_aon.all_clk_byp_ack: all_clk_byp_ack
clkmgr_aon.hi_speed_sel: hi_speed_sel
clkmgr_aon.div_step_down_req: div_step_down_req
clkmgr_aon.calib_rdy: calib_rdy
flash_ctrl.flash_bist_enable: flash_bist_enable
flash_ctrl.flash_power_down_h: flash_power_down_h
flash_ctrl.flash_power_ready_h: flash_power_ready_h
flash_ctrl.flash_test_mode_a: flash_test_mode_a
flash_ctrl.flash_test_voltage_h: flash_test_voltage_h
flash_ctrl.fla_obs: flash_obs
entropy_src.entropy_src_rng: es_rng
entropy_src.rng_fips: es_rng_fips
peri.tl_ast: ast_tl
pinmux_aon.dft_strap_test: dft_strap_test
pinmux_aon.dft_hold_tap_sel: dft_hold_tap_sel
pinmux_aon.usb_dppullup_en: usb_dp_pullup_en
pinmux_aon.usb_dnpullup_en: usb_dn_pullup_en
pwrmgr_aon.pwr_ast: pwrmgr_ast
otp_ctrl.otp_ast_pwr_seq: ""
otp_ctrl.otp_ast_pwr_seq_h: ""
otp_ctrl.otp_ext_voltage_h: otp_ext_voltage_h
otp_ctrl.otp_obs: otp_obs
rstmgr_aon.por_n: por_n
rv_core_ibex.fpga_info: fpga_info
sensor_ctrl.ast_alert: sensor_ctrl_ast_alert
sensor_ctrl.ast_status: sensor_ctrl_ast_status
sensor_ctrl.ast2pinmux: ast2pinmux
sensor_ctrl.ast_init_done: ast_init_done
spi_device.sck_monitor: sck_monitor
usbdev.usb_rx_d: ""
usbdev.usb_tx_d: ""
usbdev.usb_tx_se0: ""
usbdev.usb_tx_use_d_se0: ""
usbdev.usb_rx_enable: ""
usbdev.usb_ref_val: ""
usbdev.usb_ref_pulse: ""
}
}
xbar:
[
{
name: main
clock_srcs:
{
clk_main_i: main
clk_fixed_i: io_div4
clk_usb_i: usb
clk_spi_host0_i: io
clk_spi_host1_i: io_div2
}
clock_group: infra
reset: rst_main_ni
reset_connections:
{
rst_main_ni:
{
name: lc
domain: "0"
}
rst_fixed_ni:
{
name: lc_io_div4
domain: "0"
}
rst_usb_ni:
{
name: lc_usb
domain: "0"
}
rst_spi_host0_ni:
{
name: lc_io
domain: "0"
}
rst_spi_host1_ni:
{
name: lc_io_div2
domain: "0"
}
}
clock_connections:
{
clk_main_i: clkmgr_aon_clocks.clk_main_infra
clk_fixed_i: clkmgr_aon_clocks.clk_io_div4_infra
clk_usb_i: clkmgr_aon_clocks.clk_usb_infra
clk_spi_host0_i: clkmgr_aon_clocks.clk_io_infra
clk_spi_host1_i: clkmgr_aon_clocks.clk_io_div2_infra
}
domain:
[
"0"
]
connections:
{
rv_core_ibex.corei:
[
rom_ctrl.rom
rv_dm.mem
sram_ctrl_main.ram
flash_ctrl.mem
]
rv_core_ibex.cored:
[
rom_ctrl.rom
rom_ctrl.regs
rv_dm.mem
rv_dm.regs
sram_ctrl_main.ram
peri
spi_host0
spi_host1
usbdev
flash_ctrl.core
flash_ctrl.prim
flash_ctrl.mem
aes
entropy_src
csrng
edn0
edn1
hmac
rv_plic
otbn
keymgr
kmac
sram_ctrl_main.regs
rv_core_ibex.cfg
]
rv_dm.sba:
[
rom_ctrl.rom
rom_ctrl.regs
rv_dm.mem
rv_dm.regs
sram_ctrl_main.ram
peri
spi_host0
spi_host1
usbdev
flash_ctrl.core
flash_ctrl.prim
flash_ctrl.mem
aes
entropy_src
csrng
edn0
edn1
hmac
rv_plic
otbn
keymgr
kmac
sram_ctrl_main.regs
rv_core_ibex.cfg
]
}
nodes:
[
{
name: rv_core_ibex.corei
type: host
clock: clk_main_i
reset: rst_main_ni
pipeline: false
xbar: false
stub: false
inst_type: ""
req_fifo_pass: true
rsp_fifo_pass: true
}
{
name: rv_core_ibex.cored
type: host
clock: clk_main_i
reset: rst_main_ni
pipeline: false
xbar: false
stub: false
inst_type: ""
req_fifo_pass: true
rsp_fifo_pass: true
}
{
name: rv_dm.sba
type: host
clock: clk_main_i
reset: rst_main_ni
req_fifo_pass: false
rsp_fifo_pass: false
xbar: false
stub: false
inst_type: ""
pipeline: true
}
{
name: rv_dm.regs
type: device
clock: clk_main_i
reset: rst_main_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: rv_dm
addr_range:
[
{
base_addr: 0x41200000
size_byte: 0x4
}
]
xbar: false
stub: false
pipeline: true
}
{
name: rv_dm.mem
type: device
clock: clk_main_i
reset: rst_main_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: rv_dm
addr_range:
[
{
base_addr: 0x10000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline: true
}
{
name: rom_ctrl.rom
type: device
clock: clk_main_i
reset: rst_main_ni
req_fifo_pass: true
rsp_fifo_pass: false
inst_type: rom_ctrl
addr_range:
[
{
base_addr: 0x8000
size_byte: 0x8000
}
]
xbar: false
stub: false
pipeline: true
}
{
name: rom_ctrl.regs
type: device
clock: clk_main_i
reset: rst_main_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: rom_ctrl
addr_range:
[
{
base_addr: 0x411e0000
size_byte: 0x80
}
]
xbar: false
stub: false
pipeline: true
}
{
name: peri
type: device
clock: clk_fixed_i
reset: rst_fixed_ni
req_fifo_pass: false
rsp_fifo_pass: false
xbar: true
stub: false
pipeline: true
addr_range:
[
{
base_addr: 0x40000000
size_byte: 0x200000
}
{
base_addr: 0x40400000
size_byte: 0x400000
}
]
}
{
name: spi_host0
type: device
clock: clk_spi_host0_i
reset: rst_spi_host0_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: spi_host
addr_range:
[
{
base_addr: 0x40300000
size_byte: 0x40
}
]
xbar: false
stub: false
pipeline: true
}
{
name: spi_host1
type: device
clock: clk_spi_host1_i
reset: rst_spi_host1_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: spi_host
addr_range:
[
{
base_addr: 0x40310000
size_byte: 0x40
}
]
xbar: false
stub: false
pipeline: true
}
{
name: usbdev
type: device
clock: clk_usb_i
reset: rst_usb_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: usbdev
addr_range:
[
{
base_addr: 0x40320000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline: true
}
{
name: flash_ctrl.core
type: device
clock: clk_main_i
reset: rst_main_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: flash_ctrl
addr_range:
[
{
base_addr: 0x41000000
size_byte: 0x200
}
]
xbar: false
stub: false
pipeline: true
}
{
name: flash_ctrl.prim
type: device
clock: clk_main_i
reset: rst_main_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: flash_ctrl
addr_range:
[
{
base_addr: 0x41008000
size_byte: 0x80
}
]
xbar: false
stub: false
pipeline: true
}
{
name: flash_ctrl.mem
type: device
clock: clk_main_i
reset: rst_main_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: flash_ctrl
addr_range:
[
{
base_addr: 0x20000000
size_byte: 0x100000
}
]
xbar: false
stub: false
pipeline: true
}
{
name: hmac
type: device
clock: clk_main_i
reset: rst_main_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: hmac
addr_range:
[
{
base_addr: 0x41110000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline: true
}
{
name: kmac
type: device
clock: clk_main_i
reset: rst_main_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: kmac
addr_range:
[
{
base_addr: 0x41120000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline: true
}
{
name: aes
type: device
clock: clk_main_i
reset: rst_main_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: aes
addr_range:
[
{
base_addr: 0x41100000
size_byte: 0x100
}
]
xbar: false
stub: false
pipeline: true
}
{
name: entropy_src
type: device
clock: clk_main_i
reset: rst_main_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: entropy_src
addr_range:
[
{
base_addr: 0x41160000
size_byte: 0x100
}
]
xbar: false
stub: false
pipeline: true
}
{
name: csrng
type: device
clock: clk_main_i
reset: rst_main_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: csrng
addr_range:
[
{
base_addr: 0x41150000
size_byte: 0x80
}
]
xbar: false
stub: false
pipeline: true
}
{
name: edn0
type: device
clock: clk_main_i
reset: rst_main_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: edn
addr_range:
[
{
base_addr: 0x41170000
size_byte: 0x80
}
]
xbar: false
stub: false
pipeline: true
}
{
name: edn1
type: device
clock: clk_main_i
reset: rst_main_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: edn
addr_range:
[
{
base_addr: 0x41180000
size_byte: 0x80
}
]
xbar: false
stub: false
pipeline: true
}
{
name: rv_plic
type: device
clock: clk_main_i
reset: rst_main_ni
inst_type: rv_plic
req_fifo_pass: false
rsp_fifo_pass: false
addr_range:
[
{
base_addr: 0x48000000
size_byte: 0x8000000
}
]
xbar: false
stub: false
pipeline: true
}
{
name: otbn
type: device
clock: clk_main_i
reset: rst_main_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: otbn
addr_range:
[
{
base_addr: 0x41130000
size_byte: 0x10000
}
]
xbar: false
stub: false
pipeline: true
}
{
name: keymgr
type: device
clock: clk_main_i
reset: rst_main_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: keymgr
addr_range:
[
{
base_addr: 0x41140000
size_byte: 0x100
}
]
xbar: false
stub: false
pipeline: true
}
{
name: rv_core_ibex.cfg
type: device
clock: clk_main_i
reset: rst_main_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: rv_core_ibex
addr_range:
[
{
base_addr: 0x411f0000
size_byte: 0x100
}
]
xbar: false
stub: false
pipeline: true
}
{
name: sram_ctrl_main.regs
type: device
clock: clk_main_i
reset: rst_main_ni
req_fifo_pass: false
rsp_fifo_pass: false
inst_type: sram_ctrl
addr_range:
[
{
base_addr: 0x411c0000
size_byte: 0x20
}
]
xbar: false
stub: false
pipeline: true
}
{
name: sram_ctrl_main.ram
type: device
clock: clk_main_i
reset: rst_main_ni
pipeline: false
inst_type: sram_ctrl
addr_range:
[
{
base_addr: 0x10000000
size_byte: 0x20000
}
]
xbar: false
stub: false
req_fifo_pass: true
}
]
clock: clk_main_i
type: xbar
inter_signal_list:
[
{
name: tl_rv_core_ibex__corei
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: main
default: ""
end_idx: -1
top_signame: main_tl_rv_core_ibex__corei
index: -1
}
{
name: tl_rv_core_ibex__cored
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: main
default: ""
end_idx: -1
top_signame: main_tl_rv_core_ibex__cored
index: -1
}
{
name: tl_rv_dm__sba
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: main
default: ""
end_idx: -1
top_signame: main_tl_rv_dm__sba
index: -1
}
{
name: tl_rv_dm__regs
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: rv_dm_regs_tl_d
index: -1
}
{
name: tl_rv_dm__mem
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: rv_dm_mem_tl_d
index: -1
}
{
name: tl_rom_ctrl__rom
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: rom_ctrl_rom_tl
index: -1
}
{
name: tl_rom_ctrl__regs
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: rom_ctrl_regs_tl
index: -1
}
{
name: tl_peri
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
end_idx: -1
top_signame: main_tl_peri
index: -1
}
{
name: tl_spi_host0
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: spi_host0_tl
index: -1
}
{
name: tl_spi_host1
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: spi_host1_tl
index: -1
}
{
name: tl_usbdev
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: usbdev_tl
index: -1
}
{
name: tl_flash_ctrl__core
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: flash_ctrl_core_tl
index: -1
}
{
name: tl_flash_ctrl__prim
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: flash_ctrl_prim_tl
index: -1
}
{
name: tl_flash_ctrl__mem
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: flash_ctrl_mem_tl
index: -1
}
{
name: tl_hmac
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: hmac_tl
index: -1
}
{
name: tl_kmac
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: kmac_tl
index: -1
}
{
name: tl_aes
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: aes_tl
index: -1
}
{
name: tl_entropy_src
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: entropy_src_tl
index: -1
}
{
name: tl_csrng
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: csrng_tl
index: -1
}
{
name: tl_edn0
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: edn0_tl
index: -1
}
{
name: tl_edn1
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: edn1_tl
index: -1
}
{
name: tl_rv_plic
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: rv_plic_tl
index: -1
}
{
name: tl_otbn
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: otbn_tl
index: -1
}
{
name: tl_keymgr
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: keymgr_tl
index: -1
}
{
name: tl_rv_core_ibex__cfg
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: rv_core_ibex_cfg_tl_d
index: -1
}
{
name: tl_sram_ctrl_main__regs
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: sram_ctrl_main_regs_tl
index: -1
}
{
name: tl_sram_ctrl_main__ram
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: sram_ctrl_main_ram_tl
index: -1
}
]
}
{
name: peri
clock_srcs:
{
clk_peri_i: io_div4
}
clock_group: infra
reset: rst_peri_ni
reset_connections:
{
rst_peri_ni:
{
name: lc_io_div4
domain: "0"
}
}
clock_connections:
{
clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra
}
domain:
[
"0"
]
connections:
{
main:
[
uart0
uart1
uart2
uart3
i2c0
i2c1
i2c2
pattgen
gpio
spi_device
rv_timer
pwrmgr_aon
rstmgr_aon
clkmgr_aon
pinmux_aon
otp_ctrl.core
otp_ctrl.prim
lc_ctrl
sensor_ctrl
alert_handler
ast
sram_ctrl_ret_aon.ram
sram_ctrl_ret_aon.regs
aon_timer_aon
adc_ctrl_aon
sysrst_ctrl_aon
pwm_aon
]
}
nodes:
[
{
name: main
type: host
clock: clk_peri_i
reset: rst_peri_ni
xbar: true
pipeline: false
stub: false
inst_type: ""
req_fifo_pass: true
rsp_fifo_pass: true
}
{
name: uart0
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: uart
addr_range:
[
{
base_addr: 0x40000000
size_byte: 0x40
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: uart1
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: uart
addr_range:
[
{
base_addr: 0x40010000
size_byte: 0x40
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: uart2
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: uart
addr_range:
[
{
base_addr: 0x40020000
size_byte: 0x40
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: uart3
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: uart
addr_range:
[
{
base_addr: 0x40030000
size_byte: 0x40
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: i2c0
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: i2c
addr_range:
[
{
base_addr: 0x40080000
size_byte: 0x80
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: i2c1
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: i2c
addr_range:
[
{
base_addr: 0x40090000
size_byte: 0x80
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: i2c2
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: i2c
addr_range:
[
{
base_addr: 0x400a0000
size_byte: 0x80
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: pattgen
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: pattgen
addr_range:
[
{
base_addr: 0x400e0000
size_byte: 0x40
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: pwm_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: pwm
addr_range:
[
{
base_addr: 0x40450000
size_byte: 0x80
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: gpio
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: gpio
addr_range:
[
{
base_addr: 0x40040000
size_byte: 0x40
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: spi_device
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: spi_device
addr_range:
[
{
base_addr: 0x40050000
size_byte: 0x2000
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: rv_timer
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: rv_timer
addr_range:
[
{
base_addr: 0x40100000
size_byte: 0x200
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: pwrmgr_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: pwrmgr
addr_range:
[
{
base_addr: 0x40400000
size_byte: 0x80
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: rstmgr_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: rstmgr
addr_range:
[
{
base_addr: 0x40410000
size_byte: 0x80
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: clkmgr_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: clkmgr
addr_range:
[
{
base_addr: 0x40420000
size_byte: 0x80
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: pinmux_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: pinmux
addr_range:
[
{
base_addr: 0x40460000
size_byte: 0x1000
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: otp_ctrl.core
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: otp_ctrl
addr_range:
[
{
base_addr: 0x40130000
size_byte: 0x2000
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: otp_ctrl.prim
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: otp_ctrl
addr_range:
[
{
base_addr: 0x40132000
size_byte: 0x20
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: lc_ctrl
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: lc_ctrl
addr_range:
[
{
base_addr: 0x40140000
size_byte: 0x100
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: sensor_ctrl
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: sensor_ctrl
addr_range:
[
{
base_addr: 0x40490000
size_byte: 0x40
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: alert_handler
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: alert_handler
addr_range:
[
{
base_addr: 0x40150000
size_byte: 0x800
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: sram_ctrl_ret_aon.regs
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: sram_ctrl
addr_range:
[
{
base_addr: 0x40500000
size_byte: 0x20
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: sram_ctrl_ret_aon.ram
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: sram_ctrl
addr_range:
[
{
base_addr: 0x40600000
size_byte: 0x1000
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: aon_timer_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: aon_timer
addr_range:
[
{
base_addr: 0x40470000
size_byte: 0x40
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: sysrst_ctrl_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: sysrst_ctrl
addr_range:
[
{
base_addr: 0x40430000
size_byte: 0x100
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: adc_ctrl_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: adc_ctrl
addr_range:
[
{
base_addr: 0x40440000
size_byte: 0x80
}
]
xbar: false
stub: false
req_fifo_pass: true
}
{
name: ast
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: false
inst_type: ast
addr_range:
[
{
base_addr: 0x40480000
size_byte: 0x400
}
]
xbar: false
stub: true
req_fifo_pass: true
}
]
clock: clk_peri_i
type: xbar
inter_signal_list:
[
{
name: tl_main
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: peri
default: ""
top_signame: main_tl_peri
index: -1
}
{
name: tl_uart0
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: uart0_tl
index: -1
}
{
name: tl_uart1
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: uart1_tl
index: -1
}
{
name: tl_uart2
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: uart2_tl
index: -1
}
{
name: tl_uart3
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: uart3_tl
index: -1
}
{
name: tl_i2c0
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: i2c0_tl
index: -1
}
{
name: tl_i2c1
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: i2c1_tl
index: -1
}
{
name: tl_i2c2
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: i2c2_tl
index: -1
}
{
name: tl_pattgen
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: pattgen_tl
index: -1
}
{
name: tl_pwm_aon
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: pwm_aon_tl
index: -1
}
{
name: tl_gpio
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: gpio_tl
index: -1
}
{
name: tl_spi_device
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: spi_device_tl
index: -1
}
{
name: tl_rv_timer
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: rv_timer_tl
index: -1
}
{
name: tl_pwrmgr_aon
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: pwrmgr_aon_tl
index: -1
}
{
name: tl_rstmgr_aon
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: rstmgr_aon_tl
index: -1
}
{
name: tl_clkmgr_aon
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: clkmgr_aon_tl
index: -1
}
{
name: tl_pinmux_aon
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: pinmux_aon_tl
index: -1
}
{
name: tl_otp_ctrl__core
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: otp_ctrl_core_tl
index: -1
}
{
name: tl_otp_ctrl__prim
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: otp_ctrl_prim_tl
index: -1
}
{
name: tl_lc_ctrl
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: lc_ctrl_tl
index: -1
}
{
name: tl_sensor_ctrl
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: sensor_ctrl_tl
index: -1
}
{
name: tl_alert_handler
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: alert_handler_tl
index: -1
}
{
name: tl_sram_ctrl_ret_aon__regs
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: sram_ctrl_ret_aon_regs_tl
index: -1
}
{
name: tl_sram_ctrl_ret_aon__ram
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: sram_ctrl_ret_aon_ram_tl
index: -1
}
{
name: tl_aon_timer_aon
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: aon_timer_aon_tl
index: -1
}
{
name: tl_sysrst_ctrl_aon
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: sysrst_ctrl_aon_tl
index: -1
}
{
name: tl_adc_ctrl_aon
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: adc_ctrl_aon_tl
index: -1
}
{
name: tl_ast
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
external: true
top_signame: ast_tl
conn_type: false
index: -1
}
]
}
]
pinout:
{
banks:
[
VCC
AVCC
VIOA
VIOB
]
pads:
[
{
name: POR_N
type: InputStd
bank: VCC
connection: manual
desc: System reset
port_type: inout
idx: 0
}
{
name: USB_P
type: DualBidirTol
bank: VCC
connection: manual
desc: USB P signal
port_type: inout
idx: 1
}
{
name: USB_N
type: DualBidirTol
bank: VCC
connection: manual
desc: USB N signal
port_type: inout
idx: 2
}
{
name: CC1
type: InputStd
bank: AVCC
connection: manual
desc: ADC input 1
port_type: `INOUT_AI
idx: 3
}
{
name: CC2
type: InputStd
bank: AVCC
connection: manual
desc: ADC input 2
port_type: `INOUT_AI
idx: 4
}
{
name: FLASH_TEST_VOLT
type: AnalogIn0
bank: VCC
connection: manual
desc: Flash test voltage input
port_type: inout
idx: 5
}
{
name: FLASH_TEST_MODE0
type: InputStd
bank: VCC
connection: manual
desc: Flash test mode signal
port_type: inout
idx: 6
}
{
name: FLASH_TEST_MODE1
type: InputStd
bank: VCC
connection: manual
desc: Flash test mode signal
port_type: inout
idx: 7
}
{
name: OTP_EXT_VOLT
type: AnalogIn1
bank: VCC
connection: manual
desc: OTP external voltage input
port_type: inout
idx: 8
}
{
name: SPI_HOST_D0
type: BidirStd
bank: VIOA
connection: direct
desc: SPI host data
port_type: inout
idx: 9
}
{
name: SPI_HOST_D1
type: BidirStd
bank: VIOA
connection: direct
desc: SPI host data
port_type: inout
idx: 10
}
{
name: SPI_HOST_D2
type: BidirStd
bank: VIOA
connection: direct
desc: SPI host data
port_type: inout
idx: 11
}
{
name: SPI_HOST_D3
type: BidirStd
bank: VIOA
connection: direct
desc: SPI host data
port_type: inout
idx: 12
}
{
name: SPI_HOST_CLK
type: BidirStd
bank: VIOA
connection: direct
desc: SPI host clock
port_type: inout
idx: 13
}
{
name: SPI_HOST_CS_L
type: BidirStd
bank: VIOA
connection: direct
desc: SPI host chip select
port_type: inout
idx: 14
}
{
name: SPI_DEV_D0
type: BidirStd
bank: VIOA
connection: direct
desc: SPI device data
port_type: inout
idx: 15
}
{
name: SPI_DEV_D1
type: BidirStd
bank: VIOA
connection: direct
desc: SPI device data
port_type: inout
idx: 16
}
{
name: SPI_DEV_D2
type: BidirStd
bank: VIOA
connection: direct
desc: SPI device data
port_type: inout
idx: 17
}
{
name: SPI_DEV_D3
type: BidirStd
bank: VIOA
connection: direct
desc: SPI device data
port_type: inout
idx: 18
}
{
name: SPI_DEV_CLK
type: InputStd
bank: VIOA
connection: direct
desc: SPI device clock
port_type: inout
idx: 19
}
{
name: SPI_DEV_CS_L
type: InputStd
bank: VIOA
connection: direct
desc: SPI device chip select
port_type: inout
idx: 20
}
{
name: IOA0
type: BidirStd
bank: VIOA
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 0
}
{
name: IOA1
type: BidirStd
bank: VIOA
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 1
}
{
name: IOA2
type: BidirStd
bank: VIOA
connection: muxed
desc: Muxed IO pad
port_type: `INOUT_AO
idx: 2
}
{
name: IOA3
type: BidirStd
bank: VIOA
connection: muxed
desc: Muxed IO pad
port_type: `INOUT_AO
idx: 3
}
{
name: IOA4
type: BidirStd
bank: VIOA
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 4
}
{
name: IOA5
type: BidirStd
bank: VIOA
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 5
}
{
name: IOA6
type: BidirOd
bank: VIOA
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 6
}
{
name: IOA7
type: BidirOd
bank: VIOA
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 7
}
{
name: IOA8
type: BidirOd
bank: VIOA
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 8
}
{
name: IOB0
type: BidirStd
bank: VIOB
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 9
}
{
name: IOB1
type: BidirStd
bank: VIOB
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 10
}
{
name: IOB2
type: BidirStd
bank: VIOB
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 11
}
{
name: IOB3
type: BidirStd
bank: VIOB
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 12
}
{
name: IOB4
type: BidirStd
bank: VIOB
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 13
}
{
name: IOB5
type: BidirStd
bank: VIOB
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 14
}
{
name: IOB6
type: BidirStd
bank: VIOB
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 15
}
{
name: IOB7
type: BidirStd
bank: VIOB
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 16
}
{
name: IOB8
type: BidirStd
bank: VIOB
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 17
}
{
name: IOB9
type: BidirOd
bank: VIOB
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 18
}
{
name: IOB10
type: BidirOd
bank: VIOB
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 19
}
{
name: IOB11
type: BidirOd
bank: VIOB
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 20
}
{
name: IOB12
type: BidirOd
bank: VIOB
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 21
}
{
name: IOC0
type: BidirStd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 22
}
{
name: IOC1
type: BidirStd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 23
}
{
name: IOC2
type: BidirStd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 24
}
{
name: IOC3
type: BidirStd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 25
}
{
name: IOC4
type: BidirStd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 26
}
{
name: IOC5
type: BidirStd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 27
}
{
name: IOC6
type: BidirStd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 28
}
{
name: IOC7
type: BidirStd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 29
}
{
name: IOC8
type: BidirStd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 30
}
{
name: IOC9
type: BidirStd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 31
}
{
name: IOC10
type: BidirOd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 32
}
{
name: IOC11
type: BidirOd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 33
}
{
name: IOC12
type: BidirOd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 34
}
{
name: IOR0
type: BidirStd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 35
}
{
name: IOR1
type: BidirStd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 36
}
{
name: IOR2
type: BidirStd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 37
}
{
name: IOR3
type: BidirStd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 38
}
{
name: IOR4
type: BidirStd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 39
}
{
name: IOR5
type: BidirStd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 40
}
{
name: IOR6
type: BidirStd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 41
}
{
name: IOR7
type: BidirStd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 42
}
{
name: IOR8
type: BidirOd
bank: VCC
connection: direct
desc: Dedicated sysrst_ctrl output (ec_rst_l)
port_type: inout
idx: 21
}
{
name: IOR9
type: BidirOd
bank: VCC
connection: direct
desc: Dedicated sysrst_ctrl output (flash_wp_l))
port_type: inout
idx: 22
}
{
name: IOR10
type: BidirOd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 43
}
{
name: IOR11
type: BidirOd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 44
}
{
name: IOR12
type: BidirOd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 45
}
{
name: IOR13
type: BidirOd
bank: VCC
connection: muxed
desc: Muxed IO pad
port_type: inout
idx: 46
}
]
}
pinmux:
{
signals:
[
{
instance: usbdev
port: usb_dp
connection: manual
pad: ""
desc: ""
attr: BidirStd
}
{
instance: usbdev
port: usb_dn
connection: manual
pad: ""
desc: ""
attr: BidirStd
}
{
instance: spi_host0
port: sck
connection: direct
pad: SPI_HOST_CLK
desc: ""
attr: BidirStd
}
{
instance: spi_host0
port: csb
connection: direct
pad: SPI_HOST_CS_L
desc: ""
attr: BidirStd
}
{
instance: spi_host0
port: sd[0]
connection: direct
pad: SPI_HOST_D0
desc: ""
attr: BidirStd
}
{
instance: spi_host0
port: sd[1]
connection: direct
pad: SPI_HOST_D1
desc: ""
attr: BidirStd
}
{
instance: spi_host0
port: sd[2]
connection: direct
pad: SPI_HOST_D2
desc: ""
attr: BidirStd
}
{
instance: spi_host0
port: sd[3]
connection: direct
pad: SPI_HOST_D3
desc: ""
attr: BidirStd
}
{
instance: spi_device
port: sck
connection: direct
pad: SPI_DEV_CLK
desc: ""
attr: InputStd
}
{
instance: spi_device
port: csb
connection: direct
pad: SPI_DEV_CS_L
desc: ""
attr: InputStd
}
{
instance: spi_device
port: sd[0]
connection: direct
pad: SPI_DEV_D0
desc: ""
attr: BidirStd
}
{
instance: spi_device
port: sd[1]
connection: direct
pad: SPI_DEV_D1
desc: ""
attr: BidirStd
}
{
instance: spi_device
port: sd[2]
connection: direct
pad: SPI_DEV_D2
desc: ""
attr: BidirStd
}
{
instance: spi_device
port: sd[3]
connection: direct
pad: SPI_DEV_D3
desc: ""
attr: BidirStd
}
{
instance: gpio
port: ""
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: uart0
port: ""
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: uart1
port: ""
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: uart2
port: ""
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: uart3
port: ""
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: i2c0
port: ""
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: i2c1
port: ""
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: i2c2
port: ""
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: pattgen
port: ""
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: spi_device
port: tpm_csb
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: spi_host1
port: ""
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: flash_ctrl
port: ""
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: sensor_ctrl
port: ""
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: pwm_aon
port: ""
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: otp_ctrl
port: test[0]
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: sysrst_ctrl_aon
port: ac_present
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: sysrst_ctrl_aon
port: key0_in
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: sysrst_ctrl_aon
port: key1_in
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: sysrst_ctrl_aon
port: key2_in
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: sysrst_ctrl_aon
port: pwrb_in
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: sysrst_ctrl_aon
port: bat_disable
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: sysrst_ctrl_aon
port: ec_rst_l
connection: direct
pad: IOR8
desc: ""
attr: BidirOd
}
{
instance: sysrst_ctrl_aon
port: flash_wp_l
connection: direct
pad: IOR9
desc: ""
attr: BidirOd
}
{
instance: sysrst_ctrl_aon
port: key0_out
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: sysrst_ctrl_aon
port: key1_out
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: sysrst_ctrl_aon
port: key2_out
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: sysrst_ctrl_aon
port: pwrb_out
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: sysrst_ctrl_aon
port: lid_open
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: sysrst_ctrl_aon
port: z3_wakeup
connection: muxed
pad: ""
desc: ""
attr: ""
}
{
instance: usbdev
port: sense
connection: muxed
pad: ""
desc: ""
attr: ""
}
]
num_wkup_detect: 8
wkup_cnt_width: 8
ios:
[
{
name: usbdev_usb_dp
width: 1
type: inout
idx: -1
pad: ""
attr: BidirStd
connection: manual
desc: ""
glob_idx: 0
}
{
name: usbdev_usb_dn
width: 1
type: inout
idx: -1
pad: ""
attr: BidirStd
connection: manual
desc: ""
glob_idx: 1
}
{
name: spi_host0_sd
width: 4
type: inout
idx: 0
pad: SPI_HOST_D0
attr: BidirStd
connection: direct
desc: ""
glob_idx: 2
}
{
name: spi_host0_sd
width: 4
type: inout
idx: 1
pad: SPI_HOST_D1
attr: BidirStd
connection: direct
desc: ""
glob_idx: 3
}
{
name: spi_host0_sd
width: 4
type: inout
idx: 2
pad: SPI_HOST_D2
attr: BidirStd
connection: direct
desc: ""
glob_idx: 4
}
{
name: spi_host0_sd
width: 4
type: inout
idx: 3
pad: SPI_HOST_D3
attr: BidirStd
connection: direct
desc: ""
glob_idx: 5
}
{
name: spi_device_sd
width: 4
type: inout
idx: 0
pad: SPI_DEV_D0
attr: BidirStd
connection: direct
desc: ""
glob_idx: 6
}
{
name: spi_device_sd
width: 4
type: inout
idx: 1
pad: SPI_DEV_D1
attr: BidirStd
connection: direct
desc: ""
glob_idx: 7
}
{
name: spi_device_sd
width: 4
type: inout
idx: 2
pad: SPI_DEV_D2
attr: BidirStd
connection: direct
desc: ""
glob_idx: 8
}
{
name: spi_device_sd
width: 4
type: inout
idx: 3
pad: SPI_DEV_D3
attr: BidirStd
connection: direct
desc: ""
glob_idx: 9
}
{
name: gpio_gpio
width: 32
type: inout
idx: 0
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 0
}
{
name: gpio_gpio
width: 32
type: inout
idx: 1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 1
}
{
name: gpio_gpio
width: 32
type: inout
idx: 2
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 2
}
{
name: gpio_gpio
width: 32
type: inout
idx: 3
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 3
}
{
name: gpio_gpio
width: 32
type: inout
idx: 4
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 4
}
{
name: gpio_gpio
width: 32
type: inout
idx: 5
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 5
}
{
name: gpio_gpio
width: 32
type: inout
idx: 6
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 6
}
{
name: gpio_gpio
width: 32
type: inout
idx: 7
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 7
}
{
name: gpio_gpio
width: 32
type: inout
idx: 8
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 8
}
{
name: gpio_gpio
width: 32
type: inout
idx: 9
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 9
}
{
name: gpio_gpio
width: 32
type: inout
idx: 10
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 10
}
{
name: gpio_gpio
width: 32
type: inout
idx: 11
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 11
}
{
name: gpio_gpio
width: 32
type: inout
idx: 12
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 12
}
{
name: gpio_gpio
width: 32
type: inout
idx: 13
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 13
}
{
name: gpio_gpio
width: 32
type: inout
idx: 14
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 14
}
{
name: gpio_gpio
width: 32
type: inout
idx: 15
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 15
}
{
name: gpio_gpio
width: 32
type: inout
idx: 16
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 16
}
{
name: gpio_gpio
width: 32
type: inout
idx: 17
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 17
}
{
name: gpio_gpio
width: 32
type: inout
idx: 18
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 18
}
{
name: gpio_gpio
width: 32
type: inout
idx: 19
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 19
}
{
name: gpio_gpio
width: 32
type: inout
idx: 20
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 20
}
{
name: gpio_gpio
width: 32
type: inout
idx: 21
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 21
}
{
name: gpio_gpio
width: 32
type: inout
idx: 22
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 22
}
{
name: gpio_gpio
width: 32
type: inout
idx: 23
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 23
}
{
name: gpio_gpio
width: 32
type: inout
idx: 24
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 24
}
{
name: gpio_gpio
width: 32
type: inout
idx: 25
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 25
}
{
name: gpio_gpio
width: 32
type: inout
idx: 26
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 26
}
{
name: gpio_gpio
width: 32
type: inout
idx: 27
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 27
}
{
name: gpio_gpio
width: 32
type: inout
idx: 28
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 28
}
{
name: gpio_gpio
width: 32
type: inout
idx: 29
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 29
}
{
name: gpio_gpio
width: 32
type: inout
idx: 30
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 30
}
{
name: gpio_gpio
width: 32
type: inout
idx: 31
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 31
}
{
name: i2c0_sda
width: 1
type: inout
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 32
}
{
name: i2c0_scl
width: 1
type: inout
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 33
}
{
name: i2c1_sda
width: 1
type: inout
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 34
}
{
name: i2c1_scl
width: 1
type: inout
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 35
}
{
name: i2c2_sda
width: 1
type: inout
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 36
}
{
name: i2c2_scl
width: 1
type: inout
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 37
}
{
name: spi_host1_sd
width: 4
type: inout
idx: 0
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 38
}
{
name: spi_host1_sd
width: 4
type: inout
idx: 1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 39
}
{
name: spi_host1_sd
width: 4
type: inout
idx: 2
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 40
}
{
name: spi_host1_sd
width: 4
type: inout
idx: 3
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 41
}
{
name: sysrst_ctrl_aon_ec_rst_l
width: 1
type: inout
idx: -1
pad: IOR8
attr: BidirOd
connection: direct
desc: ""
glob_idx: 10
}
{
name: sysrst_ctrl_aon_flash_wp_l
width: 1
type: inout
idx: -1
pad: IOR9
attr: BidirOd
connection: direct
desc: ""
glob_idx: 11
}
{
name: spi_device_sck
width: 1
type: input
idx: -1
pad: SPI_DEV_CLK
attr: InputStd
connection: direct
desc: ""
glob_idx: 12
}
{
name: spi_device_csb
width: 1
type: input
idx: -1
pad: SPI_DEV_CS_L
attr: InputStd
connection: direct
desc: ""
glob_idx: 13
}
{
name: uart0_rx
width: 1
type: input
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 42
}
{
name: uart1_rx
width: 1
type: input
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 43
}
{
name: uart2_rx
width: 1
type: input
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 44
}
{
name: uart3_rx
width: 1
type: input
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 45
}
{
name: spi_device_tpm_csb
width: 1
type: input
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 46
}
{
name: flash_ctrl_tck
width: 1
type: input
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 47
}
{
name: flash_ctrl_tms
width: 1
type: input
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 48
}
{
name: flash_ctrl_tdi
width: 1
type: input
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 49
}
{
name: sysrst_ctrl_aon_ac_present
width: 1
type: input
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 50
}
{
name: sysrst_ctrl_aon_key0_in
width: 1
type: input
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 51
}
{
name: sysrst_ctrl_aon_key1_in
width: 1
type: input
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 52
}
{
name: sysrst_ctrl_aon_key2_in
width: 1
type: input
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 53
}
{
name: sysrst_ctrl_aon_pwrb_in
width: 1
type: input
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 54
}
{
name: sysrst_ctrl_aon_lid_open
width: 1
type: input
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 55
}
{
name: usbdev_sense
width: 1
type: input
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 56
}
{
name: spi_host0_sck
width: 1
type: output
idx: -1
pad: SPI_HOST_CLK
attr: BidirStd
connection: direct
desc: ""
glob_idx: 14
}
{
name: spi_host0_csb
width: 1
type: output
idx: -1
pad: SPI_HOST_CS_L
attr: BidirStd
connection: direct
desc: ""
glob_idx: 15
}
{
name: uart0_tx
width: 1
type: output
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 42
}
{
name: uart1_tx
width: 1
type: output
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 43
}
{
name: uart2_tx
width: 1
type: output
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 44
}
{
name: uart3_tx
width: 1
type: output
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 45
}
{
name: pattgen_pda0_tx
width: 1
type: output
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 46
}
{
name: pattgen_pcl0_tx
width: 1
type: output
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 47
}
{
name: pattgen_pda1_tx
width: 1
type: output
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 48
}
{
name: pattgen_pcl1_tx
width: 1
type: output
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 49
}
{
name: spi_host1_sck
width: 1
type: output
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 50
}
{
name: spi_host1_csb
width: 1
type: output
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 51
}
{
name: flash_ctrl_tdo
width: 1
type: output
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 52
}
{
name: sensor_ctrl_ast_debug_out
width: 9
type: output
idx: 0
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 53
}
{
name: sensor_ctrl_ast_debug_out
width: 9
type: output
idx: 1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 54
}
{
name: sensor_ctrl_ast_debug_out
width: 9
type: output
idx: 2
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 55
}
{
name: sensor_ctrl_ast_debug_out
width: 9
type: output
idx: 3
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 56
}
{
name: sensor_ctrl_ast_debug_out
width: 9
type: output
idx: 4
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 57
}
{
name: sensor_ctrl_ast_debug_out
width: 9
type: output
idx: 5
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 58
}
{
name: sensor_ctrl_ast_debug_out
width: 9
type: output
idx: 6
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 59
}
{
name: sensor_ctrl_ast_debug_out
width: 9
type: output
idx: 7
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 60
}
{
name: sensor_ctrl_ast_debug_out
width: 9
type: output
idx: 8
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 61
}
{
name: pwm_aon_pwm
width: 6
type: output
idx: 0
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 62
}
{
name: pwm_aon_pwm
width: 6
type: output
idx: 1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 63
}
{
name: pwm_aon_pwm
width: 6
type: output
idx: 2
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 64
}
{
name: pwm_aon_pwm
width: 6
type: output
idx: 3
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 65
}
{
name: pwm_aon_pwm
width: 6
type: output
idx: 4
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 66
}
{
name: pwm_aon_pwm
width: 6
type: output
idx: 5
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 67
}
{
name: otp_ctrl_test
width: 8
type: output
idx: 0
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 68
}
{
name: sysrst_ctrl_aon_bat_disable
width: 1
type: output
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 69
}
{
name: sysrst_ctrl_aon_key0_out
width: 1
type: output
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 70
}
{
name: sysrst_ctrl_aon_key1_out
width: 1
type: output
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 71
}
{
name: sysrst_ctrl_aon_key2_out
width: 1
type: output
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 72
}
{
name: sysrst_ctrl_aon_pwrb_out
width: 1
type: output
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 73
}
{
name: sysrst_ctrl_aon_z3_wakeup
width: 1
type: output
idx: -1
pad: ""
attr: ""
connection: muxed
desc: ""
glob_idx: 74
}
]
io_counts:
{
dedicated:
{
inouts: 12
inputs: 2
outputs: 2
pads: 23
}
muxed:
{
inouts: 42
inputs: 15
outputs: 33
pads: 47
}
}
}
targets:
[
{
name: asic
pinout:
{
remove_ports: []
remove_pads: []
add_pads:
[
{
name: AST_MISC
type: InputStd
bank: VCC
connection: manual
desc: Extra infrastructure pad for AST
port_type: inout
}
]
}
pinmux:
{
special_signals:
[
{
name: tap0
pad: IOC8
desc: TAP strap signal.
idx: 30
}
{
name: tap1
pad: IOC5
desc: TAP strap signal.
idx: 27
}
{
name: dft0
pad: IOC3
desc: DFT strap signal.
idx: 25
}
{
name: dft1
pad: IOC4
desc: DFT strap signal.
idx: 26
}
{
name: tck
pad: IOR3
desc: JTAG tck signal.
idx: 38
}
{
name: tms
pad: IOR0
desc: JTAG tms signal.
idx: 35
}
{
name: trst_n
pad: IOR4
desc: JTAG trst_n signal.
idx: 39
}
{
name: tdi
pad: IOR2
desc: JTAG tdi signal.
idx: 37
}
{
name: tdo
pad: IOR1
desc: JTAG tdo signal.
idx: 36
}
]
}
}
{
name: cw310
pinout:
{
remove_ports: []
remove_pads:
[
CC1
CC2
FLASH_TEST_VOLT
OTP_EXT_VOLT
FLASH_TEST_MODE0
FLASH_TEST_MODE1
USB_P
USB_N
]
add_pads:
[
{
name: IO_CLK
type: InputStd
bank: VCC
connection: manual
desc: Extra clock input for FPGA target
port_type: inout
}
{
name: POR_BUTTON_N
type: InputStd
bank: VCC
connection: manual
desc: Power-on reset button input
port_type: inout
}
{
name: JTAG_SRST_N
type: InputStd
bank: VCC
connection: manual
desc: JTAG header SRST, triggers POR
port_type: inout
}
{
name: IO_USB_CONNECT
type: BidirStd
bank: VCC
connection: manual
desc: Manual USB UPHY signal for FPGA target
port_type: inout
}
{
name: IO_USB_DP_TX
type: BidirStd
bank: VCC
connection: manual
desc: Manual USB UPHY signal for FPGA target
port_type: inout
}
{
name: IO_USB_DN_TX
type: BidirStd
bank: VCC
connection: manual
desc: Manual USB UPHY signal for FPGA target
port_type: inout
}
{
name: IO_USB_D_RX
type: BidirStd
bank: VCC
connection: manual
desc: Manual USB UPHY signal for FPGA target
port_type: inout
}
{
name: IO_USB_DP_RX
type: BidirStd
bank: VCC
connection: manual
desc: Manual USB UPHY signal for FPGA target
port_type: inout
}
{
name: IO_USB_DN_RX
type: BidirStd
bank: VCC
connection: manual
desc: Manual USB UPHY signal for FPGA target
port_type: inout
}
{
name: IO_USB_OE_N
type: BidirStd
bank: VCC
connection: manual
desc: Manual USB UPHY signal for FPGA target
port_type: inout
}
{
name: IO_USB_SPEED
type: BidirStd
bank: VCC
connection: manual
desc: Manual USB UPHY signal for FPGA target
port_type: inout
}
{
name: IO_USB_SUSPEND
type: BidirStd
bank: VCC
connection: manual
desc: Manual USB UPHY signal for FPGA target
port_type: inout
}
{
name: IO_CLKOUT
type: BidirStd
bank: VCC
connection: manual
desc: Manual clock output for SCA setup
port_type: inout
}
{
name: IO_TRIGGER
type: BidirStd
bank: VCC
connection: manual
desc: Manual trigger output for SCA setup
port_type: inout
}
]
}
pinmux:
{
special_signals:
[
{
name: tap0
pad: IOC8
desc: TAP strap signal.
idx: 30
}
{
name: tap1
pad: IOC5
desc: TAP strap signal.
idx: 27
}
{
name: dft0
pad: IOC3
desc: DFT strap signal.
idx: 25
}
{
name: dft1
pad: IOC4
desc: DFT strap signal.
idx: 26
}
{
name: tck
pad: IOR3
desc: JTAG tck signal.
idx: 38
}
{
name: tms
pad: IOR0
desc: JTAG tms signal.
idx: 35
}
{
name: trst_n
pad: IOR4
desc: JTAG trst_n signal.
idx: 39
}
{
name: tdi
pad: IOR2
desc: JTAG tdi signal.
idx: 37
}
{
name: tdo
pad: IOR1
desc: JTAG tdo signal.
idx: 36
}
]
}
}
]
exported_clks: {}
wakeups:
[
{
name: wkup_req
width: "1"
module: sysrst_ctrl_aon
}
{
name: wkup_req
width: "1"
module: adc_ctrl_aon
}
{
name: pin_wkup_req
width: "1"
module: pinmux_aon
}
{
name: usb_wkup_req
width: "1"
module: pinmux_aon
}
{
name: wkup_req
width: "1"
module: aon_timer_aon
}
{
name: wkup_req
width: "1"
module: sensor_ctrl
}
]
reset_requests:
{
peripheral:
[
{
name: rst_req
width: "1"
module: sysrst_ctrl_aon
desc: OpenTitan reset request to `rstmgr` (running on AON clock).
}
{
name: aon_timer_rst_req
width: "1"
module: aon_timer_aon
desc: watchdog reset requestt
}
]
int:
[
{
name: MainPwr
desc: main power glitch reset request
module: pwrmgr_aon
}
{
name: Esc
desc: escalation reset request
module: alert_handler
}
]
debug:
[
{
name: Ndm
desc: non-debug-module reset request
module: rv_dm
}
]
}
interrupt_module:
[
uart0
uart1
uart2
uart3
gpio
spi_device
i2c0
i2c1
i2c2
pattgen
rv_timer
otp_ctrl
alert_handler
spi_host0
spi_host1
usbdev
pwrmgr_aon
sysrst_ctrl_aon
adc_ctrl_aon
aon_timer_aon
sensor_ctrl
flash_ctrl
hmac
kmac
otbn
keymgr
csrng
entropy_src
edn0
edn1
]
interrupt:
[
{
name: uart0_tx_watermark
width: 1
type: interrupt
module_name: uart0
}
{
name: uart0_rx_watermark
width: 1
type: interrupt
module_name: uart0
}
{
name: uart0_tx_empty
width: 1
type: interrupt
module_name: uart0
}
{
name: uart0_rx_overflow
width: 1
type: interrupt
module_name: uart0
}
{
name: uart0_rx_frame_err
width: 1
type: interrupt
module_name: uart0
}
{
name: uart0_rx_break_err
width: 1
type: interrupt
module_name: uart0
}
{
name: uart0_rx_timeout
width: 1
type: interrupt
module_name: uart0
}
{
name: uart0_rx_parity_err
width: 1
type: interrupt
module_name: uart0
}
{
name: uart1_tx_watermark
width: 1
type: interrupt
module_name: uart1
}
{
name: uart1_rx_watermark
width: 1
type: interrupt
module_name: uart1
}
{
name: uart1_tx_empty
width: 1
type: interrupt
module_name: uart1
}
{
name: uart1_rx_overflow
width: 1
type: interrupt
module_name: uart1
}
{
name: uart1_rx_frame_err
width: 1
type: interrupt
module_name: uart1
}
{
name: uart1_rx_break_err
width: 1
type: interrupt
module_name: uart1
}
{
name: uart1_rx_timeout
width: 1
type: interrupt
module_name: uart1
}
{
name: uart1_rx_parity_err
width: 1
type: interrupt
module_name: uart1
}
{
name: uart2_tx_watermark
width: 1
type: interrupt
module_name: uart2
}
{
name: uart2_rx_watermark
width: 1
type: interrupt
module_name: uart2
}
{
name: uart2_tx_empty
width: 1
type: interrupt
module_name: uart2
}
{
name: uart2_rx_overflow
width: 1
type: interrupt
module_name: uart2
}
{
name: uart2_rx_frame_err
width: 1
type: interrupt
module_name: uart2
}
{
name: uart2_rx_break_err
width: 1
type: interrupt
module_name: uart2
}
{
name: uart2_rx_timeout
width: 1
type: interrupt
module_name: uart2
}
{
name: uart2_rx_parity_err
width: 1
type: interrupt
module_name: uart2
}
{
name: uart3_tx_watermark
width: 1
type: interrupt
module_name: uart3
}
{
name: uart3_rx_watermark
width: 1
type: interrupt
module_name: uart3
}
{
name: uart3_tx_empty
width: 1
type: interrupt
module_name: uart3
}
{
name: uart3_rx_overflow
width: 1
type: interrupt
module_name: uart3
}
{
name: uart3_rx_frame_err
width: 1
type: interrupt
module_name: uart3
}
{
name: uart3_rx_break_err
width: 1
type: interrupt
module_name: uart3
}
{
name: uart3_rx_timeout
width: 1
type: interrupt
module_name: uart3
}
{
name: uart3_rx_parity_err
width: 1
type: interrupt
module_name: uart3
}
{
name: gpio_gpio
width: 32
type: interrupt
module_name: gpio
}
{
name: spi_device_generic_rx_full
width: 1
type: interrupt
module_name: spi_device
}
{
name: spi_device_generic_rx_watermark
width: 1
type: interrupt
module_name: spi_device
}
{
name: spi_device_generic_tx_watermark
width: 1
type: interrupt
module_name: spi_device
}
{
name: spi_device_generic_rx_error
width: 1
type: interrupt
module_name: spi_device
}
{
name: spi_device_generic_rx_overflow
width: 1
type: interrupt
module_name: spi_device
}
{
name: spi_device_generic_tx_underflow
width: 1
type: interrupt
module_name: spi_device
}
{
name: spi_device_upload_cmdfifo_not_empty
width: 1
type: interrupt
module_name: spi_device
}
{
name: spi_device_upload_payload_not_empty
width: 1
type: interrupt
module_name: spi_device
}
{
name: spi_device_upload_payload_overflow
width: 1
type: interrupt
module_name: spi_device
}
{
name: spi_device_readbuf_watermark
width: 1
type: interrupt
module_name: spi_device
}
{
name: spi_device_readbuf_flip
width: 1
type: interrupt
module_name: spi_device
}
{
name: spi_device_tpm_header_not_empty
width: 1
type: interrupt
module_name: spi_device
}
{
name: i2c0_fmt_threshold
width: 1
type: interrupt
module_name: i2c0
}
{
name: i2c0_rx_threshold
width: 1
type: interrupt
module_name: i2c0
}
{
name: i2c0_fmt_overflow
width: 1
type: interrupt
module_name: i2c0
}
{
name: i2c0_rx_overflow
width: 1
type: interrupt
module_name: i2c0
}
{
name: i2c0_nak
width: 1
type: interrupt
module_name: i2c0
}
{
name: i2c0_scl_interference
width: 1
type: interrupt
module_name: i2c0
}
{
name: i2c0_sda_interference
width: 1
type: interrupt
module_name: i2c0
}
{
name: i2c0_stretch_timeout
width: 1
type: interrupt
module_name: i2c0
}
{
name: i2c0_sda_unstable
width: 1
type: interrupt
module_name: i2c0
}
{
name: i2c0_cmd_complete
width: 1
type: interrupt
module_name: i2c0
}
{
name: i2c0_tx_stretch
width: 1
type: interrupt
module_name: i2c0
}
{
name: i2c0_tx_overflow
width: 1
type: interrupt
module_name: i2c0
}
{
name: i2c0_acq_full
width: 1
type: interrupt
module_name: i2c0
}
{
name: i2c0_unexp_stop
width: 1
type: interrupt
module_name: i2c0
}
{
name: i2c0_host_timeout
width: 1
type: interrupt
module_name: i2c0
}
{
name: i2c1_fmt_threshold
width: 1
type: interrupt
module_name: i2c1
}
{
name: i2c1_rx_threshold
width: 1
type: interrupt
module_name: i2c1
}
{
name: i2c1_fmt_overflow
width: 1
type: interrupt
module_name: i2c1
}
{
name: i2c1_rx_overflow
width: 1
type: interrupt
module_name: i2c1
}
{
name: i2c1_nak
width: 1
type: interrupt
module_name: i2c1
}
{
name: i2c1_scl_interference
width: 1
type: interrupt
module_name: i2c1
}
{
name: i2c1_sda_interference
width: 1
type: interrupt
module_name: i2c1
}
{
name: i2c1_stretch_timeout
width: 1
type: interrupt
module_name: i2c1
}
{
name: i2c1_sda_unstable
width: 1
type: interrupt
module_name: i2c1
}
{
name: i2c1_cmd_complete
width: 1
type: interrupt
module_name: i2c1
}
{
name: i2c1_tx_stretch
width: 1
type: interrupt
module_name: i2c1
}
{
name: i2c1_tx_overflow
width: 1
type: interrupt
module_name: i2c1
}
{
name: i2c1_acq_full
width: 1
type: interrupt
module_name: i2c1
}
{
name: i2c1_unexp_stop
width: 1
type: interrupt
module_name: i2c1
}
{
name: i2c1_host_timeout
width: 1
type: interrupt
module_name: i2c1
}
{
name: i2c2_fmt_threshold
width: 1
type: interrupt
module_name: i2c2
}
{
name: i2c2_rx_threshold
width: 1
type: interrupt
module_name: i2c2
}
{
name: i2c2_fmt_overflow
width: 1
type: interrupt
module_name: i2c2
}
{
name: i2c2_rx_overflow
width: 1
type: interrupt
module_name: i2c2
}
{
name: i2c2_nak
width: 1
type: interrupt
module_name: i2c2
}
{
name: i2c2_scl_interference
width: 1
type: interrupt
module_name: i2c2
}
{
name: i2c2_sda_interference
width: 1
type: interrupt
module_name: i2c2
}
{
name: i2c2_stretch_timeout
width: 1
type: interrupt
module_name: i2c2
}
{
name: i2c2_sda_unstable
width: 1
type: interrupt
module_name: i2c2
}
{
name: i2c2_cmd_complete
width: 1
type: interrupt
module_name: i2c2
}
{
name: i2c2_tx_stretch
width: 1
type: interrupt
module_name: i2c2
}
{
name: i2c2_tx_overflow
width: 1
type: interrupt
module_name: i2c2
}
{
name: i2c2_acq_full
width: 1
type: interrupt
module_name: i2c2
}
{
name: i2c2_unexp_stop
width: 1
type: interrupt
module_name: i2c2
}
{
name: i2c2_host_timeout
width: 1
type: interrupt
module_name: i2c2
}
{
name: pattgen_done_ch0
width: 1
type: interrupt
module_name: pattgen
}
{
name: pattgen_done_ch1
width: 1
type: interrupt
module_name: pattgen
}
{
name: rv_timer_timer_expired_hart0_timer0
width: 1
type: interrupt
module_name: rv_timer
}
{
name: otp_ctrl_otp_operation_done
width: 1
type: interrupt
module_name: otp_ctrl
}
{
name: otp_ctrl_otp_error
width: 1
type: interrupt
module_name: otp_ctrl
}
{
name: alert_handler_classa
width: 1
type: interrupt
module_name: alert_handler
}
{
name: alert_handler_classb
width: 1
type: interrupt
module_name: alert_handler
}
{
name: alert_handler_classc
width: 1
type: interrupt
module_name: alert_handler
}
{
name: alert_handler_classd
width: 1
type: interrupt
module_name: alert_handler
}
{
name: spi_host0_error
width: 1
type: interrupt
module_name: spi_host0
}
{
name: spi_host0_spi_event
width: 1
type: interrupt
module_name: spi_host0
}
{
name: spi_host1_error
width: 1
type: interrupt
module_name: spi_host1
}
{
name: spi_host1_spi_event
width: 1
type: interrupt
module_name: spi_host1
}
{
name: usbdev_pkt_received
width: 1
type: interrupt
module_name: usbdev
}
{
name: usbdev_pkt_sent
width: 1
type: interrupt
module_name: usbdev
}
{
name: usbdev_disconnected
width: 1
type: interrupt
module_name: usbdev
}
{
name: usbdev_host_lost
width: 1
type: interrupt
module_name: usbdev
}
{
name: usbdev_link_reset
width: 1
type: interrupt
module_name: usbdev
}
{
name: usbdev_link_suspend
width: 1
type: interrupt
module_name: usbdev
}
{
name: usbdev_link_resume
width: 1
type: interrupt
module_name: usbdev
}
{
name: usbdev_av_empty
width: 1
type: interrupt
module_name: usbdev
}
{
name: usbdev_rx_full
width: 1
type: interrupt
module_name: usbdev
}
{
name: usbdev_av_overflow
width: 1
type: interrupt
module_name: usbdev
}
{
name: usbdev_link_in_err
width: 1
type: interrupt
module_name: usbdev
}
{
name: usbdev_rx_crc_err
width: 1
type: interrupt
module_name: usbdev
}
{
name: usbdev_rx_pid_err
width: 1
type: interrupt
module_name: usbdev
}
{
name: usbdev_rx_bitstuff_err
width: 1
type: interrupt
module_name: usbdev
}
{
name: usbdev_frame
width: 1
type: interrupt
module_name: usbdev
}
{
name: usbdev_powered
width: 1
type: interrupt
module_name: usbdev
}
{
name: usbdev_link_out_err
width: 1
type: interrupt
module_name: usbdev
}
{
name: pwrmgr_aon_wakeup
width: 1
type: interrupt
module_name: pwrmgr_aon
}
{
name: sysrst_ctrl_aon_event_detected
width: 1
type: interrupt
module_name: sysrst_ctrl_aon
}
{
name: adc_ctrl_aon_match_done
width: 1
type: interrupt
module_name: adc_ctrl_aon
}
{
name: aon_timer_aon_wkup_timer_expired
width: 1
type: interrupt
module_name: aon_timer_aon
}
{
name: aon_timer_aon_wdog_timer_bark
width: 1
type: interrupt
module_name: aon_timer_aon
}
{
name: sensor_ctrl_io_status_change
width: 1
type: interrupt
module_name: sensor_ctrl
}
{
name: sensor_ctrl_init_status_change
width: 1
type: interrupt
module_name: sensor_ctrl
}
{
name: flash_ctrl_prog_empty
width: 1
type: interrupt
module_name: flash_ctrl
}
{
name: flash_ctrl_prog_lvl
width: 1
type: interrupt
module_name: flash_ctrl
}
{
name: flash_ctrl_rd_full
width: 1
type: interrupt
module_name: flash_ctrl
}
{
name: flash_ctrl_rd_lvl
width: 1
type: interrupt
module_name: flash_ctrl
}
{
name: flash_ctrl_op_done
width: 1
type: interrupt
module_name: flash_ctrl
}
{
name: flash_ctrl_corr_err
width: 1
type: interrupt
module_name: flash_ctrl
}
{
name: hmac_hmac_done
width: 1
type: interrupt
module_name: hmac
}
{
name: hmac_fifo_empty
width: 1
type: interrupt
module_name: hmac
}
{
name: hmac_hmac_err
width: 1
type: interrupt
module_name: hmac
}
{
name: kmac_kmac_done
width: 1
type: interrupt
module_name: kmac
}
{
name: kmac_fifo_empty
width: 1
type: interrupt
module_name: kmac
}
{
name: kmac_kmac_err
width: 1
type: interrupt
module_name: kmac
}
{
name: otbn_done
width: 1
type: interrupt
module_name: otbn
}
{
name: keymgr_op_done
width: 1
type: interrupt
module_name: keymgr
}
{
name: csrng_cs_cmd_req_done
width: 1
type: interrupt
module_name: csrng
}
{
name: csrng_cs_entropy_req
width: 1
type: interrupt
module_name: csrng
}
{
name: csrng_cs_hw_inst_exc
width: 1
type: interrupt
module_name: csrng
}
{
name: csrng_cs_fatal_err
width: 1
type: interrupt
module_name: csrng
}
{
name: entropy_src_es_entropy_valid
width: 1
type: interrupt
module_name: entropy_src
}
{
name: entropy_src_es_health_test_failed
width: 1
type: interrupt
module_name: entropy_src
}
{
name: entropy_src_es_observe_fifo_ready
width: 1
type: interrupt
module_name: entropy_src
}
{
name: entropy_src_es_fatal_err
width: 1
type: interrupt
module_name: entropy_src
}
{
name: edn0_edn_cmd_req_done
width: 1
type: interrupt
module_name: edn0
}
{
name: edn0_edn_fatal_err
width: 1
type: interrupt
module_name: edn0
}
{
name: edn1_edn_cmd_req_done
width: 1
type: interrupt
module_name: edn1
}
{
name: edn1_edn_fatal_err
width: 1
type: interrupt
module_name: edn1
}
]
alert_module:
[
uart0
uart1
uart2
uart3
gpio
spi_device
i2c0
i2c1
i2c2
pattgen
rv_timer
otp_ctrl
lc_ctrl
spi_host0
spi_host1
usbdev
pwrmgr_aon
rstmgr_aon
clkmgr_aon
sysrst_ctrl_aon
adc_ctrl_aon
pwm_aon
pinmux_aon
aon_timer_aon
sensor_ctrl
sram_ctrl_ret_aon
flash_ctrl
rv_dm
rv_plic
aes
hmac
kmac
otbn
keymgr
csrng
entropy_src
edn0
edn1
sram_ctrl_main
rom_ctrl
rv_core_ibex
]
alert:
[
{
name: uart0_fatal_fault
width: 1
type: alert
async: "1"
module_name: uart0
lpg_name: peri_lc_io_div4_0
lpg_idx: 0
}
{
name: uart1_fatal_fault
width: 1
type: alert
async: "1"
module_name: uart1
lpg_name: peri_lc_io_div4_0
lpg_idx: 0
}
{
name: uart2_fatal_fault
width: 1
type: alert
async: "1"
module_name: uart2
lpg_name: peri_lc_io_div4_0
lpg_idx: 0
}
{
name: uart3_fatal_fault
width: 1
type: alert
async: "1"
module_name: uart3
lpg_name: peri_lc_io_div4_0
lpg_idx: 0
}
{
name: gpio_fatal_fault
width: 1
type: alert
async: "1"
module_name: gpio
lpg_name: peri_lc_io_div4_0
lpg_idx: 0
}
{
name: spi_device_fatal_fault
width: 1
type: alert
async: "1"
module_name: spi_device
lpg_name: peri_spi_device_0
lpg_idx: 1
}
{
name: i2c0_fatal_fault
width: 1
type: alert
async: "1"
module_name: i2c0
lpg_name: peri_i2c0_0
lpg_idx: 2
}
{
name: i2c1_fatal_fault
width: 1
type: alert
async: "1"
module_name: i2c1
lpg_name: peri_i2c1_0
lpg_idx: 3
}
{
name: i2c2_fatal_fault
width: 1
type: alert
async: "1"
module_name: i2c2
lpg_name: peri_i2c2_0
lpg_idx: 4
}
{
name: pattgen_fatal_fault
width: 1
type: alert
async: "1"
module_name: pattgen
lpg_name: peri_lc_io_div4_0
lpg_idx: 0
}
{
name: rv_timer_fatal_fault
width: 1
type: alert
async: "1"
module_name: rv_timer
lpg_name: timers_lc_io_div4_0
lpg_idx: 5
}
{
name: otp_ctrl_fatal_macro_error
width: 1
type: alert
async: "1"
module_name: otp_ctrl
lpg_name: secure_lc_io_div4_0
lpg_idx: 6
}
{
name: otp_ctrl_fatal_check_error
width: 1
type: alert
async: "1"
module_name: otp_ctrl
lpg_name: secure_lc_io_div4_0
lpg_idx: 6
}
{
name: otp_ctrl_fatal_bus_integ_error
width: 1
type: alert
async: "1"
module_name: otp_ctrl
lpg_name: secure_lc_io_div4_0
lpg_idx: 6
}
{
name: otp_ctrl_fatal_prim_otp_alert
width: 1
type: alert
async: "1"
module_name: otp_ctrl
lpg_name: secure_lc_io_div4_0
lpg_idx: 6
}
{
name: otp_ctrl_recov_prim_otp_alert
width: 1
type: alert
async: "1"
module_name: otp_ctrl
lpg_name: secure_lc_io_div4_0
lpg_idx: 6
}
{
name: lc_ctrl_fatal_prog_error
width: 1
type: alert
async: "1"
module_name: lc_ctrl
lpg_name: secure_lc_io_div4_0
lpg_idx: 6
}
{
name: lc_ctrl_fatal_state_error
width: 1
type: alert
async: "1"
module_name: lc_ctrl
lpg_name: secure_lc_io_div4_0
lpg_idx: 6
}
{
name: lc_ctrl_fatal_bus_integ_error
width: 1
type: alert
async: "1"
module_name: lc_ctrl
lpg_name: secure_lc_io_div4_0
lpg_idx: 6
}
{
name: spi_host0_fatal_fault
width: 1
type: alert
async: "1"
module_name: spi_host0
lpg_name: peri_spi_host0_0
lpg_idx: 7
}
{
name: spi_host1_fatal_fault
width: 1
type: alert
async: "1"
module_name: spi_host1
lpg_name: peri_spi_host1_0
lpg_idx: 8
}
{
name: usbdev_fatal_fault
width: 1
type: alert
async: "1"
module_name: usbdev
lpg_name: peri_usb_0
lpg_idx: 9
}
{
name: pwrmgr_aon_fatal_fault
width: 1
type: alert
async: "1"
module_name: pwrmgr_aon
lpg_name: powerup_por_io_div4_Aon
lpg_idx: 10
}
{
name: rstmgr_aon_fatal_fault
width: 1
type: alert
async: "1"
module_name: rstmgr_aon
lpg_name: powerup_lc_io_div4_Aon
lpg_idx: 11
}
{
name: rstmgr_aon_fatal_cnsty_fault
width: 1
type: alert
async: "1"
module_name: rstmgr_aon
lpg_name: powerup_lc_io_div4_Aon
lpg_idx: 11
}
{
name: clkmgr_aon_recov_fault
width: 1
type: alert
async: "1"
module_name: clkmgr_aon
lpg_name: powerup_lc_io_div4_Aon
lpg_idx: 11
}
{
name: clkmgr_aon_fatal_fault
width: 1
type: alert
async: "1"
module_name: clkmgr_aon
lpg_name: powerup_lc_io_div4_Aon
lpg_idx: 11
}
{
name: sysrst_ctrl_aon_fatal_fault
width: 1
type: alert
async: "1"
module_name: sysrst_ctrl_aon
lpg_name: secure_lc_io_div4_Aon
lpg_idx: 12
}
{
name: adc_ctrl_aon_fatal_fault
width: 1
type: alert
async: "1"
module_name: adc_ctrl_aon
lpg_name: peri_lc_io_div4_Aon
lpg_idx: 13
}
{
name: pwm_aon_fatal_fault
width: 1
type: alert
async: "1"
module_name: pwm_aon
lpg_name: peri_lc_io_div4_Aon
lpg_idx: 13
}
{
name: pinmux_aon_fatal_fault
width: 1
type: alert
async: "1"
module_name: pinmux_aon
lpg_name: powerup_lc_io_div4_Aon
lpg_idx: 11
}
{
name: aon_timer_aon_fatal_fault
width: 1
type: alert
async: "1"
module_name: aon_timer_aon
lpg_name: timers_lc_io_div4_Aon
lpg_idx: 14
}
{
name: sensor_ctrl_recov_alert
width: 1
type: alert
async: "1"
module_name: sensor_ctrl
lpg_name: secure_lc_io_div4_Aon
lpg_idx: 12
}
{
name: sensor_ctrl_fatal_alert
width: 1
type: alert
async: "1"
module_name: sensor_ctrl
lpg_name: secure_lc_io_div4_Aon
lpg_idx: 12
}
{
name: sram_ctrl_ret_aon_fatal_error
width: 1
type: alert
async: "1"
module_name: sram_ctrl_ret_aon
lpg_name: infra_lc_io_div4_Aon
lpg_idx: 16
}
{
name: flash_ctrl_recov_err
width: 1
type: alert
async: "1"
module_name: flash_ctrl
lpg_name: infra_lc_0
lpg_idx: 17
}
{
name: flash_ctrl_fatal_std_err
width: 1
type: alert
async: "1"
module_name: flash_ctrl
lpg_name: infra_lc_0
lpg_idx: 17
}
{
name: flash_ctrl_fatal_err
width: 1
type: alert
async: "1"
module_name: flash_ctrl
lpg_name: infra_lc_0
lpg_idx: 17
}
{
name: flash_ctrl_fatal_prim_flash_alert
width: 1
type: alert
async: "1"
module_name: flash_ctrl
lpg_name: infra_lc_0
lpg_idx: 17
}
{
name: flash_ctrl_recov_prim_flash_alert
width: 1
type: alert
async: "1"
module_name: flash_ctrl
lpg_name: infra_lc_0
lpg_idx: 17
}
{
name: rv_dm_fatal_fault
width: 1
type: alert
async: "1"
module_name: rv_dm
lpg_name: infra_sys_0
lpg_idx: 18
}
{
name: rv_plic_fatal_fault
width: 1
type: alert
async: "1"
module_name: rv_plic
lpg_name: secure_lc_0
lpg_idx: 19
}
{
name: aes_recov_ctrl_update_err
width: 1
type: alert
async: "1"
module_name: aes
lpg_name: aes_trans_lc_0
lpg_idx: 20
}
{
name: aes_fatal_fault
width: 1
type: alert
async: "1"
module_name: aes
lpg_name: aes_trans_lc_0
lpg_idx: 20
}
{
name: hmac_fatal_fault
width: 1
type: alert
async: "1"
module_name: hmac
lpg_name: hmac_trans_lc_0
lpg_idx: 21
}
{
name: kmac_recov_operation_err
width: 1
type: alert
async: "1"
module_name: kmac
lpg_name: kmac_trans_lc_0
lpg_idx: 22
}
{
name: kmac_fatal_fault_err
width: 1
type: alert
async: "1"
module_name: kmac
lpg_name: kmac_trans_lc_0
lpg_idx: 22
}
{
name: otbn_fatal
width: 1
type: alert
async: "1"
module_name: otbn
lpg_name: otbn_trans_lc_0
lpg_idx: 23
}
{
name: otbn_recov
width: 1
type: alert
async: "1"
module_name: otbn
lpg_name: otbn_trans_lc_0
lpg_idx: 23
}
{
name: keymgr_recov_operation_err
width: 1
type: alert
async: "1"
module_name: keymgr
lpg_name: secure_lc_0
lpg_idx: 19
}
{
name: keymgr_fatal_fault_err
width: 1
type: alert
async: "1"
module_name: keymgr
lpg_name: secure_lc_0
lpg_idx: 19
}
{
name: csrng_recov_alert
width: 1
type: alert
async: "1"
module_name: csrng
lpg_name: secure_lc_0
lpg_idx: 19
}
{
name: csrng_fatal_alert
width: 1
type: alert
async: "1"
module_name: csrng
lpg_name: secure_lc_0
lpg_idx: 19
}
{
name: entropy_src_recov_alert
width: 1
type: alert
async: "1"
module_name: entropy_src
lpg_name: secure_lc_0
lpg_idx: 19
}
{
name: entropy_src_fatal_alert
width: 1
type: alert
async: "1"
module_name: entropy_src
lpg_name: secure_lc_0
lpg_idx: 19
}
{
name: edn0_recov_alert
width: 1
type: alert
async: "1"
module_name: edn0
lpg_name: secure_lc_0
lpg_idx: 19
}
{
name: edn0_fatal_alert
width: 1
type: alert
async: "1"
module_name: edn0
lpg_name: secure_lc_0
lpg_idx: 19
}
{
name: edn1_recov_alert
width: 1
type: alert
async: "1"
module_name: edn1
lpg_name: secure_lc_0
lpg_idx: 19
}
{
name: edn1_fatal_alert
width: 1
type: alert
async: "1"
module_name: edn1
lpg_name: secure_lc_0
lpg_idx: 19
}
{
name: sram_ctrl_main_fatal_error
width: 1
type: alert
async: "1"
module_name: sram_ctrl_main
lpg_name: infra_lc_0
lpg_idx: 17
}
{
name: rom_ctrl_fatal
width: 1
type: alert
async: "1"
module_name: rom_ctrl
lpg_name: infra_lc_0
lpg_idx: 17
}
{
name: rv_core_ibex_fatal_sw_err
width: 1
type: alert
async: "1"
module_name: rv_core_ibex
lpg_name: infra_lc_0
lpg_idx: 17
}
{
name: rv_core_ibex_recov_sw_err
width: 1
type: alert
async: "1"
module_name: rv_core_ibex
lpg_name: infra_lc_0
lpg_idx: 17
}
{
name: rv_core_ibex_fatal_hw_err
width: 1
type: alert
async: "1"
module_name: rv_core_ibex
lpg_name: infra_lc_0
lpg_idx: 17
}
{
name: rv_core_ibex_recov_hw_err
width: 1
type: alert
async: "1"
module_name: rv_core_ibex
lpg_name: infra_lc_0
lpg_idx: 17
}
]
exported_rsts: {}
alert_lpgs:
[
{
name: peri_lc_io_div4_0
clock_group:
{
name: peri
src: top
sw_cg: yes
unique: no
clocks:
{
clk_io_div4_peri: io_div4
clk_io_div2_peri: io_div2
clk_io_peri: io
clk_usb_peri: usb
clk_aon_peri: aon
}
}
clock_connection: clkmgr_aon_clocks.clk_io_div4_peri
reset_connection:
{
name: lc_io_div4
domain: "0"
}
}
{
name: peri_spi_device_0
clock_group:
{
name: peri
src: top
sw_cg: yes
unique: no
clocks:
{
clk_io_div4_peri: io_div4
clk_io_div2_peri: io_div2
clk_io_peri: io
clk_usb_peri: usb
clk_aon_peri: aon
}
}
clock_connection: clkmgr_aon_clocks.clk_io_div4_peri
reset_connection:
{
name: spi_device
domain: "0"
}
}
{
name: peri_i2c0_0
clock_group:
{
name: peri
src: top
sw_cg: yes
unique: no
clocks:
{
clk_io_div4_peri: io_div4
clk_io_div2_peri: io_div2
clk_io_peri: io
clk_usb_peri: usb
clk_aon_peri: aon
}
}
clock_connection: clkmgr_aon_clocks.clk_io_div4_peri
reset_connection:
{
name: i2c0
domain: "0"
}
}
{
name: peri_i2c1_0
clock_group:
{
name: peri
src: top
sw_cg: yes
unique: no
clocks:
{
clk_io_div4_peri: io_div4
clk_io_div2_peri: io_div2
clk_io_peri: io
clk_usb_peri: usb
clk_aon_peri: aon
}
}
clock_connection: clkmgr_aon_clocks.clk_io_div4_peri
reset_connection:
{
name: i2c1
domain: "0"
}
}
{
name: peri_i2c2_0
clock_group:
{
name: peri
src: top
sw_cg: yes
unique: no
clocks:
{
clk_io_div4_peri: io_div4
clk_io_div2_peri: io_div2
clk_io_peri: io
clk_usb_peri: usb
clk_aon_peri: aon
}
}
clock_connection: clkmgr_aon_clocks.clk_io_div4_peri
reset_connection:
{
name: i2c2
domain: "0"
}
}
{
name: timers_lc_io_div4_0
clock_group:
{
name: timers
src: top
sw_cg: no
unique: no
clocks:
{
clk_io_div4_timers: io_div4
clk_aon_timers: aon
}
}
clock_connection: clkmgr_aon_clocks.clk_io_div4_timers
reset_connection:
{
name: lc_io_div4
domain: "0"
}
}
{
name: secure_lc_io_div4_0
clock_group:
{
name: secure
src: top
sw_cg: no
unique: no
clocks:
{
clk_io_div4_secure: io_div4
clk_main_secure: main
clk_aon_secure: aon
}
}
clock_connection: clkmgr_aon_clocks.clk_io_div4_secure
reset_connection:
{
name: lc_io_div4
domain: "0"
}
}
{
name: peri_spi_host0_0
clock_group:
{
name: peri
src: top
sw_cg: yes
unique: no
clocks:
{
clk_io_div4_peri: io_div4
clk_io_div2_peri: io_div2
clk_io_peri: io
clk_usb_peri: usb
clk_aon_peri: aon
}
}
clock_connection: clkmgr_aon_clocks.clk_io_peri
reset_connection:
{
name: spi_host0
domain: "0"
}
}
{
name: peri_spi_host1_0
clock_group:
{
name: peri
src: top
sw_cg: yes
unique: no
clocks:
{
clk_io_div4_peri: io_div4
clk_io_div2_peri: io_div2
clk_io_peri: io
clk_usb_peri: usb
clk_aon_peri: aon
}
}
clock_connection: clkmgr_aon_clocks.clk_io_div2_peri
reset_connection:
{
name: spi_host1
domain: "0"
}
}
{
name: peri_usb_0
clock_group:
{
name: peri
src: top
sw_cg: yes
unique: no
clocks:
{
clk_io_div4_peri: io_div4
clk_io_div2_peri: io_div2
clk_io_peri: io
clk_usb_peri: usb
clk_aon_peri: aon
}
}
clock_connection: clkmgr_aon_clocks.clk_usb_peri
reset_connection:
{
name: usb
domain: "0"
}
}
{
name: powerup_por_io_div4_Aon
clock_group:
{
name: powerup
src: top
sw_cg: no
unique: no
clocks:
{
clk_io_div4_powerup: io_div4
clk_aon_powerup: aon
clk_main_powerup: main
clk_io_powerup: io
clk_usb_powerup: usb
clk_io_div2_powerup: io_div2
}
}
clock_connection: clkmgr_aon_clocks.clk_io_div4_powerup
reset_connection:
{
name: por_io_div4
domain: Aon
}
}
{
name: powerup_lc_io_div4_Aon
clock_group:
{
name: powerup
src: top
sw_cg: no
unique: no
clocks:
{
clk_io_div4_powerup: io_div4
clk_aon_powerup: aon
clk_main_powerup: main
clk_io_powerup: io
clk_usb_powerup: usb
clk_io_div2_powerup: io_div2
}
}
clock_connection: clkmgr_aon_clocks.clk_io_div4_powerup
reset_connection:
{
name: lc_io_div4
domain: Aon
}
}
{
name: secure_lc_io_div4_Aon
clock_group:
{
name: secure
src: top
sw_cg: no
unique: no
clocks:
{
clk_io_div4_secure: io_div4
clk_main_secure: main
clk_aon_secure: aon
}
}
clock_connection: clkmgr_aon_clocks.clk_io_div4_secure
reset_connection:
{
name: lc_io_div4
domain: Aon
}
}
{
name: peri_lc_io_div4_Aon
clock_group:
{
name: peri
src: top
sw_cg: yes
unique: no
clocks:
{
clk_io_div4_peri: io_div4
clk_io_div2_peri: io_div2
clk_io_peri: io
clk_usb_peri: usb
clk_aon_peri: aon
}
}
clock_connection: clkmgr_aon_clocks.clk_io_div4_peri
reset_connection:
{
name: lc_io_div4
domain: Aon
}
}
{
name: timers_lc_io_div4_Aon
clock_group:
{
name: timers
src: top
sw_cg: no
unique: no
clocks:
{
clk_io_div4_timers: io_div4
clk_aon_timers: aon
}
}
clock_connection: clkmgr_aon_clocks.clk_io_div4_timers
reset_connection:
{
name: lc_io_div4
domain: Aon
}
}
{
name: infra_lc_io_div4_0
clock_group:
{
name: infra
src: top
sw_cg: no
unique: no
clocks:
{
clk_io_div4_infra: io_div4
clk_main_infra: main
clk_usb_infra: usb
clk_io_infra: io
clk_io_div2_infra: io_div2
}
}
clock_connection: clkmgr_aon_clocks.clk_io_div4_infra
reset_connection:
{
name: lc_io_div4
domain: "0"
}
}
{
name: infra_lc_io_div4_Aon
clock_group:
{
name: infra
src: top
sw_cg: no
unique: no
clocks:
{
clk_io_div4_infra: io_div4
clk_main_infra: main
clk_usb_infra: usb
clk_io_infra: io
clk_io_div2_infra: io_div2
}
}
clock_connection: clkmgr_aon_clocks.clk_io_div4_infra
reset_connection:
{
name: lc_io_div4
domain: Aon
}
}
{
name: infra_lc_0
clock_group:
{
name: infra
src: top
sw_cg: no
unique: no
clocks:
{
clk_io_div4_infra: io_div4
clk_main_infra: main
clk_usb_infra: usb
clk_io_infra: io
clk_io_div2_infra: io_div2
}
}
clock_connection: clkmgr_aon_clocks.clk_main_infra
reset_connection:
{
name: lc
domain: "0"
}
}
{
name: infra_sys_0
clock_group:
{
name: infra
src: top
sw_cg: no
unique: no
clocks:
{
clk_io_div4_infra: io_div4
clk_main_infra: main
clk_usb_infra: usb
clk_io_infra: io
clk_io_div2_infra: io_div2
}
}
clock_connection: clkmgr_aon_clocks.clk_main_infra
reset_connection:
{
name: sys
domain: "0"
}
}
{
name: secure_lc_0
clock_group:
{
name: secure
src: top
sw_cg: no
unique: no
clocks:
{
clk_io_div4_secure: io_div4
clk_main_secure: main
clk_aon_secure: aon
}
}
clock_connection: clkmgr_aon_clocks.clk_main_secure
reset_connection:
{
name: lc
domain: "0"
}
}
{
name: aes_trans_lc_0
clock_group:
{
name: trans
src: top
sw_cg: hint
unique: yes
clocks:
{
clk_main_aes: main
clk_main_hmac: main
clk_main_kmac: main
clk_main_otbn: main
}
}
clock_connection: clkmgr_aon_clocks.clk_main_aes
reset_connection:
{
name: lc
domain: "0"
}
}
{
name: hmac_trans_lc_0
clock_group:
{
name: trans
src: top
sw_cg: hint
unique: yes
clocks:
{
clk_main_aes: main
clk_main_hmac: main
clk_main_kmac: main
clk_main_otbn: main
}
}
clock_connection: clkmgr_aon_clocks.clk_main_hmac
reset_connection:
{
name: lc
domain: "0"
}
}
{
name: kmac_trans_lc_0
clock_group:
{
name: trans
src: top
sw_cg: hint
unique: yes
clocks:
{
clk_main_aes: main
clk_main_hmac: main
clk_main_kmac: main
clk_main_otbn: main
}
}
clock_connection: clkmgr_aon_clocks.clk_main_kmac
reset_connection:
{
name: lc
domain: "0"
}
}
{
name: otbn_trans_lc_0
clock_group:
{
name: trans
src: top
sw_cg: hint
unique: yes
clocks:
{
clk_main_aes: main
clk_main_hmac: main
clk_main_kmac: main
clk_main_otbn: main
}
}
clock_connection: clkmgr_aon_clocks.clk_main_otbn
reset_connection:
{
name: lc
domain: "0"
}
}
]
inter_signal:
{
signals:
[
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: uart0
default: ""
end_idx: -1
top_signame: uart0_tl
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: uart1
default: ""
end_idx: -1
top_signame: uart1_tl
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: uart2
default: ""
end_idx: -1
top_signame: uart2_tl
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: uart3
default: ""
end_idx: -1
top_signame: uart3_tl
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: gpio
default: ""
end_idx: -1
top_signame: gpio_tl
index: -1
}
{
name: ram_cfg
struct: ram_2p_cfg
package: prim_ram_2p_pkg
type: uni
act: rcv
width: 1
inst_name: spi_device
default: ""
top_signame: ast_ram_2p_cfg
index: -1
}
{
name: passthrough
struct: passthrough
package: spi_device_pkg
type: req_rsp
act: req
width: 1
inst_name: spi_device
default: ""
end_idx: -1
top_signame: spi_device_passthrough
index: -1
}
{
name: mbist_en
struct: logic
type: uni
act: rcv
width: 1
inst_name: spi_device
index: -1
}
{
name: sck_monitor
struct: logic
type: uni
act: req
width: 1
inst_name: spi_device
default: ""
package: ""
external: true
top_signame: sck_monitor
conn_type: false
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: spi_device
default: ""
end_idx: -1
top_signame: spi_device_tl
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: i2c0
default: ""
end_idx: -1
top_signame: i2c0_tl
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: i2c1
default: ""
end_idx: -1
top_signame: i2c1_tl
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: i2c2
default: ""
end_idx: -1
top_signame: i2c2_tl
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: pattgen
default: ""
end_idx: -1
top_signame: pattgen_tl
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: rv_timer
default: ""
end_idx: -1
top_signame: rv_timer_tl
index: -1
}
{
name: otp_ext_voltage_h
struct: ""
type: io
act: none
width: 1
default: "'0"
inst_name: otp_ctrl
package: ""
external: true
top_signame: otp_ext_voltage_h
conn_type: false
index: -1
}
{
name: otp_ast_pwr_seq
desc: Power sequencing signals to AST (VDD domain).
struct: otp_ast_req
package: otp_ctrl_pkg
type: uni
act: req
width: 1
default: "'0"
inst_name: otp_ctrl
external: true
top_signame: otp_ctrl_otp_ast_pwr_seq
conn_type: false
index: -1
}
{
name: otp_ast_pwr_seq_h
desc: Power sequencing signals coming from AST (VCC domain).
struct: otp_ast_rsp
package: otp_ctrl_pkg
type: uni
act: rcv
width: 1
default: "'0"
inst_name: otp_ctrl
external: true
top_signame: otp_ctrl_otp_ast_pwr_seq_h
conn_type: false
index: -1
}
{
name: edn
desc: Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation.
struct: edn
package: edn_pkg
type: req_rsp
act: req
width: 1
inst_name: otp_ctrl
default: ""
top_signame: edn0_edn
index: 1
}
{
name: pwr_otp
desc: Initialization request/acknowledge from/to power manager.
struct: pwr_otp
package: pwrmgr_pkg
type: req_rsp
act: rsp
width: 1
default: "'0"
inst_name: otp_ctrl
top_signame: pwrmgr_aon_pwr_otp
index: -1
}
{
name: lc_otp_vendor_test
desc: Vendor test control signals from/to the life cycle TAP.
struct: lc_otp_vendor_test
package: otp_ctrl_pkg
type: req_rsp
act: rsp
width: 1
default: "'0"
inst_name: otp_ctrl
top_signame: lc_ctrl_lc_otp_vendor_test
index: -1
}
{
name: lc_otp_program
desc: Life cycle state transition interface.
struct: lc_otp_program
package: otp_ctrl_pkg
type: req_rsp
act: rsp
width: 1
default: "'0"
inst_name: otp_ctrl
top_signame: lc_ctrl_lc_otp_program
index: -1
}
{
name: otp_lc_data
desc:
'''
Life cycle state output holding the current life cycle state,
the value of the transition counter and the tokens needed for life cycle transitions.
'''
struct: otp_lc_data
package: otp_ctrl_pkg
type: uni
act: req
width: 1
default: "'0"
inst_name: otp_ctrl
end_idx: -1
top_type: broadcast
top_signame: otp_ctrl_otp_lc_data
index: -1
}
{
name: lc_escalate_en
desc:
'''
Life cycle escalation enable coming from life cycle controller.
This signal moves all FSMs within OTP into the error state.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: otp_ctrl
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: lc_creator_seed_sw_rw_en
desc:
'''
Provision enable qualifier coming from life cycle controller.
This signal enables SW read / write access to the RMA_TOKEN and CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: otp_ctrl
top_signame: lc_ctrl_lc_creator_seed_sw_rw_en
index: -1
}
{
name: lc_seed_hw_rd_en
desc:
'''
Seed read enable coming from life cycle controller.
This signal enables HW read access to the CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: otp_ctrl
top_signame: lc_ctrl_lc_seed_hw_rd_en
index: -1
}
{
name: lc_dft_en
desc:
'''
Test enable qualifier coming from from life cycle controller.
This signals enables the TL-UL access port to the proprietary OTP IP.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: otp_ctrl
top_signame: lc_ctrl_lc_dft_en
index: -1
}
{
name: lc_check_byp_en
desc:
'''
Life cycle partition check bypass signal.
This signal causes the life cycle partition to bypass consistency checks during life cycle state transitions in order to prevent spurious consistency check failures.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: otp_ctrl
top_signame: lc_ctrl_lc_check_byp_en
index: -1
}
{
name: otp_keymgr_key
desc: Key output to the key manager holding CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1.
struct: otp_keymgr_key
package: otp_ctrl_pkg
type: uni
act: req
width: 1
default: "'0"
inst_name: otp_ctrl
end_idx: -1
top_type: broadcast
top_signame: otp_ctrl_otp_keymgr_key
index: -1
}
{
name: flash_otp_key
desc: Key derivation interface for FLASH scrambling.
struct: flash_otp_key
package: otp_ctrl_pkg
type: req_rsp
act: rsp
width: 1
default: "'0"
inst_name: otp_ctrl
top_signame: flash_ctrl_otp
index: -1
}
{
name: sram_otp_key
desc: Array with key derivation interfaces for SRAM scrambling devices.
struct: sram_otp_key
package: otp_ctrl_pkg
type: req_rsp
act: rsp
width: 3
default: "'0"
inst_name: otp_ctrl
end_idx: -1
top_type: one-to-N
top_signame: otp_ctrl_sram_otp_key
index: -1
}
{
name: otbn_otp_key
desc: Key derivation interface for OTBN scrambling devices.
struct: otbn_otp_key
package: otp_ctrl_pkg
type: req_rsp
act: rsp
width: 1
default: "'0"
inst_name: otp_ctrl
end_idx: -1
top_signame: otp_ctrl_otbn_otp_key
index: -1
}
{
name: otp_hw_cfg
desc: Output of the HW_CFG partition.
struct: otp_hw_cfg
package: otp_ctrl_part_pkg
type: uni
act: req
width: 1
default: "'0"
inst_name: otp_ctrl
top_signame: otp_ctrl_otp_hw_cfg
index: -1
}
{
name: obs_ctrl
desc: AST observability control signals.
struct: ast_obs_ctrl
package: ast_pkg
type: uni
act: rcv
width: 1
inst_name: otp_ctrl
default: ""
top_signame: ast_obs_ctrl
index: -1
}
{
name: otp_obs
desc: AST observability bus.
struct: logic
type: uni
act: req
width: 8
inst_name: otp_ctrl
default: ""
package: ""
external: true
top_signame: otp_obs
conn_type: false
index: -1
}
{
name: core_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: otp_ctrl
default: ""
end_idx: -1
top_signame: otp_ctrl_core_tl
index: -1
}
{
name: prim_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: otp_ctrl
default: ""
end_idx: -1
top_signame: otp_ctrl_prim_tl
index: -1
}
{
name: jtag
struct: jtag
package: jtag_pkg
type: req_rsp
act: rsp
width: 1
inst_name: lc_ctrl
default: ""
top_signame: pinmux_aon_lc_jtag
index: -1
}
{
name: esc_scrap_state0_tx
struct: esc_tx
package: prim_esc_pkg
type: uni
act: rcv
width: 1
inst_name: lc_ctrl
default: ""
top_signame: alert_handler_esc_tx
index: 1
}
{
name: esc_scrap_state0_rx
struct: esc_rx
package: prim_esc_pkg
type: uni
act: req
width: 1
inst_name: lc_ctrl
default: ""
top_signame: alert_handler_esc_rx
index: 1
}
{
name: esc_scrap_state1_tx
struct: esc_tx
package: prim_esc_pkg
type: uni
act: rcv
width: 1
inst_name: lc_ctrl
default: ""
top_signame: alert_handler_esc_tx
index: 2
}
{
name: esc_scrap_state1_rx
struct: esc_rx
package: prim_esc_pkg
type: uni
act: req
width: 1
inst_name: lc_ctrl
default: ""
top_signame: alert_handler_esc_rx
index: 2
}
{
name: pwr_lc
struct: pwr_lc
package: pwrmgr_pkg
type: req_rsp
act: rsp
width: 1
inst_name: lc_ctrl
default: ""
top_signame: pwrmgr_aon_pwr_lc
index: -1
}
{
name: lc_otp_vendor_test
struct: lc_otp_vendor_test
package: otp_ctrl_pkg
type: req_rsp
act: req
width: 1
default: "'0"
inst_name: lc_ctrl
end_idx: -1
top_signame: lc_ctrl_lc_otp_vendor_test
index: -1
}
{
name: otp_lc_data
struct: otp_lc_data
package: otp_ctrl_pkg
type: uni
act: rcv
width: 1
default: otp_ctrl_pkg::OTP_LC_DATA_DEFAULT
inst_name: lc_ctrl
top_signame: otp_ctrl_otp_lc_data
index: -1
}
{
name: lc_otp_program
struct: lc_otp_program
package: otp_ctrl_pkg
type: req_rsp
act: req
width: 1
default: "'0"
inst_name: lc_ctrl
end_idx: -1
top_signame: lc_ctrl_lc_otp_program
index: -1
}
{
name: kmac_data
struct: app
package: kmac_pkg
type: req_rsp
act: req
width: 1
default: "'0"
inst_name: lc_ctrl
top_signame: kmac_app
index: 1
}
{
name: lc_dft_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_dft_en
index: -1
}
{
name: lc_nvm_debug_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_nvm_debug_en
index: -1
}
{
name: lc_hw_debug_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
name: lc_cpu_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_cpu_en
index: -1
}
{
name: lc_keymgr_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_keymgr_en
index: -1
}
{
name: lc_escalate_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: lc_clk_byp_req
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_clk_byp_req
index: -1
}
{
name: lc_clk_byp_ack
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_clk_byp_ack
index: -1
}
{
name: lc_flash_rma_req
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_flash_rma_req
index: -1
}
{
name: lc_flash_rma_seed
struct: lc_flash_rma_seed
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: "'0"
inst_name: lc_ctrl
top_signame: flash_ctrl_rma_seed
index: -1
}
{
name: lc_flash_rma_ack
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
top_signame: otbn_lc_rma_ack
index: -1
}
{
name: lc_check_byp_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_check_byp_en
index: -1
}
{
name: lc_creator_seed_sw_rw_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_creator_seed_sw_rw_en
index: -1
}
{
name: lc_owner_seed_sw_rw_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_owner_seed_sw_rw_en
index: -1
}
{
name: lc_iso_part_sw_rd_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_iso_part_sw_rd_en
index: -1
}
{
name: lc_iso_part_sw_wr_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_iso_part_sw_wr_en
index: -1
}
{
name: lc_seed_hw_rd_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_seed_hw_rd_en
index: -1
}
{
name: lc_keymgr_div
struct: lc_keymgr_div
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: "'0"
inst_name: lc_ctrl
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_keymgr_div
index: -1
}
{
name: otp_device_id
struct: otp_device_id
package: otp_ctrl_pkg
type: uni
act: rcv
width: 1
default: "'0"
inst_name: lc_ctrl
top_signame: lc_ctrl_otp_device_id
index: -1
}
{
name: otp_manuf_state
struct: otp_manuf_state
package: otp_ctrl_pkg
type: uni
act: rcv
width: 1
default: "'0"
inst_name: lc_ctrl
top_signame: lc_ctrl_otp_manuf_state
index: -1
}
{
name: hw_rev
struct: lc_hw_rev
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: "'0"
inst_name: lc_ctrl
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: lc_ctrl
default: ""
end_idx: -1
top_signame: lc_ctrl_tl
index: -1
}
{
name: crashdump
struct: alert_crashdump
package: alert_pkg
type: uni
act: req
width: 1
inst_name: alert_handler
default: ""
end_idx: -1
top_type: broadcast
top_signame: alert_handler_crashdump
index: -1
}
{
name: edn
struct: edn
package: edn_pkg
type: req_rsp
act: req
width: 1
inst_name: alert_handler
default: ""
top_signame: edn0_edn
index: 4
}
{
name: esc_rx
struct: esc_rx
package: prim_esc_pkg
type: uni
act: rcv
width: 4
inst_name: alert_handler
default: ""
end_idx: -1
top_type: one-to-N
top_signame: alert_handler_esc_rx
index: -1
}
{
name: esc_tx
struct: esc_tx
package: prim_esc_pkg
type: uni
act: req
width: 4
inst_name: alert_handler
default: ""
end_idx: -1
top_type: one-to-N
top_signame: alert_handler_esc_tx
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: alert_handler
default: ""
end_idx: -1
top_signame: alert_handler_tl
index: -1
}
{
name: passthrough
struct: passthrough
package: spi_device_pkg
type: req_rsp
act: rsp
width: 1
inst_name: spi_host0
default: ""
top_signame: spi_device_passthrough
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: spi_host0
default: ""
end_idx: -1
top_signame: spi_host0_tl
index: -1
}
{
name: passthrough
struct: passthrough
package: spi_device_pkg
type: req_rsp
act: rsp
width: 1
inst_name: spi_host1
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: spi_host1
default: ""
end_idx: -1
top_signame: spi_host1_tl
index: -1
}
{
name: usb_rx_d
desc: USB RX data from an external differential receiver, if available
struct: logic
type: uni
act: rcv
width: 1
inst_name: usbdev
default: ""
package: ""
external: true
top_signame: usbdev_usb_rx_d
conn_type: false
index: -1
}
{
name: usb_tx_d
desc: USB transmit data value (not used if usb_tx_se0 is set)
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
external: true
top_signame: usbdev_usb_tx_d
conn_type: false
index: -1
}
{
name: usb_tx_se0
desc: Force transmission of a USB single-ended zero (i.e. both D+ and D- are low) regardless of usb_tx_d
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
external: true
top_signame: usbdev_usb_tx_se0
conn_type: false
index: -1
}
{
name: usb_tx_use_d_se0
desc: Use the usb_tx_d and usb_tx_se0 TX interface, instead of usb_dp_o and usb_dn_o
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
external: true
top_signame: usbdev_usb_tx_use_d_se0
conn_type: false
index: -1
}
{
name: usb_dp_pullup
desc: USB D+ pullup control
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_dp_pullup
index: -1
}
{
name: usb_dn_pullup
desc: USB D- pullup control
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_dn_pullup
index: -1
}
{
name: usb_rx_enable
desc: USB differential receiver enable
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
external: true
top_signame: usbdev_usb_rx_enable
conn_type: false
index: -1
}
{
name: usb_ref_val
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
external: true
top_signame: usbdev_usb_ref_val
conn_type: false
index: -1
}
{
name: usb_ref_pulse
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
external: true
top_signame: usbdev_usb_ref_pulse
conn_type: false
index: -1
}
{
name: usb_aon_suspend_req
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_aon_suspend_req
index: -1
}
{
name: usb_aon_wake_ack
struct: logic
type: uni
act: req
width: 1
inst_name: usbdev
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_aon_wake_ack
index: -1
}
{
name: usb_aon_bus_reset
struct: logic
type: uni
act: rcv
width: 1
inst_name: usbdev
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_aon_bus_reset
index: -1
}
{
name: usb_aon_sense_lost
struct: logic
type: uni
act: rcv
width: 1
inst_name: usbdev
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_aon_sense_lost
index: -1
}
{
name: usb_aon_wake_detect_active
struct: logic
type: uni
act: rcv
width: 1
inst_name: usbdev
default: ""
package: ""
top_signame: pinmux_aon_usbdev_wake_detect_active
index: -1
}
{
name: ram_cfg
struct: ram_2p_cfg
package: prim_ram_2p_pkg
type: uni
act: rcv
width: 1
inst_name: usbdev
default: ""
top_signame: ast_ram_2p_cfg
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: usbdev
default: ""
end_idx: -1
top_signame: usbdev_tl
index: -1
}
{
name: pwr_ast
struct: pwr_ast
package: pwrmgr_pkg
type: req_rsp
act: req
width: 1
inst_name: pwrmgr_aon
default: ""
external: true
top_signame: pwrmgr_ast
conn_type: false
index: -1
}
{
name: pwr_rst
struct: pwr_rst
package: pwrmgr_pkg
type: req_rsp
act: req
width: 1
inst_name: pwrmgr_aon
default: ""
end_idx: -1
top_signame: pwrmgr_aon_pwr_rst
index: -1
}
{
name: pwr_clk
struct: pwr_clk
package: pwrmgr_pkg
type: req_rsp
act: req
width: 1
inst_name: pwrmgr_aon
default: ""
end_idx: -1
top_signame: pwrmgr_aon_pwr_clk
index: -1
}
{
name: pwr_otp
struct: pwr_otp
package: pwrmgr_pkg
type: req_rsp
act: req
width: 1
inst_name: pwrmgr_aon
default: ""
end_idx: -1
top_signame: pwrmgr_aon_pwr_otp
index: -1
}
{
name: pwr_lc
struct: pwr_lc
package: pwrmgr_pkg
type: req_rsp
act: req
width: 1
inst_name: pwrmgr_aon
default: ""
end_idx: -1
top_signame: pwrmgr_aon_pwr_lc
index: -1
}
{
name: pwr_flash
struct: pwr_flash
package: pwrmgr_pkg
type: uni
act: rcv
width: 1
inst_name: pwrmgr_aon
default: ""
end_idx: -1
top_type: broadcast
top_signame: pwrmgr_aon_pwr_flash
index: -1
}
{
name: esc_rst_tx
struct: esc_tx
package: prim_esc_pkg
type: uni
act: rcv
width: 1
inst_name: pwrmgr_aon
default: ""
top_signame: alert_handler_esc_tx
index: 3
}
{
name: esc_rst_rx
struct: esc_rx
package: prim_esc_pkg
type: uni
act: req
width: 1
inst_name: pwrmgr_aon
default: ""
top_signame: alert_handler_esc_rx
index: 3
}
{
name: pwr_cpu
struct: pwr_cpu
package: pwrmgr_pkg
type: uni
act: rcv
width: 1
inst_name: pwrmgr_aon
default: ""
top_signame: rv_core_ibex_pwrmgr
index: -1
}
{
name: wakeups
struct: logic
type: uni
act: rcv
width: 6
inst_name: pwrmgr_aon
default: ""
package: ""
end_idx: -1
top_type: one-to-N
top_signame: pwrmgr_aon_wakeups
index: -1
}
{
name: rstreqs
struct: logic
type: uni
act: rcv
width: 2
inst_name: pwrmgr_aon
default: ""
package: ""
end_idx: -1
top_type: one-to-N
top_signame: pwrmgr_aon_rstreqs
index: -1
}
{
name: ndmreset_req
struct: logic
type: uni
act: rcv
width: 1
inst_name: pwrmgr_aon
default: ""
package: ""
top_signame: rv_dm_ndmreset_req
index: -1
}
{
name: strap
struct: logic
type: uni
act: req
width: 1
inst_name: pwrmgr_aon
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: pwrmgr_aon_strap
index: -1
}
{
name: low_power
struct: logic
type: uni
act: req
width: 1
inst_name: pwrmgr_aon
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: pwrmgr_aon_low_power
index: -1
}
{
name: rom_ctrl
struct: pwrmgr_data
package: rom_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: pwrmgr_aon
default: ""
top_signame: rom_ctrl_pwrmgr_data
index: -1
}
{
name: fetch_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
inst_name: pwrmgr_aon
default: ""
end_idx: -1
top_type: broadcast
top_signame: pwrmgr_aon_fetch_en
index: -1
}
{
name: lc_dft_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: pwrmgr_aon
default: ""
top_signame: lc_ctrl_lc_dft_en
index: -1
}
{
name: lc_hw_debug_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: pwrmgr_aon
default: ""
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
name: sw_rst_req
struct: mubi4
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
inst_name: pwrmgr_aon
default: ""
top_signame: rstmgr_aon_sw_rst_req
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: pwrmgr_aon
default: ""
end_idx: -1
top_signame: pwrmgr_aon_tl
index: -1
}
{
name: por_n
desc:
'''
Root power on reset signals from ast.
There is one root reset signal for each core power domain.
'''
struct: logic
type: uni
act: rcv
width: 2
inst_name: rstmgr_aon
default: ""
package: ""
external: true
top_signame: por_n
conn_type: false
index: -1
}
{
name: pwr
desc:
'''
Reset request signals from power manager.
Power manager can request for specific domains of the lc/sys reset tree to assert.
'''
struct: pwr_rst
type: req_rsp
act: rsp
width: 1
inst_name: rstmgr_aon
default: ""
package: pwrmgr_pkg
top_signame: pwrmgr_aon_pwr_rst
index: -1
}
{
name: resets
desc: Leaf resets fed to the system.
struct: rstmgr_out
package: rstmgr_pkg
type: uni
act: req
width: 1
inst_name: rstmgr_aon
default: ""
top_signame: rstmgr_aon_resets
index: -1
}
{
name: rst_en
desc: Low-power-group outputs used by alert handler.
struct: rstmgr_rst_en
package: rstmgr_pkg
type: uni
act: req
width: 1
inst_name: rstmgr_aon
default: ""
top_signame: rstmgr_aon_rst_en
index: -1
}
{
name: alert_dump
desc: Alert handler crash dump information.
struct: alert_crashdump
package: alert_pkg
type: uni
act: rcv
width: 1
inst_name: rstmgr_aon
default: ""
top_signame: alert_handler_crashdump
index: -1
}
{
name: cpu_dump
desc: Main processing element crash dump information.
struct: cpu_crash_dump
package: rv_core_ibex_pkg
type: uni
act: rcv
width: 1
inst_name: rstmgr_aon
default: ""
top_signame: rv_core_ibex_crash_dump
index: -1
}
{
name: sw_rst_req
desc: Software requested system reset to pwrmgr.
struct: mubi4
package: prim_mubi_pkg
type: uni
act: req
width: 1
inst_name: rstmgr_aon
default: ""
end_idx: -1
top_type: broadcast
top_signame: rstmgr_aon_sw_rst_req
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: rstmgr_aon
default: ""
end_idx: -1
top_signame: rstmgr_aon_tl
index: -1
}
{
name: clocks
struct: clkmgr_out
package: clkmgr_pkg
type: uni
act: req
width: 1
inst_name: clkmgr_aon
default: ""
top_signame: clkmgr_aon_clocks
index: -1
}
{
name: cg_en
struct: clkmgr_cg_en
package: clkmgr_pkg
type: uni
act: req
width: 1
inst_name: clkmgr_aon
default: ""
top_signame: clkmgr_aon_cg_en
index: -1
}
{
name: lc_hw_debug_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: clkmgr_aon
default: ""
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
name: io_clk_byp_req
struct: mubi4
package: prim_mubi_pkg
type: uni
act: req
width: 1
inst_name: clkmgr_aon
default: ""
external: true
top_signame: io_clk_byp_req
conn_type: false
index: -1
}
{
name: io_clk_byp_ack
struct: mubi4
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
inst_name: clkmgr_aon
default: ""
external: true
top_signame: io_clk_byp_ack
conn_type: false
index: -1
}
{
name: all_clk_byp_req
struct: mubi4
package: prim_mubi_pkg
type: uni
act: req
width: 1
inst_name: clkmgr_aon
default: ""
external: true
top_signame: all_clk_byp_req
conn_type: false
index: -1
}
{
name: all_clk_byp_ack
struct: mubi4
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
inst_name: clkmgr_aon
default: ""
external: true
top_signame: all_clk_byp_ack
conn_type: false
index: -1
}
{
name: hi_speed_sel
struct: mubi4
package: prim_mubi_pkg
type: uni
act: req
width: 1
inst_name: clkmgr_aon
default: ""
external: true
top_signame: hi_speed_sel
conn_type: false
index: -1
}
{
name: div_step_down_req
struct: mubi4
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
inst_name: clkmgr_aon
default: ""
external: true
top_signame: div_step_down_req
conn_type: false
index: -1
}
{
name: lc_clk_byp_req
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: clkmgr_aon
default: ""
top_signame: lc_ctrl_lc_clk_byp_req
index: -1
}
{
name: lc_clk_byp_ack
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
inst_name: clkmgr_aon
default: ""
top_signame: lc_ctrl_lc_clk_byp_ack
index: -1
}
{
name: jitter_en
struct: mubi4
package: prim_mubi_pkg
type: uni
act: req
width: 1
inst_name: clkmgr_aon
default: ""
external: true
top_signame: clk_main_jitter_en
conn_type: false
index: -1
}
{
name: pwr
struct: pwr_clk
type: req_rsp
act: rsp
width: 1
inst_name: clkmgr_aon
default: ""
package: pwrmgr_pkg
top_signame: pwrmgr_aon_pwr_clk
index: -1
}
{
name: idle
struct: mubi4
package: prim_mubi_pkg
type: uni
act: rcv
width: 4
inst_name: clkmgr_aon
default: ""
end_idx: -1
top_type: one-to-N
top_signame: clkmgr_aon_idle
index: -1
}
{
name: calib_rdy
desc: Indicates clocks are calibrated and frequencies accurate
struct: mubi4
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
default: prim_mubi_pkg::MuBi4True
inst_name: clkmgr_aon
external: true
top_signame: calib_rdy
conn_type: false
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: clkmgr_aon
default: ""
end_idx: -1
top_signame: clkmgr_aon_tl
index: -1
}
{
name: wkup_req
struct: logic
type: uni
act: req
width: 1
inst_name: sysrst_ctrl_aon
default: ""
package: ""
top_signame: pwrmgr_aon_wakeups
index: 0
}
{
name: rst_req
struct: logic
type: uni
act: req
width: 1
inst_name: sysrst_ctrl_aon
default: ""
package: ""
top_signame: pwrmgr_aon_rstreqs
index: 0
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: sysrst_ctrl_aon
default: ""
end_idx: -1
top_signame: sysrst_ctrl_aon_tl
index: -1
}
{
name: adc
struct: adc_ast
package: ast_pkg
type: req_rsp
act: req
width: 1
inst_name: adc_ctrl_aon
default: ""
external: true
top_signame: adc
conn_type: false
index: -1
}
{
name: wkup_req
struct: logic
type: uni
act: req
width: 1
inst_name: adc_ctrl_aon
default: ""
package: ""
top_signame: pwrmgr_aon_wakeups
index: 1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: adc_ctrl_aon
default: ""
end_idx: -1
top_signame: adc_ctrl_aon_tl
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: pwm_aon
default: ""
end_idx: -1
top_signame: pwm_aon_tl
index: -1
}
{
name: lc_hw_debug_en
desc: Debug enable qualifier coming from life cycle controller, used for HW strap qualification.
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: pinmux_aon
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
name: lc_dft_en
desc: Test enable qualifier coming from life cycle controller, used for HW strap qualification.
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: pinmux_aon
top_signame: lc_ctrl_lc_dft_en
index: -1
}
{
name: lc_escalate_en
desc:
'''
Escalation enable signal coming from life cycle controller, used for invalidating
the latched lc_hw_debug_en state inside the strap sampling logic.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: pinmux_aon
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: lc_check_byp_en
desc:
'''
Check bypass enable signal coming from life cycle controller, used for invalidating
the latched lc_hw_debug_en state inside the strap sampling logic. This signal is asserted
whenever the life cycle controller performs a life cycle transition. Its main use is
to skip any background checks inside the life cycle partition of the OTP controller while
a life cycle transition is in progress.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: pinmux_aon
top_signame: lc_ctrl_lc_check_byp_en
index: -1
}
{
name: pinmux_hw_debug_en
desc:
'''
This is the latched version of lc_hw_debug_en_i. We use it exclusively to gate the JTAG
signals and TAP side of the RV_DM so that RV_DM can remain live during an NDM reset cycle.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: pinmux_aon
end_idx: -1
top_type: broadcast
top_signame: pinmux_aon_pinmux_hw_debug_en
index: -1
}
{
name: lc_jtag
desc: Qualified JTAG signals for life cycle controller TAP.
struct: jtag
package: jtag_pkg
type: req_rsp
act: req
width: 1
inst_name: pinmux_aon
default: ""
end_idx: -1
top_signame: pinmux_aon_lc_jtag
index: -1
}
{
name: rv_jtag
desc: Qualified JTAG signals for RISC-V processor TAP.
struct: jtag
package: jtag_pkg
type: req_rsp
act: req
width: 1
inst_name: pinmux_aon
default: ""
end_idx: -1
top_signame: pinmux_aon_rv_jtag
index: -1
}
{
name: dft_jtag
desc: Qualified JTAG signals for DFT TAP.
struct: jtag
package: jtag_pkg
type: req_rsp
act: req
width: 1
inst_name: pinmux_aon
default: ""
top_signame: pinmux_aon_dft_jtag
index: -1
}
{
name: dft_strap_test
desc: Sampled DFT strap values, going to the DFT TAP.
struct: dft_strap_test_req
package: pinmux_pkg
type: uni
act: req
width: 1
default: "'0"
inst_name: pinmux_aon
external: true
top_signame: dft_strap_test
conn_type: false
index: -1
}
{
name: dft_hold_tap_sel
desc: TAP selection hold indication, asserted by the DFT TAP during boundary scan.
struct: logic
type: uni
act: rcv
width: 1
default: "'0"
inst_name: pinmux_aon
package: ""
external: true
top_signame: dft_hold_tap_sel
conn_type: false
index: -1
}
{
name: sleep_en
desc: Level signal that is asserted when the power manager enters sleep.
struct: logic
type: uni
act: rcv
width: 1
default: 1'b0
inst_name: pinmux_aon
package: ""
top_signame: pwrmgr_aon_low_power
index: -1
}
{
name: strap_en
desc: This signal is pulsed high by the power manager after reset in order to sample the HW straps.
struct: logic
type: uni
act: rcv
width: 1
default: 1'b0
inst_name: pinmux_aon
package: ""
top_signame: pwrmgr_aon_strap
index: -1
}
{
name: pin_wkup_req
desc: Wakeup request from wakeup detectors, to the power manager, running on the AON clock.
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: pinmux_aon
package: ""
top_signame: pwrmgr_aon_wakeups
index: 2
}
{
name: usbdev_dppullup_en
desc: Pullup enable signal coming from the USB IP.
struct: logic
type: uni
act: rcv
width: 1
inst_name: pinmux_aon
default: ""
package: ""
top_signame: usbdev_usb_dp_pullup
index: -1
}
{
name: usbdev_dnpullup_en
desc: Pullup enable signal coming from the USB IP.
struct: logic
type: uni
act: rcv
width: 1
inst_name: pinmux_aon
default: ""
package: ""
top_signame: usbdev_usb_dn_pullup
index: -1
}
{
name: usb_dppullup_en
desc: " Pullup enable signal going to USB PHY, needs to be maintained in low-power mode."
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: pinmux_aon
package: ""
external: true
top_signame: usb_dp_pullup_en
conn_type: false
index: -1
}
{
name: usb_dnpullup_en
desc: Pullup enable signal going to USB PHY, needs to be maintained in low-power mode.
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: pinmux_aon
package: ""
external: true
top_signame: usb_dn_pullup_en
conn_type: false
index: -1
}
{
name: usb_wkup_req
desc: Wakeup request from USB wakeup detector, going to the power manager, running on the AON clock.
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: pinmux_aon
package: ""
top_signame: pwrmgr_aon_wakeups
index: 3
}
{
name: usbdev_suspend_req
desc: Indicates whether USB is in suspended state, coming from the USB device.
struct: logic
type: uni
act: rcv
width: 1
inst_name: pinmux_aon
default: ""
package: ""
top_signame: usbdev_usb_aon_suspend_req
index: -1
}
{
name: usbdev_wake_ack
desc: Acknowledges the USB wakeup request, coming from the USB device.
struct: logic
type: uni
act: rcv
width: 1
inst_name: pinmux_aon
default: ""
package: ""
top_signame: usbdev_usb_aon_wake_ack
index: -1
}
{
name: usbdev_bus_reset
desc: Event signal that indicates what happened while monitoring.
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: pinmux_aon
package: ""
top_signame: usbdev_usb_aon_bus_reset
index: -1
}
{
name: usbdev_sense_lost
desc: Event signal that indicates what happened while monitoring.
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: pinmux_aon
package: ""
top_signame: usbdev_usb_aon_sense_lost
index: -1
}
{
name: usbdev_wake_detect_active
desc: State debug information.
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: pinmux_aon
package: ""
end_idx: -1
top_type: broadcast
top_signame: pinmux_aon_usbdev_wake_detect_active
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: pinmux_aon
default: ""
end_idx: -1
top_signame: pinmux_aon_tl
index: -1
}
{
name: nmi_wdog_timer_bark
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: aon_timer_aon
package: ""
end_idx: -1
top_type: broadcast
top_signame: aon_timer_aon_nmi_wdog_timer_bark
index: -1
}
{
name: wkup_req
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: aon_timer_aon
package: ""
top_signame: pwrmgr_aon_wakeups
index: 4
}
{
name: aon_timer_rst_req
struct: logic
type: uni
act: req
width: 1
default: 1'b0
inst_name: aon_timer_aon
package: ""
top_signame: pwrmgr_aon_rstreqs
index: 1
}
{
name: lc_escalate_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: aon_timer_aon
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: sleep_mode
struct: logic
type: uni
act: rcv
width: 1
inst_name: aon_timer_aon
default: ""
package: ""
top_signame: pwrmgr_aon_low_power
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: aon_timer_aon
default: ""
end_idx: -1
top_signame: aon_timer_aon_tl
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: ast
index: -1
}
{
name: ast_alert
struct: ast_alert
package: ast_pkg
type: req_rsp
act: rsp
width: 1
inst_name: sensor_ctrl
default: ""
external: true
top_signame: sensor_ctrl_ast_alert
conn_type: false
index: -1
}
{
name: ast_status
struct: ast_status
package: ast_pkg
type: uni
act: rcv
width: 1
inst_name: sensor_ctrl
default: ""
external: true
top_signame: sensor_ctrl_ast_status
conn_type: false
index: -1
}
{
name: ast_init_done
struct: mubi4
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
default: prim_mubi_pkg::MuBi4True
inst_name: sensor_ctrl
external: true
top_signame: ast_init_done
conn_type: false
index: -1
}
{
name: ast2pinmux
struct: logic
type: uni
act: rcv
width: 9
inst_name: sensor_ctrl
default: ""
package: ""
external: true
top_signame: ast2pinmux
conn_type: false
index: -1
}
{
name: wkup_req
struct: logic
type: uni
act: req
width: 1
inst_name: sensor_ctrl
default: ""
package: ""
top_signame: pwrmgr_aon_wakeups
index: 5
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: sensor_ctrl
default: ""
end_idx: -1
top_signame: sensor_ctrl_tl
index: -1
}
{
name: sram_otp_key
struct: sram_otp_key
package: otp_ctrl_pkg
type: req_rsp
act: req
width: 1
inst_name: sram_ctrl_ret_aon
default: ""
top_signame: otp_ctrl_sram_otp_key
index: 1
}
{
name: cfg
struct: ram_1p_cfg
package: prim_ram_1p_pkg
type: uni
act: rcv
width: 1
default: "'0"
inst_name: sram_ctrl_ret_aon
top_signame: ast_ram_1p_cfg
index: -1
}
{
name: lc_escalate_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: sram_ctrl_ret_aon
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: lc_hw_debug_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: sram_ctrl_ret_aon
index: -1
}
{
name: otp_en_sram_ifetch
struct: mubi8
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
default: prim_mubi_pkg::MuBi8False
inst_name: sram_ctrl_ret_aon
index: -1
}
{
name: regs_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: sram_ctrl_ret_aon
default: ""
end_idx: -1
top_signame: sram_ctrl_ret_aon_regs_tl
index: -1
}
{
name: ram_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: sram_ctrl_ret_aon
default: ""
end_idx: -1
top_signame: sram_ctrl_ret_aon_ram_tl
index: -1
}
{
name: otp
struct: flash_otp_key
package: otp_ctrl_pkg
type: req_rsp
act: req
width: 1
inst_name: flash_ctrl
default: ""
end_idx: -1
top_signame: flash_ctrl_otp
index: -1
}
{
name: lc_nvm_debug_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
top_signame: lc_ctrl_lc_nvm_debug_en
index: -1
}
{
name: flash_bist_enable
struct: mubi4
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
external: true
top_signame: flash_bist_enable
conn_type: false
index: -1
}
{
name: flash_power_down_h
struct: logic
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
package: ""
external: true
top_signame: flash_power_down_h
conn_type: false
index: -1
}
{
name: flash_power_ready_h
struct: logic
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
package: ""
external: true
top_signame: flash_power_ready_h
conn_type: false
index: -1
}
{
name: flash_test_mode_a
struct: ""
type: io
act: none
width: 2
inst_name: flash_ctrl
default: ""
package: ""
external: true
top_signame: flash_test_mode_a
conn_type: false
index: -1
}
{
name: flash_test_voltage_h
struct: ""
type: io
act: none
width: 1
inst_name: flash_ctrl
default: ""
package: ""
external: true
top_signame: flash_test_voltage_h
conn_type: false
index: -1
}
{
name: lc_creator_seed_sw_rw_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
top_signame: lc_ctrl_lc_creator_seed_sw_rw_en
index: -1
}
{
name: lc_owner_seed_sw_rw_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
top_signame: lc_ctrl_lc_owner_seed_sw_rw_en
index: -1
}
{
name: lc_iso_part_sw_rd_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
top_signame: lc_ctrl_lc_iso_part_sw_rd_en
index: -1
}
{
name: lc_iso_part_sw_wr_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
top_signame: lc_ctrl_lc_iso_part_sw_wr_en
index: -1
}
{
name: lc_seed_hw_rd_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
top_signame: lc_ctrl_lc_seed_hw_rd_en
index: -1
}
{
name: lc_escalate_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: rma_req
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
top_signame: lc_ctrl_lc_flash_rma_req
index: -1
}
{
name: rma_ack
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
inst_name: flash_ctrl
default: ""
end_idx: -1
top_type: broadcast
top_signame: flash_ctrl_rma_ack
index: -1
}
{
name: rma_seed
struct: lc_flash_rma_seed
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
end_idx: -1
top_type: broadcast
top_signame: flash_ctrl_rma_seed
index: -1
}
{
name: pwrmgr
struct: pwr_flash
package: pwrmgr_pkg
type: uni
act: req
width: 1
inst_name: flash_ctrl
default: ""
top_signame: pwrmgr_aon_pwr_flash
index: -1
}
{
name: keymgr
struct: keymgr_flash
package: flash_ctrl_pkg
type: uni
act: req
width: 1
inst_name: flash_ctrl
default: ""
end_idx: -1
top_type: broadcast
top_signame: flash_ctrl_keymgr
index: -1
}
{
name: obs_ctrl
struct: ast_obs_ctrl
package: ast_pkg
type: uni
act: rcv
width: 1
inst_name: flash_ctrl
default: ""
top_signame: ast_obs_ctrl
index: -1
}
{
name: fla_obs
struct: logic
type: uni
act: req
width: 8
inst_name: flash_ctrl
default: ""
package: ""
external: true
top_signame: flash_obs
conn_type: false
index: -1
}
{
name: core_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: flash_ctrl
default: ""
end_idx: -1
top_signame: flash_ctrl_core_tl
index: -1
}
{
name: prim_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: flash_ctrl
default: ""
end_idx: -1
top_signame: flash_ctrl_prim_tl
index: -1
}
{
name: mem_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: flash_ctrl
default: ""
end_idx: -1
top_signame: flash_ctrl_mem_tl
index: -1
}
{
name: jtag
desc: JTAG signals for the RISC-V TAP.
struct: jtag
package: jtag_pkg
type: req_rsp
act: rsp
width: 1
inst_name: rv_dm
default: ""
top_signame: pinmux_aon_rv_jtag
index: -1
}
{
name: lc_hw_debug_en
desc:
'''
Multibit life cycle hardware debug enable signal coming from life cycle controller,
asserted when the hardware debug mechanisms are enabled in the system.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: rv_dm
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
name: pinmux_hw_debug_en
desc:
'''
Multibit life cycle hardware debug enable signal coming from pinmux.
This is a latched version of the lc_hw_debug_en signal and is only used to
gate the JTAG / TAP side of the RV_DM. It is used to keep a debug session live
while the rest of the system undergoes an NDM reset.
'''
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: rv_dm
top_signame: pinmux_aon_pinmux_hw_debug_en
index: -1
}
{
name: unavailable
desc:
'''
This signal indicates to the debug module that the main processor is not available
for debug (e.g. due to a low-power state).
'''
struct: logic
type: uni
act: rcv
width: 1
default: 1'b0
inst_name: rv_dm
index: -1
}
{
name: ndmreset_req
desc: Non-debug module reset request going to the system reset infrastructure.
struct: logic
type: uni
act: req
width: 1
inst_name: rv_dm
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: rv_dm_ndmreset_req
index: -1
}
{
name: dmactive
desc:
'''
This signal indicates whether the debug module is active and can be used to prevent
power down of the core and bus-attached peripherals.
'''
struct: logic
type: uni
act: req
width: 1
inst_name: rv_dm
index: -1
}
{
name: debug_req
desc: This is the debug request interrupt going to the main processor.
struct: logic [rv_dm_reg_pkg::NrHarts-1:0]
type: uni
act: req
width: 1
inst_name: rv_dm
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: rv_dm_debug_req
index: -1
}
{
name: sba_tl_h
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: rv_dm
default: ""
top_signame: main_tl_rv_dm__sba
index: -1
}
{
name: regs_tl_d
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: rv_dm
default: ""
end_idx: -1
top_signame: rv_dm_regs_tl_d
index: -1
}
{
name: mem_tl_d
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: rv_dm
default: ""
end_idx: -1
top_signame: rv_dm_mem_tl_d
index: -1
}
{
name: irq
struct: logic
type: uni
act: req
width: 1
inst_name: rv_plic
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: rv_plic_irq
index: -1
}
{
name: irq_id
struct: logic
type: uni
act: req
width: 1
inst_name: rv_plic
index: -1
}
{
name: msip
struct: logic
type: uni
act: req
width: 1
inst_name: rv_plic
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: rv_plic_msip
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: rv_plic
default: ""
end_idx: -1
top_signame: rv_plic_tl
index: -1
}
{
name: idle
struct: mubi4
package: prim_mubi_pkg
type: uni
act: req
width: 1
inst_name: aes
default: ""
top_signame: clkmgr_aon_idle
index: 0
}
{
name: lc_escalate_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: aes
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: edn
struct: edn
package: edn_pkg
type: req_rsp
act: req
width: 1
inst_name: aes
default: ""
top_signame: edn0_edn
index: 5
}
{
name: keymgr_key
struct: hw_key_req
package: keymgr_pkg
type: uni
act: rcv
width: 1
inst_name: aes
default: ""
top_signame: keymgr_aes_key
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: aes
default: ""
end_idx: -1
top_signame: aes_tl
index: -1
}
{
name: idle
struct: mubi4
package: prim_mubi_pkg
type: uni
act: req
width: 1
inst_name: hmac
default: ""
top_signame: clkmgr_aon_idle
index: 1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: hmac
default: ""
end_idx: -1
top_signame: hmac_tl
index: -1
}
{
name: keymgr_key
struct: hw_key_req
package: keymgr_pkg
type: uni
act: rcv
width: 1
inst_name: kmac
default: ""
top_signame: keymgr_kmac_key
index: -1
}
{
name: app
struct: app
package: kmac_pkg
type: req_rsp
act: rsp
width: 3
inst_name: kmac
default: ""
end_idx: -1
top_type: one-to-N
top_signame: kmac_app
index: -1
}
{
name: entropy
struct: edn
package: edn_pkg
type: req_rsp
act: req
width: 1
inst_name: kmac
default: ""
top_signame: edn0_edn
index: 3
}
{
name: idle
struct: mubi4
package: prim_mubi_pkg
type: uni
act: req
width: 1
inst_name: kmac
default: ""
top_signame: clkmgr_aon_idle
index: 2
}
{
name: en_masking
struct: logic
type: uni
act: req
width: 1
inst_name: kmac
default: ""
package: ""
end_idx: -1
top_type: broadcast
top_signame: kmac_en_masking
index: -1
}
{
name: lc_escalate_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: kmac
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: kmac
default: ""
end_idx: -1
top_signame: kmac_tl
index: -1
}
{
name: otbn_otp_key
struct: otbn_otp_key
package: otp_ctrl_pkg
type: req_rsp
act: req
width: 1
default: "'0"
inst_name: otbn
top_signame: otp_ctrl_otbn_otp_key
index: -1
}
{
name: edn_rnd
struct: edn
package: edn_pkg
type: req_rsp
act: req
width: 1
inst_name: otbn
default: ""
top_signame: edn1_edn
index: 0
}
{
name: edn_urnd
struct: edn
package: edn_pkg
type: req_rsp
act: req
width: 1
inst_name: otbn
default: ""
top_signame: edn0_edn
index: 6
}
{
name: idle
struct: mubi4
package: prim_mubi_pkg
type: uni
act: req
width: 1
inst_name: otbn
default: ""
top_signame: clkmgr_aon_idle
index: 3
}
{
name: ram_cfg
struct: ram_1p_cfg
package: prim_ram_1p_pkg
type: uni
act: rcv
width: 1
inst_name: otbn
default: ""
top_signame: ast_ram_1p_cfg
index: -1
}
{
name: lc_escalate_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: otbn
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: lc_rma_req
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: otbn
top_signame: flash_ctrl_rma_ack
index: -1
}
{
name: lc_rma_ack
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: req
width: 1
default: lc_ctrl_pkg::Off
inst_name: otbn
end_idx: -1
top_type: broadcast
top_signame: otbn_lc_rma_ack
index: -1
}
{
name: keymgr_key
struct: otbn_key_req
package: keymgr_pkg
type: uni
act: rcv
width: 1
inst_name: otbn
default: ""
top_signame: keymgr_otbn_key
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: otbn
default: ""
end_idx: -1
top_signame: otbn_tl
index: -1
}
{
name: edn
struct: edn
package: edn_pkg
type: req_rsp
act: req
width: 1
inst_name: keymgr
default: ""
top_signame: edn0_edn
index: 0
}
{
name: aes_key
struct: hw_key_req
package: keymgr_pkg
type: uni
act: req
width: 1
inst_name: keymgr
default: ""
end_idx: -1
top_type: broadcast
top_signame: keymgr_aes_key
index: -1
}
{
name: kmac_key
struct: hw_key_req
package: keymgr_pkg
type: uni
act: req
width: 1
inst_name: keymgr
default: ""
end_idx: -1
top_type: broadcast
top_signame: keymgr_kmac_key
index: -1
}
{
name: otbn_key
struct: otbn_key_req
package: keymgr_pkg
type: uni
act: req
width: 1
inst_name: keymgr
default: ""
end_idx: -1
top_type: broadcast
top_signame: keymgr_otbn_key
index: -1
}
{
name: kmac_data
struct: app
package: kmac_pkg
type: req_rsp
act: req
width: 1
inst_name: keymgr
default: ""
top_signame: kmac_app
index: 0
}
{
name: otp_key
struct: otp_keymgr_key
package: otp_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: keymgr
default: ""
top_signame: otp_ctrl_otp_keymgr_key
index: -1
}
{
name: otp_device_id
struct: otp_device_id
package: otp_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: keymgr
default: ""
top_signame: keymgr_otp_device_id
index: -1
}
{
name: flash
struct: keymgr_flash
package: flash_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: keymgr
default: ""
top_signame: flash_ctrl_keymgr
index: -1
}
{
name: lc_keymgr_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::On
inst_name: keymgr
top_signame: lc_ctrl_lc_keymgr_en
index: -1
}
{
name: lc_keymgr_div
struct: lc_keymgr_div
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: keymgr
default: ""
top_signame: lc_ctrl_lc_keymgr_div
index: -1
}
{
name: rom_digest
struct: keymgr_data
package: rom_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: keymgr
default: ""
top_signame: rom_ctrl_keymgr_data
index: -1
}
{
name: kmac_en_masking
struct: logic
type: uni
act: rcv
width: 1
inst_name: keymgr
default: ""
package: ""
top_signame: kmac_en_masking
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: keymgr
default: ""
end_idx: -1
top_signame: keymgr_tl
index: -1
}
{
name: csrng_cmd
struct: csrng
package: csrng_pkg
type: req_rsp
act: rsp
width: 2
inst_name: csrng
default: ""
end_idx: -1
top_type: one-to-N
top_signame: csrng_csrng_cmd
index: -1
}
{
name: entropy_src_hw_if
struct: entropy_src_hw_if
package: entropy_src_pkg
type: req_rsp
act: req
width: 1
inst_name: csrng
default: ""
end_idx: -1
top_signame: csrng_entropy_src_hw_if
index: -1
}
{
name: cs_aes_halt
struct: cs_aes_halt
package: entropy_src_pkg
type: req_rsp
act: rsp
width: 1
inst_name: csrng
default: ""
end_idx: -1
top_signame: csrng_cs_aes_halt
index: -1
}
{
name: otp_en_csrng_sw_app_read
struct: mubi8
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
inst_name: csrng
default: ""
top_signame: csrng_otp_en_csrng_sw_app_read
index: -1
}
{
name: lc_hw_debug_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: csrng
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: csrng
default: ""
end_idx: -1
top_signame: csrng_tl
index: -1
}
{
name: entropy_src_hw_if
struct: entropy_src_hw_if
package: entropy_src_pkg
type: req_rsp
act: rsp
width: 1
inst_name: entropy_src
default: ""
top_signame: csrng_entropy_src_hw_if
index: -1
}
{
name: cs_aes_halt
struct: cs_aes_halt
package: entropy_src_pkg
type: req_rsp
act: req
width: 1
inst_name: entropy_src
default: ""
top_signame: csrng_cs_aes_halt
index: -1
}
{
name: entropy_src_rng
struct: entropy_src_rng
package: entropy_src_pkg
type: req_rsp
act: req
width: 1
inst_name: entropy_src
default: ""
external: true
top_signame: es_rng
conn_type: false
index: -1
}
{
name: entropy_src_xht
struct: entropy_src_xht
package: entropy_src_pkg
type: req_rsp
act: req
width: 1
inst_name: entropy_src
index: -1
}
{
name: otp_en_entropy_src_fw_read
struct: mubi8
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
inst_name: entropy_src
default: ""
top_signame: entropy_src_otp_en_entropy_src_fw_read
index: -1
}
{
name: otp_en_entropy_src_fw_over
struct: mubi8
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
inst_name: entropy_src
default: ""
top_signame: entropy_src_otp_en_entropy_src_fw_over
index: -1
}
{
name: rng_fips
struct: logic
type: uni
act: req
width: 1
inst_name: entropy_src
default: ""
package: ""
external: true
top_signame: es_rng_fips
conn_type: false
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: entropy_src
default: ""
end_idx: -1
top_signame: entropy_src_tl
index: -1
}
{
name: csrng_cmd
desc: EDN supports a signal CSRNG application interface.
struct: csrng
package: csrng_pkg
type: req_rsp
act: req
width: 1
inst_name: edn0
default: ""
top_signame: csrng_csrng_cmd
index: 0
}
{
name: edn
desc:
'''
The collection of peripheral ports supported by edn. The width (4)
indicates the number of peripheral ports on a single instance.
Due to limitations in the parametrization of top-level interconnects
this value is not currently parameterizable. However, the number
of peripheral ports may change in a future revision.
'''
struct: edn
package: edn_pkg
type: req_rsp
act: rsp
width: 8
default: "'0"
inst_name: edn0
end_idx: -1
top_type: one-to-N
top_signame: edn0_edn
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: edn0
default: ""
end_idx: -1
top_signame: edn0_tl
index: -1
}
{
name: csrng_cmd
desc: EDN supports a signal CSRNG application interface.
struct: csrng
package: csrng_pkg
type: req_rsp
act: req
width: 1
inst_name: edn1
default: ""
top_signame: csrng_csrng_cmd
index: 1
}
{
name: edn
desc:
'''
The collection of peripheral ports supported by edn. The width (4)
indicates the number of peripheral ports on a single instance.
Due to limitations in the parametrization of top-level interconnects
this value is not currently parameterizable. However, the number
of peripheral ports may change in a future revision.
'''
struct: edn
package: edn_pkg
type: req_rsp
act: rsp
width: 8
default: "'0"
inst_name: edn1
end_idx: 1
top_type: partial-one-to-N
top_signame: edn1_edn
index: -1
}
{
name: tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: edn1
default: ""
end_idx: -1
top_signame: edn1_tl
index: -1
}
{
name: sram_otp_key
struct: sram_otp_key
package: otp_ctrl_pkg
type: req_rsp
act: req
width: 1
inst_name: sram_ctrl_main
default: ""
top_signame: otp_ctrl_sram_otp_key
index: 0
}
{
name: cfg
struct: ram_1p_cfg
package: prim_ram_1p_pkg
type: uni
act: rcv
width: 1
default: "'0"
inst_name: sram_ctrl_main
top_signame: ast_ram_1p_cfg
index: -1
}
{
name: lc_escalate_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: sram_ctrl_main
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
name: lc_hw_debug_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
default: lc_ctrl_pkg::Off
inst_name: sram_ctrl_main
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
name: otp_en_sram_ifetch
struct: mubi8
package: prim_mubi_pkg
type: uni
act: rcv
width: 1
default: prim_mubi_pkg::MuBi8False
inst_name: sram_ctrl_main
top_signame: sram_ctrl_main_otp_en_sram_ifetch
index: -1
}
{
name: regs_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: sram_ctrl_main
default: ""
end_idx: -1
top_signame: sram_ctrl_main_regs_tl
index: -1
}
{
name: ram_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: sram_ctrl_main
default: ""
end_idx: -1
top_signame: sram_ctrl_main_ram_tl
index: -1
}
{
name: rom_cfg
struct: rom_cfg
package: prim_rom_pkg
type: uni
act: rcv
width: 1
inst_name: rom_ctrl
default: ""
top_signame: ast_rom_cfg
index: -1
}
{
name: pwrmgr_data
struct: pwrmgr_data
package: rom_ctrl_pkg
type: uni
act: req
width: 1
inst_name: rom_ctrl
default: ""
end_idx: -1
top_type: broadcast
top_signame: rom_ctrl_pwrmgr_data
index: -1
}
{
name: keymgr_data
struct: keymgr_data
package: rom_ctrl_pkg
type: uni
act: req
width: 1
inst_name: rom_ctrl
default: ""
end_idx: -1
top_type: broadcast
top_signame: rom_ctrl_keymgr_data
index: -1
}
{
name: kmac_data
struct: app
package: kmac_pkg
type: req_rsp
act: req
width: 1
inst_name: rom_ctrl
default: ""
top_signame: kmac_app
index: 2
}
{
name: regs_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: rom_ctrl
default: ""
end_idx: -1
top_signame: rom_ctrl_regs_tl
index: -1
}
{
name: rom_tl
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: rom_ctrl
default: ""
end_idx: -1
top_signame: rom_ctrl_rom_tl
index: -1
}
{
name: rst_cpu_n
struct: logic
type: uni
act: req
width: 1
inst_name: rv_core_ibex
index: -1
}
{
name: ram_cfg
struct: ram_1p_cfg
package: prim_ram_1p_pkg
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: ast_ram_1p_cfg
index: -1
}
{
name: hart_id
struct: logic
type: uni
act: rcv
width: 32
inst_name: rv_core_ibex
default: ""
package: ""
top_signame: rv_core_ibex_hart_id
index: -1
}
{
name: boot_addr
struct: logic
type: uni
act: rcv
width: 32
inst_name: rv_core_ibex
default: ""
package: ""
top_signame: rv_core_ibex_boot_addr
index: -1
}
{
name: irq_software
struct: logic
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
package: ""
top_signame: rv_plic_msip
index: -1
}
{
name: irq_timer
struct: logic
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
package: ""
top_signame: rv_core_ibex_irq_timer
index: -1
}
{
name: irq_external
struct: logic
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
package: ""
top_signame: rv_plic_irq
index: -1
}
{
name: esc_tx
struct: esc_tx
package: prim_esc_pkg
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: alert_handler_esc_tx
index: 0
}
{
name: esc_rx
struct: esc_rx
package: prim_esc_pkg
type: uni
act: req
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: alert_handler_esc_rx
index: 0
}
{
name: debug_req
struct: logic
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
package: ""
top_signame: rv_dm_debug_req
index: -1
}
{
name: crash_dump
struct: cpu_crash_dump
package: rv_core_ibex_pkg
type: uni
act: req
width: 1
inst_name: rv_core_ibex
default: ""
end_idx: -1
top_type: broadcast
top_signame: rv_core_ibex_crash_dump
index: -1
}
{
name: lc_cpu_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: lc_ctrl_lc_cpu_en
index: -1
}
{
name: pwrmgr_cpu_en
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: pwrmgr_aon_fetch_en
index: -1
}
{
name: pwrmgr
struct: pwr_cpu
package: pwrmgr_pkg
type: uni
act: req
width: 1
inst_name: rv_core_ibex
default: ""
end_idx: -1
top_type: broadcast
top_signame: rv_core_ibex_pwrmgr
index: -1
}
{
name: nmi_wdog
struct: logic
type: uni
act: rcv
width: 1
inst_name: rv_core_ibex
default: ""
package: ""
top_signame: aon_timer_aon_nmi_wdog_timer_bark
index: -1
}
{
name: edn
struct: edn
package: edn_pkg
type: req_rsp
act: req
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: edn0_edn
index: 7
}
{
name: icache_otp_key
struct: sram_otp_key
package: otp_ctrl_pkg
type: req_rsp
act: req
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: otp_ctrl_sram_otp_key
index: 2
}
{
name: fpga_info
struct: logic
type: uni
act: rcv
width: 32
inst_name: rv_core_ibex
default: ""
package: ""
external: true
top_signame: fpga_info
conn_type: false
index: -1
}
{
name: corei_tl_h
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: main_tl_rv_core_ibex__corei
index: -1
}
{
name: cored_tl_h
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: rv_core_ibex
default: ""
top_signame: main_tl_rv_core_ibex__cored
index: -1
}
{
name: cfg_tl_d
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: rv_core_ibex
default: ""
end_idx: -1
top_signame: rv_core_ibex_cfg_tl_d
index: -1
}
{
name: tl_rv_core_ibex__corei
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: main
default: ""
end_idx: -1
top_signame: main_tl_rv_core_ibex__corei
index: -1
}
{
name: tl_rv_core_ibex__cored
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: main
default: ""
end_idx: -1
top_signame: main_tl_rv_core_ibex__cored
index: -1
}
{
name: tl_rv_dm__sba
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: main
default: ""
end_idx: -1
top_signame: main_tl_rv_dm__sba
index: -1
}
{
name: tl_rv_dm__regs
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: rv_dm_regs_tl_d
index: -1
}
{
name: tl_rv_dm__mem
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: rv_dm_mem_tl_d
index: -1
}
{
name: tl_rom_ctrl__rom
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: rom_ctrl_rom_tl
index: -1
}
{
name: tl_rom_ctrl__regs
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: rom_ctrl_regs_tl
index: -1
}
{
name: tl_peri
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
end_idx: -1
top_signame: main_tl_peri
index: -1
}
{
name: tl_spi_host0
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: spi_host0_tl
index: -1
}
{
name: tl_spi_host1
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: spi_host1_tl
index: -1
}
{
name: tl_usbdev
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: usbdev_tl
index: -1
}
{
name: tl_flash_ctrl__core
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: flash_ctrl_core_tl
index: -1
}
{
name: tl_flash_ctrl__prim
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: flash_ctrl_prim_tl
index: -1
}
{
name: tl_flash_ctrl__mem
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: flash_ctrl_mem_tl
index: -1
}
{
name: tl_hmac
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: hmac_tl
index: -1
}
{
name: tl_kmac
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: kmac_tl
index: -1
}
{
name: tl_aes
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: aes_tl
index: -1
}
{
name: tl_entropy_src
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: entropy_src_tl
index: -1
}
{
name: tl_csrng
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: csrng_tl
index: -1
}
{
name: tl_edn0
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: edn0_tl
index: -1
}
{
name: tl_edn1
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: edn1_tl
index: -1
}
{
name: tl_rv_plic
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: rv_plic_tl
index: -1
}
{
name: tl_otbn
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: otbn_tl
index: -1
}
{
name: tl_keymgr
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: keymgr_tl
index: -1
}
{
name: tl_rv_core_ibex__cfg
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: rv_core_ibex_cfg_tl_d
index: -1
}
{
name: tl_sram_ctrl_main__regs
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: sram_ctrl_main_regs_tl
index: -1
}
{
name: tl_sram_ctrl_main__ram
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: main
default: ""
top_signame: sram_ctrl_main_ram_tl
index: -1
}
{
name: tl_main
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
width: 1
inst_name: peri
default: ""
top_signame: main_tl_peri
index: -1
}
{
name: tl_uart0
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: uart0_tl
index: -1
}
{
name: tl_uart1
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: uart1_tl
index: -1
}
{
name: tl_uart2
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: uart2_tl
index: -1
}
{
name: tl_uart3
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: uart3_tl
index: -1
}
{
name: tl_i2c0
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: i2c0_tl
index: -1
}
{
name: tl_i2c1
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: i2c1_tl
index: -1
}
{
name: tl_i2c2
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: i2c2_tl
index: -1
}
{
name: tl_pattgen
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: pattgen_tl
index: -1
}
{
name: tl_pwm_aon
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: pwm_aon_tl
index: -1
}
{
name: tl_gpio
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: gpio_tl
index: -1
}
{
name: tl_spi_device
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: spi_device_tl
index: -1
}
{
name: tl_rv_timer
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: rv_timer_tl
index: -1
}
{
name: tl_pwrmgr_aon
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: pwrmgr_aon_tl
index: -1
}
{
name: tl_rstmgr_aon
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: rstmgr_aon_tl
index: -1
}
{
name: tl_clkmgr_aon
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: clkmgr_aon_tl
index: -1
}
{
name: tl_pinmux_aon
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: pinmux_aon_tl
index: -1
}
{
name: tl_otp_ctrl__core
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: otp_ctrl_core_tl
index: -1
}
{
name: tl_otp_ctrl__prim
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: otp_ctrl_prim_tl
index: -1
}
{
name: tl_lc_ctrl
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: lc_ctrl_tl
index: -1
}
{
name: tl_sensor_ctrl
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: sensor_ctrl_tl
index: -1
}
{
name: tl_alert_handler
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: alert_handler_tl
index: -1
}
{
name: tl_sram_ctrl_ret_aon__regs
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: sram_ctrl_ret_aon_regs_tl
index: -1
}
{
name: tl_sram_ctrl_ret_aon__ram
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: sram_ctrl_ret_aon_ram_tl
index: -1
}
{
name: tl_aon_timer_aon
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: aon_timer_aon_tl
index: -1
}
{
name: tl_sysrst_ctrl_aon
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: sysrst_ctrl_aon_tl
index: -1
}
{
name: tl_adc_ctrl_aon
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
top_signame: adc_ctrl_aon_tl
index: -1
}
{
name: tl_ast
struct: tl
package: tlul_pkg
type: req_rsp
act: req
width: 1
inst_name: peri
default: ""
external: true
top_signame: ast_tl
conn_type: false
index: -1
}
{
struct: edn
type: req_rsp
name: edn
act: rsp
package: edn_pkg
inst_name: ast
width: 1
default: ""
top_signame: edn0_edn
index: 2
external: true
conn_type: true
}
{
struct: lc_tx
type: uni
name: lc_dft_en
act: req
package: lc_ctrl_pkg
inst_name: ast
width: 1
default: ""
top_signame: lc_ctrl_lc_dft_en
index: -1
external: true
conn_type: true
}
{
struct: ram_1p_cfg
package: prim_ram_1p_pkg
type: uni
name: ram_1p_cfg
act: rcv
inst_name: ast
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: ast_ram_1p_cfg
index: -1
external: true
conn_type: true
}
{
struct: ram_2p_cfg
package: prim_ram_2p_pkg
type: uni
name: ram_2p_cfg
act: rcv
inst_name: ast
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: ast_ram_2p_cfg
index: -1
external: true
conn_type: true
}
{
struct: rom_cfg
package: prim_rom_pkg
type: uni
name: rom_cfg
act: rcv
inst_name: ast
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: ast_rom_cfg
index: -1
external: true
conn_type: true
}
{
struct: ast_obs_ctrl
type: uni
name: obs_ctrl
act: rcv
package: ast_pkg
inst_name: ast
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: ast_obs_ctrl
index: -1
external: true
conn_type: true
}
]
external:
[
{
package: ast_pkg
struct: adc_ast_req
signame: adc_req_o
width: 1
type: req_rsp
default: ""
direction: out
conn_type: false
index: -1
netname: adc_req
}
{
package: ast_pkg
struct: adc_ast_rsp
signame: adc_rsp_i
width: 1
type: req_rsp
default: ""
direction: in
conn_type: false
index: -1
netname: adc_rsp
}
{
package: edn_pkg
struct: edn_req
signame: ast_edn_req_i
width: 1
type: req_rsp
default: ""
direction: in
conn_type: true
index: 2
netname: edn0_edn_req
}
{
package: edn_pkg
struct: edn_rsp
signame: ast_edn_rsp_o
width: 1
type: req_rsp
default: ""
direction: out
conn_type: true
index: 2
netname: edn0_edn_rsp
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: ast_lc_dft_en_o
width: 1
type: uni
default: ""
direction: out
conn_type: true
index: -1
netname: lc_ctrl_lc_dft_en
}
{
package: ast_pkg
struct: ast_obs_ctrl
signame: obs_ctrl_i
width: 1
type: uni
default: ""
direction: in
conn_type: true
index: -1
netname: ast_obs_ctrl
}
{
package: prim_ram_1p_pkg
struct: ram_1p_cfg
signame: ram_1p_cfg_i
width: 1
type: uni
default: ""
direction: in
conn_type: true
index: -1
netname: ast_ram_1p_cfg
}
{
package: prim_ram_2p_pkg
struct: ram_2p_cfg
signame: ram_2p_cfg_i
width: 1
type: uni
default: ""
direction: in
conn_type: true
index: -1
netname: ast_ram_2p_cfg
}
{
package: prim_rom_pkg
struct: rom_cfg
signame: rom_cfg_i
width: 1
type: uni
default: ""
direction: in
conn_type: true
index: -1
netname: ast_rom_cfg
}
{
package: prim_mubi_pkg
struct: mubi4
signame: clk_main_jitter_en_o
width: 1
type: uni
default: ""
direction: out
conn_type: false
index: -1
netname: clk_main_jitter_en
}
{
package: prim_mubi_pkg
struct: mubi4
signame: io_clk_byp_req_o
width: 1
type: uni
default: ""
direction: out
conn_type: false
index: -1
netname: io_clk_byp_req
}
{
package: prim_mubi_pkg
struct: mubi4
signame: io_clk_byp_ack_i
width: 1
type: uni
default: ""
direction: in
conn_type: false
index: -1
netname: io_clk_byp_ack
}
{
package: prim_mubi_pkg
struct: mubi4
signame: all_clk_byp_req_o
width: 1
type: uni
default: ""
direction: out
conn_type: false
index: -1
netname: all_clk_byp_req
}
{
package: prim_mubi_pkg
struct: mubi4
signame: all_clk_byp_ack_i
width: 1
type: uni
default: ""
direction: in
conn_type: false
index: -1
netname: all_clk_byp_ack
}
{
package: prim_mubi_pkg
struct: mubi4
signame: hi_speed_sel_o
width: 1
type: uni
default: ""
direction: out
conn_type: false
index: -1
netname: hi_speed_sel
}
{
package: prim_mubi_pkg
struct: mubi4
signame: div_step_down_req_i
width: 1
type: uni
default: ""
direction: in
conn_type: false
index: -1
netname: div_step_down_req
}
{
package: prim_mubi_pkg
struct: mubi4
signame: calib_rdy_i
width: 1
type: uni
default: prim_mubi_pkg::MuBi4True
direction: in
conn_type: false
index: -1
netname: calib_rdy
}
{
package: prim_mubi_pkg
struct: mubi4
signame: flash_bist_enable_i
width: 1
type: uni
default: ""
direction: in
conn_type: false
index: -1
netname: flash_bist_enable
}
{
package: ""
struct: logic
signame: flash_power_down_h_i
width: 1
type: uni
default: ""
direction: in
conn_type: false
index: -1
netname: flash_power_down_h
}
{
package: ""
struct: logic
signame: flash_power_ready_h_i
width: 1
type: uni
default: ""
direction: in
conn_type: false
index: -1
netname: flash_power_ready_h
}
{
package: ""
struct: ""
signame: flash_test_mode_a_io
width: 2
type: io
default: ""
direction: inout
conn_type: false
index: -1
netname: flash_test_mode_a
}
{
package: ""
struct: ""
signame: flash_test_voltage_h_io
width: 1
type: io
default: ""
direction: inout
conn_type: false
index: -1
netname: flash_test_voltage_h
}
{
package: ""
struct: logic
signame: flash_obs_o
width: 8
type: uni
default: ""
direction: out
conn_type: false
index: -1
netname: flash_obs
}
{
package: entropy_src_pkg
struct: entropy_src_rng_req
signame: es_rng_req_o
width: 1
type: req_rsp
default: ""
direction: out
conn_type: false
index: -1
netname: es_rng_req
}
{
package: entropy_src_pkg
struct: entropy_src_rng_rsp
signame: es_rng_rsp_i
width: 1
type: req_rsp
default: ""
direction: in
conn_type: false
index: -1
netname: es_rng_rsp
}
{
package: ""
struct: logic
signame: es_rng_fips_o
width: 1
type: uni
default: ""
direction: out
conn_type: false
index: -1
netname: es_rng_fips
}
{
package: tlul_pkg
struct: tl_h2d
signame: ast_tl_req_o
width: 1
type: req_rsp
default: ""
direction: out
conn_type: false
index: -1
netname: ast_tl_h2d
}
{
package: tlul_pkg
struct: tl_d2h
signame: ast_tl_rsp_i
width: 1
type: req_rsp
default: ""
direction: in
conn_type: false
index: -1
netname: ast_tl_d2h
}
{
package: pinmux_pkg
struct: dft_strap_test_req
signame: dft_strap_test_o
width: 1
type: uni
default: "'0"
direction: out
conn_type: false
index: -1
netname: dft_strap_test
}
{
package: ""
struct: logic
signame: dft_hold_tap_sel_i
width: 1
type: uni
default: "'0"
direction: in
conn_type: false
index: -1
netname: dft_hold_tap_sel
}
{
package: ""
struct: logic
signame: usb_dp_pullup_en_o
width: 1
type: uni
default: 1'b0
direction: out
conn_type: false
index: -1
netname: usb_dp_pullup_en
}
{
package: ""
struct: logic
signame: usb_dn_pullup_en_o
width: 1
type: uni
default: 1'b0
direction: out
conn_type: false
index: -1
netname: usb_dn_pullup_en
}
{
package: pwrmgr_pkg
struct: pwr_ast_req
signame: pwrmgr_ast_req_o
width: 1
type: req_rsp
default: ""
direction: out
conn_type: false
index: -1
netname: pwrmgr_ast_req
}
{
package: pwrmgr_pkg
struct: pwr_ast_rsp
signame: pwrmgr_ast_rsp_i
width: 1
type: req_rsp
default: ""
direction: in
conn_type: false
index: -1
netname: pwrmgr_ast_rsp
}
{
package: otp_ctrl_pkg
struct: otp_ast_req
signame: otp_ctrl_otp_ast_pwr_seq_o
width: 1
type: uni
default: "'0"
direction: out
conn_type: false
index: -1
netname: otp_ctrl_otp_ast_pwr_seq
}
{
package: otp_ctrl_pkg
struct: otp_ast_rsp
signame: otp_ctrl_otp_ast_pwr_seq_h_i
width: 1
type: uni
default: "'0"
direction: in
conn_type: false
index: -1
netname: otp_ctrl_otp_ast_pwr_seq_h
}
{
package: ""
struct: ""
signame: otp_ext_voltage_h_io
width: 1
type: io
default: "'0"
direction: inout
conn_type: false
index: -1
netname: otp_ext_voltage_h
}
{
package: ""
struct: logic
signame: otp_obs_o
width: 8
type: uni
default: ""
direction: out
conn_type: false
index: -1
netname: otp_obs
}
{
package: ""
struct: logic
signame: por_n_i
width: 2
type: uni
default: ""
direction: in
conn_type: false
index: -1
netname: por_n
}
{
package: ""
struct: logic
signame: fpga_info_i
width: 32
type: uni
default: ""
direction: in
conn_type: false
index: -1
netname: fpga_info
}
{
package: ast_pkg
struct: ast_alert_req
signame: sensor_ctrl_ast_alert_req_i
width: 1
type: req_rsp
default: ""
direction: in
conn_type: false
index: -1
netname: sensor_ctrl_ast_alert_req
}
{
package: ast_pkg
struct: ast_alert_rsp
signame: sensor_ctrl_ast_alert_rsp_o
width: 1
type: req_rsp
default: ""
direction: out
conn_type: false
index: -1
netname: sensor_ctrl_ast_alert_rsp
}
{
package: ast_pkg
struct: ast_status
signame: sensor_ctrl_ast_status_i
width: 1
type: uni
default: ""
direction: in
conn_type: false
index: -1
netname: sensor_ctrl_ast_status
}
{
package: ""
struct: logic
signame: ast2pinmux_i
width: 9
type: uni
default: ""
direction: in
conn_type: false
index: -1
netname: ast2pinmux
}
{
package: prim_mubi_pkg
struct: mubi4
signame: ast_init_done_i
width: 1
type: uni
default: prim_mubi_pkg::MuBi4True
direction: in
conn_type: false
index: -1
netname: ast_init_done
}
{
package: ""
struct: logic
signame: sck_monitor_o
width: 1
type: uni
default: ""
direction: out
conn_type: false
index: -1
netname: sck_monitor
}
{
package: ""
struct: logic
signame: usbdev_usb_rx_d_i
width: 1
type: uni
default: ""
direction: in
conn_type: false
index: -1
netname: usbdev_usb_rx_d
}
{
package: ""
struct: logic
signame: usbdev_usb_tx_d_o
width: 1
type: uni
default: ""
direction: out
conn_type: false
index: -1
netname: usbdev_usb_tx_d
}
{
package: ""
struct: logic
signame: usbdev_usb_tx_se0_o
width: 1
type: uni
default: ""
direction: out
conn_type: false
index: -1
netname: usbdev_usb_tx_se0
}
{
package: ""
struct: logic
signame: usbdev_usb_tx_use_d_se0_o
width: 1
type: uni
default: ""
direction: out
conn_type: false
index: -1
netname: usbdev_usb_tx_use_d_se0
}
{
package: ""
struct: logic
signame: usbdev_usb_rx_enable_o
width: 1
type: uni
default: ""
direction: out
conn_type: false
index: -1
netname: usbdev_usb_rx_enable
}
{
package: ""
struct: logic
signame: usbdev_usb_ref_val_o
width: 1
type: uni
default: ""
direction: out
conn_type: false
index: -1
netname: usbdev_usb_ref_val
}
{
package: ""
struct: logic
signame: usbdev_usb_ref_pulse_o
width: 1
type: uni
default: ""
direction: out
conn_type: false
index: -1
netname: usbdev_usb_ref_pulse
}
]
definitions:
[
{
package: ast_pkg
struct: ast_obs_ctrl
signame: ast_obs_ctrl
width: 1
type: uni
end_idx: -1
act: rcv
suffix: ""
default: ast_pkg::AST_OBS_CTRL_DEFAULT
}
{
package: prim_ram_1p_pkg
struct: ram_1p_cfg
signame: ast_ram_1p_cfg
width: 1
type: uni
end_idx: -1
act: rcv
suffix: ""
default: prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT
}
{
package: prim_ram_2p_pkg
struct: ram_2p_cfg
signame: ast_ram_2p_cfg
width: 1
type: uni
end_idx: -1
act: rcv
suffix: ""
default: prim_ram_2p_pkg::RAM_2P_CFG_DEFAULT
}
{
package: prim_rom_pkg
struct: rom_cfg
signame: ast_rom_cfg
width: 1
type: uni
end_idx: -1
act: rcv
suffix: ""
default: prim_rom_pkg::ROM_CFG_DEFAULT
}
{
package: alert_pkg
struct: alert_crashdump
signame: alert_handler_crashdump
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: alert_pkg::ALERT_CRASHDUMP_DEFAULT
}
{
package: prim_esc_pkg
struct: esc_rx
signame: alert_handler_esc_rx
width: 4
type: uni
end_idx: -1
act: rcv
suffix: ""
default: prim_esc_pkg::ESC_RX_DEFAULT
}
{
package: prim_esc_pkg
struct: esc_tx
signame: alert_handler_esc_tx
width: 4
type: uni
end_idx: -1
act: req
suffix: ""
default: prim_esc_pkg::ESC_TX_DEFAULT
}
{
package: ""
struct: logic
signame: aon_timer_aon_nmi_wdog_timer_bark
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: 1'b0
}
{
package: csrng_pkg
struct: csrng_req
signame: csrng_csrng_cmd_req
width: 2
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: csrng_pkg::CSRNG_REQ_DEFAULT
}
{
package: csrng_pkg
struct: csrng_rsp
signame: csrng_csrng_cmd_rsp
width: 2
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: entropy_src_pkg
struct: entropy_src_hw_if_req
signame: csrng_entropy_src_hw_if_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: entropy_src_pkg
struct: entropy_src_hw_if_rsp
signame: csrng_entropy_src_hw_if_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT
}
{
package: entropy_src_pkg
struct: cs_aes_halt_req
signame: csrng_cs_aes_halt_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: entropy_src_pkg::CS_AES_HALT_REQ_DEFAULT
}
{
package: entropy_src_pkg
struct: cs_aes_halt_rsp
signame: csrng_cs_aes_halt_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: flash_ctrl_pkg
struct: keymgr_flash
signame: flash_ctrl_keymgr
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT
}
{
package: otp_ctrl_pkg
struct: flash_otp_key_req
signame: flash_ctrl_otp_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: otp_ctrl_pkg
struct: flash_otp_key_rsp
signame: flash_ctrl_otp_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT
}
{
package: lc_ctrl_pkg
struct: lc_flash_rma_seed
signame: flash_ctrl_rma_seed
width: 1
type: uni
end_idx: -1
act: rcv
suffix: ""
default: lc_ctrl_pkg::LC_FLASH_RMA_SEED_DEFAULT
}
{
package: otp_ctrl_pkg
struct: sram_otp_key_req
signame: otp_ctrl_sram_otp_key_req
width: 3
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: "'0"
}
{
package: otp_ctrl_pkg
struct: sram_otp_key_rsp
signame: otp_ctrl_sram_otp_key_rsp
width: 3
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: pwrmgr_pkg
struct: pwr_flash
signame: pwrmgr_aon_pwr_flash
width: 1
type: uni
end_idx: -1
act: rcv
suffix: ""
default: pwrmgr_pkg::PWR_FLASH_DEFAULT
}
{
package: pwrmgr_pkg
struct: pwr_rst_req
signame: pwrmgr_aon_pwr_rst_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: pwrmgr_pkg
struct: pwr_rst_rsp
signame: pwrmgr_aon_pwr_rst_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: pwrmgr_pkg::PWR_RST_RSP_DEFAULT
}
{
package: pwrmgr_pkg
struct: pwr_clk_req
signame: pwrmgr_aon_pwr_clk_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: pwrmgr_pkg
struct: pwr_clk_rsp
signame: pwrmgr_aon_pwr_clk_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: pwrmgr_pkg::PWR_CLK_RSP_DEFAULT
}
{
package: pwrmgr_pkg
struct: pwr_otp_req
signame: pwrmgr_aon_pwr_otp_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: pwrmgr_pkg
struct: pwr_otp_rsp
signame: pwrmgr_aon_pwr_otp_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: pwrmgr_pkg::PWR_OTP_RSP_DEFAULT
}
{
package: pwrmgr_pkg
struct: pwr_lc_req
signame: pwrmgr_aon_pwr_lc_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: pwrmgr_pkg
struct: pwr_lc_rsp
signame: pwrmgr_aon_pwr_lc_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: pwrmgr_pkg::PWR_LC_RSP_DEFAULT
}
{
package: ""
struct: logic
signame: pwrmgr_aon_strap
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: "'0"
}
{
package: ""
struct: logic
signame: pwrmgr_aon_low_power
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: "'0"
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: pwrmgr_aon_fetch_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::LC_TX_DEFAULT
}
{
package: rom_ctrl_pkg
struct: pwrmgr_data
signame: rom_ctrl_pwrmgr_data
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: rom_ctrl_pkg::PWRMGR_DATA_DEFAULT
}
{
package: rom_ctrl_pkg
struct: keymgr_data
signame: rom_ctrl_keymgr_data
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: rom_ctrl_pkg::KEYMGR_DATA_DEFAULT
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_flash_rma_req
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: flash_ctrl_rma_ack
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::LC_TX_DEFAULT
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: otbn_lc_rma_ack
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: ""
struct: logic
signame: usbdev_usb_dp_pullup
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: "'0"
}
{
package: ""
struct: logic
signame: usbdev_usb_dn_pullup
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: "'0"
}
{
package: ""
struct: logic
signame: usbdev_usb_aon_suspend_req
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: "'0"
}
{
package: ""
struct: logic
signame: usbdev_usb_aon_wake_ack
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: "'0"
}
{
package: ""
struct: logic
signame: usbdev_usb_aon_bus_reset
width: 1
type: uni
end_idx: -1
act: rcv
suffix: ""
default: "'0"
}
{
package: ""
struct: logic
signame: usbdev_usb_aon_sense_lost
width: 1
type: uni
end_idx: -1
act: rcv
suffix: ""
default: "'0"
}
{
package: ""
struct: logic
signame: pinmux_aon_usbdev_wake_detect_active
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: 1'b0
}
{
package: edn_pkg
struct: edn_req
signame: edn0_edn_req
width: 8
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: "'0"
}
{
package: edn_pkg
struct: edn_rsp
signame: edn0_edn_rsp
width: 8
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: edn_pkg
struct: edn_req
signame: edn1_edn_req
width: 8
type: req_rsp
end_idx: 1
act: rsp
suffix: req
default: "'0"
}
{
package: edn_pkg
struct: edn_rsp
signame: edn1_edn_rsp
width: 8
type: req_rsp
end_idx: 1
act: rsp
suffix: rsp
default: ""
}
{
package: otp_ctrl_pkg
struct: otbn_otp_key_req
signame: otp_ctrl_otbn_otp_key_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: "'0"
}
{
package: otp_ctrl_pkg
struct: otbn_otp_key_rsp
signame: otp_ctrl_otbn_otp_key_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: otp_ctrl_pkg
struct: otp_keymgr_key
signame: otp_ctrl_otp_keymgr_key
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: "'0"
}
{
package: keymgr_pkg
struct: hw_key_req
signame: keymgr_aes_key
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: keymgr_pkg::HW_KEY_REQ_DEFAULT
}
{
package: keymgr_pkg
struct: hw_key_req
signame: keymgr_kmac_key
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: keymgr_pkg::HW_KEY_REQ_DEFAULT
}
{
package: keymgr_pkg
struct: otbn_key_req
signame: keymgr_otbn_key
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: keymgr_pkg::OTBN_KEY_REQ_DEFAULT
}
{
package: kmac_pkg
struct: app_req
signame: kmac_app_req
width: 3
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: kmac_pkg::APP_REQ_DEFAULT
}
{
package: kmac_pkg
struct: app_rsp
signame: kmac_app_rsp
width: 3
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: ""
struct: logic
signame: kmac_en_masking
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: "'0"
}
{
package: prim_mubi_pkg
struct: mubi4
signame: clkmgr_aon_idle
width: 4
type: uni
end_idx: -1
act: rcv
suffix: ""
default: prim_mubi_pkg::MUBI4_DEFAULT
}
{
package: jtag_pkg
struct: jtag_req
signame: pinmux_aon_lc_jtag_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: jtag_pkg
struct: jtag_rsp
signame: pinmux_aon_lc_jtag_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: jtag_pkg::JTAG_RSP_DEFAULT
}
{
package: jtag_pkg
struct: jtag_req
signame: pinmux_aon_rv_jtag_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: jtag_pkg
struct: jtag_rsp
signame: pinmux_aon_rv_jtag_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: jtag_pkg::JTAG_RSP_DEFAULT
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: pinmux_aon_pinmux_hw_debug_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: otp_ctrl_pkg
struct: otp_lc_data
signame: otp_ctrl_otp_lc_data
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: "'0"
}
{
package: otp_ctrl_pkg
struct: lc_otp_program_req
signame: lc_ctrl_lc_otp_program_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: otp_ctrl_pkg
struct: lc_otp_program_rsp
signame: lc_ctrl_lc_otp_program_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: "'0"
}
{
package: otp_ctrl_pkg
struct: lc_otp_vendor_test_req
signame: lc_ctrl_lc_otp_vendor_test_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: otp_ctrl_pkg
struct: lc_otp_vendor_test_rsp
signame: lc_ctrl_lc_otp_vendor_test_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: "'0"
}
{
package: lc_ctrl_pkg
struct: lc_keymgr_div
signame: lc_ctrl_lc_keymgr_div
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: "'0"
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_dft_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_nvm_debug_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_hw_debug_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_cpu_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_keymgr_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_escalate_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_check_byp_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_clk_byp_req
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_clk_byp_ack
width: 1
type: uni
end_idx: -1
act: rcv
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_creator_seed_sw_rw_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_owner_seed_sw_rw_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_iso_part_sw_rd_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_iso_part_sw_wr_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_seed_hw_rd_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: ""
struct: logic
signame: rv_plic_msip
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: "'0"
}
{
package: ""
struct: logic
signame: rv_plic_irq
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: "'0"
}
{
package: ""
struct: logic [rv_dm_reg_pkg::NrHarts-1:0]
signame: rv_dm_debug_req
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: "'0"
}
{
package: rv_core_ibex_pkg
struct: cpu_crash_dump
signame: rv_core_ibex_crash_dump
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: rv_core_ibex_pkg::CPU_CRASH_DUMP_DEFAULT
}
{
package: pwrmgr_pkg
struct: pwr_cpu
signame: rv_core_ibex_pwrmgr
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: pwrmgr_pkg::PWR_CPU_DEFAULT
}
{
package: spi_device_pkg
struct: passthrough_req
signame: spi_device_passthrough_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: spi_device_pkg
struct: passthrough_rsp
signame: spi_device_passthrough_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: spi_device_pkg::PASSTHROUGH_RSP_DEFAULT
}
{
package: ""
struct: logic
signame: rv_dm_ndmreset_req
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: "'0"
}
{
package: prim_mubi_pkg
struct: mubi4
signame: rstmgr_aon_sw_rst_req
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: prim_mubi_pkg::MUBI4_DEFAULT
}
{
package: ""
struct: logic
signame: pwrmgr_aon_wakeups
width: 6
type: uni
end_idx: -1
act: rcv
suffix: ""
default: "'0"
}
{
package: ""
struct: logic
signame: pwrmgr_aon_rstreqs
width: 2
type: uni
end_idx: -1
act: rcv
suffix: ""
default: "'0"
}
{
package: tlul_pkg
struct: tl_h2d
signame: main_tl_rv_core_ibex__corei_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: main_tl_rv_core_ibex__corei_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: main_tl_rv_core_ibex__cored_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: main_tl_rv_core_ibex__cored_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: main_tl_rv_dm__sba_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: main_tl_rv_dm__sba_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: rv_dm_regs_tl_d_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: rv_dm_regs_tl_d_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: rv_dm_mem_tl_d_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: rv_dm_mem_tl_d_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: rom_ctrl_rom_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: rom_ctrl_rom_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: rom_ctrl_regs_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: rom_ctrl_regs_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: main_tl_peri_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: main_tl_peri_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: tlul_pkg::TL_D2H_DEFAULT
}
{
package: tlul_pkg
struct: tl_h2d
signame: spi_host0_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: spi_host0_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: spi_host1_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: spi_host1_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: usbdev_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: usbdev_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: flash_ctrl_core_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: flash_ctrl_core_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: flash_ctrl_prim_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: flash_ctrl_prim_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: flash_ctrl_mem_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: flash_ctrl_mem_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: hmac_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: hmac_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: kmac_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: kmac_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: aes_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: aes_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: entropy_src_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: entropy_src_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: csrng_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: csrng_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: edn0_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: edn0_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: edn1_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: edn1_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: rv_plic_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: rv_plic_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: otbn_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: otbn_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: keymgr_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: keymgr_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: rv_core_ibex_cfg_tl_d_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: rv_core_ibex_cfg_tl_d_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: sram_ctrl_main_regs_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: sram_ctrl_main_regs_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: sram_ctrl_main_ram_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: sram_ctrl_main_ram_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: uart0_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: uart0_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: uart1_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: uart1_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: uart2_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: uart2_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: uart3_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: uart3_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: i2c0_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: i2c0_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: i2c1_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: i2c1_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: i2c2_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: i2c2_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: pattgen_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: pattgen_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: pwm_aon_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: pwm_aon_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: gpio_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: gpio_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: spi_device_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: spi_device_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: rv_timer_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: rv_timer_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: pwrmgr_aon_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: pwrmgr_aon_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: rstmgr_aon_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: rstmgr_aon_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: clkmgr_aon_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: clkmgr_aon_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: pinmux_aon_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: pinmux_aon_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: otp_ctrl_core_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: otp_ctrl_core_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: otp_ctrl_prim_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: otp_ctrl_prim_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: lc_ctrl_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: lc_ctrl_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: sensor_ctrl_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: sensor_ctrl_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: alert_handler_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: alert_handler_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: sram_ctrl_ret_aon_regs_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: sram_ctrl_ret_aon_regs_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: sram_ctrl_ret_aon_ram_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: sram_ctrl_ret_aon_ram_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: aon_timer_aon_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: aon_timer_aon_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: sysrst_ctrl_aon_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: sysrst_ctrl_aon_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: adc_ctrl_aon_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: tlul_pkg::TL_H2D_DEFAULT
}
{
package: tlul_pkg
struct: tl_d2h
signame: adc_ctrl_aon_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: clkmgr_pkg
struct: clkmgr_out
signame: clkmgr_aon_clocks
width: 1
type: uni
end_idx: -1
default: ""
}
{
package: clkmgr_pkg
struct: clkmgr_cg_en
signame: clkmgr_aon_cg_en
width: 1
type: uni
end_idx: -1
default: ""
}
{
package: rstmgr_pkg
struct: rstmgr_out
signame: rstmgr_aon_resets
width: 1
type: uni
end_idx: -1
default: ""
}
{
package: rstmgr_pkg
struct: rstmgr_rst_en
signame: rstmgr_aon_rst_en
width: 1
type: uni
end_idx: -1
default: ""
}
{
package: ""
struct: logic
signame: rv_core_ibex_irq_timer
width: 1
type: uni
end_idx: -1
default: ""
}
{
package: ""
struct: logic
signame: rv_core_ibex_hart_id
width: 32
type: uni
end_idx: -1
default: ""
}
{
package: ""
struct: logic
signame: rv_core_ibex_boot_addr
width: 32
type: uni
end_idx: -1
default: ""
}
{
package: jtag_pkg
struct: jtag_req
signame: pinmux_aon_dft_jtag_req
width: 1
type: req_rsp
end_idx: -1
default: ""
}
{
package: jtag_pkg
struct: jtag_rsp
signame: pinmux_aon_dft_jtag_rsp
width: 1
type: req_rsp
end_idx: -1
default: ""
}
{
package: otp_ctrl_part_pkg
struct: otp_hw_cfg
signame: otp_ctrl_otp_hw_cfg
width: 1
type: uni
end_idx: -1
default: "'0"
}
{
package: prim_mubi_pkg
struct: mubi8
signame: csrng_otp_en_csrng_sw_app_read
width: 1
type: uni
end_idx: -1
default: ""
}
{
package: prim_mubi_pkg
struct: mubi8
signame: entropy_src_otp_en_entropy_src_fw_read
width: 1
type: uni
end_idx: -1
default: ""
}
{
package: prim_mubi_pkg
struct: mubi8
signame: entropy_src_otp_en_entropy_src_fw_over
width: 1
type: uni
end_idx: -1
default: ""
}
{
package: otp_ctrl_pkg
struct: otp_device_id
signame: lc_ctrl_otp_device_id
width: 1
type: uni
end_idx: -1
default: "'0"
}
{
package: otp_ctrl_pkg
struct: otp_manuf_state
signame: lc_ctrl_otp_manuf_state
width: 1
type: uni
end_idx: -1
default: "'0"
}
{
package: otp_ctrl_pkg
struct: otp_device_id
signame: keymgr_otp_device_id
width: 1
type: uni
end_idx: -1
default: ""
}
{
package: prim_mubi_pkg
struct: mubi8
signame: sram_ctrl_main_otp_en_sram_ifetch
width: 1
type: uni
end_idx: -1
default: prim_mubi_pkg::MuBi8False
}
]
}
}