| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| { |
| // Name of the sim cfg - typically same as the name of the DUT. |
| name: csrng |
| |
| // Top level dut name (sv module). |
| dut: csrng |
| |
| // Top level testbench name (sv module). |
| tb: tb |
| |
| // Simulator used to sign off this block |
| tool: xcelium |
| |
| // Fusesoc core file used for building the file list. |
| fusesoc_core: lowrisc:dv:csrng_sim:0.1 |
| |
| // Testplan hjson file. |
| testplan: "{proj_root}/hw/ip/csrng/data/csrng_testplan.hjson" |
| |
| // RAL spec - used to generate the RAL model. |
| ral_spec: "{proj_root}/hw/ip/csrng/data/csrng.hjson" |
| |
| // Import additional common sim cfg files. |
| // TODO: remove imported cfgs that do not apply. |
| import_cfgs: [// Project wide common sim cfg file |
| "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", |
| // Enable C compilation of AES model for DPI-C |
| "{proj_root}/hw/ip/aes/model/aes_model_sim_opts.hjson", |
| // Common CIP test lists |
| "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", |
| "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", |
| "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", |
| "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", |
| "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", |
| "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"] |
| |
| // Add additional tops for simulation. |
| sim_tops: ["csrng_bind", "csrng_cov_bind", "sec_cm_prim_onehot_check_bind"] |
| |
| // Default iterations for all tests - each test entry can override this. |
| reseed: 50 |
| |
| // Update all builds to add options specific to AES C model compilation. |
| en_build_modes: ["{tool}_aes_model_build_opts"] |
| |
| xcelium_cov_refine_files: ["{proj_root}/hw/ip/csrng/dv/cov/csrng_v2s_exclusions.vRefine"] |
| |
| // Default UVM test and seq class name. |
| uvm_test: csrng_base_test |
| uvm_test_seq: csrng_base_vseq |
| |
| run_opts: ["+cdc_instrumentation_enabled=1"] |
| |
| // List of test specifications. |
| tests: [ |
| { |
| name: csrng_smoke |
| uvm_test: csrng_smoke_test |
| uvm_test_seq: csrng_smoke_vseq |
| } |
| |
| { |
| name: csrng_cmds |
| uvm_test: csrng_cmds_test |
| uvm_test_seq: csrng_cmds_vseq |
| } |
| |
| { |
| name: csrng_stress_all |
| uvm_test: csrng_stress_all_test |
| uvm_test_seq: csrng_stress_all_vseq |
| } |
| |
| { |
| name: csrng_intr |
| reseed: 200 |
| uvm_test: csrng_intr_test |
| uvm_test_seq: csrng_intr_vseq |
| } |
| |
| { |
| name: csrng_alert |
| reseed: 500 |
| uvm_test: csrng_alert_test |
| uvm_test_seq: csrng_alert_vseq |
| } |
| |
| { |
| name: csrng_err |
| reseed: 500 |
| uvm_test: csrng_intr_test |
| uvm_test_seq: csrng_err_vseq |
| } |
| |
| { |
| name: csrng_regwen |
| uvm_test: csrng_regwen_test |
| uvm_test_seq: csrng_regwen_vseq |
| } |
| |
| // TODO: add more tests here |
| ] |
| |
| // List of regressions. |
| regressions: [ |
| { |
| name: smoke |
| tests: ["csrng_smoke"] |
| } |
| ] |
| } |