[clkmgr, top] - Add clk_aon_i, and rename other clocks - renamed clk_fixed_i to clk_io_i - renamed clk_usb_48mhz_i to clk_usb_i - Renaming is NOT done to individual modules, only clkmgr/rstmgr/top - clkmgr/rstmgr are not yet making use of clk_aon_i in this commit Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/clkmgr/data/clkmgr.hjson.tpl b/hw/ip/clkmgr/data/clkmgr.hjson.tpl index b9284d9..76d5369 100644 --- a/hw/ip/clkmgr/data/clkmgr.hjson.tpl +++ b/hw/ip/clkmgr/data/clkmgr.hjson.tpl
@@ -24,7 +24,9 @@ reset_primary: "rst_ni", other_reset_list: [ % for src in srcs: + % if src['aon'] == 'no': "rst_${src['name']}_ni" + % endif % endfor ] bus_device: "tlul",
diff --git a/hw/ip/clkmgr/data/clkmgr.sv.tpl b/hw/ip/clkmgr/data/clkmgr.sv.tpl index 0dcff9c..176c3d4 100644 --- a/hw/ip/clkmgr/data/clkmgr.sv.tpl +++ b/hw/ip/clkmgr/data/clkmgr.sv.tpl
@@ -12,12 +12,18 @@ %> module clkmgr import clkmgr_pkg::*; ( - // Primary module clocks + // Primary module control clocks and resets + // This drives the register interface input clk_i, input rst_ni, + + // System clocks and resets + // These are the source clocks for the system % for src in srcs: input clk_${src['name']}_i, + % if src['aon'] == 'no': input rst_${src['name']}_ni, + % endif % endfor // Bus Interface @@ -67,29 +73,29 @@ logic async_roots_en; logic roots_en_q2, roots_en_q1, roots_en_d; -% for src in srcs: - logic clk_${src['name']}_root; - logic clk_${src['name']}_en; +% for src in rg_srcs: + logic clk_${src}_root; + logic clk_${src}_en; % endfor -% for src in srcs: - prim_clock_gating_sync i_${src['name']}_cg ( - .clk_i(clk_${src['name']}_i), - .rst_ni(rst_${src['name']}_ni), +% for src in rg_srcs: + prim_clock_gating_sync i_${src}_cg ( + .clk_i(clk_${src}_i), + .rst_ni(rst_${src}_ni), .test_en_i(dft_i.test_en), .async_en_i(pwr_i.ip_clk_en), - .en_o(clk_${src['name']}_en), - .clk_o(clk_${src['name']}_root) + .en_o(clk_${src}_en), + .clk_o(clk_${src}_root) ); % endfor // an async OR of all the synchronized enables assign async_roots_en = -% for src in srcs: +% for src in rg_srcs: % if loop.last: - clk_${src['name']}_en; + clk_${src}_en; % else: - clk_${src['name']}_en | + clk_${src}_en | % endif % endfor
diff --git a/hw/ip/rstmgr/data/rstmgr.hjson b/hw/ip/rstmgr/data/rstmgr.hjson index b73212c..8789b64 100644 --- a/hw/ip/rstmgr/data/rstmgr.hjson +++ b/hw/ip/rstmgr/data/rstmgr.hjson
@@ -11,7 +11,7 @@ clock_primary: "clk_i", other_clock_list: [ "clk_main_i", - "clk_fixed_i", + "clk_io_i", "clk_usb_i" ], bus_device: "tlul",
diff --git a/hw/ip/rstmgr/rtl/rstmgr.sv b/hw/ip/rstmgr/rtl/rstmgr.sv index 8ad5aad..21f1d8c 100644 --- a/hw/ip/rstmgr/rtl/rstmgr.sv +++ b/hw/ip/rstmgr/rtl/rstmgr.sv
@@ -14,7 +14,7 @@ input clk_i, input rst_ni, input clk_main_i, - input clk_fixed_i, + input clk_io_i, input clk_usb_i, // Bus Interface @@ -135,7 +135,7 @@ .Width(1), .ResetValue(0) ) i_lc ( - .clk_i(clk_fixed_i), + .clk_i(clk_io_i), .rst_ni(rst_lc_src_n[ALWAYS_ON_SEL]), .d(1'b1), .q(resets_o.rst_lc_n) @@ -154,18 +154,18 @@ prim_flop_2sync #( .Width(1), .ResetValue(0) - ) i_sys_fixed ( - .clk_i(clk_fixed_i), + ) i_sys_io ( + .clk_i(clk_io_i), .rst_ni(rst_sys_src_n[ALWAYS_ON_SEL]), .d(1'b1), - .q(resets_o.rst_sys_fixed_n) + .q(resets_o.rst_sys_io_n) ); prim_flop_2sync #( .Width(1), .ResetValue(0) ) i_spi_device ( - .clk_i(clk_fixed_i), + .clk_i(clk_io_i), .rst_ni(rst_sys_src_n[ALWAYS_ON_SEL]), .d(reg2hw.rst_spi_device_n.q), .q(resets_o.rst_spi_device_n)
diff --git a/hw/ip/rstmgr/rtl/rstmgr_pkg.sv b/hw/ip/rstmgr/rtl/rstmgr_pkg.sv index 6f162f9..add2efa 100644 --- a/hw/ip/rstmgr/rtl/rstmgr_pkg.sv +++ b/hw/ip/rstmgr/rtl/rstmgr_pkg.sv
@@ -30,7 +30,7 @@ typedef struct packed { logic rst_por_n; logic rst_lc_n; - logic rst_sys_fixed_n; + logic rst_sys_io_n; logic rst_sys_n; logic rst_spi_device_n; logic rst_usb_n;
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 7ac0cd4..9296bf7 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -20,16 +20,24 @@ [ { name: main + aon: no freq: "100000000" } { - name: fixed + name: io + aon: no freq: "100000000" } { - name: usb_48mhz + name: usb + aon: no freq: "48000000" } + { + name: aon + aon: yes + freq: "200000" + } ] groups: [ @@ -40,9 +48,10 @@ unique: no clocks: { - clk_fixed_i: fixed + clk_io_i: io clk_i: main - clk_usb_48mhz_i: usb_48mhz + clk_usb_i: usb + clk_aon_i: aon } } { @@ -64,7 +73,7 @@ clocks: { clk_main_infra: main - clk_fixed_infra: fixed + clk_io_infra: io } } { @@ -74,7 +83,7 @@ unique: no clocks: { - clk_fixed_secure: fixed + clk_io_secure: io clk_main_secure: main } } @@ -85,8 +94,8 @@ unique: no clocks: { - clk_fixed_peri: fixed - clk_usb_48mhz_peri: usb_48mhz + clk_io_peri: io + clk_usb_peri: usb } } { @@ -96,7 +105,7 @@ unique: no clocks: { - clk_fixed_timers: fixed + clk_io_timers: io } } { @@ -121,13 +130,13 @@ name: por type: gen root: lc - clk: fixed + clk: io } { name: lc type: gen root: lc - clk: fixed + clk: io } { name: sys @@ -136,16 +145,16 @@ clk: main } { - name: sys_fixed + name: sys_io type: gen root: sys - clk: fixed + clk: io } { name: spi_device type: gen root: sys - clk: fixed + clk: io sw: 1 } { @@ -164,17 +173,17 @@ type: uart clock_srcs: { - clk_i: fixed + clk_i: io } reset_connections: { - rst_ni: sys_fixed + rst_ni: sys_io } base_addr: 0x40000000 clock_group: secure clock_connections: { - clk_i: clkmgr_clocks.clk_fixed_secure + clk_i: clkmgr_clocks.clk_io_secure } size: 0x1000 bus_device: tlul @@ -303,17 +312,17 @@ type: gpio clock_srcs: { - clk_i: fixed + clk_i: io } clock_group: peri reset_connections: { - rst_ni: sys_fixed + rst_ni: sys_io } base_addr: 0x40010000 clock_connections: { - clk_i: clkmgr_clocks.clk_fixed_peri + clk_i: clkmgr_clocks.clk_io_peri } size: 0x1000 bus_device: tlul @@ -351,7 +360,7 @@ type: spi_device clock_srcs: { - clk_i: fixed + clk_i: io } clock_group: peri reset_connections: @@ -361,7 +370,7 @@ base_addr: 0x40020000 clock_connections: { - clk_i: clkmgr_clocks.clk_fixed_peri + clk_i: clkmgr_clocks.clk_io_peri } size: 0x1000 bus_device: tlul @@ -591,17 +600,17 @@ type: rv_timer clock_srcs: { - clk_i: fixed + clk_i: io } clock_group: timers reset_connections: { - rst_ni: sys_fixed + rst_ni: sys_io } base_addr: 0x40080000 clock_connections: { - clk_i: clkmgr_clocks.clk_fixed_timers + clk_i: clkmgr_clocks.clk_io_timers } size: 0x1000 bus_device: tlul @@ -928,8 +937,8 @@ type: pwrmgr clock_srcs: { - clk_i: fixed - clk_slow_i: fixed + clk_i: io + clk_slow_i: io } clock_group: powerup reset_connections: @@ -940,8 +949,8 @@ base_addr: 0x400A0000 clock_connections: { - clk_i: clk_fixed_i - clk_slow_i: clk_fixed_i + clk_i: clk_io_i + clk_slow_i: clk_io_i } size: 0x1000 bus_device: tlul @@ -1053,10 +1062,10 @@ type: rstmgr clock_srcs: { - clk_i: fixed + clk_i: io clk_main_i: main - clk_fixed_i: fixed - clk_usb_i: usb_48mhz + clk_io_i: io + clk_usb_i: usb } clock_group: powerup reset_connections: @@ -1066,10 +1075,10 @@ base_addr: 0x400B0000 clock_connections: { - clk_i: clk_fixed_i + clk_i: clk_io_i clk_main_i: clk_i - clk_fixed_i: clk_fixed_i - clk_usb_i: clk_usb_48mhz_i + clk_io_i: clk_io_i + clk_usb_i: clk_usb_i } size: 0x1000 bus_device: tlul @@ -1140,27 +1149,29 @@ type: clkmgr clock_srcs: { - clk_i: fixed + clk_i: io clk_main_i: main - clk_fixed_i: fixed - clk_usb_48mhz_i: usb_48mhz + clk_io_i: io + clk_usb_i: usb + clk_aon_i: aon } clock_group: powerup reset_connections: { rst_ni: por rst_main_ni: por - rst_fixed_ni: por - rst_usb_48mhz_ni: por + rst_io_ni: por + rst_usb_ni: por } base_addr: 0x400C0000 generated: "true" clock_connections: { - clk_i: clk_fixed_i + clk_i: clk_io_i clk_main_i: clk_i - clk_fixed_i: clk_fixed_i - clk_usb_48mhz_i: clk_usb_48mhz_i + clk_io_i: clk_io_i + clk_usb_i: clk_usb_i + clk_aon_i: clk_aon_i } size: 0x1000 bus_device: tlul @@ -1297,20 +1308,20 @@ type: usbdev clock_srcs: { - clk_i: fixed - clk_usb_48mhz_i: usb_48mhz + clk_i: io + clk_usb_48mhz_i: usb } clock_group: peri reset_connections: { - rst_ni: sys_fixed + rst_ni: sys_io rst_usb_48mhz_ni: usb } base_addr: 0x40150000 clock_connections: { - clk_i: clkmgr_clocks.clk_fixed_peri - clk_usb_48mhz_i: clkmgr_clocks.clk_usb_48mhz_peri + clk_i: clkmgr_clocks.clk_io_peri + clk_usb_48mhz_i: clkmgr_clocks.clk_usb_peri } size: 0x1000 bus_device: tlul @@ -1672,19 +1683,19 @@ clock_srcs: { clk_main_i: main - clk_fixed_i: fixed + clk_fixed_i: io } clock_group: infra reset: rst_main_ni reset_connections: { rst_main_ni: sys - rst_fixed_ni: sys_fixed + rst_fixed_ni: sys_io } clock_connections: { clk_main_i: clkmgr_clocks.clk_main_infra - clk_fixed_i: clkmgr_clocks.clk_fixed_infra + clk_fixed_i: clkmgr_clocks.clk_io_infra } connections: { @@ -2012,17 +2023,17 @@ name: peri clock_srcs: { - clk_peri_i: fixed + clk_peri_i: io } clock_group: infra reset: rst_peri_ni reset_connections: { - rst_peri_ni: sys_fixed + rst_peri_ni: sys_io } clock_connections: { - clk_peri_i: clkmgr_clocks.clk_fixed_infra + clk_peri_i: clkmgr_clocks.clk_io_infra } connections: { @@ -3133,7 +3144,7 @@ por: rstmgr_resets.rst_por_n lc: rstmgr_resets.rst_lc_n sys: rstmgr_resets.rst_sys_n - sys_fixed: rstmgr_resets.rst_sys_fixed_n + sys_io: rstmgr_resets.rst_sys_io_n spi_device: rstmgr_resets.rst_spi_device_n usb: rstmgr_resets.rst_usb_n }
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index f1d2097..bb263fc 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -20,10 +20,17 @@ ext: "", // ext is a port of the clock name }, + // Clock Source attributes + // name: Name of group. + // aon: Whether the clock is free running all the time. + // If it is, the clock is not hanlded by clkmgr. + // freq: Absolute frequency of clk in Hz + srcs: [ - { name: "main", freq: "100000000" } - { name: "fixed", freq: "100000000" } - { name: "usb_48mhz", freq: "48000000" } + { name: "main", aon: "no", freq: "100000000" } + { name: "io", aon: "no", freq: "100000000" } + { name: "usb", aon: "no", freq: "48000000" } + { name: "aon", aon: "yes", freq: "200000" } ], // Clock Group attributes @@ -44,7 +51,7 @@ // "no" - the group is controlled as one single unit // // The powerup and proc groups are unique. - // The powerup group of clocks do not need through the clock + // The powerup group of clocks do not feed through the clock // controller as they manage clock controller behavior // The proc group is not peripheral, and direclty hardwired @@ -80,11 +87,11 @@ // resets: [ { name: "rst_ni", type: "por" } - { name: "por", type: "gen", root: "lc", clk: "fixed" } - { name: "lc", type: "gen", root: "lc", clk: "fixed" } - { name: "sys", type: "gen", root: "sys", clk: "main" } - { name: "sys_fixed", type: "gen", root: "sys", clk: "fixed" } - { name: "spi_device", type: "gen", root: "sys", clk: "fixed", sw: 1} + { name: "por", type: "gen", root: "lc", clk: "io" } + { name: "lc", type: "gen", root: "lc", clk: "io" } + { name: "sys", type: "gen", root: "sys", clk: "main"} + { name: "sys_io", type: "gen", root: "sys", clk: "io" } + { name: "spi_device", type: "gen", root: "sys", clk: "io", sw: 1} { name: "usb", type: "gen", root: "sys", clk: "usb", sw: 1} ] @@ -102,26 +109,26 @@ // clock connections defines the port to top level clock connection // the ip.hjson will declare the clock port names // If none are defined at ip.hjson, clk_i is used by default - clock_srcs: {clk_i: "fixed"}, + clock_srcs: {clk_i: "io"}, // reset connections defines the port to top level reset connection // the ip.hjson will declare the reset port names // If none are defined at ip.hjson, rst_ni is used by default - reset_connections: {rst_ni: "sys_fixed"}, + reset_connections: {rst_ni: "sys_io"}, base_addr: "0x40000000", }, { name: "gpio", type: "gpio", - clock_srcs: {clk_i: "fixed"}, + clock_srcs: {clk_i: "io"}, clock_group: "peri", - reset_connections: {rst_ni: "sys_fixed"}, + reset_connections: {rst_ni: "sys_io"}, base_addr: "0x40010000", } { name: "spi_device", type: "spi_device", - clock_srcs: {clk_i: "fixed"}, + clock_srcs: {clk_i: "io"}, clock_group: "peri", reset_connections: {rst_ni: "spi_device"}, base_addr: "0x40020000", @@ -135,9 +142,9 @@ }, { name: "rv_timer", type: "rv_timer", - clock_srcs: {clk_i: "fixed"}, + clock_srcs: {clk_i: "io"}, clock_group: "timers", - reset_connections: {rst_ni: "sys_fixed"}, + reset_connections: {rst_ni: "sys_io"}, base_addr: "0x40080000", }, { name: "aes", @@ -195,7 +202,7 @@ } { name: "pwrmgr", type: "pwrmgr", - clock_srcs: {clk_i: "fixed", clk_slow_i: "fixed"}, + clock_srcs: {clk_i: "io", clk_slow_i: "io"}, clock_group: "powerup", reset_connections: {rst_ni: "por", rst_slow_ni: "por"}, base_addr: "0x400A0000", @@ -203,16 +210,16 @@ }, { name: "rstmgr", type: "rstmgr", - clock_srcs: {clk_i: "fixed", clk_main_i: "main", clk_fixed_i: "fixed", clk_usb_i: "usb_48mhz"}, + clock_srcs: {clk_i: "io", clk_main_i: "main", clk_io_i: "io", clk_usb_i: "usb"}, clock_group: "powerup", reset_connections: {rst_ni: "rst_ni"}, base_addr: "0x400B0000", }, { name: "clkmgr", type: "clkmgr", - clock_srcs: {clk_i: "fixed", clk_main_i: "main", clk_fixed_i: "fixed", clk_usb_48mhz_i: "usb_48mhz"}, + clock_srcs: {clk_i: "io", clk_main_i: "main", clk_io_i: "io", clk_usb_i: "usb", clk_aon_i: "aon"}, clock_group: "powerup", - reset_connections: {rst_ni: "por", rst_main_ni: "por", rst_fixed_ni: "por", rst_usb_48mhz_ni: "por"}, + reset_connections: {rst_ni: "por", rst_main_ni: "por", rst_io_ni: "por", rst_usb_ni: "por"}, base_addr: "0x400C0000", generated: "true" }, @@ -227,9 +234,9 @@ } { name: "usbdev", type: "usbdev", - clock_srcs: {clk_i: "fixed", clk_usb_48mhz_i: "usb_48mhz"}, + clock_srcs: {clk_i: "io", clk_usb_48mhz_i: "usb"}, clock_group: "peri", - reset_connections: {rst_ni: "sys_fixed", rst_usb_48mhz_ni: "usb"}, + reset_connections: {rst_ni: "sys_io", rst_usb_48mhz_ni: "usb"}, base_addr: "0x40150000", }, ] @@ -300,16 +307,16 @@ // Assume xbar.hjson is located in the same directory of top.hjson xbar: [ { name: "main", - clock_srcs: {clk_main_i: "main", clk_fixed_i: "fixed"}, + clock_srcs: {clk_main_i: "main", clk_fixed_i: "io"}, clock_group: "infra", reset: "sys", - reset_connections: {rst_main_ni: "sys", rst_fixed_ni: "sys_fixed"} + reset_connections: {rst_main_ni: "sys", rst_fixed_ni: "sys_io"} }, { name: "peri", - clock_srcs: {clk_peri_i: "fixed"}, + clock_srcs: {clk_peri_i: "io"}, clock_group: "infra", - reset: "sys_fixed", - reset_connections: {rst_peri_ni: "sys_fixed"}, + reset: "sys_io", + reset_connections: {rst_peri_ni: "sys_io"}, } ],
diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl index bff227c..c8021c9 100644 --- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl +++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -36,11 +36,14 @@ input clk_i, input rst_ni, - // Fixed clock - input clk_fixed_i, + // Fixed io clock + input clk_io_i, // USB clock - input clk_usb_48mhz_i, + input clk_usb_i, + + // aon clock + input clk_aon_i, // JTAG interface input jtag_tck_i,
diff --git a/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson b/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson index 5868366..3971985 100644 --- a/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson +++ b/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson
@@ -19,14 +19,15 @@ clock_primary: "clk_i", other_clock_list: [ "clk_main_i", - "clk_fixed_i", - "clk_usb_48mhz_i", + "clk_io_i", + "clk_usb_i", + "clk_aon_i", ], reset_primary: "rst_ni", other_reset_list: [ "rst_main_ni" - "rst_fixed_ni" - "rst_usb_48mhz_ni" + "rst_io_ni" + "rst_usb_ni" ] bus_device: "tlul", regwidth: "32", @@ -81,20 +82,20 @@ fields: [ { bits: "0", - name: "CLK_FIXED_PERI_EN", + name: "CLK_IO_PERI_EN", resval: 1, desc: ''' - 0 CLK_FIXED_PERI is disabled. - 1 CLK_FIXED_PERI is enabled. + 0 CLK_IO_PERI is disabled. + 1 CLK_IO_PERI is enabled. ''' } { bits: "1", - name: "CLK_USB_48MHZ_PERI_EN", + name: "CLK_USB_PERI_EN", resval: 1, desc: ''' - 0 CLK_USB_48MHZ_PERI is disabled. - 1 CLK_USB_48MHZ_PERI is enabled. + 0 CLK_USB_PERI is disabled. + 1 CLK_USB_PERI is enabled. ''' } ]
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv index 45cbec7..ca00c89 100644 --- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv +++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
@@ -15,15 +15,20 @@ module clkmgr import clkmgr_pkg::*; ( - // Primary module clocks + // Primary module control clocks and resets + // This drives the register interface input clk_i, input rst_ni, + + // System clocks and resets + // These are the source clocks for the system input clk_main_i, input rst_main_ni, - input clk_fixed_i, - input rst_fixed_ni, - input clk_usb_48mhz_i, - input rst_usb_48mhz_ni, + input clk_io_i, + input rst_io_ni, + input clk_usb_i, + input rst_usb_ni, + input clk_aon_i, // Bus Interface input tlul_pkg::tl_h2d_t tl_i, @@ -74,10 +79,10 @@ logic roots_en_q2, roots_en_q1, roots_en_d; logic clk_main_root; logic clk_main_en; - logic clk_fixed_root; - logic clk_fixed_en; - logic clk_usb_48mhz_root; - logic clk_usb_48mhz_en; + logic clk_io_root; + logic clk_io_en; + logic clk_usb_root; + logic clk_usb_en; prim_clock_gating_sync i_main_cg ( .clk_i(clk_main_i), @@ -87,28 +92,28 @@ .en_o(clk_main_en), .clk_o(clk_main_root) ); - prim_clock_gating_sync i_fixed_cg ( - .clk_i(clk_fixed_i), - .rst_ni(rst_fixed_ni), + prim_clock_gating_sync i_io_cg ( + .clk_i(clk_io_i), + .rst_ni(rst_io_ni), .test_en_i(dft_i.test_en), .async_en_i(pwr_i.ip_clk_en), - .en_o(clk_fixed_en), - .clk_o(clk_fixed_root) + .en_o(clk_io_en), + .clk_o(clk_io_root) ); - prim_clock_gating_sync i_usb_48mhz_cg ( - .clk_i(clk_usb_48mhz_i), - .rst_ni(rst_usb_48mhz_ni), + prim_clock_gating_sync i_usb_cg ( + .clk_i(clk_usb_i), + .rst_ni(rst_usb_ni), .test_en_i(dft_i.test_en), .async_en_i(pwr_i.ip_clk_en), - .en_o(clk_usb_48mhz_en), - .clk_o(clk_usb_48mhz_root) + .en_o(clk_usb_en), + .clk_o(clk_usb_root) ); // an async OR of all the synchronized enables assign async_roots_en = clk_main_en | - clk_fixed_en | - clk_usb_48mhz_en; + clk_io_en | + clk_usb_en; // Sync the OR back into clkmgr domain for feedback to pwrmgr. // Since the signal is combo / converged on the other side, de-bounce @@ -141,10 +146,10 @@ // Clocks with only root gate //////////////////////////////////////////////////// assign clocks_o.clk_main_infra = clk_main_root; - assign clocks_o.clk_fixed_infra = clk_fixed_root; - assign clocks_o.clk_fixed_secure = clk_fixed_root; + assign clocks_o.clk_io_infra = clk_io_root; + assign clocks_o.clk_io_secure = clk_io_root; assign clocks_o.clk_main_secure = clk_main_root; - assign clocks_o.clk_fixed_timers = clk_fixed_root; + assign clocks_o.clk_io_timers = clk_io_root; assign clocks_o.clk_proc_main = clk_main_root; //////////////////////////////////////////////////// @@ -154,39 +159,39 @@ // the rst_ni connection below is incorrect, need to find a proper reset in the sequence to use // if the clkmgr is always on, can use por synced directly // if not, then need to generate something ahead of lc/sys - logic clk_fixed_peri_sw_en; - logic clk_usb_48mhz_peri_sw_en; + logic clk_io_peri_sw_en; + logic clk_usb_peri_sw_en; prim_flop_2sync #( .Width(1) - ) i_clk_fixed_peri_sw_en_sync ( - .clk_i(clk_fixed_i), - .rst_ni(rst_fixed_ni), - .d(reg2hw.clk_enables.clk_fixed_peri_en.q), - .q(clk_fixed_peri_sw_en) + ) i_clk_io_peri_sw_en_sync ( + .clk_i(clk_io_i), + .rst_ni(rst_io_ni), + .d(reg2hw.clk_enables.clk_io_peri_en.q), + .q(clk_io_peri_sw_en) ); - prim_clock_gating i_clk_fixed_peri_cg ( - .clk_i(clk_fixed_i), - .en_i(clk_fixed_peri_sw_en & clk_fixed_en), + prim_clock_gating i_clk_io_peri_cg ( + .clk_i(clk_io_i), + .en_i(clk_io_peri_sw_en & clk_io_en), .test_en_i(dft_i.test_en), - .clk_o(clocks_o.clk_fixed_peri) + .clk_o(clocks_o.clk_io_peri) ); prim_flop_2sync #( .Width(1) - ) i_clk_usb_48mhz_peri_sw_en_sync ( - .clk_i(clk_usb_48mhz_i), - .rst_ni(rst_usb_48mhz_ni), - .d(reg2hw.clk_enables.clk_usb_48mhz_peri_en.q), - .q(clk_usb_48mhz_peri_sw_en) + ) i_clk_usb_peri_sw_en_sync ( + .clk_i(clk_usb_i), + .rst_ni(rst_usb_ni), + .d(reg2hw.clk_enables.clk_usb_peri_en.q), + .q(clk_usb_peri_sw_en) ); - prim_clock_gating i_clk_usb_48mhz_peri_cg ( - .clk_i(clk_usb_48mhz_i), - .en_i(clk_usb_48mhz_peri_sw_en & clk_usb_48mhz_en), + prim_clock_gating i_clk_usb_peri_cg ( + .clk_i(clk_usb_i), + .en_i(clk_usb_peri_sw_en & clk_usb_en), .test_en_i(dft_i.test_en), - .clk_o(clocks_o.clk_usb_48mhz_peri) + .clk_o(clocks_o.clk_usb_peri) );
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv index 09dd868..0b65244 100644 --- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv +++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
@@ -20,13 +20,13 @@ logic clk_main_aes; logic clk_main_hmac; logic clk_main_infra; - logic clk_fixed_infra; - logic clk_fixed_secure; + logic clk_io_infra; + logic clk_io_secure; logic clk_main_secure; - logic clk_fixed_timers; + logic clk_io_timers; logic clk_proc_main; - logic clk_fixed_peri; - logic clk_usb_48mhz_peri; + logic clk_io_peri; + logic clk_usb_peri; } clkmgr_out_t;
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv index 6983b10..b1668c2 100644 --- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv +++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv
@@ -15,10 +15,10 @@ typedef struct packed { struct packed { logic q; - } clk_fixed_peri_en; + } clk_io_peri_en; struct packed { logic q; - } clk_usb_48mhz_peri_en; + } clk_usb_peri_en; } clkmgr_reg2hw_clk_enables_reg_t; typedef struct packed {
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv index 2717958..8a1c418 100644 --- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv +++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv
@@ -71,12 +71,12 @@ // Define SW related signals // Format: <reg>_<field>_{wd|we|qs} // or <reg>_{wd|we|qs} if field == 1 or 0 - logic clk_enables_clk_fixed_peri_en_qs; - logic clk_enables_clk_fixed_peri_en_wd; - logic clk_enables_clk_fixed_peri_en_we; - logic clk_enables_clk_usb_48mhz_peri_en_qs; - logic clk_enables_clk_usb_48mhz_peri_en_wd; - logic clk_enables_clk_usb_48mhz_peri_en_we; + logic clk_enables_clk_io_peri_en_qs; + logic clk_enables_clk_io_peri_en_wd; + logic clk_enables_clk_io_peri_en_we; + logic clk_enables_clk_usb_peri_en_qs; + logic clk_enables_clk_usb_peri_en_wd; + logic clk_enables_clk_usb_peri_en_we; logic clk_hints_clk_main_aes_hint_qs; logic clk_hints_clk_main_aes_hint_wd; logic clk_hints_clk_main_aes_hint_we; @@ -89,18 +89,18 @@ // Register instances // R[clk_enables]: V(False) - // F[clk_fixed_peri_en]: 0:0 + // F[clk_io_peri_en]: 0:0 prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h1) - ) u_clk_enables_clk_fixed_peri_en ( + ) u_clk_enables_clk_io_peri_en ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (clk_enables_clk_fixed_peri_en_we), - .wd (clk_enables_clk_fixed_peri_en_wd), + .we (clk_enables_clk_io_peri_en_we), + .wd (clk_enables_clk_io_peri_en_wd), // from internal hardware .de (1'b0), @@ -108,25 +108,25 @@ // to internal hardware .qe (), - .q (reg2hw.clk_enables.clk_fixed_peri_en.q ), + .q (reg2hw.clk_enables.clk_io_peri_en.q ), // to register interface (read) - .qs (clk_enables_clk_fixed_peri_en_qs) + .qs (clk_enables_clk_io_peri_en_qs) ); - // F[clk_usb_48mhz_peri_en]: 1:1 + // F[clk_usb_peri_en]: 1:1 prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h1) - ) u_clk_enables_clk_usb_48mhz_peri_en ( + ) u_clk_enables_clk_usb_peri_en ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (clk_enables_clk_usb_48mhz_peri_en_we), - .wd (clk_enables_clk_usb_48mhz_peri_en_wd), + .we (clk_enables_clk_usb_peri_en_we), + .wd (clk_enables_clk_usb_peri_en_wd), // from internal hardware .de (1'b0), @@ -134,10 +134,10 @@ // to internal hardware .qe (), - .q (reg2hw.clk_enables.clk_usb_48mhz_peri_en.q ), + .q (reg2hw.clk_enables.clk_usb_peri_en.q ), // to register interface (read) - .qs (clk_enables_clk_usb_48mhz_peri_en_qs) + .qs (clk_enables_clk_usb_peri_en_qs) ); @@ -267,11 +267,11 @@ if (addr_hit[2] && reg_we && (CLKMGR_PERMIT[2] != (CLKMGR_PERMIT[2] & reg_be))) wr_err = 1'b1 ; end - assign clk_enables_clk_fixed_peri_en_we = addr_hit[0] & reg_we & ~wr_err; - assign clk_enables_clk_fixed_peri_en_wd = reg_wdata[0]; + assign clk_enables_clk_io_peri_en_we = addr_hit[0] & reg_we & ~wr_err; + assign clk_enables_clk_io_peri_en_wd = reg_wdata[0]; - assign clk_enables_clk_usb_48mhz_peri_en_we = addr_hit[0] & reg_we & ~wr_err; - assign clk_enables_clk_usb_48mhz_peri_en_wd = reg_wdata[1]; + assign clk_enables_clk_usb_peri_en_we = addr_hit[0] & reg_we & ~wr_err; + assign clk_enables_clk_usb_peri_en_wd = reg_wdata[1]; assign clk_hints_clk_main_aes_hint_we = addr_hit[1] & reg_we & ~wr_err; assign clk_hints_clk_main_aes_hint_wd = reg_wdata[0]; @@ -286,8 +286,8 @@ reg_rdata_next = '0; unique case (1'b1) addr_hit[0]: begin - reg_rdata_next[0] = clk_enables_clk_fixed_peri_en_qs; - reg_rdata_next[1] = clk_enables_clk_usb_48mhz_peri_en_qs; + reg_rdata_next[0] = clk_enables_clk_io_peri_en_qs; + reg_rdata_next[1] = clk_enables_clk_usb_peri_en_qs; end addr_hit[1]: begin
diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson index 8cbfa7c..477c2a2 100644 --- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson +++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
@@ -11,19 +11,19 @@ clock_srcs: { clk_main_i: main - clk_fixed_i: fixed + clk_fixed_i: io } clock_group: infra reset: rst_main_ni reset_connections: { rst_main_ni: sys - rst_fixed_ni: sys_fixed + rst_fixed_ni: sys_io } clock_connections: { clk_main_i: clkmgr_clocks.clk_main_infra - clk_fixed_i: clkmgr_clocks.clk_fixed_infra + clk_fixed_i: clkmgr_clocks.clk_io_infra } connections: {
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson index 781835f..bdf990f 100644 --- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson +++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
@@ -10,17 +10,17 @@ name: peri clock_srcs: { - clk_peri_i: fixed + clk_peri_i: io } clock_group: infra reset: rst_peri_ni reset_connections: { - rst_peri_ni: sys_fixed + rst_peri_ni: sys_io } clock_connections: { - clk_peri_i: clkmgr_clocks.clk_fixed_infra + clk_peri_i: clkmgr_clocks.clk_io_infra } connections: {
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 68bb8a6..8ef0a68 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -9,11 +9,14 @@ input clk_i, input rst_ni, - // Fixed clock - input clk_fixed_i, + // Fixed io clock + input clk_io_i, // USB clock - input clk_usb_48mhz_i, + input clk_usb_i, + + // aon clock + input clk_aon_i, // JTAG interface input jtag_tck_i, @@ -491,8 +494,8 @@ .intr_rx_timeout_o (intr_uart_rx_timeout), .intr_rx_parity_err_o (intr_uart_rx_parity_err), - .clk_i (clkmgr_clocks.clk_fixed_secure), - .rst_ni (rstmgr_resets.rst_sys_fixed_n) + .clk_i (clkmgr_clocks.clk_io_secure), + .rst_ni (rstmgr_resets.rst_sys_io_n) ); gpio u_gpio ( @@ -509,8 +512,8 @@ // Interrupt .intr_gpio_o (intr_gpio_gpio), - .clk_i (clkmgr_clocks.clk_fixed_peri), - .rst_ni (rstmgr_resets.rst_sys_fixed_n) + .clk_i (clkmgr_clocks.clk_io_peri), + .rst_ni (rstmgr_resets.rst_sys_io_n) ); spi_device u_spi_device ( @@ -535,7 +538,7 @@ .intr_txunderflow_o (intr_spi_device_txunderflow), .scanmode_i (scanmode_i), - .clk_i (clkmgr_clocks.clk_fixed_peri), + .clk_i (clkmgr_clocks.clk_io_peri), .rst_ni (rstmgr_resets.rst_spi_device_n) ); @@ -566,8 +569,8 @@ // Interrupt .intr_timer_expired_0_0_o (intr_rv_timer_timer_expired_0_0), - .clk_i (clkmgr_clocks.clk_fixed_timers), - .rst_ni (rstmgr_resets.rst_sys_fixed_n) + .clk_i (clkmgr_clocks.clk_io_timers), + .rst_ni (rstmgr_resets.rst_sys_io_n) ); aes u_aes ( @@ -697,8 +700,8 @@ .pwr_cpu_i(pwrmgr_pwr_cpu), .pwr_peri_i(pwrmgr_pkg::PWR_PERI_DEFAULT), - .clk_i (clk_fixed_i), - .clk_slow_i (clk_fixed_i), + .clk_i (clk_io_i), + .clk_slow_i (clk_io_i), .rst_ni (rstmgr_resets.rst_por_n), .rst_slow_ni (rstmgr_resets.rst_por_n) ); @@ -715,10 +718,10 @@ .cpu_i(rstmgr_cpu), .peri_i(rstmgr_pkg::RSTMGR_PERI_DEFAULT), - .clk_i (clk_fixed_i), + .clk_i (clk_io_i), .clk_main_i (clk_i), - .clk_fixed_i (clk_fixed_i), - .clk_usb_i (clk_usb_48mhz_i), + .clk_io_i (clk_io_i), + .clk_usb_i (clk_usb_i), .rst_ni (rst_ni) ); @@ -733,14 +736,15 @@ .dft_i(clkmgr_pkg::CLK_DFT_DEFAULT), .status_i(clkmgr_pkg::CLK_HINT_STATUS_DEFAULT), - .clk_i (clk_fixed_i), + .clk_i (clk_io_i), .clk_main_i (clk_i), - .clk_fixed_i (clk_fixed_i), - .clk_usb_48mhz_i (clk_usb_48mhz_i), + .clk_io_i (clk_io_i), + .clk_usb_i (clk_usb_i), + .clk_aon_i (clk_aon_i), .rst_ni (rstmgr_resets.rst_por_n), .rst_main_ni (rstmgr_resets.rst_por_n), - .rst_fixed_ni (rstmgr_resets.rst_por_n), - .rst_usb_48mhz_ni (rstmgr_resets.rst_por_n) + .rst_io_ni (rstmgr_resets.rst_por_n), + .rst_usb_ni (rstmgr_resets.rst_por_n) ); nmi_gen u_nmi_gen ( @@ -804,9 +808,9 @@ .intr_frame_o (intr_usbdev_frame), .intr_connected_o (intr_usbdev_connected), - .clk_i (clkmgr_clocks.clk_fixed_peri), - .clk_usb_48mhz_i (clkmgr_clocks.clk_usb_48mhz_peri), - .rst_ni (rstmgr_resets.rst_sys_fixed_n), + .clk_i (clkmgr_clocks.clk_io_peri), + .clk_usb_48mhz_i (clkmgr_clocks.clk_usb_peri), + .rst_ni (rstmgr_resets.rst_sys_io_n), .rst_usb_48mhz_ni (rstmgr_resets.rst_usb_n) ); @@ -867,9 +871,9 @@ // TL-UL Crossbar xbar_main u_xbar_main ( .clk_main_i (clkmgr_clocks.clk_main_infra), - .clk_fixed_i (clkmgr_clocks.clk_fixed_infra), + .clk_fixed_i (clkmgr_clocks.clk_io_infra), .rst_main_ni (rstmgr_resets.rst_sys_n), - .rst_fixed_ni (rstmgr_resets.rst_sys_fixed_n), + .rst_fixed_ni (rstmgr_resets.rst_sys_io_n), .tl_corei_i (tl_corei_h_h2d), .tl_corei_o (tl_corei_h_d2h), .tl_cored_i (tl_cored_h_h2d), @@ -906,8 +910,8 @@ .scanmode_i ); xbar_peri u_xbar_peri ( - .clk_peri_i (clkmgr_clocks.clk_fixed_infra), - .rst_peri_ni (rstmgr_resets.rst_sys_fixed_n), + .clk_peri_i (clkmgr_clocks.clk_io_infra), + .rst_peri_ni (rstmgr_resets.rst_sys_io_n), .tl_main_i (tl_main_h_h2d), .tl_main_o (tl_main_h_d2h), .tl_uart_o (tl_uart_d_h2d),
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv index 2bb4897..311f81f 100644 --- a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv +++ b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
@@ -180,11 +180,10 @@ ////////////////////// top_earlgrey top_earlgrey ( - // Clocks, resets .clk_i ( clk ), .rst_ni ( rst_n ), - .clk_fixed_i ( clk ), - .clk_usb_48mhz_i ( clk_usb_48mhz ), + .clk_io_i ( clk ), + .clk_usb_i ( clk_usb_48mhz ), // JTAG .jtag_tck_i ( jtag_tck ),
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv index a1700f8..8c12213 100644 --- a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv +++ b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
@@ -42,10 +42,12 @@ inout IO_GP15 ); + ////////////////////// // Padring Instance // ////////////////////// + logic clk, clk_usb_48mhz, rst_n; logic [padctrl_reg_pkg::NMioPads-1:0][padctrl_reg_pkg::AttrDw-1:0] mio_attr; logic [padctrl_reg_pkg::NDioPads-1:0][padctrl_reg_pkg::AttrDw-1:0] dio_attr; @@ -198,8 +200,9 @@ // Clocks, resets .clk_i ( clk ), .rst_ni ( rst_n ), - .clk_fixed_i ( clk ), - .clk_usb_48mhz_i ( clk_usb_48mhz ), + .clk_io_i ( clk ), + .clk_aon_i ( clk ), + .clk_usb_i ( clk_usb_48mhz ), // JTAG .jtag_tck_i ( jtag_tck ),
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv b/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv index b4b01f4..8e2c9e8 100644 --- a/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv +++ b/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
@@ -73,8 +73,9 @@ top_earlgrey top_earlgrey ( .clk_i (clk_i), .rst_ni (rst_ni), - .clk_fixed_i (clk_i), - .clk_usb_48mhz_i (clk_i), + .clk_io_i (clk_i), + .clk_usb_i (clk_i), + .clk_aon_i (clk_i), .jtag_tck_i (cio_jtag_tck), .jtag_tms_i (cio_jtag_tms),
diff --git a/util/topgen.py b/util/topgen.py index 4bea02d..105cd90 100755 --- a/util/topgen.py +++ b/util/topgen.py
@@ -492,25 +492,38 @@ # clock classification grps = top['clocks']['groups'] + src_aon_attr = OrderedDict() ft_clks = OrderedDict() rg_clks = OrderedDict() sw_clks = OrderedDict() hint_clks = OrderedDict() + # construct a dictionary of the aon attribute for easier lookup + # ie, src_name_A: True, src_name_B: False + for src in top['clocks']['srcs']: + if src['aon'] == 'yes': + src_aon_attr[src['name']] = True + else: + src_aon_attr[src['name']] = False + + rg_srcs = [src for (src, attr) in src_aon_attr.items() if not attr] + + # clocks fed through clkmgr but are not disturbed in any way + # This maintains the clocking structure consistency ft_clks = {clk:src for grp in grps for (clk,src) in grp['clocks'].items() - if grp['name'] == 'powerup'} + if src_aon_attr[src]} # root-gate clocks rg_clks = {clk:src for grp in grps for (clk,src) in grp['clocks'].items() - if grp['name'] != 'powerup' and grp['sw_cg'] == 'no'} + if grp['name'] != 'powerup' and grp['sw_cg'] == 'no' and not src_aon_attr[src]} # direct sw control clocks sw_clks = {clk:src for grp in grps for (clk,src) in grp['clocks'].items() - if grp['sw_cg'] == 'yes'} + if grp['sw_cg'] == 'yes' and not src_aon_attr[src]} # sw hint clocks hint_clks = {clk:src for grp in grps for (clk,src) in grp['clocks'].items() - if grp['sw_cg'] == 'hint'} + if grp['sw_cg'] == 'hint' and not src_aon_attr[src]} out = StringIO() @@ -519,6 +532,7 @@ tpl = Template(fin.read()) try: out = tpl.render(cfg=top, + rg_srcs=rg_srcs, ft_clks=ft_clks, rg_clks=rg_clks, sw_clks=sw_clks,
diff --git a/util/topgen/validate.py b/util/topgen/validate.py index e34e173..94646f3 100644 --- a/util/topgen/validate.py +++ b/util/topgen/validate.py
@@ -89,6 +89,12 @@ } padctrl_added = {} +clock_srcs_required = { + 'name': ['s', 'name of clock group'], + 'aon': ['s', 'yes, no. aon attribute of a clock'], + 'freq': ['s', 'frequency of clock in Hz'], +} + clock_groups_required = { 'name': ['s', 'name of clock group'], 'src': ['s', 'yes, no. This clock group is directly from source'], @@ -202,6 +208,11 @@ def check_clocks_resets(top, ipobjs, ip_idxs, xbarobjs, xbar_idxs): + + # check clock fields are all there + for src in top['clocks']['srcs']: + check_keys(src, clock_srcs_required, {}, {}, "Clock source") + # all defined clock/reset nets reset_nets = [reset['name'] for reset in top['resets']] clock_srcs = [clock['name'] for clock in top['clocks']['srcs']]