[rv_core_ibex] Minor clean-up - re-name reg to cfg, this removes the reg_reg duplication - cfg is appropriate here since there is almost no function attached to that interface - minor clean-up of various hjson / python to remove things no longer used. Signed-off-by: Timothy Chen <timothytim@google.com> [top] Auto gen Signed-off-by: Timothy Chen <timothytim@google.com> [sw] Update software base addr Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson b/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson index 86cef12..236bfff 100644 --- a/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson +++ b/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson
@@ -8,7 +8,7 @@ bus_interfaces: [ { protocol: "tlul", direction: "host", name: "corei" } { protocol: "tlul", direction: "host", name: "cored" } - { protocol: "tlul", direction: "device", name: "reg" } + { protocol: "tlul", direction: "device", name: "cfg" } ], scan: "true", // Enable `scanmode_i` port scan_reset: "true", // Enable `scan_rst_ni` port @@ -284,7 +284,7 @@ regwidth: "32", registers: { - reg: [ + cfg: [ { multireg: { cname: "SW_ALERTS_REGWEN", name: "SW_ALERT_REGWEN",
diff --git a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv index b526934..e1f739c 100644 --- a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv +++ b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
@@ -80,8 +80,8 @@ input lc_ctrl_pkg::lc_tx_t scanmode_i, // peripheral interface access - input tlul_pkg::tl_h2d_t reg_tl_d_i, - output tlul_pkg::tl_d2h_t reg_tl_d_o, + input tlul_pkg::tl_h2d_t cfg_tl_d_i, + output tlul_pkg::tl_d2h_t cfg_tl_d_o, // interrupts and alerts input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, @@ -93,8 +93,8 @@ import tlul_pkg::*; // Register module - rv_core_ibex_reg_reg2hw_t reg2hw; - rv_core_ibex_reg_hw2reg_t hw2reg; + rv_core_ibex_cfg_reg2hw_t reg2hw; + rv_core_ibex_cfg_hw2reg_t hw2reg; // if pipeline=1, do not allow pass through and always break the path // if pipeline is 0, passthrough the fifo completely @@ -463,11 +463,11 @@ ////////////////////////////////// logic intg_err; - rv_core_ibex_reg_reg_top u_reg_reg ( + rv_core_ibex_cfg_reg_top u_reg_cfg ( .clk_i, .rst_ni, - .tl_i(reg_tl_d_i), - .tl_o(reg_tl_d_o), + .tl_i(cfg_tl_d_i), + .tl_o(cfg_tl_d_o), .reg2hw, .hw2reg, .intg_err_o (intg_err),
diff --git a/hw/ip/rv_core_ibex/rtl/rv_core_ibex_reg_reg_top.sv b/hw/ip/rv_core_ibex/rtl/rv_core_ibex_cfg_reg_top.sv similarity index 94% rename from hw/ip/rv_core_ibex/rtl/rv_core_ibex_reg_reg_top.sv rename to hw/ip/rv_core_ibex/rtl/rv_core_ibex_cfg_reg_top.sv index 4da8ab3..8fe01d4 100644 --- a/hw/ip/rv_core_ibex/rtl/rv_core_ibex_reg_reg_top.sv +++ b/hw/ip/rv_core_ibex/rtl/rv_core_ibex_cfg_reg_top.sv
@@ -6,15 +6,15 @@ `include "prim_assert.sv" -module rv_core_ibex_reg_reg_top ( +module rv_core_ibex_cfg_reg_top ( input clk_i, input rst_ni, input tlul_pkg::tl_h2d_t tl_i, output tlul_pkg::tl_d2h_t tl_o, // To HW - output rv_core_ibex_reg_pkg::rv_core_ibex_reg_reg2hw_t reg2hw, // Write - input rv_core_ibex_reg_pkg::rv_core_ibex_reg_hw2reg_t hw2reg, // Read + output rv_core_ibex_reg_pkg::rv_core_ibex_cfg_reg2hw_t reg2hw, // Write + input rv_core_ibex_reg_pkg::rv_core_ibex_cfg_hw2reg_t hw2reg, // Read // Integrity check errors output logic intg_err_o, @@ -942,28 +942,28 @@ // Check sub-word write is permitted always_comb begin wr_err = (reg_we & - ((addr_hit[ 0] & (|(RV_CORE_IBEX_REG_PERMIT[ 0] & ~reg_be))) | - (addr_hit[ 1] & (|(RV_CORE_IBEX_REG_PERMIT[ 1] & ~reg_be))) | - (addr_hit[ 2] & (|(RV_CORE_IBEX_REG_PERMIT[ 2] & ~reg_be))) | - (addr_hit[ 3] & (|(RV_CORE_IBEX_REG_PERMIT[ 3] & ~reg_be))) | - (addr_hit[ 4] & (|(RV_CORE_IBEX_REG_PERMIT[ 4] & ~reg_be))) | - (addr_hit[ 5] & (|(RV_CORE_IBEX_REG_PERMIT[ 5] & ~reg_be))) | - (addr_hit[ 6] & (|(RV_CORE_IBEX_REG_PERMIT[ 6] & ~reg_be))) | - (addr_hit[ 7] & (|(RV_CORE_IBEX_REG_PERMIT[ 7] & ~reg_be))) | - (addr_hit[ 8] & (|(RV_CORE_IBEX_REG_PERMIT[ 8] & ~reg_be))) | - (addr_hit[ 9] & (|(RV_CORE_IBEX_REG_PERMIT[ 9] & ~reg_be))) | - (addr_hit[10] & (|(RV_CORE_IBEX_REG_PERMIT[10] & ~reg_be))) | - (addr_hit[11] & (|(RV_CORE_IBEX_REG_PERMIT[11] & ~reg_be))) | - (addr_hit[12] & (|(RV_CORE_IBEX_REG_PERMIT[12] & ~reg_be))) | - (addr_hit[13] & (|(RV_CORE_IBEX_REG_PERMIT[13] & ~reg_be))) | - (addr_hit[14] & (|(RV_CORE_IBEX_REG_PERMIT[14] & ~reg_be))) | - (addr_hit[15] & (|(RV_CORE_IBEX_REG_PERMIT[15] & ~reg_be))) | - (addr_hit[16] & (|(RV_CORE_IBEX_REG_PERMIT[16] & ~reg_be))) | - (addr_hit[17] & (|(RV_CORE_IBEX_REG_PERMIT[17] & ~reg_be))) | - (addr_hit[18] & (|(RV_CORE_IBEX_REG_PERMIT[18] & ~reg_be))) | - (addr_hit[19] & (|(RV_CORE_IBEX_REG_PERMIT[19] & ~reg_be))) | - (addr_hit[20] & (|(RV_CORE_IBEX_REG_PERMIT[20] & ~reg_be))) | - (addr_hit[21] & (|(RV_CORE_IBEX_REG_PERMIT[21] & ~reg_be))))); + ((addr_hit[ 0] & (|(RV_CORE_IBEX_CFG_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(RV_CORE_IBEX_CFG_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(RV_CORE_IBEX_CFG_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(RV_CORE_IBEX_CFG_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(RV_CORE_IBEX_CFG_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(RV_CORE_IBEX_CFG_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(RV_CORE_IBEX_CFG_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(RV_CORE_IBEX_CFG_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(RV_CORE_IBEX_CFG_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(RV_CORE_IBEX_CFG_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(RV_CORE_IBEX_CFG_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(RV_CORE_IBEX_CFG_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(RV_CORE_IBEX_CFG_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(RV_CORE_IBEX_CFG_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(RV_CORE_IBEX_CFG_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(RV_CORE_IBEX_CFG_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(RV_CORE_IBEX_CFG_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(RV_CORE_IBEX_CFG_PERMIT[17] & ~reg_be))) | + (addr_hit[18] & (|(RV_CORE_IBEX_CFG_PERMIT[18] & ~reg_be))) | + (addr_hit[19] & (|(RV_CORE_IBEX_CFG_PERMIT[19] & ~reg_be))) | + (addr_hit[20] & (|(RV_CORE_IBEX_CFG_PERMIT[20] & ~reg_be))) | + (addr_hit[21] & (|(RV_CORE_IBEX_CFG_PERMIT[21] & ~reg_be))))); end assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
diff --git a/hw/ip/rv_core_ibex/rtl/rv_core_ibex_reg_pkg.sv b/hw/ip/rv_core_ibex/rtl/rv_core_ibex_reg_pkg.sv index e39b13b..ebaac40 100644 --- a/hw/ip/rv_core_ibex/rtl/rv_core_ibex_reg_pkg.sv +++ b/hw/ip/rv_core_ibex/rtl/rv_core_ibex_reg_pkg.sv
@@ -12,10 +12,10 @@ parameter int NumAlerts = 4; // Address widths within the block - parameter int RegAw = 7; + parameter int CfgAw = 7; ////////////////////////////////////////////// - // Typedefs for registers for reg interface // + // Typedefs for registers for cfg interface // ////////////////////////////////////////////// typedef struct packed { @@ -84,7 +84,7 @@ } recov_core_err; } rv_core_ibex_hw2reg_err_status_reg_t; - // Register -> HW type for reg interface + // Register -> HW type for cfg interface typedef struct packed { rv_core_ibex_reg2hw_alert_test_reg_t alert_test; // [271:264] rv_core_ibex_reg2hw_sw_alert_mreg_t [1:0] sw_alert; // [263:260] @@ -94,45 +94,45 @@ rv_core_ibex_reg2hw_dbus_addr_en_mreg_t [1:0] dbus_addr_en; // [129:128] rv_core_ibex_reg2hw_dbus_addr_matching_mreg_t [1:0] dbus_addr_matching; // [127:64] rv_core_ibex_reg2hw_dbus_remap_addr_mreg_t [1:0] dbus_remap_addr; // [63:0] - } rv_core_ibex_reg_reg2hw_t; + } rv_core_ibex_cfg_reg2hw_t; - // HW -> register type for reg interface + // HW -> register type for cfg interface typedef struct packed { rv_core_ibex_hw2reg_err_status_reg_t err_status; // [7:0] - } rv_core_ibex_reg_hw2reg_t; + } rv_core_ibex_cfg_hw2reg_t; - // Register offsets for reg interface - parameter logic [RegAw-1:0] RV_CORE_IBEX_ALERT_TEST_OFFSET = 7'h 0; - parameter logic [RegAw-1:0] RV_CORE_IBEX_SW_ALERT_REGWEN_0_OFFSET = 7'h 4; - parameter logic [RegAw-1:0] RV_CORE_IBEX_SW_ALERT_REGWEN_1_OFFSET = 7'h 8; - parameter logic [RegAw-1:0] RV_CORE_IBEX_SW_ALERT_0_OFFSET = 7'h c; - parameter logic [RegAw-1:0] RV_CORE_IBEX_SW_ALERT_1_OFFSET = 7'h 10; - parameter logic [RegAw-1:0] RV_CORE_IBEX_IBUS_REGWEN_0_OFFSET = 7'h 14; - parameter logic [RegAw-1:0] RV_CORE_IBEX_IBUS_REGWEN_1_OFFSET = 7'h 18; - parameter logic [RegAw-1:0] RV_CORE_IBEX_IBUS_ADDR_EN_0_OFFSET = 7'h 1c; - parameter logic [RegAw-1:0] RV_CORE_IBEX_IBUS_ADDR_EN_1_OFFSET = 7'h 20; - parameter logic [RegAw-1:0] RV_CORE_IBEX_IBUS_ADDR_MATCHING_0_OFFSET = 7'h 24; - parameter logic [RegAw-1:0] RV_CORE_IBEX_IBUS_ADDR_MATCHING_1_OFFSET = 7'h 28; - parameter logic [RegAw-1:0] RV_CORE_IBEX_IBUS_REMAP_ADDR_0_OFFSET = 7'h 2c; - parameter logic [RegAw-1:0] RV_CORE_IBEX_IBUS_REMAP_ADDR_1_OFFSET = 7'h 30; - parameter logic [RegAw-1:0] RV_CORE_IBEX_DBUS_REGWEN_0_OFFSET = 7'h 34; - parameter logic [RegAw-1:0] RV_CORE_IBEX_DBUS_REGWEN_1_OFFSET = 7'h 38; - parameter logic [RegAw-1:0] RV_CORE_IBEX_DBUS_ADDR_EN_0_OFFSET = 7'h 3c; - parameter logic [RegAw-1:0] RV_CORE_IBEX_DBUS_ADDR_EN_1_OFFSET = 7'h 40; - parameter logic [RegAw-1:0] RV_CORE_IBEX_DBUS_ADDR_MATCHING_0_OFFSET = 7'h 44; - parameter logic [RegAw-1:0] RV_CORE_IBEX_DBUS_ADDR_MATCHING_1_OFFSET = 7'h 48; - parameter logic [RegAw-1:0] RV_CORE_IBEX_DBUS_REMAP_ADDR_0_OFFSET = 7'h 4c; - parameter logic [RegAw-1:0] RV_CORE_IBEX_DBUS_REMAP_ADDR_1_OFFSET = 7'h 50; - parameter logic [RegAw-1:0] RV_CORE_IBEX_ERR_STATUS_OFFSET = 7'h 54; + // Register offsets for cfg interface + parameter logic [CfgAw-1:0] RV_CORE_IBEX_ALERT_TEST_OFFSET = 7'h 0; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_SW_ALERT_REGWEN_0_OFFSET = 7'h 4; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_SW_ALERT_REGWEN_1_OFFSET = 7'h 8; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_SW_ALERT_0_OFFSET = 7'h c; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_SW_ALERT_1_OFFSET = 7'h 10; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_IBUS_REGWEN_0_OFFSET = 7'h 14; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_IBUS_REGWEN_1_OFFSET = 7'h 18; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_IBUS_ADDR_EN_0_OFFSET = 7'h 1c; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_IBUS_ADDR_EN_1_OFFSET = 7'h 20; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_IBUS_ADDR_MATCHING_0_OFFSET = 7'h 24; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_IBUS_ADDR_MATCHING_1_OFFSET = 7'h 28; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_IBUS_REMAP_ADDR_0_OFFSET = 7'h 2c; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_IBUS_REMAP_ADDR_1_OFFSET = 7'h 30; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_DBUS_REGWEN_0_OFFSET = 7'h 34; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_DBUS_REGWEN_1_OFFSET = 7'h 38; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_DBUS_ADDR_EN_0_OFFSET = 7'h 3c; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_DBUS_ADDR_EN_1_OFFSET = 7'h 40; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_DBUS_ADDR_MATCHING_0_OFFSET = 7'h 44; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_DBUS_ADDR_MATCHING_1_OFFSET = 7'h 48; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_DBUS_REMAP_ADDR_0_OFFSET = 7'h 4c; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_DBUS_REMAP_ADDR_1_OFFSET = 7'h 50; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_ERR_STATUS_OFFSET = 7'h 54; - // Reset values for hwext registers and their fields for reg interface + // Reset values for hwext registers and their fields for cfg interface parameter logic [3:0] RV_CORE_IBEX_ALERT_TEST_RESVAL = 4'h 0; parameter logic [0:0] RV_CORE_IBEX_ALERT_TEST_FATAL_SW_ERR_RESVAL = 1'h 0; parameter logic [0:0] RV_CORE_IBEX_ALERT_TEST_RECOV_SW_ERR_RESVAL = 1'h 0; parameter logic [0:0] RV_CORE_IBEX_ALERT_TEST_FATAL_HW_ERR_RESVAL = 1'h 0; parameter logic [0:0] RV_CORE_IBEX_ALERT_TEST_RECOV_HW_ERR_RESVAL = 1'h 0; - // Register index for reg interface + // Register index for cfg interface typedef enum int { RV_CORE_IBEX_ALERT_TEST, RV_CORE_IBEX_SW_ALERT_REGWEN_0, @@ -156,10 +156,10 @@ RV_CORE_IBEX_DBUS_REMAP_ADDR_0, RV_CORE_IBEX_DBUS_REMAP_ADDR_1, RV_CORE_IBEX_ERR_STATUS - } rv_core_ibex_reg_id_e; + } rv_core_ibex_cfg_id_e; - // Register width information to check illegal writes for reg interface - parameter logic [3:0] RV_CORE_IBEX_REG_PERMIT [22] = '{ + // Register width information to check illegal writes for cfg interface + parameter logic [3:0] RV_CORE_IBEX_CFG_PERMIT [22] = '{ 4'b 0001, // index[ 0] RV_CORE_IBEX_ALERT_TEST 4'b 0001, // index[ 1] RV_CORE_IBEX_SW_ALERT_REGWEN_0 4'b 0001, // index[ 2] RV_CORE_IBEX_SW_ALERT_REGWEN_1
diff --git a/hw/ip/rv_core_ibex/rv_core_ibex.core b/hw/ip/rv_core_ibex/rv_core_ibex.core index 3d1a4be..e48add5 100644 --- a/hw/ip/rv_core_ibex/rv_core_ibex.core +++ b/hw/ip/rv_core_ibex/rv_core_ibex.core
@@ -21,7 +21,7 @@ files: - rtl/rv_core_ibex_pkg.sv - rtl/rv_core_ibex_reg_pkg.sv - - rtl/rv_core_ibex_reg_reg_top.sv + - rtl/rv_core_ibex_cfg_reg_top.sv - rtl/rv_core_ibex.sv - rtl/rv_core_addr_trans.sv file_type: systemVerilogSource
diff --git a/hw/ip/rv_core_ibex_peri/rv_core_ibex_peri.core b/hw/ip/rv_core_ibex_peri/rv_core_ibex_peri.core deleted file mode 100644 index e8c1674..0000000 --- a/hw/ip/rv_core_ibex_peri/rv_core_ibex_peri.core +++ /dev/null
@@ -1,41 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:rv_core_ibex_peri:0.1" -description: "RV core ibex peripheral" - -filesets: - files_rtl: - depend: - - lowrisc:ip:tlul - - lowrisc:prim:all - - lowrisc:ip:rv_core_ibex_peri_pkg - files: - - rtl/rv_core_ibex_peri_reg_pkg.sv - - rtl/rv_core_ibex_peri_reg_top.sv - - rtl/rv_core_ibex_peri.sv - file_type: systemVerilogSource - -parameters: - SYNTHESIS: - datatype: bool - paramtype: vlogdefine - - -targets: - default: &default_target - filesets: - - files_rtl - toplevel: rv_core_ibex_peri - - lint: - <<: *default_target - default_tool: verilator - parameters: - - SYNTHESIS=true - tools: - verilator: - mode: lint-only - verilator_options: - - "-Wall"
diff --git a/hw/ip/rv_core_ibex_peri/rv_core_ibex_peri_pkg.core b/hw/ip/rv_core_ibex_peri/rv_core_ibex_peri_pkg.core deleted file mode 100644 index 0e95360..0000000 --- a/hw/ip/rv_core_ibex_peri/rv_core_ibex_peri_pkg.core +++ /dev/null
@@ -1,19 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:rv_core_ibex_peri_pkg:0.1" -description: "rv_core_ibex_peri Package" - -filesets: - files_rtl: - depend: - - lowrisc:constants:top_pkg - files: - - rtl/rv_core_ibex_peri_pkg.sv - file_type: systemVerilogSource - -targets: - default: - filesets: - - files_rtl
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 9e889c0..96fb345 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -408,7 +408,6 @@ ] } num_cores: "1" - host: [] module: [ { @@ -6012,7 +6011,7 @@ index: -1 } { - name: reg_tl_d + name: cfg_tl_d struct: tl package: tlul_pkg type: req_rsp @@ -6021,13 +6020,13 @@ inst_name: rv_core_ibex default: "" end_idx: -1 - top_signame: rv_core_ibex_reg_tl_d + top_signame: rv_core_ibex_cfg_tl_d index: -1 } ] base_addrs: { - reg: 0x411F0000 + cfg: 0x411F0000 } } ] @@ -6898,9 +6897,9 @@ [ main.tl_keymgr ] - rv_core_ibex.reg_tl_d: + rv_core_ibex.cfg_tl_d: [ - main.tl_rv_core_ibex__reg + main.tl_rv_core_ibex__cfg ] sram_ctrl_main.tl: [ @@ -7131,7 +7130,7 @@ keymgr kmac sram_ctrl_main - rv_core_ibex.reg + rv_core_ibex.cfg ] rv_dm.sba: [ @@ -7154,7 +7153,7 @@ keymgr kmac sram_ctrl_main - rv_core_ibex.reg + rv_core_ibex.cfg ] } nodes: @@ -7534,7 +7533,7 @@ pipeline: "true" } { - name: rv_core_ibex.reg + name: rv_core_ibex.cfg type: device clock: clk_main_i reset: rst_main_ni @@ -7843,7 +7842,7 @@ index: -1 } { - name: tl_rv_core_ibex__reg + name: tl_rv_core_ibex__cfg struct: tl package: tlul_pkg type: req_rsp @@ -7851,7 +7850,7 @@ width: 1 inst_name: main default: "" - top_signame: rv_core_ibex_reg_tl_d + top_signame: rv_core_ibex_cfg_tl_d index: -1 } { @@ -16473,7 +16472,7 @@ index: -1 } { - name: reg_tl_d + name: cfg_tl_d struct: tl package: tlul_pkg type: req_rsp @@ -16482,7 +16481,7 @@ inst_name: rv_core_ibex default: "" end_idx: -1 - top_signame: rv_core_ibex_reg_tl_d + top_signame: rv_core_ibex_cfg_tl_d index: -1 } { @@ -17012,7 +17011,7 @@ index: -1 } { - name: tl_rv_core_ibex__reg + name: tl_rv_core_ibex__cfg struct: tl package: tlul_pkg type: req_rsp @@ -17020,7 +17019,7 @@ width: 1 inst_name: main default: "" - top_signame: rv_core_ibex_reg_tl_d + top_signame: rv_core_ibex_cfg_tl_d index: -1 } { @@ -19519,7 +19518,7 @@ { package: tlul_pkg struct: tl_h2d - signame: rv_core_ibex_reg_tl_d_req + signame: rv_core_ibex_cfg_tl_d_req width: 1 type: req_rsp end_idx: -1 @@ -19530,7 +19529,7 @@ { package: tlul_pkg struct: tl_d2h - signame: rv_core_ibex_reg_tl_d_rsp + signame: rv_core_ibex_cfg_tl_d_rsp width: 1 type: req_rsp end_idx: -1
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index e9094f5..226eb1f 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -167,12 +167,6 @@ // Number of cores: used in rv_plic and timer num_cores: "1", - - // `host` defines the host only components in the system - // This function is deprecated and will be removed as a separate PR. - host: [ - ] - // `module` defines the peripherals. // Details are coming from each modules' config file `ip.hjson` // TODO: Define parameter here
diff --git a/hw/top_earlgrey/data/xbar_main.hjson b/hw/top_earlgrey/data/xbar_main.hjson index f3326bd..0779392 100644 --- a/hw/top_earlgrey/data/xbar_main.hjson +++ b/hw/top_earlgrey/data/xbar_main.hjson
@@ -143,7 +143,7 @@ reset: "rst_main_ni" pipeline_byp: "false" }, - { name: "rv_core_ibex.reg", + { name: "rv_core_ibex.cfg", type: "device", clock: "clk_main_i" reset: "rst_main_ni" @@ -163,13 +163,13 @@ "ram_main", "eflash", "peri", "flash_ctrl.core", "flash_ctrl.prim", "aes", "entropy_src", "csrng", "edn0", "edn1", "hmac", "rv_plic", "otbn", "keymgr", "kmac", "sram_ctrl_main", - "rv_core_ibex.reg" + "rv_core_ibex.cfg" ], rv_dm.sba: [ "rom_ctrl.rom", "rom_ctrl.regs", "rv_dm.regs", "ram_main", "eflash", "peri", "flash_ctrl.core", "flash_ctrl.prim", "aes", "entropy_src", "csrng", "edn0", "edn1", "hmac", "rv_plic", - "otbn", "keymgr", "kmac", "sram_ctrl_main", "rv_core_ibex.reg" + "otbn", "keymgr", "kmac", "sram_ctrl_main", "rv_core_ibex.cfg" ], }, }
diff --git a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv index d22c167..360270d 100644 --- a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
@@ -51,7 +51,7 @@ tl_if rv_plic_tl_if(clk_main, rst_n); tl_if otbn_tl_if(clk_main, rst_n); tl_if keymgr_tl_if(clk_main, rst_n); -tl_if rv_core_ibex__reg_tl_if(clk_main, rst_n); +tl_if rv_core_ibex__cfg_tl_if(clk_main, rst_n); tl_if sram_ctrl_main_tl_if(clk_main, rst_n); tl_if uart0_tl_if(clk_io_div4, rst_n); tl_if uart1_tl_if(clk_io_div4, rst_n); @@ -129,7 +129,7 @@ `DRIVE_CHIP_TL_DEVICE_IF(rv_plic, rv_plic, tl) `DRIVE_CHIP_TL_DEVICE_IF(otbn, otbn, tl) `DRIVE_CHIP_TL_DEVICE_IF(keymgr, keymgr, tl) - `DRIVE_CHIP_TL_DEVICE_IF(rv_core_ibex__reg, rv_core_ibex, reg_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(rv_core_ibex__cfg, rv_core_ibex, cfg_tl_d) `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_main, sram_ctrl_main, tl) `DRIVE_CHIP_TL_DEVICE_IF(uart0, uart0, tl) `DRIVE_CHIP_TL_DEVICE_IF(uart1, uart1, tl)
diff --git a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv index 9c6c0b3..f12d59b 100644 --- a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
@@ -61,7 +61,7 @@ '{"keymgr", '{ '{32'h41130000, 32'h41130fff} }}, - '{"rv_core_ibex__reg", '{ + '{"rv_core_ibex__cfg", '{ '{32'h411f0000, 32'h411f0fff} }}, '{"sram_ctrl_main", '{ @@ -216,7 +216,7 @@ "keymgr", "kmac", "sram_ctrl_main", - "rv_core_ibex__reg"}} + "rv_core_ibex__cfg"}} , '{"rv_dm__sba", 2, '{ "rom_ctrl__rom", @@ -267,5 +267,5 @@ "keymgr", "kmac", "sram_ctrl_main", - "rv_core_ibex__reg"}} + "rv_core_ibex__cfg"}} };
diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson index b84e6f2..2d3de21 100644 --- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson +++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
@@ -57,7 +57,7 @@ keymgr kmac sram_ctrl_main - rv_core_ibex.reg + rv_core_ibex.cfg ] rv_dm.sba: [ @@ -80,7 +80,7 @@ keymgr kmac sram_ctrl_main - rv_core_ibex.reg + rv_core_ibex.cfg ] } nodes: @@ -460,7 +460,7 @@ pipeline: "true" } { - name: rv_core_ibex.reg + name: rv_core_ibex.cfg type: device clock: clk_main_i reset: rst_main_ni
diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson index 8712af4..f92b5bb 100644 --- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson +++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson
@@ -147,7 +147,7 @@ } { struct: "tl" type: "req_rsp" - name: "tl_rv_core_ibex__reg" + name: "tl_rv_core_ibex__cfg" act: "req" package: "tlul_pkg" }
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv index 4443ea7..e801046 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv
@@ -41,5 +41,5 @@ `CONNECT_TL_DEVICE_IF(rv_plic, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(otbn, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(keymgr, dut, clk_main_i, rst_n) -`CONNECT_TL_DEVICE_IF(rv_core_ibex__reg, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(rv_core_ibex__cfg, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(sram_ctrl_main, dut, clk_main_i, rst_n)
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg index 518ee21..ac995cf 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg
@@ -88,10 +88,10 @@ -node tb.dut tl_keymgr_o.a_address[23:21] -node tb.dut tl_keymgr_o.a_address[29:25] -node tb.dut tl_keymgr_o.a_address[31:31] --node tb.dut tl_rv_core_ibex__reg_o.a_address[15:12] --node tb.dut tl_rv_core_ibex__reg_o.a_address[23:21] --node tb.dut tl_rv_core_ibex__reg_o.a_address[29:25] --node tb.dut tl_rv_core_ibex__reg_o.a_address[31:31] +-node tb.dut tl_rv_core_ibex__cfg_o.a_address[15:12] +-node tb.dut tl_rv_core_ibex__cfg_o.a_address[23:21] +-node tb.dut tl_rv_core_ibex__cfg_o.a_address[29:25] +-node tb.dut tl_rv_core_ibex__cfg_o.a_address[31:31] -node tb.dut tl_sram_ctrl_main_o.a_address[17:12] -node tb.dut tl_sram_ctrl_main_o.a_address[23:21] -node tb.dut tl_sram_ctrl_main_o.a_address[29:25]
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv index 0f88388..5ece78e 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
@@ -64,7 +64,7 @@ '{"keymgr", '{ '{32'h41130000, 32'h41130fff} }}, - '{"rv_core_ibex__reg", '{ + '{"rv_core_ibex__cfg", '{ '{32'h411f0000, 32'h411f0fff} }}, '{"sram_ctrl_main", '{ @@ -100,7 +100,7 @@ "keymgr", "kmac", "sram_ctrl_main", - "rv_core_ibex__reg"}} + "rv_core_ibex__cfg"}} , '{"rv_dm__sba", 2, '{ "rom_ctrl__rom", @@ -122,5 +122,5 @@ "keymgr", "kmac", "sram_ctrl_main", - "rv_core_ibex__reg"}} + "rv_core_ibex__cfg"}} };
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv index 42051a0..c9c5920 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv
@@ -140,11 +140,11 @@ .h2d (tl_keymgr_o), .d2h (tl_keymgr_i) ); - bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_core_ibex__reg ( + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_core_ibex__cfg ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .h2d (tl_rv_core_ibex__reg_o), - .d2h (tl_rv_core_ibex__reg_i) + .h2d (tl_rv_core_ibex__cfg_o), + .d2h (tl_rv_core_ibex__cfg_i) ); bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_main ( .clk_i (clk_main_i),
diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv index a7dc731..84e1652 100644 --- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv +++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
@@ -27,7 +27,7 @@ localparam logic [31:0] ADDR_SPACE_RV_PLIC = 32'h 41010000; localparam logic [31:0] ADDR_SPACE_OTBN = 32'h 411d0000; localparam logic [31:0] ADDR_SPACE_KEYMGR = 32'h 41130000; - localparam logic [31:0] ADDR_SPACE_RV_CORE_IBEX__REG = 32'h 411f0000; + localparam logic [31:0] ADDR_SPACE_RV_CORE_IBEX__CFG = 32'h 411f0000; localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_MAIN = 32'h 411c0000; localparam logic [31:0] ADDR_MASK_RV_DM__REGS = 32'h 00000fff; @@ -51,7 +51,7 @@ localparam logic [31:0] ADDR_MASK_RV_PLIC = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_OTBN = 32'h 0000ffff; localparam logic [31:0] ADDR_MASK_KEYMGR = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_RV_CORE_IBEX__REG = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_RV_CORE_IBEX__CFG = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN = 32'h 00000fff; localparam int N_HOST = 3; @@ -77,7 +77,7 @@ TlRvPlic = 16, TlOtbn = 17, TlKeymgr = 18, - TlRvCoreIbexReg = 19, + TlRvCoreIbexCfg = 19, TlSramCtrlMain = 20 } tl_device_e;
diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv index 2712c5d..393b362 100644 --- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv +++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
@@ -60,7 +60,7 @@ // -> sm1_46 // -> sram_ctrl_main // -> sm1_47 -// -> rv_core_ibex.reg +// -> rv_core_ibex.cfg // rv_dm.sba // -> s1n_48 // -> sm1_25 @@ -103,7 +103,7 @@ // -> sm1_46 // -> sram_ctrl_main // -> sm1_47 -// -> rv_core_ibex.reg +// -> rv_core_ibex.cfg module xbar_main ( input clk_main_i, @@ -158,8 +158,8 @@ input tlul_pkg::tl_d2h_t tl_otbn_i, output tlul_pkg::tl_h2d_t tl_keymgr_o, input tlul_pkg::tl_d2h_t tl_keymgr_i, - output tlul_pkg::tl_h2d_t tl_rv_core_ibex__reg_o, - input tlul_pkg::tl_d2h_t tl_rv_core_ibex__reg_i, + output tlul_pkg::tl_h2d_t tl_rv_core_ibex__cfg_o, + input tlul_pkg::tl_d2h_t tl_rv_core_ibex__cfg_i, output tlul_pkg::tl_h2d_t tl_sram_ctrl_main_o, input tlul_pkg::tl_d2h_t tl_sram_ctrl_main_i, @@ -562,8 +562,8 @@ assign tl_sram_ctrl_main_o = tl_sm1_46_ds_h2d; assign tl_sm1_46_ds_d2h = tl_sram_ctrl_main_i; - assign tl_rv_core_ibex__reg_o = tl_sm1_47_ds_h2d; - assign tl_sm1_47_ds_d2h = tl_rv_core_ibex__reg_i; + assign tl_rv_core_ibex__cfg_o = tl_sm1_47_ds_h2d; + assign tl_sm1_47_ds_d2h = tl_rv_core_ibex__cfg_i; assign tl_s1n_48_us_h2d = tl_rv_dm__sba_i; assign tl_rv_dm__sba_o = tl_s1n_48_us_d2h; @@ -673,7 +673,7 @@ dev_sel_s1n_29 = 5'd19; end else if ((tl_s1n_29_us_h2d.a_address & - ~(ADDR_MASK_RV_CORE_IBEX__REG)) == ADDR_SPACE_RV_CORE_IBEX__REG) begin + ~(ADDR_MASK_RV_CORE_IBEX__CFG)) == ADDR_SPACE_RV_CORE_IBEX__CFG) begin dev_sel_s1n_29 = 5'd20; end end @@ -758,7 +758,7 @@ dev_sel_s1n_48 = 5'd18; end else if ((tl_s1n_48_us_h2d.a_address & - ~(ADDR_MASK_RV_CORE_IBEX__REG)) == ADDR_SPACE_RV_CORE_IBEX__REG) begin + ~(ADDR_MASK_RV_CORE_IBEX__CFG)) == ADDR_SPACE_RV_CORE_IBEX__CFG) begin dev_sel_s1n_48 = 5'd19; end end
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 792d026..aa49628 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -646,8 +646,8 @@ tlul_pkg::tl_d2h_t otbn_tl_rsp; tlul_pkg::tl_h2d_t keymgr_tl_req; tlul_pkg::tl_d2h_t keymgr_tl_rsp; - tlul_pkg::tl_h2d_t rv_core_ibex_reg_tl_d_req; - tlul_pkg::tl_d2h_t rv_core_ibex_reg_tl_d_rsp; + tlul_pkg::tl_h2d_t rv_core_ibex_cfg_tl_d_req; + tlul_pkg::tl_d2h_t rv_core_ibex_cfg_tl_d_rsp; tlul_pkg::tl_h2d_t sram_ctrl_main_tl_req; tlul_pkg::tl_d2h_t sram_ctrl_main_tl_rsp; tlul_pkg::tl_h2d_t uart0_tl_req; @@ -2577,8 +2577,8 @@ .corei_tl_h_i(main_tl_rv_core_ibex__corei_rsp), .cored_tl_h_o(main_tl_rv_core_ibex__cored_req), .cored_tl_h_i(main_tl_rv_core_ibex__cored_rsp), - .reg_tl_d_i(rv_core_ibex_reg_tl_d_req), - .reg_tl_d_o(rv_core_ibex_reg_tl_d_rsp), + .cfg_tl_d_i(rv_core_ibex_cfg_tl_d_req), + .cfg_tl_d_o(rv_core_ibex_cfg_tl_d_rsp), .scanmode_i, .scan_rst_ni, @@ -2837,9 +2837,9 @@ .tl_keymgr_o(keymgr_tl_req), .tl_keymgr_i(keymgr_tl_rsp), - // port: tl_rv_core_ibex__reg - .tl_rv_core_ibex__reg_o(rv_core_ibex_reg_tl_d_req), - .tl_rv_core_ibex__reg_i(rv_core_ibex_reg_tl_d_rsp), + // port: tl_rv_core_ibex__cfg + .tl_rv_core_ibex__cfg_o(rv_core_ibex_cfg_tl_d_req), + .tl_rv_core_ibex__cfg_i(rv_core_ibex_cfg_tl_d_rsp), // port: tl_sram_ctrl_main .tl_sram_ctrl_main_o(sram_ctrl_main_tl_req),
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv index 2ca971d..64f1045 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
@@ -471,14 +471,14 @@ parameter int unsigned TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES = 32'h4000; /** - * Peripheral base address for reg device on rv_core_ibex in top earlgrey. + * Peripheral base address for cfg device on rv_core_ibex in top earlgrey. */ - parameter int unsigned TOP_EARLGREY_RV_CORE_IBEX_REG_BASE_ADDR = 32'h411F0000; + parameter int unsigned TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR = 32'h411F0000; /** - * Peripheral size in bytes for reg device on rv_core_ibex in top earlgrey. + * Peripheral size in bytes for cfg device on rv_core_ibex in top earlgrey. */ - parameter int unsigned TOP_EARLGREY_RV_CORE_IBEX_REG_SIZE_BYTES = 32'h1000; + parameter int unsigned TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES = 32'h1000; /** * Memory base address for ram_main in top earlgrey.
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h index 31b90e9..1dbe6ea 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -854,22 +854,22 @@ #define TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES 0x4000u /** - * Peripheral base address for reg device on rv_core_ibex in top earlgrey. + * Peripheral base address for cfg device on rv_core_ibex in top earlgrey. * * This should be used with #mmio_region_from_addr to access the memory-mapped * registers associated with the peripheral (usually via a DIF). */ -#define TOP_EARLGREY_RV_CORE_IBEX_REG_BASE_ADDR 0x411F0000u +#define TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR 0x411F0000u /** - * Peripheral size for reg device on rv_core_ibex in top earlgrey. + * Peripheral size for cfg device on rv_core_ibex in top earlgrey. * * This is the size (in bytes) of the peripheral's reserved memory area. All * memory-mapped registers associated with this peripheral should have an - * address between #TOP_EARLGREY_RV_CORE_IBEX_REG_BASE_ADDR and - * `TOP_EARLGREY_RV_CORE_IBEX_REG_BASE_ADDR + TOP_EARLGREY_RV_CORE_IBEX_REG_SIZE_BYTES`. + * address between #TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR and + * `TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES`. */ -#define TOP_EARLGREY_RV_CORE_IBEX_REG_SIZE_BYTES 0x1000u +#define TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES 0x1000u /**
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h index 212dfd6..1c71811 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
@@ -386,12 +386,12 @@ */ #define TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR 0x8000 /** - * Peripheral base address for reg device on rv_core_ibex in top earlgrey. + * Peripheral base address for cfg device on rv_core_ibex in top earlgrey. * * This should be used with #mmio_region_from_addr to access the memory-mapped * registers associated with the peripheral (usually via a DIF). */ -#define TOP_EARLGREY_RV_CORE_IBEX_REG_BASE_ADDR 0x411F0000 +#define TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR 0x411F0000 #endif // __ASSEMBLER__ #endif // OPENTITAN_HW_TOP_EARLGREY_SW_AUTOGEN_TOP_EARLGREY_MEMORY_H_
diff --git a/sw/device/lib/ibex_peri.c b/sw/device/lib/ibex_peri.c index fb44daa..b5ef76a 100644 --- a/sw/device/lib/ibex_peri.c +++ b/sw/device/lib/ibex_peri.c
@@ -11,7 +11,7 @@ void init_translation(uint32_t src_addr, uint32_t size, uint32_t dst_addr) { mmio_region_t ibex_base = - mmio_region_from_addr(TOP_EARLGREY_RV_CORE_IBEX_REG_BASE_ADDR); + mmio_region_from_addr(TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR); uint32_t mask = src_addr | ((size - 1) >> 1); mmio_region_write32(ibex_base, RV_CORE_IBEX_IBUS_ADDR_MATCHING_0_REG_OFFSET,
diff --git a/util/topgen/intermodule.py b/util/topgen/intermodule.py index baeac36..2c761a1 100644 --- a/util/topgen/intermodule.py +++ b/util/topgen/intermodule.py
@@ -279,7 +279,7 @@ # Gather the inter_signal_list instances = topcfg["module"] + topcfg["memory"] + topcfg["xbar"] + \ - topcfg["host"] + topcfg["port"] + topcfg["port"] for x in instances: old_isl = x.get('inter_signal_list') @@ -662,12 +662,9 @@ """ # TODO: handle special cases special_inst_names = { - ('main', 'tl_rom'): ('tl_adapter_rom', 'tl'), ('main', 'tl_ram_main'): ('tl_adapter_ram_main', 'tl'), ('main', 'tl_eflash'): ('tl_adapter_eflash', 'tl'), ('peri', 'tl_ram_ret_aon'): ('tl_adapter_ram_ret_aon', 'tl'), - ('main', 'tl_dm_sba'): ('dm_top', 'tl_h'), - ('main', 'tl_debug_mem'): ('dm_top', 'tl_d'), ('peri', 'tl_ast'): ('ast', 'tl') } special_result = special_inst_names.get((m, s))