[primgen] Make primgen "portable" again Primgen is vendored into Ibex and there we don't have the full directory structure of OpenTitan, but only the primgen folder. To go back into a state where we can vendor primgen into Ibex, this commit does two things: * Move the vendored-in Verible Python code into a subdirectory of primgen. No functional change. * Remove the dependency on check_tool_requirements. We only use that dependency to show the version number of Verible in human-readable output for eventual debugging. I don't think we've ever used this information, so I'm just removing it for now to keep things simple, instead of reimplementing parts of the logic inside primgen. Signed-off-by: Philipp Wagner <phw@lowrisc.org>

diff --git a/hw/ip/prim/util/primgen.py b/hw/ip/prim/util/primgen.py
index b7a97cd..1d9d0f8 100755
--- a/hw/ip/prim/util/primgen.py
+++ b/hw/ip/prim/util/primgen.py

@@ -5,14 +5,8 @@
 import os
 import sys
 
-_SELF_DIR = os.path.dirname(__file__)
-_REPO_TOP = os.path.normpath(os.path.join(_SELF_DIR, '../../../../'))
-_UTIL_DIR = os.path.join(_REPO_TOP, 'util/')
-_VERIBLE_VERILOG_SYNTAX_PY_DIR = os.path.join(
-    _REPO_TOP, 'sw/host/vendor/google_verible_verilog_syntax_py/')
-
-sys.path.append(_UTIL_DIR)
-sys.path.append(_VERIBLE_VERILOG_SYNTAX_PY_DIR)
+# Make vendored packages available in the search path.
+sys.path.append('vendor')
 
 import re
 import shutil
@@ -22,7 +16,6 @@
 import yaml
 from mako.template import Template
 
-import check_tool_requirements  # noqa
 
 try:
     from yaml import CSafeLoader as YamlLoader, CSafeDumper as YamlDumper
@@ -108,7 +101,7 @@
     See _parse_module_header() for API details.
     """
 
-    from verible_verilog_syntax import VeribleVerilogSyntax, PreOrderTreeIterator
+    from google_verible_verilog_syntax_py.verible_verilog_syntax import VeribleVerilogSyntax, PreOrderTreeIterator
 
     parser = VeribleVerilogSyntax()
 
@@ -148,15 +141,6 @@
 
     ports = header.find({"tag": "kPortDeclarationList"})
 
-    try:
-        # Get Verible version for eventual debugging
-        tool_requirements = check_tool_requirements.read_tool_requirements()
-        verible_req = tool_requirements['verible']
-        verible_version = verible_req.get_version()
-        parser_info = f'Verible {verible_version}'
-    except:
-        parser_info = f'Verible'
-
     return {
         'module_header': header.text,
         'package_import_declaration': '\n'.join([i.text for i in imports]),
@@ -164,7 +148,7 @@
             parameters_list.text if parameters_list else '',
         'ports': ports.text if ports else '',
         'parameters': parameters,
-        'parser': parser_info
+        'parser': 'Verible'
     }
 
 

diff --git a/sw/host/vendor/google_verible_verilog_syntax_py.lock.hjson b/hw/ip/prim/util/vendor/google_verible_verilog_syntax_py.lock.hjson
similarity index 100%
rename from sw/host/vendor/google_verible_verilog_syntax_py.lock.hjson
rename to hw/ip/prim/util/vendor/google_verible_verilog_syntax_py.lock.hjson


diff --git a/sw/host/vendor/google_verible_verilog_syntax_py.vendor.hjson b/hw/ip/prim/util/vendor/google_verible_verilog_syntax_py.vendor.hjson
similarity index 100%
rename from sw/host/vendor/google_verible_verilog_syntax_py.vendor.hjson
rename to hw/ip/prim/util/vendor/google_verible_verilog_syntax_py.vendor.hjson


diff --git a/sw/host/vendor/google_verible_verilog_syntax_py/BUILD b/hw/ip/prim/util/vendor/google_verible_verilog_syntax_py/BUILD
similarity index 100%
rename from sw/host/vendor/google_verible_verilog_syntax_py/BUILD
rename to hw/ip/prim/util/vendor/google_verible_verilog_syntax_py/BUILD


diff --git a/sw/host/vendor/google_verible_verilog_syntax_py/print_modules.py b/hw/ip/prim/util/vendor/google_verible_verilog_syntax_py/print_modules.py
similarity index 100%
rename from sw/host/vendor/google_verible_verilog_syntax_py/print_modules.py
rename to hw/ip/prim/util/vendor/google_verible_verilog_syntax_py/print_modules.py


diff --git a/sw/host/vendor/google_verible_verilog_syntax_py/print_tree.py b/hw/ip/prim/util/vendor/google_verible_verilog_syntax_py/print_tree.py
similarity index 100%
rename from sw/host/vendor/google_verible_verilog_syntax_py/print_tree.py
rename to hw/ip/prim/util/vendor/google_verible_verilog_syntax_py/print_tree.py


diff --git a/sw/host/vendor/google_verible_verilog_syntax_py/verible_verilog_syntax.py b/hw/ip/prim/util/vendor/google_verible_verilog_syntax_py/verible_verilog_syntax.py
similarity index 100%
rename from sw/host/vendor/google_verible_verilog_syntax_py/verible_verilog_syntax.py
rename to hw/ip/prim/util/vendor/google_verible_verilog_syntax_py/verible_verilog_syntax.py


diff --git a/sw/host/vendor/google_verible_verilog_syntax_py/verible_verilog_syntax_test.py b/hw/ip/prim/util/vendor/google_verible_verilog_syntax_py/verible_verilog_syntax_test.py
similarity index 100%
rename from sw/host/vendor/google_verible_verilog_syntax_py/verible_verilog_syntax_test.py
rename to hw/ip/prim/util/vendor/google_verible_verilog_syntax_py/verible_verilog_syntax_test.py