hw/ip/i2c/dv/i2c_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: i2c

  // Top level dut name (sv module).
  dut: i2c

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: vcs

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:i2c_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/ip/i2c/data/i2c_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/ip/i2c/data/i2c.hjson"

  // Import additional common sim cfg files.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson"]

  // Add additional tops for simulation.
  sim_tops: ["i2c_bind", "sec_cm_prim_onehot_check_bind"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  // Default UVM test and seq class name.
  uvm_test: i2c_base_test
  uvm_test_seq: i2c_base_vseq

  // List of test specifications.
  tests: [
    {
      name: i2c_host_smoke
      uvm_test_seq: i2c_host_smoke_vseq
    }

    {
      name: i2c_host_override
      uvm_test_seq: i2c_host_override_vseq
      run_opts: ["+en_scb=0"]
    }

    {
      name: i2c_host_rx_oversample
      uvm_test_seq: i2c_host_rx_oversample_vseq
      run_opts: ["+test_timeout_ns=10_000_000"]
    }

    {
      name: i2c_host_fifo_watermark
      uvm_test_seq: i2c_host_fifo_watermark_vseq
    }

    {
      name: i2c_host_fifo_overflow
      uvm_test_seq: i2c_host_fifo_overflow_vseq
    }

    {
      name: i2c_host_fifo_reset_fmt
      uvm_test_seq: i2c_host_fifo_reset_fmt_vseq
      run_opts: ["+test_timeout_ns=10_000_000"]
    }

    {
      name: i2c_host_fifo_fmt_empty
      uvm_test_seq: i2c_host_fifo_fmt_empty_vseq
      run_opts: ["+test_timeout_ns=10_000_000"]
    }

    {
      name: i2c_host_fifo_reset_rx
      uvm_test_seq: i2c_host_fifo_reset_rx_vseq
      run_opts: ["+test_timeout_ns=10_000_000"]
    }

    {
      name: i2c_host_timeout
      uvm_test_seq: i2c_host_timeout_vseq
    }

    {
      name: i2c_host_fifo_full
      uvm_test_seq: i2c_host_fifo_full_vseq
    }

    {
      name: i2c_host_perf
      uvm_test_seq: i2c_host_perf_vseq
    }

    {
      name: i2c_host_stretch_timeout
      uvm_test_seq: i2c_host_stretch_timeout_vseq
    }

    {
      name: i2c_host_error_intr
      uvm_test_seq: i2c_host_error_intr_vseq
    }

    {
      name: i2c_host_stress_all
      uvm_test_seq: i2c_host_stress_all_vseq
    }
    {
      name: i2c_target_smoke
      uvm_test_seq: i2c_target_smoke_vseq
      run_opts: ["+i2c_agent_mode=Host", "+test_timeout_ns=10_000_000"]
    }
  ]

  // List of regressions.
  regressions: [
    {
       name: smoke
       tests: ["i2c_host_smoke"]
    }
  ]
}