[fpga] Add SRST delay option to OpenOCD args

This commit increases the SRST delay from the default of zero to 10 ms.
Now, OpenOCD will wait after deasserting SRST before it issues JTAG
commands. This is necessary to give the chip time to boot, since the
SRST signal is interpreted as POR.

The additional SRST delay eliminates these warnings from the log:

    [OPENOCD] Error: JTAG scan chain interrogation failed: all ones
    [OPENOCD] Error: Check JTAG interface, timings, target power, etc.

This commit also disables adaptive clock speed (RCLK) because we do not
support that feature. I don't have a great justification for the value
of 200 KHz, but it's less than the ARM-USB-TINY-H's max of 500 KHz and
it appears to work.

Signed-off-by: Dan McArdle <dmcardle@google.com>
1 file changed
tree: 2a8822ea44379634240b36d971e9129e8d737c84
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README.md

OpenTitan

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OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.

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