hw/ip/keymgr/dv/keymgr_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: keymgr

  // Top level dut name (sv module).
  dut: keymgr

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: vcs

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:keymgr_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/ip/keymgr/data/keymgr_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/ip/keymgr/data/keymgr.hjson"

  // Import additional common sim cfg files.
  // TODO: remove imported cfgs that do not apply.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"
                ]

  // Add additional tops for simulation.
  sim_tops: ["keymgr_bind", "keymgr_cov_bind", "sec_cm_prim_count_bind",
             "sec_cm_prim_sparse_fsm_flop_bind", "sec_cm_prim_onehot_check_bind"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  // Add UART specific exclusion files.
  vcs_cov_excl_files: ["{proj_root}/hw/ip/keymgr/dv/cov/keymgr_cov_excl.el"]

  // Default UVM test and seq class name.
  uvm_test: keymgr_base_test
  uvm_test_seq: keymgr_base_vseq

  // List of test specifications.
  tests: [
    {
      name: keymgr_smoke
      uvm_test_seq: keymgr_smoke_vseq
    }

    {
      name: keymgr_sideload
      uvm_test_seq: keymgr_sideload_vseq
    }

    {
      name: keymgr_sideload_kmac
      uvm_test_seq: keymgr_sideload_one_intf_vseq
      run_opts: ["+sideload_dest=Kmac"]
    }

    {
      name: keymgr_sideload_aes
      uvm_test_seq: keymgr_sideload_one_intf_vseq
      run_opts: ["+sideload_dest=Aes"]
    }

    {
      name: keymgr_sideload_otbn
      uvm_test_seq: keymgr_sideload_one_intf_vseq
      run_opts: ["+sideload_dest=Otbn"]
    }

    {
      name: keymgr_random
      uvm_test_seq: keymgr_random_vseq
    }

    {
      name: keymgr_cfg_regwen
      uvm_test_seq: keymgr_cfg_regwen_vseq
      // This test is to check reg programming is gated when cfg_regwen=0, it's timing sensitive
      run_opts: ["+zero_delays=1"]
    }

    {
      name: keymgr_direct_to_disabled
      uvm_test_seq: keymgr_direct_to_disabled_vseq
    }

    {
      name: keymgr_lc_disable
      uvm_test_seq: keymgr_lc_disable_vseq
    }

    {
      name: keymgr_sw_invalid_input
      uvm_test_seq: keymgr_sw_invalid_input_vseq
    }

    {
      name: keymgr_hwsw_invalid_input
      uvm_test_seq: keymgr_hwsw_invalid_input_vseq
    }

    {
      name: keymgr_kmac_rsp_err
      uvm_test_seq: keymgr_kmac_rsp_err_vseq
    }

    {
      name: keymgr_custom_cm
      uvm_test_seq: keymgr_custom_cm_vseq
    }

    {
      name: keymgr_sideload_protect
      uvm_test_seq: keymgr_sideload_protect_vseq
    }

    {
      name: keymgr_sync_async_fault_cross
      uvm_test_seq: keymgr_sync_async_fault_cross_vseq
    }

    {
      name: keymgr_stress_all
      uvm_test_seq: keymgr_stress_all_vseq
    }
  ]

  // List of regressions.
  regressions: [
    {
      name: smoke
      tests: ["keymgr_smoke"]
    }
  ]
}