| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| // Register Top module auto-generated by `reggen` |
| |
| `include "prim_assert.sv" |
| |
| module spi_device_reg_top ( |
| input clk_i, |
| input rst_ni, |
| input tlul_pkg::tl_h2d_t tl_i, |
| output tlul_pkg::tl_d2h_t tl_o, |
| |
| // Output port for window |
| output tlul_pkg::tl_h2d_t tl_win_o, |
| input tlul_pkg::tl_d2h_t tl_win_i, |
| |
| // To HW |
| output spi_device_reg_pkg::spi_device_reg2hw_t reg2hw, // Write |
| input spi_device_reg_pkg::spi_device_hw2reg_t hw2reg, // Read |
| |
| // Integrity check errors |
| output logic intg_err_o, |
| |
| // Config |
| input devmode_i // If 1, explicit error return for unmapped register access |
| ); |
| |
| import spi_device_reg_pkg::* ; |
| |
| localparam int AW = 13; |
| localparam int DW = 32; |
| localparam int DBW = DW/8; // Byte Width |
| |
| // register signals |
| logic reg_we; |
| logic reg_re; |
| logic [AW-1:0] reg_addr; |
| logic [DW-1:0] reg_wdata; |
| logic [DBW-1:0] reg_be; |
| logic [DW-1:0] reg_rdata; |
| logic reg_error; |
| |
| logic addrmiss, wr_err; |
| |
| logic [DW-1:0] reg_rdata_next; |
| logic reg_busy; |
| |
| tlul_pkg::tl_h2d_t tl_reg_h2d; |
| tlul_pkg::tl_d2h_t tl_reg_d2h; |
| |
| |
| // incoming payload check |
| logic intg_err; |
| tlul_cmd_intg_chk u_chk ( |
| .tl_i(tl_i), |
| .err_o(intg_err) |
| ); |
| |
| // also check for spurious write enables |
| logic reg_we_err; |
| logic [78:0] reg_we_check; |
| prim_reg_we_check #( |
| .OneHotWidth(79) |
| ) u_prim_reg_we_check ( |
| .clk_i(clk_i), |
| .rst_ni(rst_ni), |
| .oh_i (reg_we_check), |
| .en_i (reg_we && !addrmiss), |
| .err_o (reg_we_err) |
| ); |
| |
| logic err_q; |
| always_ff @(posedge clk_i or negedge rst_ni) begin |
| if (!rst_ni) begin |
| err_q <= '0; |
| end else if (intg_err || reg_we_err) begin |
| err_q <= 1'b1; |
| end |
| end |
| |
| // integrity error output is permanent and should be used for alert generation |
| // register errors are transactional |
| assign intg_err_o = err_q | intg_err | reg_we_err; |
| |
| // outgoing integrity generation |
| tlul_pkg::tl_d2h_t tl_o_pre; |
| tlul_rsp_intg_gen #( |
| .EnableRspIntgGen(1), |
| .EnableDataIntgGen(1) |
| ) u_rsp_intg_gen ( |
| .tl_i(tl_o_pre), |
| .tl_o(tl_o) |
| ); |
| |
| tlul_pkg::tl_h2d_t tl_socket_h2d [2]; |
| tlul_pkg::tl_d2h_t tl_socket_d2h [2]; |
| |
| logic [0:0] reg_steer; |
| |
| // socket_1n connection |
| assign tl_reg_h2d = tl_socket_h2d[1]; |
| assign tl_socket_d2h[1] = tl_reg_d2h; |
| |
| assign tl_win_o = tl_socket_h2d[0]; |
| assign tl_socket_d2h[0] = tl_win_i; |
| |
| // Create Socket_1n |
| tlul_socket_1n #( |
| .N (2), |
| .HReqPass (1'b1), |
| .HRspPass (1'b1), |
| .DReqPass ({2{1'b1}}), |
| .DRspPass ({2{1'b1}}), |
| .HReqDepth (4'h0), |
| .HRspDepth (4'h0), |
| .DReqDepth ({2{4'h0}}), |
| .DRspDepth ({2{4'h0}}), |
| .ExplicitErrs (1'b0) |
| ) u_socket ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| .tl_h_i (tl_i), |
| .tl_h_o (tl_o_pre), |
| .tl_d_o (tl_socket_h2d), |
| .tl_d_i (tl_socket_d2h), |
| .dev_select_i (reg_steer) |
| ); |
| |
| // Create steering logic |
| always_comb begin |
| reg_steer = |
| tl_i.a_address[AW-1:0] inside {[4096:8191]} ? 1'd0 : |
| // Default set to register |
| 1'd1; |
| |
| // Override this in case of an integrity error |
| if (intg_err) begin |
| reg_steer = 1'd1; |
| end |
| end |
| |
| tlul_adapter_reg #( |
| .RegAw(AW), |
| .RegDw(DW), |
| .EnableDataIntgGen(0) |
| ) u_reg_if ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| .tl_i (tl_reg_h2d), |
| .tl_o (tl_reg_d2h), |
| |
| .en_ifetch_i(prim_mubi_pkg::MuBi4False), |
| .intg_error_o(), |
| |
| .we_o (reg_we), |
| .re_o (reg_re), |
| .addr_o (reg_addr), |
| .wdata_o (reg_wdata), |
| .be_o (reg_be), |
| .busy_i (reg_busy), |
| .rdata_i (reg_rdata), |
| .error_i (reg_error) |
| ); |
| |
| // cdc oversampling signals |
| |
| assign reg_rdata = reg_rdata_next ; |
| assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err; |
| |
| // Define SW related signals |
| // Format: <reg>_<field>_{wd|we|qs} |
| // or <reg>_{wd|we|qs} if field == 1 or 0 |
| logic intr_state_we; |
| logic intr_state_generic_rx_full_qs; |
| logic intr_state_generic_rx_full_wd; |
| logic intr_state_generic_rx_watermark_qs; |
| logic intr_state_generic_rx_watermark_wd; |
| logic intr_state_generic_tx_watermark_qs; |
| logic intr_state_generic_tx_watermark_wd; |
| logic intr_state_generic_rx_error_qs; |
| logic intr_state_generic_rx_error_wd; |
| logic intr_state_generic_rx_overflow_qs; |
| logic intr_state_generic_rx_overflow_wd; |
| logic intr_state_generic_tx_underflow_qs; |
| logic intr_state_generic_tx_underflow_wd; |
| logic intr_state_upload_cmdfifo_not_empty_qs; |
| logic intr_state_upload_cmdfifo_not_empty_wd; |
| logic intr_state_upload_payload_not_empty_qs; |
| logic intr_state_upload_payload_not_empty_wd; |
| logic intr_state_upload_payload_overflow_qs; |
| logic intr_state_upload_payload_overflow_wd; |
| logic intr_state_readbuf_watermark_qs; |
| logic intr_state_readbuf_watermark_wd; |
| logic intr_state_readbuf_flip_qs; |
| logic intr_state_readbuf_flip_wd; |
| logic intr_state_tpm_header_not_empty_qs; |
| logic intr_enable_we; |
| logic intr_enable_generic_rx_full_qs; |
| logic intr_enable_generic_rx_full_wd; |
| logic intr_enable_generic_rx_watermark_qs; |
| logic intr_enable_generic_rx_watermark_wd; |
| logic intr_enable_generic_tx_watermark_qs; |
| logic intr_enable_generic_tx_watermark_wd; |
| logic intr_enable_generic_rx_error_qs; |
| logic intr_enable_generic_rx_error_wd; |
| logic intr_enable_generic_rx_overflow_qs; |
| logic intr_enable_generic_rx_overflow_wd; |
| logic intr_enable_generic_tx_underflow_qs; |
| logic intr_enable_generic_tx_underflow_wd; |
| logic intr_enable_upload_cmdfifo_not_empty_qs; |
| logic intr_enable_upload_cmdfifo_not_empty_wd; |
| logic intr_enable_upload_payload_not_empty_qs; |
| logic intr_enable_upload_payload_not_empty_wd; |
| logic intr_enable_upload_payload_overflow_qs; |
| logic intr_enable_upload_payload_overflow_wd; |
| logic intr_enable_readbuf_watermark_qs; |
| logic intr_enable_readbuf_watermark_wd; |
| logic intr_enable_readbuf_flip_qs; |
| logic intr_enable_readbuf_flip_wd; |
| logic intr_enable_tpm_header_not_empty_qs; |
| logic intr_enable_tpm_header_not_empty_wd; |
| logic intr_test_we; |
| logic intr_test_generic_rx_full_wd; |
| logic intr_test_generic_rx_watermark_wd; |
| logic intr_test_generic_tx_watermark_wd; |
| logic intr_test_generic_rx_error_wd; |
| logic intr_test_generic_rx_overflow_wd; |
| logic intr_test_generic_tx_underflow_wd; |
| logic intr_test_upload_cmdfifo_not_empty_wd; |
| logic intr_test_upload_payload_not_empty_wd; |
| logic intr_test_upload_payload_overflow_wd; |
| logic intr_test_readbuf_watermark_wd; |
| logic intr_test_readbuf_flip_wd; |
| logic intr_test_tpm_header_not_empty_wd; |
| logic alert_test_we; |
| logic alert_test_wd; |
| logic control_we; |
| logic control_abort_qs; |
| logic control_abort_wd; |
| logic [1:0] control_mode_qs; |
| logic [1:0] control_mode_wd; |
| logic control_rst_txfifo_qs; |
| logic control_rst_txfifo_wd; |
| logic control_rst_rxfifo_qs; |
| logic control_rst_rxfifo_wd; |
| logic control_sram_clk_en_qs; |
| logic control_sram_clk_en_wd; |
| logic cfg_we; |
| logic cfg_cpol_qs; |
| logic cfg_cpol_wd; |
| logic cfg_cpha_qs; |
| logic cfg_cpha_wd; |
| logic cfg_tx_order_qs; |
| logic cfg_tx_order_wd; |
| logic cfg_rx_order_qs; |
| logic cfg_rx_order_wd; |
| logic [7:0] cfg_timer_v_qs; |
| logic [7:0] cfg_timer_v_wd; |
| logic cfg_addr_4b_en_qs; |
| logic cfg_addr_4b_en_wd; |
| logic cfg_mailbox_en_qs; |
| logic cfg_mailbox_en_wd; |
| logic fifo_level_we; |
| logic [15:0] fifo_level_rxlvl_qs; |
| logic [15:0] fifo_level_rxlvl_wd; |
| logic [15:0] fifo_level_txlvl_qs; |
| logic [15:0] fifo_level_txlvl_wd; |
| logic async_fifo_level_re; |
| logic [7:0] async_fifo_level_rxlvl_qs; |
| logic [7:0] async_fifo_level_txlvl_qs; |
| logic status_re; |
| logic status_rxf_full_qs; |
| logic status_rxf_empty_qs; |
| logic status_txf_full_qs; |
| logic status_txf_empty_qs; |
| logic status_abort_done_qs; |
| logic status_csb_qs; |
| logic status_tpm_csb_qs; |
| logic rxf_ptr_we; |
| logic [15:0] rxf_ptr_rptr_qs; |
| logic [15:0] rxf_ptr_rptr_wd; |
| logic [15:0] rxf_ptr_wptr_qs; |
| logic txf_ptr_we; |
| logic [15:0] txf_ptr_rptr_qs; |
| logic [15:0] txf_ptr_wptr_qs; |
| logic [15:0] txf_ptr_wptr_wd; |
| logic rxf_addr_we; |
| logic [15:0] rxf_addr_base_qs; |
| logic [15:0] rxf_addr_base_wd; |
| logic [15:0] rxf_addr_limit_qs; |
| logic [15:0] rxf_addr_limit_wd; |
| logic txf_addr_we; |
| logic [15:0] txf_addr_base_qs; |
| logic [15:0] txf_addr_base_wd; |
| logic [15:0] txf_addr_limit_qs; |
| logic [15:0] txf_addr_limit_wd; |
| logic intercept_en_we; |
| logic intercept_en_status_qs; |
| logic intercept_en_status_wd; |
| logic intercept_en_jedec_qs; |
| logic intercept_en_jedec_wd; |
| logic intercept_en_sfdp_qs; |
| logic intercept_en_sfdp_wd; |
| logic intercept_en_mbx_qs; |
| logic intercept_en_mbx_wd; |
| logic last_read_addr_re; |
| logic [31:0] last_read_addr_qs; |
| logic flash_status_re; |
| logic flash_status_we; |
| logic flash_status_busy_qs; |
| logic flash_status_busy_wd; |
| logic [22:0] flash_status_status_qs; |
| logic [22:0] flash_status_status_wd; |
| logic jedec_cc_we; |
| logic [7:0] jedec_cc_cc_qs; |
| logic [7:0] jedec_cc_cc_wd; |
| logic [7:0] jedec_cc_num_cc_qs; |
| logic [7:0] jedec_cc_num_cc_wd; |
| logic jedec_id_we; |
| logic [15:0] jedec_id_id_qs; |
| logic [15:0] jedec_id_id_wd; |
| logic [7:0] jedec_id_mf_qs; |
| logic [7:0] jedec_id_mf_wd; |
| logic read_threshold_we; |
| logic [9:0] read_threshold_qs; |
| logic [9:0] read_threshold_wd; |
| logic mailbox_addr_we; |
| logic [31:0] mailbox_addr_qs; |
| logic [31:0] mailbox_addr_wd; |
| logic [4:0] upload_status_cmdfifo_depth_qs; |
| logic upload_status_cmdfifo_notempty_qs; |
| logic [4:0] upload_status_addrfifo_depth_qs; |
| logic upload_status_addrfifo_notempty_qs; |
| logic [8:0] upload_status2_payload_depth_qs; |
| logic [7:0] upload_status2_payload_start_idx_qs; |
| logic upload_cmdfifo_re; |
| logic [7:0] upload_cmdfifo_qs; |
| logic upload_addrfifo_re; |
| logic [31:0] upload_addrfifo_qs; |
| logic cmd_filter_0_we; |
| logic cmd_filter_0_filter_0_qs; |
| logic cmd_filter_0_filter_0_wd; |
| logic cmd_filter_0_filter_1_qs; |
| logic cmd_filter_0_filter_1_wd; |
| logic cmd_filter_0_filter_2_qs; |
| logic cmd_filter_0_filter_2_wd; |
| logic cmd_filter_0_filter_3_qs; |
| logic cmd_filter_0_filter_3_wd; |
| logic cmd_filter_0_filter_4_qs; |
| logic cmd_filter_0_filter_4_wd; |
| logic cmd_filter_0_filter_5_qs; |
| logic cmd_filter_0_filter_5_wd; |
| logic cmd_filter_0_filter_6_qs; |
| logic cmd_filter_0_filter_6_wd; |
| logic cmd_filter_0_filter_7_qs; |
| logic cmd_filter_0_filter_7_wd; |
| logic cmd_filter_0_filter_8_qs; |
| logic cmd_filter_0_filter_8_wd; |
| logic cmd_filter_0_filter_9_qs; |
| logic cmd_filter_0_filter_9_wd; |
| logic cmd_filter_0_filter_10_qs; |
| logic cmd_filter_0_filter_10_wd; |
| logic cmd_filter_0_filter_11_qs; |
| logic cmd_filter_0_filter_11_wd; |
| logic cmd_filter_0_filter_12_qs; |
| logic cmd_filter_0_filter_12_wd; |
| logic cmd_filter_0_filter_13_qs; |
| logic cmd_filter_0_filter_13_wd; |
| logic cmd_filter_0_filter_14_qs; |
| logic cmd_filter_0_filter_14_wd; |
| logic cmd_filter_0_filter_15_qs; |
| logic cmd_filter_0_filter_15_wd; |
| logic cmd_filter_0_filter_16_qs; |
| logic cmd_filter_0_filter_16_wd; |
| logic cmd_filter_0_filter_17_qs; |
| logic cmd_filter_0_filter_17_wd; |
| logic cmd_filter_0_filter_18_qs; |
| logic cmd_filter_0_filter_18_wd; |
| logic cmd_filter_0_filter_19_qs; |
| logic cmd_filter_0_filter_19_wd; |
| logic cmd_filter_0_filter_20_qs; |
| logic cmd_filter_0_filter_20_wd; |
| logic cmd_filter_0_filter_21_qs; |
| logic cmd_filter_0_filter_21_wd; |
| logic cmd_filter_0_filter_22_qs; |
| logic cmd_filter_0_filter_22_wd; |
| logic cmd_filter_0_filter_23_qs; |
| logic cmd_filter_0_filter_23_wd; |
| logic cmd_filter_0_filter_24_qs; |
| logic cmd_filter_0_filter_24_wd; |
| logic cmd_filter_0_filter_25_qs; |
| logic cmd_filter_0_filter_25_wd; |
| logic cmd_filter_0_filter_26_qs; |
| logic cmd_filter_0_filter_26_wd; |
| logic cmd_filter_0_filter_27_qs; |
| logic cmd_filter_0_filter_27_wd; |
| logic cmd_filter_0_filter_28_qs; |
| logic cmd_filter_0_filter_28_wd; |
| logic cmd_filter_0_filter_29_qs; |
| logic cmd_filter_0_filter_29_wd; |
| logic cmd_filter_0_filter_30_qs; |
| logic cmd_filter_0_filter_30_wd; |
| logic cmd_filter_0_filter_31_qs; |
| logic cmd_filter_0_filter_31_wd; |
| logic cmd_filter_1_we; |
| logic cmd_filter_1_filter_32_qs; |
| logic cmd_filter_1_filter_32_wd; |
| logic cmd_filter_1_filter_33_qs; |
| logic cmd_filter_1_filter_33_wd; |
| logic cmd_filter_1_filter_34_qs; |
| logic cmd_filter_1_filter_34_wd; |
| logic cmd_filter_1_filter_35_qs; |
| logic cmd_filter_1_filter_35_wd; |
| logic cmd_filter_1_filter_36_qs; |
| logic cmd_filter_1_filter_36_wd; |
| logic cmd_filter_1_filter_37_qs; |
| logic cmd_filter_1_filter_37_wd; |
| logic cmd_filter_1_filter_38_qs; |
| logic cmd_filter_1_filter_38_wd; |
| logic cmd_filter_1_filter_39_qs; |
| logic cmd_filter_1_filter_39_wd; |
| logic cmd_filter_1_filter_40_qs; |
| logic cmd_filter_1_filter_40_wd; |
| logic cmd_filter_1_filter_41_qs; |
| logic cmd_filter_1_filter_41_wd; |
| logic cmd_filter_1_filter_42_qs; |
| logic cmd_filter_1_filter_42_wd; |
| logic cmd_filter_1_filter_43_qs; |
| logic cmd_filter_1_filter_43_wd; |
| logic cmd_filter_1_filter_44_qs; |
| logic cmd_filter_1_filter_44_wd; |
| logic cmd_filter_1_filter_45_qs; |
| logic cmd_filter_1_filter_45_wd; |
| logic cmd_filter_1_filter_46_qs; |
| logic cmd_filter_1_filter_46_wd; |
| logic cmd_filter_1_filter_47_qs; |
| logic cmd_filter_1_filter_47_wd; |
| logic cmd_filter_1_filter_48_qs; |
| logic cmd_filter_1_filter_48_wd; |
| logic cmd_filter_1_filter_49_qs; |
| logic cmd_filter_1_filter_49_wd; |
| logic cmd_filter_1_filter_50_qs; |
| logic cmd_filter_1_filter_50_wd; |
| logic cmd_filter_1_filter_51_qs; |
| logic cmd_filter_1_filter_51_wd; |
| logic cmd_filter_1_filter_52_qs; |
| logic cmd_filter_1_filter_52_wd; |
| logic cmd_filter_1_filter_53_qs; |
| logic cmd_filter_1_filter_53_wd; |
| logic cmd_filter_1_filter_54_qs; |
| logic cmd_filter_1_filter_54_wd; |
| logic cmd_filter_1_filter_55_qs; |
| logic cmd_filter_1_filter_55_wd; |
| logic cmd_filter_1_filter_56_qs; |
| logic cmd_filter_1_filter_56_wd; |
| logic cmd_filter_1_filter_57_qs; |
| logic cmd_filter_1_filter_57_wd; |
| logic cmd_filter_1_filter_58_qs; |
| logic cmd_filter_1_filter_58_wd; |
| logic cmd_filter_1_filter_59_qs; |
| logic cmd_filter_1_filter_59_wd; |
| logic cmd_filter_1_filter_60_qs; |
| logic cmd_filter_1_filter_60_wd; |
| logic cmd_filter_1_filter_61_qs; |
| logic cmd_filter_1_filter_61_wd; |
| logic cmd_filter_1_filter_62_qs; |
| logic cmd_filter_1_filter_62_wd; |
| logic cmd_filter_1_filter_63_qs; |
| logic cmd_filter_1_filter_63_wd; |
| logic cmd_filter_2_we; |
| logic cmd_filter_2_filter_64_qs; |
| logic cmd_filter_2_filter_64_wd; |
| logic cmd_filter_2_filter_65_qs; |
| logic cmd_filter_2_filter_65_wd; |
| logic cmd_filter_2_filter_66_qs; |
| logic cmd_filter_2_filter_66_wd; |
| logic cmd_filter_2_filter_67_qs; |
| logic cmd_filter_2_filter_67_wd; |
| logic cmd_filter_2_filter_68_qs; |
| logic cmd_filter_2_filter_68_wd; |
| logic cmd_filter_2_filter_69_qs; |
| logic cmd_filter_2_filter_69_wd; |
| logic cmd_filter_2_filter_70_qs; |
| logic cmd_filter_2_filter_70_wd; |
| logic cmd_filter_2_filter_71_qs; |
| logic cmd_filter_2_filter_71_wd; |
| logic cmd_filter_2_filter_72_qs; |
| logic cmd_filter_2_filter_72_wd; |
| logic cmd_filter_2_filter_73_qs; |
| logic cmd_filter_2_filter_73_wd; |
| logic cmd_filter_2_filter_74_qs; |
| logic cmd_filter_2_filter_74_wd; |
| logic cmd_filter_2_filter_75_qs; |
| logic cmd_filter_2_filter_75_wd; |
| logic cmd_filter_2_filter_76_qs; |
| logic cmd_filter_2_filter_76_wd; |
| logic cmd_filter_2_filter_77_qs; |
| logic cmd_filter_2_filter_77_wd; |
| logic cmd_filter_2_filter_78_qs; |
| logic cmd_filter_2_filter_78_wd; |
| logic cmd_filter_2_filter_79_qs; |
| logic cmd_filter_2_filter_79_wd; |
| logic cmd_filter_2_filter_80_qs; |
| logic cmd_filter_2_filter_80_wd; |
| logic cmd_filter_2_filter_81_qs; |
| logic cmd_filter_2_filter_81_wd; |
| logic cmd_filter_2_filter_82_qs; |
| logic cmd_filter_2_filter_82_wd; |
| logic cmd_filter_2_filter_83_qs; |
| logic cmd_filter_2_filter_83_wd; |
| logic cmd_filter_2_filter_84_qs; |
| logic cmd_filter_2_filter_84_wd; |
| logic cmd_filter_2_filter_85_qs; |
| logic cmd_filter_2_filter_85_wd; |
| logic cmd_filter_2_filter_86_qs; |
| logic cmd_filter_2_filter_86_wd; |
| logic cmd_filter_2_filter_87_qs; |
| logic cmd_filter_2_filter_87_wd; |
| logic cmd_filter_2_filter_88_qs; |
| logic cmd_filter_2_filter_88_wd; |
| logic cmd_filter_2_filter_89_qs; |
| logic cmd_filter_2_filter_89_wd; |
| logic cmd_filter_2_filter_90_qs; |
| logic cmd_filter_2_filter_90_wd; |
| logic cmd_filter_2_filter_91_qs; |
| logic cmd_filter_2_filter_91_wd; |
| logic cmd_filter_2_filter_92_qs; |
| logic cmd_filter_2_filter_92_wd; |
| logic cmd_filter_2_filter_93_qs; |
| logic cmd_filter_2_filter_93_wd; |
| logic cmd_filter_2_filter_94_qs; |
| logic cmd_filter_2_filter_94_wd; |
| logic cmd_filter_2_filter_95_qs; |
| logic cmd_filter_2_filter_95_wd; |
| logic cmd_filter_3_we; |
| logic cmd_filter_3_filter_96_qs; |
| logic cmd_filter_3_filter_96_wd; |
| logic cmd_filter_3_filter_97_qs; |
| logic cmd_filter_3_filter_97_wd; |
| logic cmd_filter_3_filter_98_qs; |
| logic cmd_filter_3_filter_98_wd; |
| logic cmd_filter_3_filter_99_qs; |
| logic cmd_filter_3_filter_99_wd; |
| logic cmd_filter_3_filter_100_qs; |
| logic cmd_filter_3_filter_100_wd; |
| logic cmd_filter_3_filter_101_qs; |
| logic cmd_filter_3_filter_101_wd; |
| logic cmd_filter_3_filter_102_qs; |
| logic cmd_filter_3_filter_102_wd; |
| logic cmd_filter_3_filter_103_qs; |
| logic cmd_filter_3_filter_103_wd; |
| logic cmd_filter_3_filter_104_qs; |
| logic cmd_filter_3_filter_104_wd; |
| logic cmd_filter_3_filter_105_qs; |
| logic cmd_filter_3_filter_105_wd; |
| logic cmd_filter_3_filter_106_qs; |
| logic cmd_filter_3_filter_106_wd; |
| logic cmd_filter_3_filter_107_qs; |
| logic cmd_filter_3_filter_107_wd; |
| logic cmd_filter_3_filter_108_qs; |
| logic cmd_filter_3_filter_108_wd; |
| logic cmd_filter_3_filter_109_qs; |
| logic cmd_filter_3_filter_109_wd; |
| logic cmd_filter_3_filter_110_qs; |
| logic cmd_filter_3_filter_110_wd; |
| logic cmd_filter_3_filter_111_qs; |
| logic cmd_filter_3_filter_111_wd; |
| logic cmd_filter_3_filter_112_qs; |
| logic cmd_filter_3_filter_112_wd; |
| logic cmd_filter_3_filter_113_qs; |
| logic cmd_filter_3_filter_113_wd; |
| logic cmd_filter_3_filter_114_qs; |
| logic cmd_filter_3_filter_114_wd; |
| logic cmd_filter_3_filter_115_qs; |
| logic cmd_filter_3_filter_115_wd; |
| logic cmd_filter_3_filter_116_qs; |
| logic cmd_filter_3_filter_116_wd; |
| logic cmd_filter_3_filter_117_qs; |
| logic cmd_filter_3_filter_117_wd; |
| logic cmd_filter_3_filter_118_qs; |
| logic cmd_filter_3_filter_118_wd; |
| logic cmd_filter_3_filter_119_qs; |
| logic cmd_filter_3_filter_119_wd; |
| logic cmd_filter_3_filter_120_qs; |
| logic cmd_filter_3_filter_120_wd; |
| logic cmd_filter_3_filter_121_qs; |
| logic cmd_filter_3_filter_121_wd; |
| logic cmd_filter_3_filter_122_qs; |
| logic cmd_filter_3_filter_122_wd; |
| logic cmd_filter_3_filter_123_qs; |
| logic cmd_filter_3_filter_123_wd; |
| logic cmd_filter_3_filter_124_qs; |
| logic cmd_filter_3_filter_124_wd; |
| logic cmd_filter_3_filter_125_qs; |
| logic cmd_filter_3_filter_125_wd; |
| logic cmd_filter_3_filter_126_qs; |
| logic cmd_filter_3_filter_126_wd; |
| logic cmd_filter_3_filter_127_qs; |
| logic cmd_filter_3_filter_127_wd; |
| logic cmd_filter_4_we; |
| logic cmd_filter_4_filter_128_qs; |
| logic cmd_filter_4_filter_128_wd; |
| logic cmd_filter_4_filter_129_qs; |
| logic cmd_filter_4_filter_129_wd; |
| logic cmd_filter_4_filter_130_qs; |
| logic cmd_filter_4_filter_130_wd; |
| logic cmd_filter_4_filter_131_qs; |
| logic cmd_filter_4_filter_131_wd; |
| logic cmd_filter_4_filter_132_qs; |
| logic cmd_filter_4_filter_132_wd; |
| logic cmd_filter_4_filter_133_qs; |
| logic cmd_filter_4_filter_133_wd; |
| logic cmd_filter_4_filter_134_qs; |
| logic cmd_filter_4_filter_134_wd; |
| logic cmd_filter_4_filter_135_qs; |
| logic cmd_filter_4_filter_135_wd; |
| logic cmd_filter_4_filter_136_qs; |
| logic cmd_filter_4_filter_136_wd; |
| logic cmd_filter_4_filter_137_qs; |
| logic cmd_filter_4_filter_137_wd; |
| logic cmd_filter_4_filter_138_qs; |
| logic cmd_filter_4_filter_138_wd; |
| logic cmd_filter_4_filter_139_qs; |
| logic cmd_filter_4_filter_139_wd; |
| logic cmd_filter_4_filter_140_qs; |
| logic cmd_filter_4_filter_140_wd; |
| logic cmd_filter_4_filter_141_qs; |
| logic cmd_filter_4_filter_141_wd; |
| logic cmd_filter_4_filter_142_qs; |
| logic cmd_filter_4_filter_142_wd; |
| logic cmd_filter_4_filter_143_qs; |
| logic cmd_filter_4_filter_143_wd; |
| logic cmd_filter_4_filter_144_qs; |
| logic cmd_filter_4_filter_144_wd; |
| logic cmd_filter_4_filter_145_qs; |
| logic cmd_filter_4_filter_145_wd; |
| logic cmd_filter_4_filter_146_qs; |
| logic cmd_filter_4_filter_146_wd; |
| logic cmd_filter_4_filter_147_qs; |
| logic cmd_filter_4_filter_147_wd; |
| logic cmd_filter_4_filter_148_qs; |
| logic cmd_filter_4_filter_148_wd; |
| logic cmd_filter_4_filter_149_qs; |
| logic cmd_filter_4_filter_149_wd; |
| logic cmd_filter_4_filter_150_qs; |
| logic cmd_filter_4_filter_150_wd; |
| logic cmd_filter_4_filter_151_qs; |
| logic cmd_filter_4_filter_151_wd; |
| logic cmd_filter_4_filter_152_qs; |
| logic cmd_filter_4_filter_152_wd; |
| logic cmd_filter_4_filter_153_qs; |
| logic cmd_filter_4_filter_153_wd; |
| logic cmd_filter_4_filter_154_qs; |
| logic cmd_filter_4_filter_154_wd; |
| logic cmd_filter_4_filter_155_qs; |
| logic cmd_filter_4_filter_155_wd; |
| logic cmd_filter_4_filter_156_qs; |
| logic cmd_filter_4_filter_156_wd; |
| logic cmd_filter_4_filter_157_qs; |
| logic cmd_filter_4_filter_157_wd; |
| logic cmd_filter_4_filter_158_qs; |
| logic cmd_filter_4_filter_158_wd; |
| logic cmd_filter_4_filter_159_qs; |
| logic cmd_filter_4_filter_159_wd; |
| logic cmd_filter_5_we; |
| logic cmd_filter_5_filter_160_qs; |
| logic cmd_filter_5_filter_160_wd; |
| logic cmd_filter_5_filter_161_qs; |
| logic cmd_filter_5_filter_161_wd; |
| logic cmd_filter_5_filter_162_qs; |
| logic cmd_filter_5_filter_162_wd; |
| logic cmd_filter_5_filter_163_qs; |
| logic cmd_filter_5_filter_163_wd; |
| logic cmd_filter_5_filter_164_qs; |
| logic cmd_filter_5_filter_164_wd; |
| logic cmd_filter_5_filter_165_qs; |
| logic cmd_filter_5_filter_165_wd; |
| logic cmd_filter_5_filter_166_qs; |
| logic cmd_filter_5_filter_166_wd; |
| logic cmd_filter_5_filter_167_qs; |
| logic cmd_filter_5_filter_167_wd; |
| logic cmd_filter_5_filter_168_qs; |
| logic cmd_filter_5_filter_168_wd; |
| logic cmd_filter_5_filter_169_qs; |
| logic cmd_filter_5_filter_169_wd; |
| logic cmd_filter_5_filter_170_qs; |
| logic cmd_filter_5_filter_170_wd; |
| logic cmd_filter_5_filter_171_qs; |
| logic cmd_filter_5_filter_171_wd; |
| logic cmd_filter_5_filter_172_qs; |
| logic cmd_filter_5_filter_172_wd; |
| logic cmd_filter_5_filter_173_qs; |
| logic cmd_filter_5_filter_173_wd; |
| logic cmd_filter_5_filter_174_qs; |
| logic cmd_filter_5_filter_174_wd; |
| logic cmd_filter_5_filter_175_qs; |
| logic cmd_filter_5_filter_175_wd; |
| logic cmd_filter_5_filter_176_qs; |
| logic cmd_filter_5_filter_176_wd; |
| logic cmd_filter_5_filter_177_qs; |
| logic cmd_filter_5_filter_177_wd; |
| logic cmd_filter_5_filter_178_qs; |
| logic cmd_filter_5_filter_178_wd; |
| logic cmd_filter_5_filter_179_qs; |
| logic cmd_filter_5_filter_179_wd; |
| logic cmd_filter_5_filter_180_qs; |
| logic cmd_filter_5_filter_180_wd; |
| logic cmd_filter_5_filter_181_qs; |
| logic cmd_filter_5_filter_181_wd; |
| logic cmd_filter_5_filter_182_qs; |
| logic cmd_filter_5_filter_182_wd; |
| logic cmd_filter_5_filter_183_qs; |
| logic cmd_filter_5_filter_183_wd; |
| logic cmd_filter_5_filter_184_qs; |
| logic cmd_filter_5_filter_184_wd; |
| logic cmd_filter_5_filter_185_qs; |
| logic cmd_filter_5_filter_185_wd; |
| logic cmd_filter_5_filter_186_qs; |
| logic cmd_filter_5_filter_186_wd; |
| logic cmd_filter_5_filter_187_qs; |
| logic cmd_filter_5_filter_187_wd; |
| logic cmd_filter_5_filter_188_qs; |
| logic cmd_filter_5_filter_188_wd; |
| logic cmd_filter_5_filter_189_qs; |
| logic cmd_filter_5_filter_189_wd; |
| logic cmd_filter_5_filter_190_qs; |
| logic cmd_filter_5_filter_190_wd; |
| logic cmd_filter_5_filter_191_qs; |
| logic cmd_filter_5_filter_191_wd; |
| logic cmd_filter_6_we; |
| logic cmd_filter_6_filter_192_qs; |
| logic cmd_filter_6_filter_192_wd; |
| logic cmd_filter_6_filter_193_qs; |
| logic cmd_filter_6_filter_193_wd; |
| logic cmd_filter_6_filter_194_qs; |
| logic cmd_filter_6_filter_194_wd; |
| logic cmd_filter_6_filter_195_qs; |
| logic cmd_filter_6_filter_195_wd; |
| logic cmd_filter_6_filter_196_qs; |
| logic cmd_filter_6_filter_196_wd; |
| logic cmd_filter_6_filter_197_qs; |
| logic cmd_filter_6_filter_197_wd; |
| logic cmd_filter_6_filter_198_qs; |
| logic cmd_filter_6_filter_198_wd; |
| logic cmd_filter_6_filter_199_qs; |
| logic cmd_filter_6_filter_199_wd; |
| logic cmd_filter_6_filter_200_qs; |
| logic cmd_filter_6_filter_200_wd; |
| logic cmd_filter_6_filter_201_qs; |
| logic cmd_filter_6_filter_201_wd; |
| logic cmd_filter_6_filter_202_qs; |
| logic cmd_filter_6_filter_202_wd; |
| logic cmd_filter_6_filter_203_qs; |
| logic cmd_filter_6_filter_203_wd; |
| logic cmd_filter_6_filter_204_qs; |
| logic cmd_filter_6_filter_204_wd; |
| logic cmd_filter_6_filter_205_qs; |
| logic cmd_filter_6_filter_205_wd; |
| logic cmd_filter_6_filter_206_qs; |
| logic cmd_filter_6_filter_206_wd; |
| logic cmd_filter_6_filter_207_qs; |
| logic cmd_filter_6_filter_207_wd; |
| logic cmd_filter_6_filter_208_qs; |
| logic cmd_filter_6_filter_208_wd; |
| logic cmd_filter_6_filter_209_qs; |
| logic cmd_filter_6_filter_209_wd; |
| logic cmd_filter_6_filter_210_qs; |
| logic cmd_filter_6_filter_210_wd; |
| logic cmd_filter_6_filter_211_qs; |
| logic cmd_filter_6_filter_211_wd; |
| logic cmd_filter_6_filter_212_qs; |
| logic cmd_filter_6_filter_212_wd; |
| logic cmd_filter_6_filter_213_qs; |
| logic cmd_filter_6_filter_213_wd; |
| logic cmd_filter_6_filter_214_qs; |
| logic cmd_filter_6_filter_214_wd; |
| logic cmd_filter_6_filter_215_qs; |
| logic cmd_filter_6_filter_215_wd; |
| logic cmd_filter_6_filter_216_qs; |
| logic cmd_filter_6_filter_216_wd; |
| logic cmd_filter_6_filter_217_qs; |
| logic cmd_filter_6_filter_217_wd; |
| logic cmd_filter_6_filter_218_qs; |
| logic cmd_filter_6_filter_218_wd; |
| logic cmd_filter_6_filter_219_qs; |
| logic cmd_filter_6_filter_219_wd; |
| logic cmd_filter_6_filter_220_qs; |
| logic cmd_filter_6_filter_220_wd; |
| logic cmd_filter_6_filter_221_qs; |
| logic cmd_filter_6_filter_221_wd; |
| logic cmd_filter_6_filter_222_qs; |
| logic cmd_filter_6_filter_222_wd; |
| logic cmd_filter_6_filter_223_qs; |
| logic cmd_filter_6_filter_223_wd; |
| logic cmd_filter_7_we; |
| logic cmd_filter_7_filter_224_qs; |
| logic cmd_filter_7_filter_224_wd; |
| logic cmd_filter_7_filter_225_qs; |
| logic cmd_filter_7_filter_225_wd; |
| logic cmd_filter_7_filter_226_qs; |
| logic cmd_filter_7_filter_226_wd; |
| logic cmd_filter_7_filter_227_qs; |
| logic cmd_filter_7_filter_227_wd; |
| logic cmd_filter_7_filter_228_qs; |
| logic cmd_filter_7_filter_228_wd; |
| logic cmd_filter_7_filter_229_qs; |
| logic cmd_filter_7_filter_229_wd; |
| logic cmd_filter_7_filter_230_qs; |
| logic cmd_filter_7_filter_230_wd; |
| logic cmd_filter_7_filter_231_qs; |
| logic cmd_filter_7_filter_231_wd; |
| logic cmd_filter_7_filter_232_qs; |
| logic cmd_filter_7_filter_232_wd; |
| logic cmd_filter_7_filter_233_qs; |
| logic cmd_filter_7_filter_233_wd; |
| logic cmd_filter_7_filter_234_qs; |
| logic cmd_filter_7_filter_234_wd; |
| logic cmd_filter_7_filter_235_qs; |
| logic cmd_filter_7_filter_235_wd; |
| logic cmd_filter_7_filter_236_qs; |
| logic cmd_filter_7_filter_236_wd; |
| logic cmd_filter_7_filter_237_qs; |
| logic cmd_filter_7_filter_237_wd; |
| logic cmd_filter_7_filter_238_qs; |
| logic cmd_filter_7_filter_238_wd; |
| logic cmd_filter_7_filter_239_qs; |
| logic cmd_filter_7_filter_239_wd; |
| logic cmd_filter_7_filter_240_qs; |
| logic cmd_filter_7_filter_240_wd; |
| logic cmd_filter_7_filter_241_qs; |
| logic cmd_filter_7_filter_241_wd; |
| logic cmd_filter_7_filter_242_qs; |
| logic cmd_filter_7_filter_242_wd; |
| logic cmd_filter_7_filter_243_qs; |
| logic cmd_filter_7_filter_243_wd; |
| logic cmd_filter_7_filter_244_qs; |
| logic cmd_filter_7_filter_244_wd; |
| logic cmd_filter_7_filter_245_qs; |
| logic cmd_filter_7_filter_245_wd; |
| logic cmd_filter_7_filter_246_qs; |
| logic cmd_filter_7_filter_246_wd; |
| logic cmd_filter_7_filter_247_qs; |
| logic cmd_filter_7_filter_247_wd; |
| logic cmd_filter_7_filter_248_qs; |
| logic cmd_filter_7_filter_248_wd; |
| logic cmd_filter_7_filter_249_qs; |
| logic cmd_filter_7_filter_249_wd; |
| logic cmd_filter_7_filter_250_qs; |
| logic cmd_filter_7_filter_250_wd; |
| logic cmd_filter_7_filter_251_qs; |
| logic cmd_filter_7_filter_251_wd; |
| logic cmd_filter_7_filter_252_qs; |
| logic cmd_filter_7_filter_252_wd; |
| logic cmd_filter_7_filter_253_qs; |
| logic cmd_filter_7_filter_253_wd; |
| logic cmd_filter_7_filter_254_qs; |
| logic cmd_filter_7_filter_254_wd; |
| logic cmd_filter_7_filter_255_qs; |
| logic cmd_filter_7_filter_255_wd; |
| logic addr_swap_mask_we; |
| logic [31:0] addr_swap_mask_qs; |
| logic [31:0] addr_swap_mask_wd; |
| logic addr_swap_data_we; |
| logic [31:0] addr_swap_data_qs; |
| logic [31:0] addr_swap_data_wd; |
| logic payload_swap_mask_we; |
| logic [31:0] payload_swap_mask_qs; |
| logic [31:0] payload_swap_mask_wd; |
| logic payload_swap_data_we; |
| logic [31:0] payload_swap_data_qs; |
| logic [31:0] payload_swap_data_wd; |
| logic cmd_info_0_we; |
| logic [7:0] cmd_info_0_opcode_0_qs; |
| logic [7:0] cmd_info_0_opcode_0_wd; |
| logic [1:0] cmd_info_0_addr_mode_0_qs; |
| logic [1:0] cmd_info_0_addr_mode_0_wd; |
| logic cmd_info_0_addr_swap_en_0_qs; |
| logic cmd_info_0_addr_swap_en_0_wd; |
| logic cmd_info_0_mbyte_en_0_qs; |
| logic cmd_info_0_mbyte_en_0_wd; |
| logic [2:0] cmd_info_0_dummy_size_0_qs; |
| logic [2:0] cmd_info_0_dummy_size_0_wd; |
| logic cmd_info_0_dummy_en_0_qs; |
| logic cmd_info_0_dummy_en_0_wd; |
| logic [3:0] cmd_info_0_payload_en_0_qs; |
| logic [3:0] cmd_info_0_payload_en_0_wd; |
| logic cmd_info_0_payload_dir_0_qs; |
| logic cmd_info_0_payload_dir_0_wd; |
| logic cmd_info_0_payload_swap_en_0_qs; |
| logic cmd_info_0_payload_swap_en_0_wd; |
| logic cmd_info_0_upload_0_qs; |
| logic cmd_info_0_upload_0_wd; |
| logic cmd_info_0_busy_0_qs; |
| logic cmd_info_0_busy_0_wd; |
| logic cmd_info_0_valid_0_qs; |
| logic cmd_info_0_valid_0_wd; |
| logic cmd_info_1_we; |
| logic [7:0] cmd_info_1_opcode_1_qs; |
| logic [7:0] cmd_info_1_opcode_1_wd; |
| logic [1:0] cmd_info_1_addr_mode_1_qs; |
| logic [1:0] cmd_info_1_addr_mode_1_wd; |
| logic cmd_info_1_addr_swap_en_1_qs; |
| logic cmd_info_1_addr_swap_en_1_wd; |
| logic cmd_info_1_mbyte_en_1_qs; |
| logic cmd_info_1_mbyte_en_1_wd; |
| logic [2:0] cmd_info_1_dummy_size_1_qs; |
| logic [2:0] cmd_info_1_dummy_size_1_wd; |
| logic cmd_info_1_dummy_en_1_qs; |
| logic cmd_info_1_dummy_en_1_wd; |
| logic [3:0] cmd_info_1_payload_en_1_qs; |
| logic [3:0] cmd_info_1_payload_en_1_wd; |
| logic cmd_info_1_payload_dir_1_qs; |
| logic cmd_info_1_payload_dir_1_wd; |
| logic cmd_info_1_payload_swap_en_1_qs; |
| logic cmd_info_1_payload_swap_en_1_wd; |
| logic cmd_info_1_upload_1_qs; |
| logic cmd_info_1_upload_1_wd; |
| logic cmd_info_1_busy_1_qs; |
| logic cmd_info_1_busy_1_wd; |
| logic cmd_info_1_valid_1_qs; |
| logic cmd_info_1_valid_1_wd; |
| logic cmd_info_2_we; |
| logic [7:0] cmd_info_2_opcode_2_qs; |
| logic [7:0] cmd_info_2_opcode_2_wd; |
| logic [1:0] cmd_info_2_addr_mode_2_qs; |
| logic [1:0] cmd_info_2_addr_mode_2_wd; |
| logic cmd_info_2_addr_swap_en_2_qs; |
| logic cmd_info_2_addr_swap_en_2_wd; |
| logic cmd_info_2_mbyte_en_2_qs; |
| logic cmd_info_2_mbyte_en_2_wd; |
| logic [2:0] cmd_info_2_dummy_size_2_qs; |
| logic [2:0] cmd_info_2_dummy_size_2_wd; |
| logic cmd_info_2_dummy_en_2_qs; |
| logic cmd_info_2_dummy_en_2_wd; |
| logic [3:0] cmd_info_2_payload_en_2_qs; |
| logic [3:0] cmd_info_2_payload_en_2_wd; |
| logic cmd_info_2_payload_dir_2_qs; |
| logic cmd_info_2_payload_dir_2_wd; |
| logic cmd_info_2_payload_swap_en_2_qs; |
| logic cmd_info_2_payload_swap_en_2_wd; |
| logic cmd_info_2_upload_2_qs; |
| logic cmd_info_2_upload_2_wd; |
| logic cmd_info_2_busy_2_qs; |
| logic cmd_info_2_busy_2_wd; |
| logic cmd_info_2_valid_2_qs; |
| logic cmd_info_2_valid_2_wd; |
| logic cmd_info_3_we; |
| logic [7:0] cmd_info_3_opcode_3_qs; |
| logic [7:0] cmd_info_3_opcode_3_wd; |
| logic [1:0] cmd_info_3_addr_mode_3_qs; |
| logic [1:0] cmd_info_3_addr_mode_3_wd; |
| logic cmd_info_3_addr_swap_en_3_qs; |
| logic cmd_info_3_addr_swap_en_3_wd; |
| logic cmd_info_3_mbyte_en_3_qs; |
| logic cmd_info_3_mbyte_en_3_wd; |
| logic [2:0] cmd_info_3_dummy_size_3_qs; |
| logic [2:0] cmd_info_3_dummy_size_3_wd; |
| logic cmd_info_3_dummy_en_3_qs; |
| logic cmd_info_3_dummy_en_3_wd; |
| logic [3:0] cmd_info_3_payload_en_3_qs; |
| logic [3:0] cmd_info_3_payload_en_3_wd; |
| logic cmd_info_3_payload_dir_3_qs; |
| logic cmd_info_3_payload_dir_3_wd; |
| logic cmd_info_3_payload_swap_en_3_qs; |
| logic cmd_info_3_payload_swap_en_3_wd; |
| logic cmd_info_3_upload_3_qs; |
| logic cmd_info_3_upload_3_wd; |
| logic cmd_info_3_busy_3_qs; |
| logic cmd_info_3_busy_3_wd; |
| logic cmd_info_3_valid_3_qs; |
| logic cmd_info_3_valid_3_wd; |
| logic cmd_info_4_we; |
| logic [7:0] cmd_info_4_opcode_4_qs; |
| logic [7:0] cmd_info_4_opcode_4_wd; |
| logic [1:0] cmd_info_4_addr_mode_4_qs; |
| logic [1:0] cmd_info_4_addr_mode_4_wd; |
| logic cmd_info_4_addr_swap_en_4_qs; |
| logic cmd_info_4_addr_swap_en_4_wd; |
| logic cmd_info_4_mbyte_en_4_qs; |
| logic cmd_info_4_mbyte_en_4_wd; |
| logic [2:0] cmd_info_4_dummy_size_4_qs; |
| logic [2:0] cmd_info_4_dummy_size_4_wd; |
| logic cmd_info_4_dummy_en_4_qs; |
| logic cmd_info_4_dummy_en_4_wd; |
| logic [3:0] cmd_info_4_payload_en_4_qs; |
| logic [3:0] cmd_info_4_payload_en_4_wd; |
| logic cmd_info_4_payload_dir_4_qs; |
| logic cmd_info_4_payload_dir_4_wd; |
| logic cmd_info_4_payload_swap_en_4_qs; |
| logic cmd_info_4_payload_swap_en_4_wd; |
| logic cmd_info_4_upload_4_qs; |
| logic cmd_info_4_upload_4_wd; |
| logic cmd_info_4_busy_4_qs; |
| logic cmd_info_4_busy_4_wd; |
| logic cmd_info_4_valid_4_qs; |
| logic cmd_info_4_valid_4_wd; |
| logic cmd_info_5_we; |
| logic [7:0] cmd_info_5_opcode_5_qs; |
| logic [7:0] cmd_info_5_opcode_5_wd; |
| logic [1:0] cmd_info_5_addr_mode_5_qs; |
| logic [1:0] cmd_info_5_addr_mode_5_wd; |
| logic cmd_info_5_addr_swap_en_5_qs; |
| logic cmd_info_5_addr_swap_en_5_wd; |
| logic cmd_info_5_mbyte_en_5_qs; |
| logic cmd_info_5_mbyte_en_5_wd; |
| logic [2:0] cmd_info_5_dummy_size_5_qs; |
| logic [2:0] cmd_info_5_dummy_size_5_wd; |
| logic cmd_info_5_dummy_en_5_qs; |
| logic cmd_info_5_dummy_en_5_wd; |
| logic [3:0] cmd_info_5_payload_en_5_qs; |
| logic [3:0] cmd_info_5_payload_en_5_wd; |
| logic cmd_info_5_payload_dir_5_qs; |
| logic cmd_info_5_payload_dir_5_wd; |
| logic cmd_info_5_payload_swap_en_5_qs; |
| logic cmd_info_5_payload_swap_en_5_wd; |
| logic cmd_info_5_upload_5_qs; |
| logic cmd_info_5_upload_5_wd; |
| logic cmd_info_5_busy_5_qs; |
| logic cmd_info_5_busy_5_wd; |
| logic cmd_info_5_valid_5_qs; |
| logic cmd_info_5_valid_5_wd; |
| logic cmd_info_6_we; |
| logic [7:0] cmd_info_6_opcode_6_qs; |
| logic [7:0] cmd_info_6_opcode_6_wd; |
| logic [1:0] cmd_info_6_addr_mode_6_qs; |
| logic [1:0] cmd_info_6_addr_mode_6_wd; |
| logic cmd_info_6_addr_swap_en_6_qs; |
| logic cmd_info_6_addr_swap_en_6_wd; |
| logic cmd_info_6_mbyte_en_6_qs; |
| logic cmd_info_6_mbyte_en_6_wd; |
| logic [2:0] cmd_info_6_dummy_size_6_qs; |
| logic [2:0] cmd_info_6_dummy_size_6_wd; |
| logic cmd_info_6_dummy_en_6_qs; |
| logic cmd_info_6_dummy_en_6_wd; |
| logic [3:0] cmd_info_6_payload_en_6_qs; |
| logic [3:0] cmd_info_6_payload_en_6_wd; |
| logic cmd_info_6_payload_dir_6_qs; |
| logic cmd_info_6_payload_dir_6_wd; |
| logic cmd_info_6_payload_swap_en_6_qs; |
| logic cmd_info_6_payload_swap_en_6_wd; |
| logic cmd_info_6_upload_6_qs; |
| logic cmd_info_6_upload_6_wd; |
| logic cmd_info_6_busy_6_qs; |
| logic cmd_info_6_busy_6_wd; |
| logic cmd_info_6_valid_6_qs; |
| logic cmd_info_6_valid_6_wd; |
| logic cmd_info_7_we; |
| logic [7:0] cmd_info_7_opcode_7_qs; |
| logic [7:0] cmd_info_7_opcode_7_wd; |
| logic [1:0] cmd_info_7_addr_mode_7_qs; |
| logic [1:0] cmd_info_7_addr_mode_7_wd; |
| logic cmd_info_7_addr_swap_en_7_qs; |
| logic cmd_info_7_addr_swap_en_7_wd; |
| logic cmd_info_7_mbyte_en_7_qs; |
| logic cmd_info_7_mbyte_en_7_wd; |
| logic [2:0] cmd_info_7_dummy_size_7_qs; |
| logic [2:0] cmd_info_7_dummy_size_7_wd; |
| logic cmd_info_7_dummy_en_7_qs; |
| logic cmd_info_7_dummy_en_7_wd; |
| logic [3:0] cmd_info_7_payload_en_7_qs; |
| logic [3:0] cmd_info_7_payload_en_7_wd; |
| logic cmd_info_7_payload_dir_7_qs; |
| logic cmd_info_7_payload_dir_7_wd; |
| logic cmd_info_7_payload_swap_en_7_qs; |
| logic cmd_info_7_payload_swap_en_7_wd; |
| logic cmd_info_7_upload_7_qs; |
| logic cmd_info_7_upload_7_wd; |
| logic cmd_info_7_busy_7_qs; |
| logic cmd_info_7_busy_7_wd; |
| logic cmd_info_7_valid_7_qs; |
| logic cmd_info_7_valid_7_wd; |
| logic cmd_info_8_we; |
| logic [7:0] cmd_info_8_opcode_8_qs; |
| logic [7:0] cmd_info_8_opcode_8_wd; |
| logic [1:0] cmd_info_8_addr_mode_8_qs; |
| logic [1:0] cmd_info_8_addr_mode_8_wd; |
| logic cmd_info_8_addr_swap_en_8_qs; |
| logic cmd_info_8_addr_swap_en_8_wd; |
| logic cmd_info_8_mbyte_en_8_qs; |
| logic cmd_info_8_mbyte_en_8_wd; |
| logic [2:0] cmd_info_8_dummy_size_8_qs; |
| logic [2:0] cmd_info_8_dummy_size_8_wd; |
| logic cmd_info_8_dummy_en_8_qs; |
| logic cmd_info_8_dummy_en_8_wd; |
| logic [3:0] cmd_info_8_payload_en_8_qs; |
| logic [3:0] cmd_info_8_payload_en_8_wd; |
| logic cmd_info_8_payload_dir_8_qs; |
| logic cmd_info_8_payload_dir_8_wd; |
| logic cmd_info_8_payload_swap_en_8_qs; |
| logic cmd_info_8_payload_swap_en_8_wd; |
| logic cmd_info_8_upload_8_qs; |
| logic cmd_info_8_upload_8_wd; |
| logic cmd_info_8_busy_8_qs; |
| logic cmd_info_8_busy_8_wd; |
| logic cmd_info_8_valid_8_qs; |
| logic cmd_info_8_valid_8_wd; |
| logic cmd_info_9_we; |
| logic [7:0] cmd_info_9_opcode_9_qs; |
| logic [7:0] cmd_info_9_opcode_9_wd; |
| logic [1:0] cmd_info_9_addr_mode_9_qs; |
| logic [1:0] cmd_info_9_addr_mode_9_wd; |
| logic cmd_info_9_addr_swap_en_9_qs; |
| logic cmd_info_9_addr_swap_en_9_wd; |
| logic cmd_info_9_mbyte_en_9_qs; |
| logic cmd_info_9_mbyte_en_9_wd; |
| logic [2:0] cmd_info_9_dummy_size_9_qs; |
| logic [2:0] cmd_info_9_dummy_size_9_wd; |
| logic cmd_info_9_dummy_en_9_qs; |
| logic cmd_info_9_dummy_en_9_wd; |
| logic [3:0] cmd_info_9_payload_en_9_qs; |
| logic [3:0] cmd_info_9_payload_en_9_wd; |
| logic cmd_info_9_payload_dir_9_qs; |
| logic cmd_info_9_payload_dir_9_wd; |
| logic cmd_info_9_payload_swap_en_9_qs; |
| logic cmd_info_9_payload_swap_en_9_wd; |
| logic cmd_info_9_upload_9_qs; |
| logic cmd_info_9_upload_9_wd; |
| logic cmd_info_9_busy_9_qs; |
| logic cmd_info_9_busy_9_wd; |
| logic cmd_info_9_valid_9_qs; |
| logic cmd_info_9_valid_9_wd; |
| logic cmd_info_10_we; |
| logic [7:0] cmd_info_10_opcode_10_qs; |
| logic [7:0] cmd_info_10_opcode_10_wd; |
| logic [1:0] cmd_info_10_addr_mode_10_qs; |
| logic [1:0] cmd_info_10_addr_mode_10_wd; |
| logic cmd_info_10_addr_swap_en_10_qs; |
| logic cmd_info_10_addr_swap_en_10_wd; |
| logic cmd_info_10_mbyte_en_10_qs; |
| logic cmd_info_10_mbyte_en_10_wd; |
| logic [2:0] cmd_info_10_dummy_size_10_qs; |
| logic [2:0] cmd_info_10_dummy_size_10_wd; |
| logic cmd_info_10_dummy_en_10_qs; |
| logic cmd_info_10_dummy_en_10_wd; |
| logic [3:0] cmd_info_10_payload_en_10_qs; |
| logic [3:0] cmd_info_10_payload_en_10_wd; |
| logic cmd_info_10_payload_dir_10_qs; |
| logic cmd_info_10_payload_dir_10_wd; |
| logic cmd_info_10_payload_swap_en_10_qs; |
| logic cmd_info_10_payload_swap_en_10_wd; |
| logic cmd_info_10_upload_10_qs; |
| logic cmd_info_10_upload_10_wd; |
| logic cmd_info_10_busy_10_qs; |
| logic cmd_info_10_busy_10_wd; |
| logic cmd_info_10_valid_10_qs; |
| logic cmd_info_10_valid_10_wd; |
| logic cmd_info_11_we; |
| logic [7:0] cmd_info_11_opcode_11_qs; |
| logic [7:0] cmd_info_11_opcode_11_wd; |
| logic [1:0] cmd_info_11_addr_mode_11_qs; |
| logic [1:0] cmd_info_11_addr_mode_11_wd; |
| logic cmd_info_11_addr_swap_en_11_qs; |
| logic cmd_info_11_addr_swap_en_11_wd; |
| logic cmd_info_11_mbyte_en_11_qs; |
| logic cmd_info_11_mbyte_en_11_wd; |
| logic [2:0] cmd_info_11_dummy_size_11_qs; |
| logic [2:0] cmd_info_11_dummy_size_11_wd; |
| logic cmd_info_11_dummy_en_11_qs; |
| logic cmd_info_11_dummy_en_11_wd; |
| logic [3:0] cmd_info_11_payload_en_11_qs; |
| logic [3:0] cmd_info_11_payload_en_11_wd; |
| logic cmd_info_11_payload_dir_11_qs; |
| logic cmd_info_11_payload_dir_11_wd; |
| logic cmd_info_11_payload_swap_en_11_qs; |
| logic cmd_info_11_payload_swap_en_11_wd; |
| logic cmd_info_11_upload_11_qs; |
| logic cmd_info_11_upload_11_wd; |
| logic cmd_info_11_busy_11_qs; |
| logic cmd_info_11_busy_11_wd; |
| logic cmd_info_11_valid_11_qs; |
| logic cmd_info_11_valid_11_wd; |
| logic cmd_info_12_we; |
| logic [7:0] cmd_info_12_opcode_12_qs; |
| logic [7:0] cmd_info_12_opcode_12_wd; |
| logic [1:0] cmd_info_12_addr_mode_12_qs; |
| logic [1:0] cmd_info_12_addr_mode_12_wd; |
| logic cmd_info_12_addr_swap_en_12_qs; |
| logic cmd_info_12_addr_swap_en_12_wd; |
| logic cmd_info_12_mbyte_en_12_qs; |
| logic cmd_info_12_mbyte_en_12_wd; |
| logic [2:0] cmd_info_12_dummy_size_12_qs; |
| logic [2:0] cmd_info_12_dummy_size_12_wd; |
| logic cmd_info_12_dummy_en_12_qs; |
| logic cmd_info_12_dummy_en_12_wd; |
| logic [3:0] cmd_info_12_payload_en_12_qs; |
| logic [3:0] cmd_info_12_payload_en_12_wd; |
| logic cmd_info_12_payload_dir_12_qs; |
| logic cmd_info_12_payload_dir_12_wd; |
| logic cmd_info_12_payload_swap_en_12_qs; |
| logic cmd_info_12_payload_swap_en_12_wd; |
| logic cmd_info_12_upload_12_qs; |
| logic cmd_info_12_upload_12_wd; |
| logic cmd_info_12_busy_12_qs; |
| logic cmd_info_12_busy_12_wd; |
| logic cmd_info_12_valid_12_qs; |
| logic cmd_info_12_valid_12_wd; |
| logic cmd_info_13_we; |
| logic [7:0] cmd_info_13_opcode_13_qs; |
| logic [7:0] cmd_info_13_opcode_13_wd; |
| logic [1:0] cmd_info_13_addr_mode_13_qs; |
| logic [1:0] cmd_info_13_addr_mode_13_wd; |
| logic cmd_info_13_addr_swap_en_13_qs; |
| logic cmd_info_13_addr_swap_en_13_wd; |
| logic cmd_info_13_mbyte_en_13_qs; |
| logic cmd_info_13_mbyte_en_13_wd; |
| logic [2:0] cmd_info_13_dummy_size_13_qs; |
| logic [2:0] cmd_info_13_dummy_size_13_wd; |
| logic cmd_info_13_dummy_en_13_qs; |
| logic cmd_info_13_dummy_en_13_wd; |
| logic [3:0] cmd_info_13_payload_en_13_qs; |
| logic [3:0] cmd_info_13_payload_en_13_wd; |
| logic cmd_info_13_payload_dir_13_qs; |
| logic cmd_info_13_payload_dir_13_wd; |
| logic cmd_info_13_payload_swap_en_13_qs; |
| logic cmd_info_13_payload_swap_en_13_wd; |
| logic cmd_info_13_upload_13_qs; |
| logic cmd_info_13_upload_13_wd; |
| logic cmd_info_13_busy_13_qs; |
| logic cmd_info_13_busy_13_wd; |
| logic cmd_info_13_valid_13_qs; |
| logic cmd_info_13_valid_13_wd; |
| logic cmd_info_14_we; |
| logic [7:0] cmd_info_14_opcode_14_qs; |
| logic [7:0] cmd_info_14_opcode_14_wd; |
| logic [1:0] cmd_info_14_addr_mode_14_qs; |
| logic [1:0] cmd_info_14_addr_mode_14_wd; |
| logic cmd_info_14_addr_swap_en_14_qs; |
| logic cmd_info_14_addr_swap_en_14_wd; |
| logic cmd_info_14_mbyte_en_14_qs; |
| logic cmd_info_14_mbyte_en_14_wd; |
| logic [2:0] cmd_info_14_dummy_size_14_qs; |
| logic [2:0] cmd_info_14_dummy_size_14_wd; |
| logic cmd_info_14_dummy_en_14_qs; |
| logic cmd_info_14_dummy_en_14_wd; |
| logic [3:0] cmd_info_14_payload_en_14_qs; |
| logic [3:0] cmd_info_14_payload_en_14_wd; |
| logic cmd_info_14_payload_dir_14_qs; |
| logic cmd_info_14_payload_dir_14_wd; |
| logic cmd_info_14_payload_swap_en_14_qs; |
| logic cmd_info_14_payload_swap_en_14_wd; |
| logic cmd_info_14_upload_14_qs; |
| logic cmd_info_14_upload_14_wd; |
| logic cmd_info_14_busy_14_qs; |
| logic cmd_info_14_busy_14_wd; |
| logic cmd_info_14_valid_14_qs; |
| logic cmd_info_14_valid_14_wd; |
| logic cmd_info_15_we; |
| logic [7:0] cmd_info_15_opcode_15_qs; |
| logic [7:0] cmd_info_15_opcode_15_wd; |
| logic [1:0] cmd_info_15_addr_mode_15_qs; |
| logic [1:0] cmd_info_15_addr_mode_15_wd; |
| logic cmd_info_15_addr_swap_en_15_qs; |
| logic cmd_info_15_addr_swap_en_15_wd; |
| logic cmd_info_15_mbyte_en_15_qs; |
| logic cmd_info_15_mbyte_en_15_wd; |
| logic [2:0] cmd_info_15_dummy_size_15_qs; |
| logic [2:0] cmd_info_15_dummy_size_15_wd; |
| logic cmd_info_15_dummy_en_15_qs; |
| logic cmd_info_15_dummy_en_15_wd; |
| logic [3:0] cmd_info_15_payload_en_15_qs; |
| logic [3:0] cmd_info_15_payload_en_15_wd; |
| logic cmd_info_15_payload_dir_15_qs; |
| logic cmd_info_15_payload_dir_15_wd; |
| logic cmd_info_15_payload_swap_en_15_qs; |
| logic cmd_info_15_payload_swap_en_15_wd; |
| logic cmd_info_15_upload_15_qs; |
| logic cmd_info_15_upload_15_wd; |
| logic cmd_info_15_busy_15_qs; |
| logic cmd_info_15_busy_15_wd; |
| logic cmd_info_15_valid_15_qs; |
| logic cmd_info_15_valid_15_wd; |
| logic cmd_info_16_we; |
| logic [7:0] cmd_info_16_opcode_16_qs; |
| logic [7:0] cmd_info_16_opcode_16_wd; |
| logic [1:0] cmd_info_16_addr_mode_16_qs; |
| logic [1:0] cmd_info_16_addr_mode_16_wd; |
| logic cmd_info_16_addr_swap_en_16_qs; |
| logic cmd_info_16_addr_swap_en_16_wd; |
| logic cmd_info_16_mbyte_en_16_qs; |
| logic cmd_info_16_mbyte_en_16_wd; |
| logic [2:0] cmd_info_16_dummy_size_16_qs; |
| logic [2:0] cmd_info_16_dummy_size_16_wd; |
| logic cmd_info_16_dummy_en_16_qs; |
| logic cmd_info_16_dummy_en_16_wd; |
| logic [3:0] cmd_info_16_payload_en_16_qs; |
| logic [3:0] cmd_info_16_payload_en_16_wd; |
| logic cmd_info_16_payload_dir_16_qs; |
| logic cmd_info_16_payload_dir_16_wd; |
| logic cmd_info_16_payload_swap_en_16_qs; |
| logic cmd_info_16_payload_swap_en_16_wd; |
| logic cmd_info_16_upload_16_qs; |
| logic cmd_info_16_upload_16_wd; |
| logic cmd_info_16_busy_16_qs; |
| logic cmd_info_16_busy_16_wd; |
| logic cmd_info_16_valid_16_qs; |
| logic cmd_info_16_valid_16_wd; |
| logic cmd_info_17_we; |
| logic [7:0] cmd_info_17_opcode_17_qs; |
| logic [7:0] cmd_info_17_opcode_17_wd; |
| logic [1:0] cmd_info_17_addr_mode_17_qs; |
| logic [1:0] cmd_info_17_addr_mode_17_wd; |
| logic cmd_info_17_addr_swap_en_17_qs; |
| logic cmd_info_17_addr_swap_en_17_wd; |
| logic cmd_info_17_mbyte_en_17_qs; |
| logic cmd_info_17_mbyte_en_17_wd; |
| logic [2:0] cmd_info_17_dummy_size_17_qs; |
| logic [2:0] cmd_info_17_dummy_size_17_wd; |
| logic cmd_info_17_dummy_en_17_qs; |
| logic cmd_info_17_dummy_en_17_wd; |
| logic [3:0] cmd_info_17_payload_en_17_qs; |
| logic [3:0] cmd_info_17_payload_en_17_wd; |
| logic cmd_info_17_payload_dir_17_qs; |
| logic cmd_info_17_payload_dir_17_wd; |
| logic cmd_info_17_payload_swap_en_17_qs; |
| logic cmd_info_17_payload_swap_en_17_wd; |
| logic cmd_info_17_upload_17_qs; |
| logic cmd_info_17_upload_17_wd; |
| logic cmd_info_17_busy_17_qs; |
| logic cmd_info_17_busy_17_wd; |
| logic cmd_info_17_valid_17_qs; |
| logic cmd_info_17_valid_17_wd; |
| logic cmd_info_18_we; |
| logic [7:0] cmd_info_18_opcode_18_qs; |
| logic [7:0] cmd_info_18_opcode_18_wd; |
| logic [1:0] cmd_info_18_addr_mode_18_qs; |
| logic [1:0] cmd_info_18_addr_mode_18_wd; |
| logic cmd_info_18_addr_swap_en_18_qs; |
| logic cmd_info_18_addr_swap_en_18_wd; |
| logic cmd_info_18_mbyte_en_18_qs; |
| logic cmd_info_18_mbyte_en_18_wd; |
| logic [2:0] cmd_info_18_dummy_size_18_qs; |
| logic [2:0] cmd_info_18_dummy_size_18_wd; |
| logic cmd_info_18_dummy_en_18_qs; |
| logic cmd_info_18_dummy_en_18_wd; |
| logic [3:0] cmd_info_18_payload_en_18_qs; |
| logic [3:0] cmd_info_18_payload_en_18_wd; |
| logic cmd_info_18_payload_dir_18_qs; |
| logic cmd_info_18_payload_dir_18_wd; |
| logic cmd_info_18_payload_swap_en_18_qs; |
| logic cmd_info_18_payload_swap_en_18_wd; |
| logic cmd_info_18_upload_18_qs; |
| logic cmd_info_18_upload_18_wd; |
| logic cmd_info_18_busy_18_qs; |
| logic cmd_info_18_busy_18_wd; |
| logic cmd_info_18_valid_18_qs; |
| logic cmd_info_18_valid_18_wd; |
| logic cmd_info_19_we; |
| logic [7:0] cmd_info_19_opcode_19_qs; |
| logic [7:0] cmd_info_19_opcode_19_wd; |
| logic [1:0] cmd_info_19_addr_mode_19_qs; |
| logic [1:0] cmd_info_19_addr_mode_19_wd; |
| logic cmd_info_19_addr_swap_en_19_qs; |
| logic cmd_info_19_addr_swap_en_19_wd; |
| logic cmd_info_19_mbyte_en_19_qs; |
| logic cmd_info_19_mbyte_en_19_wd; |
| logic [2:0] cmd_info_19_dummy_size_19_qs; |
| logic [2:0] cmd_info_19_dummy_size_19_wd; |
| logic cmd_info_19_dummy_en_19_qs; |
| logic cmd_info_19_dummy_en_19_wd; |
| logic [3:0] cmd_info_19_payload_en_19_qs; |
| logic [3:0] cmd_info_19_payload_en_19_wd; |
| logic cmd_info_19_payload_dir_19_qs; |
| logic cmd_info_19_payload_dir_19_wd; |
| logic cmd_info_19_payload_swap_en_19_qs; |
| logic cmd_info_19_payload_swap_en_19_wd; |
| logic cmd_info_19_upload_19_qs; |
| logic cmd_info_19_upload_19_wd; |
| logic cmd_info_19_busy_19_qs; |
| logic cmd_info_19_busy_19_wd; |
| logic cmd_info_19_valid_19_qs; |
| logic cmd_info_19_valid_19_wd; |
| logic cmd_info_20_we; |
| logic [7:0] cmd_info_20_opcode_20_qs; |
| logic [7:0] cmd_info_20_opcode_20_wd; |
| logic [1:0] cmd_info_20_addr_mode_20_qs; |
| logic [1:0] cmd_info_20_addr_mode_20_wd; |
| logic cmd_info_20_addr_swap_en_20_qs; |
| logic cmd_info_20_addr_swap_en_20_wd; |
| logic cmd_info_20_mbyte_en_20_qs; |
| logic cmd_info_20_mbyte_en_20_wd; |
| logic [2:0] cmd_info_20_dummy_size_20_qs; |
| logic [2:0] cmd_info_20_dummy_size_20_wd; |
| logic cmd_info_20_dummy_en_20_qs; |
| logic cmd_info_20_dummy_en_20_wd; |
| logic [3:0] cmd_info_20_payload_en_20_qs; |
| logic [3:0] cmd_info_20_payload_en_20_wd; |
| logic cmd_info_20_payload_dir_20_qs; |
| logic cmd_info_20_payload_dir_20_wd; |
| logic cmd_info_20_payload_swap_en_20_qs; |
| logic cmd_info_20_payload_swap_en_20_wd; |
| logic cmd_info_20_upload_20_qs; |
| logic cmd_info_20_upload_20_wd; |
| logic cmd_info_20_busy_20_qs; |
| logic cmd_info_20_busy_20_wd; |
| logic cmd_info_20_valid_20_qs; |
| logic cmd_info_20_valid_20_wd; |
| logic cmd_info_21_we; |
| logic [7:0] cmd_info_21_opcode_21_qs; |
| logic [7:0] cmd_info_21_opcode_21_wd; |
| logic [1:0] cmd_info_21_addr_mode_21_qs; |
| logic [1:0] cmd_info_21_addr_mode_21_wd; |
| logic cmd_info_21_addr_swap_en_21_qs; |
| logic cmd_info_21_addr_swap_en_21_wd; |
| logic cmd_info_21_mbyte_en_21_qs; |
| logic cmd_info_21_mbyte_en_21_wd; |
| logic [2:0] cmd_info_21_dummy_size_21_qs; |
| logic [2:0] cmd_info_21_dummy_size_21_wd; |
| logic cmd_info_21_dummy_en_21_qs; |
| logic cmd_info_21_dummy_en_21_wd; |
| logic [3:0] cmd_info_21_payload_en_21_qs; |
| logic [3:0] cmd_info_21_payload_en_21_wd; |
| logic cmd_info_21_payload_dir_21_qs; |
| logic cmd_info_21_payload_dir_21_wd; |
| logic cmd_info_21_payload_swap_en_21_qs; |
| logic cmd_info_21_payload_swap_en_21_wd; |
| logic cmd_info_21_upload_21_qs; |
| logic cmd_info_21_upload_21_wd; |
| logic cmd_info_21_busy_21_qs; |
| logic cmd_info_21_busy_21_wd; |
| logic cmd_info_21_valid_21_qs; |
| logic cmd_info_21_valid_21_wd; |
| logic cmd_info_22_we; |
| logic [7:0] cmd_info_22_opcode_22_qs; |
| logic [7:0] cmd_info_22_opcode_22_wd; |
| logic [1:0] cmd_info_22_addr_mode_22_qs; |
| logic [1:0] cmd_info_22_addr_mode_22_wd; |
| logic cmd_info_22_addr_swap_en_22_qs; |
| logic cmd_info_22_addr_swap_en_22_wd; |
| logic cmd_info_22_mbyte_en_22_qs; |
| logic cmd_info_22_mbyte_en_22_wd; |
| logic [2:0] cmd_info_22_dummy_size_22_qs; |
| logic [2:0] cmd_info_22_dummy_size_22_wd; |
| logic cmd_info_22_dummy_en_22_qs; |
| logic cmd_info_22_dummy_en_22_wd; |
| logic [3:0] cmd_info_22_payload_en_22_qs; |
| logic [3:0] cmd_info_22_payload_en_22_wd; |
| logic cmd_info_22_payload_dir_22_qs; |
| logic cmd_info_22_payload_dir_22_wd; |
| logic cmd_info_22_payload_swap_en_22_qs; |
| logic cmd_info_22_payload_swap_en_22_wd; |
| logic cmd_info_22_upload_22_qs; |
| logic cmd_info_22_upload_22_wd; |
| logic cmd_info_22_busy_22_qs; |
| logic cmd_info_22_busy_22_wd; |
| logic cmd_info_22_valid_22_qs; |
| logic cmd_info_22_valid_22_wd; |
| logic cmd_info_23_we; |
| logic [7:0] cmd_info_23_opcode_23_qs; |
| logic [7:0] cmd_info_23_opcode_23_wd; |
| logic [1:0] cmd_info_23_addr_mode_23_qs; |
| logic [1:0] cmd_info_23_addr_mode_23_wd; |
| logic cmd_info_23_addr_swap_en_23_qs; |
| logic cmd_info_23_addr_swap_en_23_wd; |
| logic cmd_info_23_mbyte_en_23_qs; |
| logic cmd_info_23_mbyte_en_23_wd; |
| logic [2:0] cmd_info_23_dummy_size_23_qs; |
| logic [2:0] cmd_info_23_dummy_size_23_wd; |
| logic cmd_info_23_dummy_en_23_qs; |
| logic cmd_info_23_dummy_en_23_wd; |
| logic [3:0] cmd_info_23_payload_en_23_qs; |
| logic [3:0] cmd_info_23_payload_en_23_wd; |
| logic cmd_info_23_payload_dir_23_qs; |
| logic cmd_info_23_payload_dir_23_wd; |
| logic cmd_info_23_payload_swap_en_23_qs; |
| logic cmd_info_23_payload_swap_en_23_wd; |
| logic cmd_info_23_upload_23_qs; |
| logic cmd_info_23_upload_23_wd; |
| logic cmd_info_23_busy_23_qs; |
| logic cmd_info_23_busy_23_wd; |
| logic cmd_info_23_valid_23_qs; |
| logic cmd_info_23_valid_23_wd; |
| logic cmd_info_en4b_we; |
| logic [7:0] cmd_info_en4b_opcode_qs; |
| logic [7:0] cmd_info_en4b_opcode_wd; |
| logic cmd_info_en4b_valid_qs; |
| logic cmd_info_en4b_valid_wd; |
| logic cmd_info_ex4b_we; |
| logic [7:0] cmd_info_ex4b_opcode_qs; |
| logic [7:0] cmd_info_ex4b_opcode_wd; |
| logic cmd_info_ex4b_valid_qs; |
| logic cmd_info_ex4b_valid_wd; |
| logic cmd_info_wren_we; |
| logic [7:0] cmd_info_wren_opcode_qs; |
| logic [7:0] cmd_info_wren_opcode_wd; |
| logic cmd_info_wren_valid_qs; |
| logic cmd_info_wren_valid_wd; |
| logic cmd_info_wrdi_we; |
| logic [7:0] cmd_info_wrdi_opcode_qs; |
| logic [7:0] cmd_info_wrdi_opcode_wd; |
| logic cmd_info_wrdi_valid_qs; |
| logic cmd_info_wrdi_valid_wd; |
| logic [7:0] tpm_cap_rev_qs; |
| logic tpm_cap_locality_qs; |
| logic [2:0] tpm_cap_max_wr_size_qs; |
| logic [2:0] tpm_cap_max_rd_size_qs; |
| logic tpm_cfg_we; |
| logic tpm_cfg_en_qs; |
| logic tpm_cfg_en_wd; |
| logic tpm_cfg_tpm_mode_qs; |
| logic tpm_cfg_tpm_mode_wd; |
| logic tpm_cfg_hw_reg_dis_qs; |
| logic tpm_cfg_hw_reg_dis_wd; |
| logic tpm_cfg_tpm_reg_chk_dis_qs; |
| logic tpm_cfg_tpm_reg_chk_dis_wd; |
| logic tpm_cfg_invalid_locality_qs; |
| logic tpm_cfg_invalid_locality_wd; |
| logic tpm_status_cmdaddr_notempty_qs; |
| logic [6:0] tpm_status_wrfifo_depth_qs; |
| logic tpm_access_0_we; |
| logic [7:0] tpm_access_0_access_0_qs; |
| logic [7:0] tpm_access_0_access_0_wd; |
| logic [7:0] tpm_access_0_access_1_qs; |
| logic [7:0] tpm_access_0_access_1_wd; |
| logic [7:0] tpm_access_0_access_2_qs; |
| logic [7:0] tpm_access_0_access_2_wd; |
| logic [7:0] tpm_access_0_access_3_qs; |
| logic [7:0] tpm_access_0_access_3_wd; |
| logic tpm_access_1_we; |
| logic [7:0] tpm_access_1_qs; |
| logic [7:0] tpm_access_1_wd; |
| logic tpm_sts_we; |
| logic [31:0] tpm_sts_qs; |
| logic [31:0] tpm_sts_wd; |
| logic tpm_intf_capability_we; |
| logic [31:0] tpm_intf_capability_qs; |
| logic [31:0] tpm_intf_capability_wd; |
| logic tpm_int_enable_we; |
| logic [31:0] tpm_int_enable_qs; |
| logic [31:0] tpm_int_enable_wd; |
| logic tpm_int_vector_we; |
| logic [7:0] tpm_int_vector_qs; |
| logic [7:0] tpm_int_vector_wd; |
| logic tpm_int_status_we; |
| logic [31:0] tpm_int_status_qs; |
| logic [31:0] tpm_int_status_wd; |
| logic tpm_did_vid_we; |
| logic [15:0] tpm_did_vid_vid_qs; |
| logic [15:0] tpm_did_vid_vid_wd; |
| logic [15:0] tpm_did_vid_did_qs; |
| logic [15:0] tpm_did_vid_did_wd; |
| logic tpm_rid_we; |
| logic [7:0] tpm_rid_qs; |
| logic [7:0] tpm_rid_wd; |
| logic tpm_cmd_addr_re; |
| logic [23:0] tpm_cmd_addr_addr_qs; |
| logic [7:0] tpm_cmd_addr_cmd_qs; |
| logic tpm_read_fifo_we; |
| logic [31:0] tpm_read_fifo_wd; |
| logic tpm_write_fifo_re; |
| logic [7:0] tpm_write_fifo_qs; |
| |
| // Register instances |
| // R[intr_state]: V(False) |
| // F[generic_rx_full]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_generic_rx_full ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_generic_rx_full_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.generic_rx_full.de), |
| .d (hw2reg.intr_state.generic_rx_full.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.generic_rx_full.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_generic_rx_full_qs) |
| ); |
| |
| // F[generic_rx_watermark]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_generic_rx_watermark ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_generic_rx_watermark_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.generic_rx_watermark.de), |
| .d (hw2reg.intr_state.generic_rx_watermark.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.generic_rx_watermark.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_generic_rx_watermark_qs) |
| ); |
| |
| // F[generic_tx_watermark]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_generic_tx_watermark ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_generic_tx_watermark_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.generic_tx_watermark.de), |
| .d (hw2reg.intr_state.generic_tx_watermark.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.generic_tx_watermark.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_generic_tx_watermark_qs) |
| ); |
| |
| // F[generic_rx_error]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_generic_rx_error ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_generic_rx_error_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.generic_rx_error.de), |
| .d (hw2reg.intr_state.generic_rx_error.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.generic_rx_error.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_generic_rx_error_qs) |
| ); |
| |
| // F[generic_rx_overflow]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_generic_rx_overflow ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_generic_rx_overflow_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.generic_rx_overflow.de), |
| .d (hw2reg.intr_state.generic_rx_overflow.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.generic_rx_overflow.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_generic_rx_overflow_qs) |
| ); |
| |
| // F[generic_tx_underflow]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_generic_tx_underflow ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_generic_tx_underflow_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.generic_tx_underflow.de), |
| .d (hw2reg.intr_state.generic_tx_underflow.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.generic_tx_underflow.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_generic_tx_underflow_qs) |
| ); |
| |
| // F[upload_cmdfifo_not_empty]: 6:6 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_upload_cmdfifo_not_empty ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_upload_cmdfifo_not_empty_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.upload_cmdfifo_not_empty.de), |
| .d (hw2reg.intr_state.upload_cmdfifo_not_empty.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.upload_cmdfifo_not_empty.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_upload_cmdfifo_not_empty_qs) |
| ); |
| |
| // F[upload_payload_not_empty]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_upload_payload_not_empty ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_upload_payload_not_empty_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.upload_payload_not_empty.de), |
| .d (hw2reg.intr_state.upload_payload_not_empty.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.upload_payload_not_empty.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_upload_payload_not_empty_qs) |
| ); |
| |
| // F[upload_payload_overflow]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_upload_payload_overflow ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_upload_payload_overflow_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.upload_payload_overflow.de), |
| .d (hw2reg.intr_state.upload_payload_overflow.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.upload_payload_overflow.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_upload_payload_overflow_qs) |
| ); |
| |
| // F[readbuf_watermark]: 9:9 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_readbuf_watermark ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_readbuf_watermark_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.readbuf_watermark.de), |
| .d (hw2reg.intr_state.readbuf_watermark.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.readbuf_watermark.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_readbuf_watermark_qs) |
| ); |
| |
| // F[readbuf_flip]: 10:10 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_readbuf_flip ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_readbuf_flip_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.readbuf_flip.de), |
| .d (hw2reg.intr_state.readbuf_flip.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.readbuf_flip.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_readbuf_flip_qs) |
| ); |
| |
| // F[tpm_header_not_empty]: 11:11 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (1'h0) |
| ) u_intr_state_tpm_header_not_empty ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.tpm_header_not_empty.de), |
| .d (hw2reg.intr_state.tpm_header_not_empty.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.tpm_header_not_empty.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_tpm_header_not_empty_qs) |
| ); |
| |
| |
| // R[intr_enable]: V(False) |
| // F[generic_rx_full]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_generic_rx_full ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_generic_rx_full_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.generic_rx_full.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_generic_rx_full_qs) |
| ); |
| |
| // F[generic_rx_watermark]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_generic_rx_watermark ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_generic_rx_watermark_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.generic_rx_watermark.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_generic_rx_watermark_qs) |
| ); |
| |
| // F[generic_tx_watermark]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_generic_tx_watermark ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_generic_tx_watermark_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.generic_tx_watermark.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_generic_tx_watermark_qs) |
| ); |
| |
| // F[generic_rx_error]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_generic_rx_error ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_generic_rx_error_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.generic_rx_error.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_generic_rx_error_qs) |
| ); |
| |
| // F[generic_rx_overflow]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_generic_rx_overflow ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_generic_rx_overflow_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.generic_rx_overflow.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_generic_rx_overflow_qs) |
| ); |
| |
| // F[generic_tx_underflow]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_generic_tx_underflow ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_generic_tx_underflow_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.generic_tx_underflow.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_generic_tx_underflow_qs) |
| ); |
| |
| // F[upload_cmdfifo_not_empty]: 6:6 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_upload_cmdfifo_not_empty ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_upload_cmdfifo_not_empty_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.upload_cmdfifo_not_empty.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_upload_cmdfifo_not_empty_qs) |
| ); |
| |
| // F[upload_payload_not_empty]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_upload_payload_not_empty ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_upload_payload_not_empty_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.upload_payload_not_empty.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_upload_payload_not_empty_qs) |
| ); |
| |
| // F[upload_payload_overflow]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_upload_payload_overflow ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_upload_payload_overflow_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.upload_payload_overflow.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_upload_payload_overflow_qs) |
| ); |
| |
| // F[readbuf_watermark]: 9:9 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_readbuf_watermark ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_readbuf_watermark_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.readbuf_watermark.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_readbuf_watermark_qs) |
| ); |
| |
| // F[readbuf_flip]: 10:10 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_readbuf_flip ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_readbuf_flip_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.readbuf_flip.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_readbuf_flip_qs) |
| ); |
| |
| // F[tpm_header_not_empty]: 11:11 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_tpm_header_not_empty ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_tpm_header_not_empty_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.tpm_header_not_empty.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_tpm_header_not_empty_qs) |
| ); |
| |
| |
| // R[intr_test]: V(True) |
| logic intr_test_qe; |
| logic [11:0] intr_test_flds_we; |
| assign intr_test_qe = &intr_test_flds_we; |
| // F[generic_rx_full]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_generic_rx_full ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_generic_rx_full_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[0]), |
| .q (reg2hw.intr_test.generic_rx_full.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.generic_rx_full.qe = intr_test_qe; |
| |
| // F[generic_rx_watermark]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_generic_rx_watermark ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_generic_rx_watermark_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[1]), |
| .q (reg2hw.intr_test.generic_rx_watermark.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.generic_rx_watermark.qe = intr_test_qe; |
| |
| // F[generic_tx_watermark]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_generic_tx_watermark ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_generic_tx_watermark_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[2]), |
| .q (reg2hw.intr_test.generic_tx_watermark.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.generic_tx_watermark.qe = intr_test_qe; |
| |
| // F[generic_rx_error]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_generic_rx_error ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_generic_rx_error_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[3]), |
| .q (reg2hw.intr_test.generic_rx_error.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.generic_rx_error.qe = intr_test_qe; |
| |
| // F[generic_rx_overflow]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_generic_rx_overflow ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_generic_rx_overflow_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[4]), |
| .q (reg2hw.intr_test.generic_rx_overflow.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.generic_rx_overflow.qe = intr_test_qe; |
| |
| // F[generic_tx_underflow]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_generic_tx_underflow ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_generic_tx_underflow_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[5]), |
| .q (reg2hw.intr_test.generic_tx_underflow.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.generic_tx_underflow.qe = intr_test_qe; |
| |
| // F[upload_cmdfifo_not_empty]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_upload_cmdfifo_not_empty ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_upload_cmdfifo_not_empty_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[6]), |
| .q (reg2hw.intr_test.upload_cmdfifo_not_empty.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.upload_cmdfifo_not_empty.qe = intr_test_qe; |
| |
| // F[upload_payload_not_empty]: 7:7 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_upload_payload_not_empty ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_upload_payload_not_empty_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[7]), |
| .q (reg2hw.intr_test.upload_payload_not_empty.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.upload_payload_not_empty.qe = intr_test_qe; |
| |
| // F[upload_payload_overflow]: 8:8 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_upload_payload_overflow ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_upload_payload_overflow_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[8]), |
| .q (reg2hw.intr_test.upload_payload_overflow.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.upload_payload_overflow.qe = intr_test_qe; |
| |
| // F[readbuf_watermark]: 9:9 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_readbuf_watermark ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_readbuf_watermark_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[9]), |
| .q (reg2hw.intr_test.readbuf_watermark.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.readbuf_watermark.qe = intr_test_qe; |
| |
| // F[readbuf_flip]: 10:10 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_readbuf_flip ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_readbuf_flip_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[10]), |
| .q (reg2hw.intr_test.readbuf_flip.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.readbuf_flip.qe = intr_test_qe; |
| |
| // F[tpm_header_not_empty]: 11:11 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_tpm_header_not_empty ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_tpm_header_not_empty_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[11]), |
| .q (reg2hw.intr_test.tpm_header_not_empty.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.tpm_header_not_empty.qe = intr_test_qe; |
| |
| |
| // R[alert_test]: V(True) |
| logic alert_test_qe; |
| logic [0:0] alert_test_flds_we; |
| assign alert_test_qe = &alert_test_flds_we; |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_alert_test ( |
| .re (1'b0), |
| .we (alert_test_we), |
| .wd (alert_test_wd), |
| .d ('0), |
| .qre (), |
| .qe (alert_test_flds_we[0]), |
| .q (reg2hw.alert_test.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.alert_test.qe = alert_test_qe; |
| |
| |
| // R[control]: V(False) |
| // F[abort]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_control_abort ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (control_we), |
| .wd (control_abort_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.control.abort.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (control_abort_qs) |
| ); |
| |
| // F[mode]: 5:4 |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h1) |
| ) u_control_mode ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (control_we), |
| .wd (control_mode_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.control.mode.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (control_mode_qs) |
| ); |
| |
| // F[rst_txfifo]: 16:16 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_control_rst_txfifo ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (control_we), |
| .wd (control_rst_txfifo_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.control.rst_txfifo.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (control_rst_txfifo_qs) |
| ); |
| |
| // F[rst_rxfifo]: 17:17 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_control_rst_rxfifo ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (control_we), |
| .wd (control_rst_rxfifo_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.control.rst_rxfifo.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (control_rst_rxfifo_qs) |
| ); |
| |
| // F[sram_clk_en]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h1) |
| ) u_control_sram_clk_en ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (control_we), |
| .wd (control_sram_clk_en_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.control.sram_clk_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (control_sram_clk_en_qs) |
| ); |
| |
| |
| // R[cfg]: V(False) |
| // F[cpol]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cfg_cpol ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cfg_we), |
| .wd (cfg_cpol_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cfg.cpol.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cfg_cpol_qs) |
| ); |
| |
| // F[cpha]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cfg_cpha ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cfg_we), |
| .wd (cfg_cpha_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cfg.cpha.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cfg_cpha_qs) |
| ); |
| |
| // F[tx_order]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cfg_tx_order ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cfg_we), |
| .wd (cfg_tx_order_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cfg.tx_order.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cfg_tx_order_qs) |
| ); |
| |
| // F[rx_order]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cfg_rx_order ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cfg_we), |
| .wd (cfg_rx_order_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cfg.rx_order.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cfg_rx_order_qs) |
| ); |
| |
| // F[timer_v]: 15:8 |
| prim_subreg #( |
| .DW (8), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (8'h7f) |
| ) u_cfg_timer_v ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cfg_we), |
| .wd (cfg_timer_v_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cfg.timer_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cfg_timer_v_qs) |
| ); |
| |
| // F[addr_4b_en]: 16:16 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cfg_addr_4b_en ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cfg_we), |
| .wd (cfg_addr_4b_en_wd), |
| |
| // from internal hardware |
| .de (hw2reg.cfg.addr_4b_en.de), |
| .d (hw2reg.cfg.addr_4b_en.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cfg.addr_4b_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cfg_addr_4b_en_qs) |
| ); |
| |
| // F[mailbox_en]: 24:24 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cfg_mailbox_en ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cfg_we), |
| .wd (cfg_mailbox_en_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cfg.mailbox_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cfg_mailbox_en_qs) |
| ); |
| |
| |
| // R[fifo_level]: V(False) |
| // F[rxlvl]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h80) |
| ) u_fifo_level_rxlvl ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fifo_level_we), |
| .wd (fifo_level_rxlvl_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fifo_level.rxlvl.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fifo_level_rxlvl_qs) |
| ); |
| |
| // F[txlvl]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h0) |
| ) u_fifo_level_txlvl ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fifo_level_we), |
| .wd (fifo_level_txlvl_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fifo_level.txlvl.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fifo_level_txlvl_qs) |
| ); |
| |
| |
| // R[async_fifo_level]: V(True) |
| // F[rxlvl]: 7:0 |
| prim_subreg_ext #( |
| .DW (8) |
| ) u_async_fifo_level_rxlvl ( |
| .re (async_fifo_level_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.async_fifo_level.rxlvl.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (async_fifo_level_rxlvl_qs) |
| ); |
| |
| // F[txlvl]: 23:16 |
| prim_subreg_ext #( |
| .DW (8) |
| ) u_async_fifo_level_txlvl ( |
| .re (async_fifo_level_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.async_fifo_level.txlvl.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (async_fifo_level_txlvl_qs) |
| ); |
| |
| |
| // R[status]: V(True) |
| // F[rxf_full]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_status_rxf_full ( |
| .re (status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.status.rxf_full.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (status_rxf_full_qs) |
| ); |
| |
| // F[rxf_empty]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_status_rxf_empty ( |
| .re (status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.status.rxf_empty.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (status_rxf_empty_qs) |
| ); |
| |
| // F[txf_full]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_status_txf_full ( |
| .re (status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.status.txf_full.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (status_txf_full_qs) |
| ); |
| |
| // F[txf_empty]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_status_txf_empty ( |
| .re (status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.status.txf_empty.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (status_txf_empty_qs) |
| ); |
| |
| // F[abort_done]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_status_abort_done ( |
| .re (status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.status.abort_done.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (status_abort_done_qs) |
| ); |
| |
| // F[csb]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_status_csb ( |
| .re (status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.status.csb.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (status_csb_qs) |
| ); |
| |
| // F[tpm_csb]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_status_tpm_csb ( |
| .re (status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.status.tpm_csb.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (status_tpm_csb_qs) |
| ); |
| |
| |
| // R[rxf_ptr]: V(False) |
| // F[rptr]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h0) |
| ) u_rxf_ptr_rptr ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (rxf_ptr_we), |
| .wd (rxf_ptr_rptr_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.rxf_ptr.rptr.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (rxf_ptr_rptr_qs) |
| ); |
| |
| // F[wptr]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (16'h0) |
| ) u_rxf_ptr_wptr ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.rxf_ptr.wptr.de), |
| .d (hw2reg.rxf_ptr.wptr.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (rxf_ptr_wptr_qs) |
| ); |
| |
| |
| // R[txf_ptr]: V(False) |
| // F[rptr]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (16'h0) |
| ) u_txf_ptr_rptr ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.txf_ptr.rptr.de), |
| .d (hw2reg.txf_ptr.rptr.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (txf_ptr_rptr_qs) |
| ); |
| |
| // F[wptr]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h0) |
| ) u_txf_ptr_wptr ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (txf_ptr_we), |
| .wd (txf_ptr_wptr_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.txf_ptr.wptr.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (txf_ptr_wptr_qs) |
| ); |
| |
| |
| // R[rxf_addr]: V(False) |
| // F[base]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h0) |
| ) u_rxf_addr_base ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (rxf_addr_we), |
| .wd (rxf_addr_base_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.rxf_addr.base.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (rxf_addr_base_qs) |
| ); |
| |
| // F[limit]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h1fc) |
| ) u_rxf_addr_limit ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (rxf_addr_we), |
| .wd (rxf_addr_limit_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.rxf_addr.limit.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (rxf_addr_limit_qs) |
| ); |
| |
| |
| // R[txf_addr]: V(False) |
| // F[base]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h200) |
| ) u_txf_addr_base ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (txf_addr_we), |
| .wd (txf_addr_base_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.txf_addr.base.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (txf_addr_base_qs) |
| ); |
| |
| // F[limit]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h3fc) |
| ) u_txf_addr_limit ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (txf_addr_we), |
| .wd (txf_addr_limit_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.txf_addr.limit.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (txf_addr_limit_qs) |
| ); |
| |
| |
| // R[intercept_en]: V(False) |
| // F[status]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intercept_en_status ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intercept_en_we), |
| .wd (intercept_en_status_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intercept_en.status.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intercept_en_status_qs) |
| ); |
| |
| // F[jedec]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intercept_en_jedec ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intercept_en_we), |
| .wd (intercept_en_jedec_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intercept_en.jedec.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intercept_en_jedec_qs) |
| ); |
| |
| // F[sfdp]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intercept_en_sfdp ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intercept_en_we), |
| .wd (intercept_en_sfdp_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intercept_en.sfdp.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intercept_en_sfdp_qs) |
| ); |
| |
| // F[mbx]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intercept_en_mbx ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intercept_en_we), |
| .wd (intercept_en_mbx_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intercept_en.mbx.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intercept_en_mbx_qs) |
| ); |
| |
| |
| // R[last_read_addr]: V(True) |
| prim_subreg_ext #( |
| .DW (32) |
| ) u_last_read_addr ( |
| .re (last_read_addr_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.last_read_addr.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (last_read_addr_qs) |
| ); |
| |
| |
| // R[flash_status]: V(True) |
| logic flash_status_qe; |
| logic [1:0] flash_status_flds_we; |
| assign flash_status_qe = &flash_status_flds_we; |
| // F[busy]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_flash_status_busy ( |
| .re (flash_status_re), |
| .we (flash_status_we), |
| .wd (flash_status_busy_wd), |
| .d (hw2reg.flash_status.busy.d), |
| .qre (), |
| .qe (flash_status_flds_we[0]), |
| .q (reg2hw.flash_status.busy.q), |
| .ds (), |
| .qs (flash_status_busy_qs) |
| ); |
| assign reg2hw.flash_status.busy.qe = flash_status_qe; |
| |
| // F[status]: 23:1 |
| prim_subreg_ext #( |
| .DW (23) |
| ) u_flash_status_status ( |
| .re (flash_status_re), |
| .we (flash_status_we), |
| .wd (flash_status_status_wd), |
| .d (hw2reg.flash_status.status.d), |
| .qre (), |
| .qe (flash_status_flds_we[1]), |
| .q (reg2hw.flash_status.status.q), |
| .ds (), |
| .qs (flash_status_status_qs) |
| ); |
| assign reg2hw.flash_status.status.qe = flash_status_qe; |
| |
| |
| // R[jedec_cc]: V(False) |
| // F[cc]: 7:0 |
| prim_subreg #( |
| .DW (8), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (8'h7f) |
| ) u_jedec_cc_cc ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (jedec_cc_we), |
| .wd (jedec_cc_cc_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.jedec_cc.cc.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (jedec_cc_cc_qs) |
| ); |
| |
| // F[num_cc]: 15:8 |
| prim_subreg #( |
| .DW (8), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (8'h0) |
| ) u_jedec_cc_num_cc ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (jedec_cc_we), |
| .wd (jedec_cc_num_cc_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.jedec_cc.num_cc.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (jedec_cc_num_cc_qs) |
| ); |
| |
| |
| // R[jedec_id]: V(False) |
| // F[id]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h0) |
| ) u_jedec_id_id ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (jedec_id_we), |
| .wd (jedec_id_id_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.jedec_id.id.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (jedec_id_id_qs) |
| ); |
| |
| // F[mf]: 23:16 |
| prim_subreg #( |
| .DW (8), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (8'h0) |
| ) u_jedec_id_mf ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (jedec_id_we), |
| .wd (jedec_id_mf_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.jedec_id.mf.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (jedec_id_mf_qs) |
| ); |
| |
| |
| // R[read_threshold]: V(False) |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_read_threshold ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (read_threshold_we), |
| .wd (read_threshold_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.read_threshold.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (read_threshold_qs) |
| ); |
| |
| |
| // R[mailbox_addr]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (32'h0) |
| ) u_mailbox_addr ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mailbox_addr_we), |
| .wd (mailbox_addr_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mailbox_addr.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mailbox_addr_qs) |
| ); |
| |
| |
| // R[upload_status]: V(False) |
| // F[cmdfifo_depth]: 4:0 |
| prim_subreg #( |
| .DW (5), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (5'h0) |
| ) u_upload_status_cmdfifo_depth ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.upload_status.cmdfifo_depth.de), |
| .d (hw2reg.upload_status.cmdfifo_depth.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (upload_status_cmdfifo_depth_qs) |
| ); |
| |
| // F[cmdfifo_notempty]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (1'h0) |
| ) u_upload_status_cmdfifo_notempty ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.upload_status.cmdfifo_notempty.de), |
| .d (hw2reg.upload_status.cmdfifo_notempty.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (upload_status_cmdfifo_notempty_qs) |
| ); |
| |
| // F[addrfifo_depth]: 12:8 |
| prim_subreg #( |
| .DW (5), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (5'h0) |
| ) u_upload_status_addrfifo_depth ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.upload_status.addrfifo_depth.de), |
| .d (hw2reg.upload_status.addrfifo_depth.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (upload_status_addrfifo_depth_qs) |
| ); |
| |
| // F[addrfifo_notempty]: 15:15 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (1'h0) |
| ) u_upload_status_addrfifo_notempty ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.upload_status.addrfifo_notempty.de), |
| .d (hw2reg.upload_status.addrfifo_notempty.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (upload_status_addrfifo_notempty_qs) |
| ); |
| |
| |
| // R[upload_status2]: V(False) |
| // F[payload_depth]: 8:0 |
| prim_subreg #( |
| .DW (9), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (9'h0) |
| ) u_upload_status2_payload_depth ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.upload_status2.payload_depth.de), |
| .d (hw2reg.upload_status2.payload_depth.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (upload_status2_payload_depth_qs) |
| ); |
| |
| // F[payload_start_idx]: 23:16 |
| prim_subreg #( |
| .DW (8), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (8'h0) |
| ) u_upload_status2_payload_start_idx ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.upload_status2.payload_start_idx.de), |
| .d (hw2reg.upload_status2.payload_start_idx.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (upload_status2_payload_start_idx_qs) |
| ); |
| |
| |
| // R[upload_cmdfifo]: V(True) |
| prim_subreg_ext #( |
| .DW (8) |
| ) u_upload_cmdfifo ( |
| .re (upload_cmdfifo_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.upload_cmdfifo.d), |
| .qre (reg2hw.upload_cmdfifo.re), |
| .qe (), |
| .q (reg2hw.upload_cmdfifo.q), |
| .ds (), |
| .qs (upload_cmdfifo_qs) |
| ); |
| |
| |
| // R[upload_addrfifo]: V(True) |
| prim_subreg_ext #( |
| .DW (32) |
| ) u_upload_addrfifo ( |
| .re (upload_addrfifo_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.upload_addrfifo.d), |
| .qre (reg2hw.upload_addrfifo.re), |
| .qe (), |
| .q (reg2hw.upload_addrfifo.q), |
| .ds (), |
| .qs (upload_addrfifo_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg cmd_filter |
| // R[cmd_filter_0]: V(False) |
| // F[filter_0]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[0].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_0_qs) |
| ); |
| |
| // F[filter_1]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[1].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_1_qs) |
| ); |
| |
| // F[filter_2]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[2].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_2_qs) |
| ); |
| |
| // F[filter_3]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[3].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_3_qs) |
| ); |
| |
| // F[filter_4]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[4].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_4_qs) |
| ); |
| |
| // F[filter_5]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[5].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_5_qs) |
| ); |
| |
| // F[filter_6]: 6:6 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[6].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_6_qs) |
| ); |
| |
| // F[filter_7]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[7].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_7_qs) |
| ); |
| |
| // F[filter_8]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_8_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[8].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_8_qs) |
| ); |
| |
| // F[filter_9]: 9:9 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_9_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[9].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_9_qs) |
| ); |
| |
| // F[filter_10]: 10:10 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_10_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[10].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_10_qs) |
| ); |
| |
| // F[filter_11]: 11:11 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_11 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_11_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[11].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_11_qs) |
| ); |
| |
| // F[filter_12]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_12 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_12_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[12].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_12_qs) |
| ); |
| |
| // F[filter_13]: 13:13 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_13 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_13_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[13].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_13_qs) |
| ); |
| |
| // F[filter_14]: 14:14 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_14 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_14_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[14].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_14_qs) |
| ); |
| |
| // F[filter_15]: 15:15 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_15 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_15_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[15].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_15_qs) |
| ); |
| |
| // F[filter_16]: 16:16 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_16 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_16_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[16].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_16_qs) |
| ); |
| |
| // F[filter_17]: 17:17 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_17 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_17_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[17].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_17_qs) |
| ); |
| |
| // F[filter_18]: 18:18 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_18 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_18_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[18].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_18_qs) |
| ); |
| |
| // F[filter_19]: 19:19 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_19 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_19_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[19].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_19_qs) |
| ); |
| |
| // F[filter_20]: 20:20 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_20 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_20_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[20].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_20_qs) |
| ); |
| |
| // F[filter_21]: 21:21 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_21 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_21_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[21].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_21_qs) |
| ); |
| |
| // F[filter_22]: 22:22 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_22 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_22_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[22].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_22_qs) |
| ); |
| |
| // F[filter_23]: 23:23 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_23 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_23_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[23].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_23_qs) |
| ); |
| |
| // F[filter_24]: 24:24 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_24 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_24_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[24].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_24_qs) |
| ); |
| |
| // F[filter_25]: 25:25 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_25 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_25_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[25].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_25_qs) |
| ); |
| |
| // F[filter_26]: 26:26 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_26 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_26_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[26].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_26_qs) |
| ); |
| |
| // F[filter_27]: 27:27 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_27 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_27_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[27].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_27_qs) |
| ); |
| |
| // F[filter_28]: 28:28 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_28 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_28_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[28].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_28_qs) |
| ); |
| |
| // F[filter_29]: 29:29 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_29 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cmd_filter_0_we), |
| .wd (cmd_filter_0_filter_29_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cmd_filter[29].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cmd_filter_0_filter_29_qs) |
| ); |
| |
| // F[filter_30]: 30:30 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_cmd_filter_0_filter_30 ( |
| .clk_i (clk_i), |
|
