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opensecura / 3p / lowrisc / opentitan / 1dd0765805a537a8b48139ff695101d04d073214 / . / hw / ip / usbdev / rtl / usbdev_reg_top.sv
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Top module auto-generated by `reggen`
module usbdev_reg_top (
input clk_i,
input rst_ni,
// Below Regster interface can be changed
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
// Output port for window
output tlul_pkg::tl_h2d_t tl_win_o [1],
input tlul_pkg::tl_d2h_t tl_win_i [1],
// To HW
output usbdev_reg_pkg::usbdev_reg2hw_t reg2hw, // Write
input usbdev_reg_pkg::usbdev_hw2reg_t hw2reg // Read
);
import usbdev_reg_pkg::* ;
localparam AW = 12;
localparam IW = $bits(tl_i.a_source);
localparam DW = 32;
localparam DBW = DW/8; // Byte Width
localparam logic [$clog2($clog2(DBW)+1)-1:0] FSZ = $clog2(DBW); // Full Size 2^(FSZ) = DBW;
// register signals
logic reg_we;
logic reg_re;
logic [AW-1:0] reg_addr;
logic [DW-1:0] reg_wdata;
logic reg_valid;
logic [DW-1:0] reg_rdata;
logic tl_malformed, tl_addrmiss;
// Bus signals
tlul_pkg::tl_d_op_e rsp_opcode; // AccessAck or AccessAckData
logic reqready;
logic [IW-1:0] reqid;
logic [IW-1:0] rspid;
logic outstanding;
tlul_pkg::tl_h2d_t tl_reg_h2d;
tlul_pkg::tl_d2h_t tl_reg_d2h;
tlul_pkg::tl_h2d_t tl_socket_h2d [2];
tlul_pkg::tl_d2h_t tl_socket_d2h [2];
logic [1:0] reg_steer;
// socket_1n connection
assign tl_reg_h2d = tl_socket_h2d[1];
assign tl_socket_d2h[1] = tl_reg_d2h;
assign tl_win_o[0] = tl_socket_h2d[0];
assign tl_socket_d2h[0] = tl_win_i[0];
// Create Socket_1n
tlul_socket_1n #(
.N (2),
.HReqPass (1'b1),
.HRspPass (1'b1),
.DReqPass ({2{1'b1}}),
.DRspPass ({2{1'b1}}),
.HReqDepth (4'h1),
.HRspDepth (4'h1),
.DReqDepth ({2{4'h1}}),
.DRspDepth ({2{4'h1}})
) u_socket (
.clk_i,
.rst_ni,
.tl_h_i (tl_i),
.tl_h_o (tl_o),
.tl_d_o (tl_socket_h2d),
.tl_d_i (tl_socket_d2h),
.dev_select (reg_steer)
);
// Create steering logic
always_comb begin
reg_steer = 1; // Default set to register
// TODO: Can below codes be unique case () inside ?
if (tl_i.a_address[AW-1:0] >= 2048 && tl_i.a_address[AW-1:0] < 4096) begin
reg_steer = 0;
end
end
// TODO(eunchan): Fix it after bus interface is finalized
assign reg_we = tl_reg_h2d.a_valid && tl_reg_d2h.a_ready &&
((tl_reg_h2d.a_opcode == tlul_pkg::PutFullData) ||
(tl_reg_h2d.a_opcode == tlul_pkg::PutPartialData));
assign reg_re = tl_reg_h2d.a_valid && tl_reg_d2h.a_ready &&
(tl_reg_h2d.a_opcode == tlul_pkg::Get);
assign reg_addr = tl_reg_h2d.a_address[AW-1:0];
assign reg_wdata = tl_reg_h2d.a_data;
assign tl_reg_d2h.d_valid = reg_valid;
assign tl_reg_d2h.d_opcode = rsp_opcode;
assign tl_reg_d2h.d_param = '0;
assign tl_reg_d2h.d_size = FSZ; // always Full Size
assign tl_reg_d2h.d_source = rspid;
assign tl_reg_d2h.d_sink = '0; // Used in TL-C
assign tl_reg_d2h.d_data = reg_rdata;
assign tl_reg_d2h.d_user = '0; // Doesn't allow additional features yet
assign tl_reg_d2h.d_error = tl_malformed | tl_addrmiss;
assign tl_reg_d2h.a_ready = reqready;
assign reqid = tl_reg_h2d.a_source;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
tl_malformed <= 1'b1;
end else if (tl_reg_h2d.a_valid && tl_reg_d2h.a_ready) begin
if ((tl_reg_h2d.a_opcode != tlul_pkg::Get) &&
(tl_reg_h2d.a_opcode != tlul_pkg::PutFullData) &&
(tl_reg_h2d.a_opcode != tlul_pkg::PutPartialData)) begin
tl_malformed <= 1'b1;
// Only allow Full Write with full mask
end else if (tl_reg_h2d.a_size != FSZ || tl_reg_h2d.a_mask != {DBW{1'b1}}) begin
tl_malformed <= 1'b1;
end else if (tl_reg_h2d.a_user.parity_en == 1'b1) begin
tl_malformed <= 1'b1;
end else begin
tl_malformed <= 1'b0;
end
end
end
// TODO(eunchan): Revise Register Interface logic after REG INTF finalized
// TODO(eunchan): Make concrete scenario
// 1. Write: No response, so that it can guarantee a request completes a clock after we
// It means, bus_reg_ready doesn't have to be lowered.
// 2. Read: response. So bus_reg_ready should assert after reg_bus_valid & reg_bus_ready
// _____ _____
// a_valid _____/ \_______/ \______
// ___________ _____
// a_ready \_______/ \______ <- ERR though no logic malfunction
// _____________
// d_valid ___________/ \______
// _____
// d_ready ___________________/ \______
//
// Above example is fine but if r.b.r doesn't assert within two cycle, then it can be wrong.
always_ff @(posedge clk_i or negedge rst_ni) begin
// Not to accept new request when a request is handling
// #Outstanding := 1
if (!rst_ni) begin
reqready <= 1'b0;
end else if (reg_we || reg_re) begin
reqready <= 1'b0;
end else if (outstanding == 1'b0) begin
reqready <= 1'b1;
end
end
// Request/ Response ID
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rspid <= '0;
end else if (reg_we || reg_re) begin
rspid <= reqid;
end
end
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
// or <reg>_{wd|we|qs} if field == 1 or 0
logic intr_state_pkt_received_qs;
logic intr_state_pkt_received_wd;
logic intr_state_pkt_received_we;
logic intr_state_pkt_sent_qs;
logic intr_state_pkt_sent_wd;
logic intr_state_pkt_sent_we;
logic intr_state_disconnected_qs;
logic intr_state_disconnected_wd;
logic intr_state_disconnected_we;
logic intr_state_host_lost_qs;
logic intr_state_host_lost_wd;
logic intr_state_host_lost_we;
logic intr_state_link_reset_qs;
logic intr_state_link_reset_wd;
logic intr_state_link_reset_we;
logic intr_state_link_suspend_qs;
logic intr_state_link_suspend_wd;
logic intr_state_link_suspend_we;
logic intr_state_link_resume_qs;
logic intr_state_link_resume_wd;
logic intr_state_link_resume_we;
logic intr_state_av_empty_qs;
logic intr_state_av_empty_wd;
logic intr_state_av_empty_we;
logic intr_state_rx_full_qs;
logic intr_state_rx_full_wd;
logic intr_state_rx_full_we;
logic intr_state_av_overflow_qs;
logic intr_state_av_overflow_wd;
logic intr_state_av_overflow_we;
logic intr_enable_pkt_received_qs;
logic intr_enable_pkt_received_wd;
logic intr_enable_pkt_received_we;
logic intr_enable_pkt_sent_qs;
logic intr_enable_pkt_sent_wd;
logic intr_enable_pkt_sent_we;
logic intr_enable_disconnected_qs;
logic intr_enable_disconnected_wd;
logic intr_enable_disconnected_we;
logic intr_enable_host_lost_qs;
logic intr_enable_host_lost_wd;
logic intr_enable_host_lost_we;
logic intr_enable_link_reset_qs;
logic intr_enable_link_reset_wd;
logic intr_enable_link_reset_we;
logic intr_enable_link_suspend_qs;
logic intr_enable_link_suspend_wd;
logic intr_enable_link_suspend_we;
logic intr_enable_link_resume_qs;
logic intr_enable_link_resume_wd;
logic intr_enable_link_resume_we;
logic intr_enable_av_empty_qs;
logic intr_enable_av_empty_wd;
logic intr_enable_av_empty_we;
logic intr_enable_rx_full_qs;
logic intr_enable_rx_full_wd;
logic intr_enable_rx_full_we;
logic intr_enable_av_overflow_qs;
logic intr_enable_av_overflow_wd;
logic intr_enable_av_overflow_we;
logic intr_test_pkt_received_wd;
logic intr_test_pkt_received_we;
logic intr_test_pkt_sent_wd;
logic intr_test_pkt_sent_we;
logic intr_test_disconnected_wd;
logic intr_test_disconnected_we;
logic intr_test_host_lost_wd;
logic intr_test_host_lost_we;
logic intr_test_link_reset_wd;
logic intr_test_link_reset_we;
logic intr_test_link_suspend_wd;
logic intr_test_link_suspend_we;
logic intr_test_link_resume_wd;
logic intr_test_link_resume_we;
logic intr_test_av_empty_wd;
logic intr_test_av_empty_we;
logic intr_test_rx_full_wd;
logic intr_test_rx_full_we;
logic intr_test_av_overflow_wd;
logic intr_test_av_overflow_we;
logic usbctrl_enable_qs;
logic usbctrl_enable_wd;
logic usbctrl_enable_we;
logic [6:0] usbctrl_device_address_qs;
logic [6:0] usbctrl_device_address_wd;
logic usbctrl_device_address_we;
logic [10:0] usbstat_frame_qs;
logic usbstat_frame_re;
logic usbstat_host_lost_qs;
logic usbstat_host_lost_re;
logic [1:0] usbstat_link_state_qs;
logic usbstat_link_state_re;
logic usbstat_usb_sense_qs;
logic usbstat_usb_sense_re;
logic [2:0] usbstat_av_depth_qs;
logic usbstat_av_depth_re;
logic usbstat_av_full_qs;
logic usbstat_av_full_re;
logic [2:0] usbstat_rx_depth_qs;
logic usbstat_rx_depth_re;
logic usbstat_rx_empty_qs;
logic usbstat_rx_empty_re;
logic [4:0] avbuffer_wd;
logic avbuffer_we;
logic [4:0] rxfifo_buffer_qs;
logic rxfifo_buffer_re;
logic [6:0] rxfifo_size_qs;
logic rxfifo_size_re;
logic rxfifo_setup_qs;
logic rxfifo_setup_re;
logic [3:0] rxfifo_ep_qs;
logic rxfifo_ep_re;
logic rxenable_setup0_qs;
logic rxenable_setup0_wd;
logic rxenable_setup0_we;
logic rxenable_setup1_qs;
logic rxenable_setup1_wd;
logic rxenable_setup1_we;
logic rxenable_setup2_qs;
logic rxenable_setup2_wd;
logic rxenable_setup2_we;
logic rxenable_setup3_qs;
logic rxenable_setup3_wd;
logic rxenable_setup3_we;
logic rxenable_setup4_qs;
logic rxenable_setup4_wd;
logic rxenable_setup4_we;
logic rxenable_setup5_qs;
logic rxenable_setup5_wd;
logic rxenable_setup5_we;
logic rxenable_setup6_qs;
logic rxenable_setup6_wd;
logic rxenable_setup6_we;
logic rxenable_setup7_qs;
logic rxenable_setup7_wd;
logic rxenable_setup7_we;
logic rxenable_setup8_qs;
logic rxenable_setup8_wd;
logic rxenable_setup8_we;
logic rxenable_setup9_qs;
logic rxenable_setup9_wd;
logic rxenable_setup9_we;
logic rxenable_setup10_qs;
logic rxenable_setup10_wd;
logic rxenable_setup10_we;
logic rxenable_setup11_qs;
logic rxenable_setup11_wd;
logic rxenable_setup11_we;
logic rxenable_out0_qs;
logic rxenable_out0_wd;
logic rxenable_out0_we;
logic rxenable_out1_qs;
logic rxenable_out1_wd;
logic rxenable_out1_we;
logic rxenable_out2_qs;
logic rxenable_out2_wd;
logic rxenable_out2_we;
logic rxenable_out3_qs;
logic rxenable_out3_wd;
logic rxenable_out3_we;
logic rxenable_out4_qs;
logic rxenable_out4_wd;
logic rxenable_out4_we;
logic rxenable_out5_qs;
logic rxenable_out5_wd;
logic rxenable_out5_we;
logic rxenable_out6_qs;
logic rxenable_out6_wd;
logic rxenable_out6_we;
logic rxenable_out7_qs;
logic rxenable_out7_wd;
logic rxenable_out7_we;
logic rxenable_out8_qs;
logic rxenable_out8_wd;
logic rxenable_out8_we;
logic rxenable_out9_qs;
logic rxenable_out9_wd;
logic rxenable_out9_we;
logic rxenable_out10_qs;
logic rxenable_out10_wd;
logic rxenable_out10_we;
logic rxenable_out11_qs;
logic rxenable_out11_wd;
logic rxenable_out11_we;
logic in_sent_sent0_qs;
logic in_sent_sent0_wd;
logic in_sent_sent0_we;
logic in_sent_sent1_qs;
logic in_sent_sent1_wd;
logic in_sent_sent1_we;
logic in_sent_sent2_qs;
logic in_sent_sent2_wd;
logic in_sent_sent2_we;
logic in_sent_sent3_qs;
logic in_sent_sent3_wd;
logic in_sent_sent3_we;
logic in_sent_sent4_qs;
logic in_sent_sent4_wd;
logic in_sent_sent4_we;
logic in_sent_sent5_qs;
logic in_sent_sent5_wd;
logic in_sent_sent5_we;
logic in_sent_sent6_qs;
logic in_sent_sent6_wd;
logic in_sent_sent6_we;
logic in_sent_sent7_qs;
logic in_sent_sent7_wd;
logic in_sent_sent7_we;
logic in_sent_sent8_qs;
logic in_sent_sent8_wd;
logic in_sent_sent8_we;
logic in_sent_sent9_qs;
logic in_sent_sent9_wd;
logic in_sent_sent9_we;
logic in_sent_sent10_qs;
logic in_sent_sent10_wd;
logic in_sent_sent10_we;
logic in_sent_sent11_qs;
logic in_sent_sent11_wd;
logic in_sent_sent11_we;
logic stall_stall0_qs;
logic stall_stall0_wd;
logic stall_stall0_we;
logic stall_stall1_qs;
logic stall_stall1_wd;
logic stall_stall1_we;
logic stall_stall2_qs;
logic stall_stall2_wd;
logic stall_stall2_we;
logic stall_stall3_qs;
logic stall_stall3_wd;
logic stall_stall3_we;
logic stall_stall4_qs;
logic stall_stall4_wd;
logic stall_stall4_we;
logic stall_stall5_qs;
logic stall_stall5_wd;
logic stall_stall5_we;
logic stall_stall6_qs;
logic stall_stall6_wd;
logic stall_stall6_we;
logic stall_stall7_qs;
logic stall_stall7_wd;
logic stall_stall7_we;
logic stall_stall8_qs;
logic stall_stall8_wd;
logic stall_stall8_we;
logic stall_stall9_qs;
logic stall_stall9_wd;
logic stall_stall9_we;
logic stall_stall10_qs;
logic stall_stall10_wd;
logic stall_stall10_we;
logic stall_stall11_qs;
logic stall_stall11_wd;
logic stall_stall11_we;
logic [4:0] configin0_buffer0_qs;
logic [4:0] configin0_buffer0_wd;
logic configin0_buffer0_we;
logic [6:0] configin0_size0_qs;
logic [6:0] configin0_size0_wd;
logic configin0_size0_we;
logic configin0_pend0_qs;
logic configin0_pend0_wd;
logic configin0_pend0_we;
logic configin0_rdy0_qs;
logic configin0_rdy0_wd;
logic configin0_rdy0_we;
logic [4:0] configin1_buffer1_qs;
logic [4:0] configin1_buffer1_wd;
logic configin1_buffer1_we;
logic [6:0] configin1_size1_qs;
logic [6:0] configin1_size1_wd;
logic configin1_size1_we;
logic configin1_pend1_qs;
logic configin1_pend1_wd;
logic configin1_pend1_we;
logic configin1_rdy1_qs;
logic configin1_rdy1_wd;
logic configin1_rdy1_we;
logic [4:0] configin2_buffer2_qs;
logic [4:0] configin2_buffer2_wd;
logic configin2_buffer2_we;
logic [6:0] configin2_size2_qs;
logic [6:0] configin2_size2_wd;
logic configin2_size2_we;
logic configin2_pend2_qs;
logic configin2_pend2_wd;
logic configin2_pend2_we;
logic configin2_rdy2_qs;
logic configin2_rdy2_wd;
logic configin2_rdy2_we;
logic [4:0] configin3_buffer3_qs;
logic [4:0] configin3_buffer3_wd;
logic configin3_buffer3_we;
logic [6:0] configin3_size3_qs;
logic [6:0] configin3_size3_wd;
logic configin3_size3_we;
logic configin3_pend3_qs;
logic configin3_pend3_wd;
logic configin3_pend3_we;
logic configin3_rdy3_qs;
logic configin3_rdy3_wd;
logic configin3_rdy3_we;
logic [4:0] configin4_buffer4_qs;
logic [4:0] configin4_buffer4_wd;
logic configin4_buffer4_we;
logic [6:0] configin4_size4_qs;
logic [6:0] configin4_size4_wd;
logic configin4_size4_we;
logic configin4_pend4_qs;
logic configin4_pend4_wd;
logic configin4_pend4_we;
logic configin4_rdy4_qs;
logic configin4_rdy4_wd;
logic configin4_rdy4_we;
logic [4:0] configin5_buffer5_qs;
logic [4:0] configin5_buffer5_wd;
logic configin5_buffer5_we;
logic [6:0] configin5_size5_qs;
logic [6:0] configin5_size5_wd;
logic configin5_size5_we;
logic configin5_pend5_qs;
logic configin5_pend5_wd;
logic configin5_pend5_we;
logic configin5_rdy5_qs;
logic configin5_rdy5_wd;
logic configin5_rdy5_we;
logic [4:0] configin6_buffer6_qs;
logic [4:0] configin6_buffer6_wd;
logic configin6_buffer6_we;
logic [6:0] configin6_size6_qs;
logic [6:0] configin6_size6_wd;
logic configin6_size6_we;
logic configin6_pend6_qs;
logic configin6_pend6_wd;
logic configin6_pend6_we;
logic configin6_rdy6_qs;
logic configin6_rdy6_wd;
logic configin6_rdy6_we;
logic [4:0] configin7_buffer7_qs;
logic [4:0] configin7_buffer7_wd;
logic configin7_buffer7_we;
logic [6:0] configin7_size7_qs;
logic [6:0] configin7_size7_wd;
logic configin7_size7_we;
logic configin7_pend7_qs;
logic configin7_pend7_wd;
logic configin7_pend7_we;
logic configin7_rdy7_qs;
logic configin7_rdy7_wd;
logic configin7_rdy7_we;
logic [4:0] configin8_buffer8_qs;
logic [4:0] configin8_buffer8_wd;
logic configin8_buffer8_we;
logic [6:0] configin8_size8_qs;
logic [6:0] configin8_size8_wd;
logic configin8_size8_we;
logic configin8_pend8_qs;
logic configin8_pend8_wd;
logic configin8_pend8_we;
logic configin8_rdy8_qs;
logic configin8_rdy8_wd;
logic configin8_rdy8_we;
logic [4:0] configin9_buffer9_qs;
logic [4:0] configin9_buffer9_wd;
logic configin9_buffer9_we;
logic [6:0] configin9_size9_qs;
logic [6:0] configin9_size9_wd;
logic configin9_size9_we;
logic configin9_pend9_qs;
logic configin9_pend9_wd;
logic configin9_pend9_we;
logic configin9_rdy9_qs;
logic configin9_rdy9_wd;
logic configin9_rdy9_we;
logic [4:0] configin10_buffer10_qs;
logic [4:0] configin10_buffer10_wd;
logic configin10_buffer10_we;
logic [6:0] configin10_size10_qs;
logic [6:0] configin10_size10_wd;
logic configin10_size10_we;
logic configin10_pend10_qs;
logic configin10_pend10_wd;
logic configin10_pend10_we;
logic configin10_rdy10_qs;
logic configin10_rdy10_wd;
logic configin10_rdy10_we;
logic [4:0] configin11_buffer11_qs;
logic [4:0] configin11_buffer11_wd;
logic configin11_buffer11_we;
logic [6:0] configin11_size11_qs;
logic [6:0] configin11_size11_wd;
logic configin11_size11_we;
logic configin11_pend11_qs;
logic configin11_pend11_wd;
logic configin11_pend11_we;
logic configin11_rdy11_qs;
logic configin11_rdy11_wd;
logic configin11_rdy11_we;
// Register instances
// R[intr_state]: V(False)
// F[pkt_received]: 0:0
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_pkt_received (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_state_pkt_received_we),
.wd (intr_state_pkt_received_wd),
// from internal hardware
.de (hw2reg.intr_state.pkt_received.de),
.d (hw2reg.intr_state.pkt_received.d ),
// to internal hardware
.qe (),
.q (reg2hw.intr_state.pkt_received.q ),
// to register interface (read)
.qs (intr_state_pkt_received_qs)
);
// F[pkt_sent]: 1:1
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_pkt_sent (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_state_pkt_sent_we),
.wd (intr_state_pkt_sent_wd),
// from internal hardware
.de (hw2reg.intr_state.pkt_sent.de),
.d (hw2reg.intr_state.pkt_sent.d ),
// to internal hardware
.qe (),
.q (reg2hw.intr_state.pkt_sent.q ),
// to register interface (read)
.qs (intr_state_pkt_sent_qs)
);
// F[disconnected]: 2:2
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_disconnected (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_state_disconnected_we),
.wd (intr_state_disconnected_wd),
// from internal hardware
.de (hw2reg.intr_state.disconnected.de),
.d (hw2reg.intr_state.disconnected.d ),
// to internal hardware
.qe (),
.q (reg2hw.intr_state.disconnected.q ),
// to register interface (read)
.qs (intr_state_disconnected_qs)
);
// F[host_lost]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_host_lost (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_state_host_lost_we),
.wd (intr_state_host_lost_wd),
// from internal hardware
.de (hw2reg.intr_state.host_lost.de),
.d (hw2reg.intr_state.host_lost.d ),
// to internal hardware
.qe (),
.q (reg2hw.intr_state.host_lost.q ),
// to register interface (read)
.qs (intr_state_host_lost_qs)
);
// F[link_reset]: 4:4
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_link_reset (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_state_link_reset_we),
.wd (intr_state_link_reset_wd),
// from internal hardware
.de (hw2reg.intr_state.link_reset.de),
.d (hw2reg.intr_state.link_reset.d ),
// to internal hardware
.qe (),
.q (reg2hw.intr_state.link_reset.q ),
// to register interface (read)
.qs (intr_state_link_reset_qs)
);
// F[link_suspend]: 5:5
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_link_suspend (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_state_link_suspend_we),
.wd (intr_state_link_suspend_wd),
// from internal hardware
.de (hw2reg.intr_state.link_suspend.de),
.d (hw2reg.intr_state.link_suspend.d ),
// to internal hardware
.qe (),
.q (reg2hw.intr_state.link_suspend.q ),
// to register interface (read)
.qs (intr_state_link_suspend_qs)
);
// F[link_resume]: 6:6
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_link_resume (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_state_link_resume_we),
.wd (intr_state_link_resume_wd),
// from internal hardware
.de (hw2reg.intr_state.link_resume.de),
.d (hw2reg.intr_state.link_resume.d ),
// to internal hardware
.qe (),
.q (reg2hw.intr_state.link_resume.q ),
// to register interface (read)
.qs (intr_state_link_resume_qs)
);
// F[av_empty]: 7:7
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_av_empty (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_state_av_empty_we),
.wd (intr_state_av_empty_wd),
// from internal hardware
.de (hw2reg.intr_state.av_empty.de),
.d (hw2reg.intr_state.av_empty.d ),
// to internal hardware
.qe (),
.q (reg2hw.intr_state.av_empty.q ),
// to register interface (read)
.qs (intr_state_av_empty_qs)
);
// F[rx_full]: 8:8
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rx_full (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_state_rx_full_we),
.wd (intr_state_rx_full_wd),
// from internal hardware
.de (hw2reg.intr_state.rx_full.de),
.d (hw2reg.intr_state.rx_full.d ),
// to internal hardware
.qe (),
.q (reg2hw.intr_state.rx_full.q ),
// to register interface (read)
.qs (intr_state_rx_full_qs)
);
// F[av_overflow]: 9:9
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_av_overflow (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_state_av_overflow_we),
.wd (intr_state_av_overflow_wd),
// from internal hardware
.de (hw2reg.intr_state.av_overflow.de),
.d (hw2reg.intr_state.av_overflow.d ),
// to internal hardware
.qe (),
.q (reg2hw.intr_state.av_overflow.q ),
// to register interface (read)
.qs (intr_state_av_overflow_qs)
);
// R[intr_enable]: V(False)
// F[pkt_received]: 0:0
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_pkt_received (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_enable_pkt_received_we),
.wd (intr_enable_pkt_received_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.intr_enable.pkt_received.q ),
// to register interface (read)
.qs (intr_enable_pkt_received_qs)
);
// F[pkt_sent]: 1:1
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_pkt_sent (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_enable_pkt_sent_we),
.wd (intr_enable_pkt_sent_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.intr_enable.pkt_sent.q ),
// to register interface (read)
.qs (intr_enable_pkt_sent_qs)
);
// F[disconnected]: 2:2
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_disconnected (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_enable_disconnected_we),
.wd (intr_enable_disconnected_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.intr_enable.disconnected.q ),
// to register interface (read)
.qs (intr_enable_disconnected_qs)
);
// F[host_lost]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_host_lost (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_enable_host_lost_we),
.wd (intr_enable_host_lost_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.intr_enable.host_lost.q ),
// to register interface (read)
.qs (intr_enable_host_lost_qs)
);
// F[link_reset]: 4:4
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_link_reset (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_enable_link_reset_we),
.wd (intr_enable_link_reset_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.intr_enable.link_reset.q ),
// to register interface (read)
.qs (intr_enable_link_reset_qs)
);
// F[link_suspend]: 5:5
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_link_suspend (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_enable_link_suspend_we),
.wd (intr_enable_link_suspend_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.intr_enable.link_suspend.q ),
// to register interface (read)
.qs (intr_enable_link_suspend_qs)
);
// F[link_resume]: 6:6
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_link_resume (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_enable_link_resume_we),
.wd (intr_enable_link_resume_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.intr_enable.link_resume.q ),
// to register interface (read)
.qs (intr_enable_link_resume_qs)
);
// F[av_empty]: 7:7
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_av_empty (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_enable_av_empty_we),
.wd (intr_enable_av_empty_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.intr_enable.av_empty.q ),
// to register interface (read)
.qs (intr_enable_av_empty_qs)
);
// F[rx_full]: 8:8
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rx_full (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_enable_rx_full_we),
.wd (intr_enable_rx_full_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.intr_enable.rx_full.q ),
// to register interface (read)
.qs (intr_enable_rx_full_qs)
);
// F[av_overflow]: 9:9
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_av_overflow (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (intr_enable_av_overflow_we),
.wd (intr_enable_av_overflow_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.intr_enable.av_overflow.q ),
// to register interface (read)
.qs (intr_enable_av_overflow_qs)
);
// R[intr_test]: V(True)
// F[pkt_received]: 0:0
prim_subreg_ext #(
.DW (1)
) u_intr_test_pkt_received (
.re (1'b0),
.we (intr_test_pkt_received_we),
.wd (intr_test_pkt_received_wd),
.d ('0),
.qre (),
.qe (reg2hw.intr_test.pkt_received.qe),
.q (reg2hw.intr_test.pkt_received.q ),
.qs ()
);
// F[pkt_sent]: 1:1
prim_subreg_ext #(
.DW (1)
) u_intr_test_pkt_sent (
.re (1'b0),
.we (intr_test_pkt_sent_we),
.wd (intr_test_pkt_sent_wd),
.d ('0),
.qre (),
.qe (reg2hw.intr_test.pkt_sent.qe),
.q (reg2hw.intr_test.pkt_sent.q ),
.qs ()
);
// F[disconnected]: 2:2
prim_subreg_ext #(
.DW (1)
) u_intr_test_disconnected (
.re (1'b0),
.we (intr_test_disconnected_we),
.wd (intr_test_disconnected_wd),
.d ('0),
.qre (),
.qe (reg2hw.intr_test.disconnected.qe),
.q (reg2hw.intr_test.disconnected.q ),
.qs ()
);
// F[host_lost]: 3:3
prim_subreg_ext #(
.DW (1)
) u_intr_test_host_lost (
.re (1'b0),
.we (intr_test_host_lost_we),
.wd (intr_test_host_lost_wd),
.d ('0),
.qre (),
.qe (reg2hw.intr_test.host_lost.qe),
.q (reg2hw.intr_test.host_lost.q ),
.qs ()
);
// F[link_reset]: 4:4
prim_subreg_ext #(
.DW (1)
) u_intr_test_link_reset (
.re (1'b0),
.we (intr_test_link_reset_we),
.wd (intr_test_link_reset_wd),
.d ('0),
.qre (),
.qe (reg2hw.intr_test.link_reset.qe),
.q (reg2hw.intr_test.link_reset.q ),
.qs ()
);
// F[link_suspend]: 5:5
prim_subreg_ext #(
.DW (1)
) u_intr_test_link_suspend (
.re (1'b0),
.we (intr_test_link_suspend_we),
.wd (intr_test_link_suspend_wd),
.d ('0),
.qre (),
.qe (reg2hw.intr_test.link_suspend.qe),
.q (reg2hw.intr_test.link_suspend.q ),
.qs ()
);
// F[link_resume]: 6:6
prim_subreg_ext #(
.DW (1)
) u_intr_test_link_resume (
.re (1'b0),
.we (intr_test_link_resume_we),
.wd (intr_test_link_resume_wd),
.d ('0),
.qre (),
.qe (reg2hw.intr_test.link_resume.qe),
.q (reg2hw.intr_test.link_resume.q ),
.qs ()
);
// F[av_empty]: 7:7
prim_subreg_ext #(
.DW (1)
) u_intr_test_av_empty (
.re (1'b0),
.we (intr_test_av_empty_we),
.wd (intr_test_av_empty_wd),
.d ('0),
.qre (),
.qe (reg2hw.intr_test.av_empty.qe),
.q (reg2hw.intr_test.av_empty.q ),
.qs ()
);
// F[rx_full]: 8:8
prim_subreg_ext #(
.DW (1)
) u_intr_test_rx_full (
.re (1'b0),
.we (intr_test_rx_full_we),
.wd (intr_test_rx_full_wd),
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rx_full.qe),
.q (reg2hw.intr_test.rx_full.q ),
.qs ()
);
// F[av_overflow]: 9:9
prim_subreg_ext #(
.DW (1)
) u_intr_test_av_overflow (
.re (1'b0),
.we (intr_test_av_overflow_we),
.wd (intr_test_av_overflow_wd),
.d ('0),
.qre (),
.qe (reg2hw.intr_test.av_overflow.qe),
.q (reg2hw.intr_test.av_overflow.q ),
.qs ()
);
// R[usbctrl]: V(False)
// F[enable]: 0:0
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_usbctrl_enable (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (usbctrl_enable_we),
.wd (usbctrl_enable_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.usbctrl.enable.q ),
// to register interface (read)
.qs (usbctrl_enable_qs)
);
// F[device_address]: 22:16
prim_subreg #(
.DW (7),
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_usbctrl_device_address (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (usbctrl_device_address_we),
.wd (usbctrl_device_address_wd),
// from internal hardware
.de (hw2reg.usbctrl.device_address.de),
.d (hw2reg.usbctrl.device_address.d ),
// to internal hardware
.qe (),
.q (reg2hw.usbctrl.device_address.q ),
// to register interface (read)
.qs (usbctrl_device_address_qs)
);
// R[usbstat]: V(True)
// F[frame]: 10:0
prim_subreg_ext #(
.DW (11)
) u_usbstat_frame (
.re (usbstat_frame_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.usbstat.frame.d),
.qre (),
.qe (),
.q (),
.qs (usbstat_frame_qs)
);
// F[host_lost]: 11:11
prim_subreg_ext #(
.DW (1)
) u_usbstat_host_lost (
.re (usbstat_host_lost_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.usbstat.host_lost.d),
.qre (),
.qe (),
.q (),
.qs (usbstat_host_lost_qs)
);
// F[link_state]: 13:12
prim_subreg_ext #(
.DW (2)
) u_usbstat_link_state (
.re (usbstat_link_state_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.usbstat.link_state.d),
.qre (),
.qe (),
.q (),
.qs (usbstat_link_state_qs)
);
// F[usb_sense]: 14:14
prim_subreg_ext #(
.DW (1)
) u_usbstat_usb_sense (
.re (usbstat_usb_sense_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.usbstat.usb_sense.d),
.qre (),
.qe (),
.q (),
.qs (usbstat_usb_sense_qs)
);
// F[av_depth]: 18:16
prim_subreg_ext #(
.DW (3)
) u_usbstat_av_depth (
.re (usbstat_av_depth_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.usbstat.av_depth.d),
.qre (),
.qe (),
.q (),
.qs (usbstat_av_depth_qs)
);
// F[av_full]: 23:23
prim_subreg_ext #(
.DW (1)
) u_usbstat_av_full (
.re (usbstat_av_full_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.usbstat.av_full.d),
.qre (),
.qe (),
.q (),
.qs (usbstat_av_full_qs)
);
// F[rx_depth]: 26:24
prim_subreg_ext #(
.DW (3)
) u_usbstat_rx_depth (
.re (usbstat_rx_depth_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.usbstat.rx_depth.d),
.qre (),
.qe (),
.q (),
.qs (usbstat_rx_depth_qs)
);
// F[rx_empty]: 31:31
prim_subreg_ext #(
.DW (1)
) u_usbstat_rx_empty (
.re (usbstat_rx_empty_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.usbstat.rx_empty.d),
.qre (),
.qe (),
.q (),
.qs (usbstat_rx_empty_qs)
);
// R[avbuffer]: V(False)
prim_subreg #(
.DW (5),
.SWACCESS("WO"),
.RESVAL (5'h0)
) u_avbuffer (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (avbuffer_we),
.wd (avbuffer_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (reg2hw.avbuffer.qe),
.q (reg2hw.avbuffer.q ),
.qs ()
);
// R[rxfifo]: V(True)
// F[buffer]: 4:0
prim_subreg_ext #(
.DW (5)
) u_rxfifo_buffer (
.re (rxfifo_buffer_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.rxfifo.buffer.d),
.qre (reg2hw.rxfifo.buffer.re),
.qe (),
.q (reg2hw.rxfifo.buffer.q ),
.qs (rxfifo_buffer_qs)
);
// F[size]: 14:8
prim_subreg_ext #(
.DW (7)
) u_rxfifo_size (
.re (rxfifo_size_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.rxfifo.size.d),
.qre (reg2hw.rxfifo.size.re),
.qe (),
.q (reg2hw.rxfifo.size.q ),
.qs (rxfifo_size_qs)
);
// F[setup]: 19:19
prim_subreg_ext #(
.DW (1)
) u_rxfifo_setup (
.re (rxfifo_setup_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.rxfifo.setup.d),
.qre (reg2hw.rxfifo.setup.re),
.qe (),
.q (reg2hw.rxfifo.setup.q ),
.qs (rxfifo_setup_qs)
);
// F[ep]: 23:20
prim_subreg_ext #(
.DW (4)
) u_rxfifo_ep (
.re (rxfifo_ep_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.rxfifo.ep.d),
.qre (reg2hw.rxfifo.ep.re),
.qe (),
.q (reg2hw.rxfifo.ep.q ),
.qs (rxfifo_ep_qs)
);
// R[rxenable]: V(False)
// F[setup0]: 0:0
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_setup0_we),
.wd (rxenable_setup0_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.setup0.q ),
// to register interface (read)
.qs (rxenable_setup0_qs)
);
// F[setup1]: 1:1
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_setup1_we),
.wd (rxenable_setup1_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.setup1.q ),
// to register interface (read)
.qs (rxenable_setup1_qs)
);
// F[setup2]: 2:2
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_setup2_we),
.wd (rxenable_setup2_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.setup2.q ),
// to register interface (read)
.qs (rxenable_setup2_qs)
);
// F[setup3]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_setup3_we),
.wd (rxenable_setup3_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.setup3.q ),
// to register interface (read)
.qs (rxenable_setup3_qs)
);
// F[setup4]: 4:4
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_setup4_we),
.wd (rxenable_setup4_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.setup4.q ),
// to register interface (read)
.qs (rxenable_setup4_qs)
);
// F[setup5]: 5:5
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_setup5_we),
.wd (rxenable_setup5_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.setup5.q ),
// to register interface (read)
.qs (rxenable_setup5_qs)
);
// F[setup6]: 6:6
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_setup6_we),
.wd (rxenable_setup6_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.setup6.q ),
// to register interface (read)
.qs (rxenable_setup6_qs)
);
// F[setup7]: 7:7
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_setup7_we),
.wd (rxenable_setup7_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.setup7.q ),
// to register interface (read)
.qs (rxenable_setup7_qs)
);
// F[setup8]: 8:8
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup8 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_setup8_we),
.wd (rxenable_setup8_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.setup8.q ),
// to register interface (read)
.qs (rxenable_setup8_qs)
);
// F[setup9]: 9:9
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup9 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_setup9_we),
.wd (rxenable_setup9_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.setup9.q ),
// to register interface (read)
.qs (rxenable_setup9_qs)
);
// F[setup10]: 10:10
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup10 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_setup10_we),
.wd (rxenable_setup10_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.setup10.q ),
// to register interface (read)
.qs (rxenable_setup10_qs)
);
// F[setup11]: 11:11
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup11 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_setup11_we),
.wd (rxenable_setup11_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.setup11.q ),
// to register interface (read)
.qs (rxenable_setup11_qs)
);
// F[out0]: 16:16
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_out0_we),
.wd (rxenable_out0_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.out0.q ),
// to register interface (read)
.qs (rxenable_out0_qs)
);
// F[out1]: 17:17
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_out1_we),
.wd (rxenable_out1_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.out1.q ),
// to register interface (read)
.qs (rxenable_out1_qs)
);
// F[out2]: 18:18
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_out2_we),
.wd (rxenable_out2_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.out2.q ),
// to register interface (read)
.qs (rxenable_out2_qs)
);
// F[out3]: 19:19
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_out3_we),
.wd (rxenable_out3_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.out3.q ),
// to register interface (read)
.qs (rxenable_out3_qs)
);
// F[out4]: 20:20
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_out4_we),
.wd (rxenable_out4_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.out4.q ),
// to register interface (read)
.qs (rxenable_out4_qs)
);
// F[out5]: 21:21
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_out5_we),
.wd (rxenable_out5_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.out5.q ),
// to register interface (read)
.qs (rxenable_out5_qs)
);
// F[out6]: 22:22
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_out6_we),
.wd (rxenable_out6_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.out6.q ),
// to register interface (read)
.qs (rxenable_out6_qs)
);
// F[out7]: 23:23
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_out7_we),
.wd (rxenable_out7_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.out7.q ),
// to register interface (read)
.qs (rxenable_out7_qs)
);
// F[out8]: 24:24
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out8 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_out8_we),
.wd (rxenable_out8_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.out8.q ),
// to register interface (read)
.qs (rxenable_out8_qs)
);
// F[out9]: 25:25
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out9 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_out9_we),
.wd (rxenable_out9_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.out9.q ),
// to register interface (read)
.qs (rxenable_out9_qs)
);
// F[out10]: 26:26
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out10 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_out10_we),
.wd (rxenable_out10_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.out10.q ),
// to register interface (read)
.qs (rxenable_out10_qs)
);
// F[out11]: 27:27
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out11 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (rxenable_out11_we),
.wd (rxenable_out11_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.rxenable.out11.q ),
// to register interface (read)
.qs (rxenable_out11_qs)
);
// R[in_sent]: V(False)
// F[sent0]: 0:0
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (in_sent_sent0_we),
.wd (in_sent_sent0_wd),
// from internal hardware
.de (hw2reg.in_sent.sent0.de),
.d (hw2reg.in_sent.sent0.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (in_sent_sent0_qs)
);
// F[sent1]: 1:1
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (in_sent_sent1_we),
.wd (in_sent_sent1_wd),
// from internal hardware
.de (hw2reg.in_sent.sent1.de),
.d (hw2reg.in_sent.sent1.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (in_sent_sent1_qs)
);
// F[sent2]: 2:2
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (in_sent_sent2_we),
.wd (in_sent_sent2_wd),
// from internal hardware
.de (hw2reg.in_sent.sent2.de),
.d (hw2reg.in_sent.sent2.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (in_sent_sent2_qs)
);
// F[sent3]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (in_sent_sent3_we),
.wd (in_sent_sent3_wd),
// from internal hardware
.de (hw2reg.in_sent.sent3.de),
.d (hw2reg.in_sent.sent3.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (in_sent_sent3_qs)
);
// F[sent4]: 4:4
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (in_sent_sent4_we),
.wd (in_sent_sent4_wd),
// from internal hardware
.de (hw2reg.in_sent.sent4.de),
.d (hw2reg.in_sent.sent4.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (in_sent_sent4_qs)
);
// F[sent5]: 5:5
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (in_sent_sent5_we),
.wd (in_sent_sent5_wd),
// from internal hardware
.de (hw2reg.in_sent.sent5.de),
.d (hw2reg.in_sent.sent5.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (in_sent_sent5_qs)
);
// F[sent6]: 6:6
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (in_sent_sent6_we),
.wd (in_sent_sent6_wd),
// from internal hardware
.de (hw2reg.in_sent.sent6.de),
.d (hw2reg.in_sent.sent6.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (in_sent_sent6_qs)
);
// F[sent7]: 7:7
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (in_sent_sent7_we),
.wd (in_sent_sent7_wd),
// from internal hardware
.de (hw2reg.in_sent.sent7.de),
.d (hw2reg.in_sent.sent7.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (in_sent_sent7_qs)
);
// F[sent8]: 8:8
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent8 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (in_sent_sent8_we),
.wd (in_sent_sent8_wd),
// from internal hardware
.de (hw2reg.in_sent.sent8.de),
.d (hw2reg.in_sent.sent8.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (in_sent_sent8_qs)
);
// F[sent9]: 9:9
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent9 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (in_sent_sent9_we),
.wd (in_sent_sent9_wd),
// from internal hardware
.de (hw2reg.in_sent.sent9.de),
.d (hw2reg.in_sent.sent9.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (in_sent_sent9_qs)
);
// F[sent10]: 10:10
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent10 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (in_sent_sent10_we),
.wd (in_sent_sent10_wd),
// from internal hardware
.de (hw2reg.in_sent.sent10.de),
.d (hw2reg.in_sent.sent10.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (in_sent_sent10_qs)
);
// F[sent11]: 11:11
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent11 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (in_sent_sent11_we),
.wd (in_sent_sent11_wd),
// from internal hardware
.de (hw2reg.in_sent.sent11.de),
.d (hw2reg.in_sent.sent11.d ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (in_sent_sent11_qs)
);
// R[stall]: V(False)
// F[stall0]: 0:0
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (stall_stall0_we),
.wd (stall_stall0_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.stall.stall0.q ),
// to register interface (read)
.qs (stall_stall0_qs)
);
// F[stall1]: 1:1
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (stall_stall1_we),
.wd (stall_stall1_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.stall.stall1.q ),
// to register interface (read)
.qs (stall_stall1_qs)
);
// F[stall2]: 2:2
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (stall_stall2_we),
.wd (stall_stall2_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.stall.stall2.q ),
// to register interface (read)
.qs (stall_stall2_qs)
);
// F[stall3]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (stall_stall3_we),
.wd (stall_stall3_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.stall.stall3.q ),
// to register interface (read)
.qs (stall_stall3_qs)
);
// F[stall4]: 4:4
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (stall_stall4_we),
.wd (stall_stall4_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.stall.stall4.q ),
// to register interface (read)
.qs (stall_stall4_qs)
);
// F[stall5]: 5:5
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (stall_stall5_we),
.wd (stall_stall5_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.stall.stall5.q ),
// to register interface (read)
.qs (stall_stall5_qs)
);
// F[stall6]: 6:6
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (stall_stall6_we),
.wd (stall_stall6_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.stall.stall6.q ),
// to register interface (read)
.qs (stall_stall6_qs)
);
// F[stall7]: 7:7
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (stall_stall7_we),
.wd (stall_stall7_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.stall.stall7.q ),
// to register interface (read)
.qs (stall_stall7_qs)
);
// F[stall8]: 8:8
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall8 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (stall_stall8_we),
.wd (stall_stall8_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.stall.stall8.q ),
// to register interface (read)
.qs (stall_stall8_qs)
);
// F[stall9]: 9:9
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall9 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (stall_stall9_we),
.wd (stall_stall9_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.stall.stall9.q ),
// to register interface (read)
.qs (stall_stall9_qs)
);
// F[stall10]: 10:10
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall10 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (stall_stall10_we),
.wd (stall_stall10_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.stall.stall10.q ),
// to register interface (read)
.qs (stall_stall10_qs)
);
// F[stall11]: 11:11
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall11 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (stall_stall11_we),
.wd (stall_stall11_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.stall.stall11.q ),
// to register interface (read)
.qs (stall_stall11_qs)
);
// R[configin0]: V(False)
// F[buffer0]: 4:0
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin0_buffer0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin0_buffer0_we),
.wd (configin0_buffer0_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin0.buffer0.q ),
// to register interface (read)
.qs (configin0_buffer0_qs)
);
// F[size0]: 14:8
prim_subreg #(
.DW (7),
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin0_size0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin0_size0_we),
.wd (configin0_size0_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin0.size0.q ),
// to register interface (read)
.qs (configin0_size0_qs)
);
// F[pend0]: 30:30
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin0_pend0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin0_pend0_we),
.wd (configin0_pend0_wd),
// from internal hardware
.de (hw2reg.configin0.pend0.de),
.d (hw2reg.configin0.pend0.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin0.pend0.q ),
// to register interface (read)
.qs (configin0_pend0_qs)
);
// F[rdy0]: 31:31
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin0_rdy0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin0_rdy0_we),
.wd (configin0_rdy0_wd),
// from internal hardware
.de (hw2reg.configin0.rdy0.de),
.d (hw2reg.configin0.rdy0.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin0.rdy0.q ),
// to register interface (read)
.qs (configin0_rdy0_qs)
);
// R[configin1]: V(False)
// F[buffer1]: 4:0
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin1_buffer1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin1_buffer1_we),
.wd (configin1_buffer1_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin1.buffer1.q ),
// to register interface (read)
.qs (configin1_buffer1_qs)
);
// F[size1]: 14:8
prim_subreg #(
.DW (7),
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin1_size1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin1_size1_we),
.wd (configin1_size1_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin1.size1.q ),
// to register interface (read)
.qs (configin1_size1_qs)
);
// F[pend1]: 30:30
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin1_pend1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin1_pend1_we),
.wd (configin1_pend1_wd),
// from internal hardware
.de (hw2reg.configin1.pend1.de),
.d (hw2reg.configin1.pend1.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin1.pend1.q ),
// to register interface (read)
.qs (configin1_pend1_qs)
);
// F[rdy1]: 31:31
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin1_rdy1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin1_rdy1_we),
.wd (configin1_rdy1_wd),
// from internal hardware
.de (hw2reg.configin1.rdy1.de),
.d (hw2reg.configin1.rdy1.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin1.rdy1.q ),
// to register interface (read)
.qs (configin1_rdy1_qs)
);
// R[configin2]: V(False)
// F[buffer2]: 4:0
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin2_buffer2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin2_buffer2_we),
.wd (configin2_buffer2_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin2.buffer2.q ),
// to register interface (read)
.qs (configin2_buffer2_qs)
);
// F[size2]: 14:8
prim_subreg #(
.DW (7),
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin2_size2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin2_size2_we),
.wd (configin2_size2_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin2.size2.q ),
// to register interface (read)
.qs (configin2_size2_qs)
);
// F[pend2]: 30:30
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin2_pend2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin2_pend2_we),
.wd (configin2_pend2_wd),
// from internal hardware
.de (hw2reg.configin2.pend2.de),
.d (hw2reg.configin2.pend2.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin2.pend2.q ),
// to register interface (read)
.qs (configin2_pend2_qs)
);
// F[rdy2]: 31:31
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin2_rdy2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin2_rdy2_we),
.wd (configin2_rdy2_wd),
// from internal hardware
.de (hw2reg.configin2.rdy2.de),
.d (hw2reg.configin2.rdy2.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin2.rdy2.q ),
// to register interface (read)
.qs (configin2_rdy2_qs)
);
// R[configin3]: V(False)
// F[buffer3]: 4:0
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin3_buffer3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin3_buffer3_we),
.wd (configin3_buffer3_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin3.buffer3.q ),
// to register interface (read)
.qs (configin3_buffer3_qs)
);
// F[size3]: 14:8
prim_subreg #(
.DW (7),
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin3_size3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin3_size3_we),
.wd (configin3_size3_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin3.size3.q ),
// to register interface (read)
.qs (configin3_size3_qs)
);
// F[pend3]: 30:30
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin3_pend3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin3_pend3_we),
.wd (configin3_pend3_wd),
// from internal hardware
.de (hw2reg.configin3.pend3.de),
.d (hw2reg.configin3.pend3.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin3.pend3.q ),
// to register interface (read)
.qs (configin3_pend3_qs)
);
// F[rdy3]: 31:31
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin3_rdy3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin3_rdy3_we),
.wd (configin3_rdy3_wd),
// from internal hardware
.de (hw2reg.configin3.rdy3.de),
.d (hw2reg.configin3.rdy3.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin3.rdy3.q ),
// to register interface (read)
.qs (configin3_rdy3_qs)
);
// R[configin4]: V(False)
// F[buffer4]: 4:0
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin4_buffer4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin4_buffer4_we),
.wd (configin4_buffer4_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin4.buffer4.q ),
// to register interface (read)
.qs (configin4_buffer4_qs)
);
// F[size4]: 14:8
prim_subreg #(
.DW (7),
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin4_size4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin4_size4_we),
.wd (configin4_size4_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin4.size4.q ),
// to register interface (read)
.qs (configin4_size4_qs)
);
// F[pend4]: 30:30
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin4_pend4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin4_pend4_we),
.wd (configin4_pend4_wd),
// from internal hardware
.de (hw2reg.configin4.pend4.de),
.d (hw2reg.configin4.pend4.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin4.pend4.q ),
// to register interface (read)
.qs (configin4_pend4_qs)
);
// F[rdy4]: 31:31
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin4_rdy4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin4_rdy4_we),
.wd (configin4_rdy4_wd),
// from internal hardware
.de (hw2reg.configin4.rdy4.de),
.d (hw2reg.configin4.rdy4.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin4.rdy4.q ),
// to register interface (read)
.qs (configin4_rdy4_qs)
);
// R[configin5]: V(False)
// F[buffer5]: 4:0
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin5_buffer5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin5_buffer5_we),
.wd (configin5_buffer5_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin5.buffer5.q ),
// to register interface (read)
.qs (configin5_buffer5_qs)
);
// F[size5]: 14:8
prim_subreg #(
.DW (7),
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin5_size5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin5_size5_we),
.wd (configin5_size5_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin5.size5.q ),
// to register interface (read)
.qs (configin5_size5_qs)
);
// F[pend5]: 30:30
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin5_pend5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin5_pend5_we),
.wd (configin5_pend5_wd),
// from internal hardware
.de (hw2reg.configin5.pend5.de),
.d (hw2reg.configin5.pend5.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin5.pend5.q ),
// to register interface (read)
.qs (configin5_pend5_qs)
);
// F[rdy5]: 31:31
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin5_rdy5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin5_rdy5_we),
.wd (configin5_rdy5_wd),
// from internal hardware
.de (hw2reg.configin5.rdy5.de),
.d (hw2reg.configin5.rdy5.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin5.rdy5.q ),
// to register interface (read)
.qs (configin5_rdy5_qs)
);
// R[configin6]: V(False)
// F[buffer6]: 4:0
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin6_buffer6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin6_buffer6_we),
.wd (configin6_buffer6_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin6.buffer6.q ),
// to register interface (read)
.qs (configin6_buffer6_qs)
);
// F[size6]: 14:8
prim_subreg #(
.DW (7),
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin6_size6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin6_size6_we),
.wd (configin6_size6_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin6.size6.q ),
// to register interface (read)
.qs (configin6_size6_qs)
);
// F[pend6]: 30:30
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin6_pend6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin6_pend6_we),
.wd (configin6_pend6_wd),
// from internal hardware
.de (hw2reg.configin6.pend6.de),
.d (hw2reg.configin6.pend6.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin6.pend6.q ),
// to register interface (read)
.qs (configin6_pend6_qs)
);
// F[rdy6]: 31:31
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin6_rdy6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin6_rdy6_we),
.wd (configin6_rdy6_wd),
// from internal hardware
.de (hw2reg.configin6.rdy6.de),
.d (hw2reg.configin6.rdy6.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin6.rdy6.q ),
// to register interface (read)
.qs (configin6_rdy6_qs)
);
// R[configin7]: V(False)
// F[buffer7]: 4:0
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin7_buffer7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin7_buffer7_we),
.wd (configin7_buffer7_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin7.buffer7.q ),
// to register interface (read)
.qs (configin7_buffer7_qs)
);
// F[size7]: 14:8
prim_subreg #(
.DW (7),
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin7_size7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin7_size7_we),
.wd (configin7_size7_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin7.size7.q ),
// to register interface (read)
.qs (configin7_size7_qs)
);
// F[pend7]: 30:30
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin7_pend7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin7_pend7_we),
.wd (configin7_pend7_wd),
// from internal hardware
.de (hw2reg.configin7.pend7.de),
.d (hw2reg.configin7.pend7.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin7.pend7.q ),
// to register interface (read)
.qs (configin7_pend7_qs)
);
// F[rdy7]: 31:31
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin7_rdy7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin7_rdy7_we),
.wd (configin7_rdy7_wd),
// from internal hardware
.de (hw2reg.configin7.rdy7.de),
.d (hw2reg.configin7.rdy7.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin7.rdy7.q ),
// to register interface (read)
.qs (configin7_rdy7_qs)
);
// R[configin8]: V(False)
// F[buffer8]: 4:0
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin8_buffer8 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin8_buffer8_we),
.wd (configin8_buffer8_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin8.buffer8.q ),
// to register interface (read)
.qs (configin8_buffer8_qs)
);
// F[size8]: 14:8
prim_subreg #(
.DW (7),
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin8_size8 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin8_size8_we),
.wd (configin8_size8_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin8.size8.q ),
// to register interface (read)
.qs (configin8_size8_qs)
);
// F[pend8]: 30:30
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin8_pend8 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin8_pend8_we),
.wd (configin8_pend8_wd),
// from internal hardware
.de (hw2reg.configin8.pend8.de),
.d (hw2reg.configin8.pend8.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin8.pend8.q ),
// to register interface (read)
.qs (configin8_pend8_qs)
);
// F[rdy8]: 31:31
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin8_rdy8 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin8_rdy8_we),
.wd (configin8_rdy8_wd),
// from internal hardware
.de (hw2reg.configin8.rdy8.de),
.d (hw2reg.configin8.rdy8.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin8.rdy8.q ),
// to register interface (read)
.qs (configin8_rdy8_qs)
);
// R[configin9]: V(False)
// F[buffer9]: 4:0
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin9_buffer9 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin9_buffer9_we),
.wd (configin9_buffer9_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin9.buffer9.q ),
// to register interface (read)
.qs (configin9_buffer9_qs)
);
// F[size9]: 14:8
prim_subreg #(
.DW (7),
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin9_size9 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin9_size9_we),
.wd (configin9_size9_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin9.size9.q ),
// to register interface (read)
.qs (configin9_size9_qs)
);
// F[pend9]: 30:30
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin9_pend9 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin9_pend9_we),
.wd (configin9_pend9_wd),
// from internal hardware
.de (hw2reg.configin9.pend9.de),
.d (hw2reg.configin9.pend9.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin9.pend9.q ),
// to register interface (read)
.qs (configin9_pend9_qs)
);
// F[rdy9]: 31:31
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin9_rdy9 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin9_rdy9_we),
.wd (configin9_rdy9_wd),
// from internal hardware
.de (hw2reg.configin9.rdy9.de),
.d (hw2reg.configin9.rdy9.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin9.rdy9.q ),
// to register interface (read)
.qs (configin9_rdy9_qs)
);
// R[configin10]: V(False)
// F[buffer10]: 4:0
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin10_buffer10 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin10_buffer10_we),
.wd (configin10_buffer10_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin10.buffer10.q ),
// to register interface (read)
.qs (configin10_buffer10_qs)
);
// F[size10]: 14:8
prim_subreg #(
.DW (7),
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin10_size10 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin10_size10_we),
.wd (configin10_size10_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin10.size10.q ),
// to register interface (read)
.qs (configin10_size10_qs)
);
// F[pend10]: 30:30
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin10_pend10 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin10_pend10_we),
.wd (configin10_pend10_wd),
// from internal hardware
.de (hw2reg.configin10.pend10.de),
.d (hw2reg.configin10.pend10.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin10.pend10.q ),
// to register interface (read)
.qs (configin10_pend10_qs)
);
// F[rdy10]: 31:31
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin10_rdy10 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin10_rdy10_we),
.wd (configin10_rdy10_wd),
// from internal hardware
.de (hw2reg.configin10.rdy10.de),
.d (hw2reg.configin10.rdy10.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin10.rdy10.q ),
// to register interface (read)
.qs (configin10_rdy10_qs)
);
// R[configin11]: V(False)
// F[buffer11]: 4:0
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin11_buffer11 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin11_buffer11_we),
.wd (configin11_buffer11_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin11.buffer11.q ),
// to register interface (read)
.qs (configin11_buffer11_qs)
);
// F[size11]: 14:8
prim_subreg #(
.DW (7),
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin11_size11 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin11_size11_we),
.wd (configin11_size11_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.configin11.size11.q ),
// to register interface (read)
.qs (configin11_size11_qs)
);
// F[pend11]: 30:30
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin11_pend11 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin11_pend11_we),
.wd (configin11_pend11_wd),
// from internal hardware
.de (hw2reg.configin11.pend11.de),
.d (hw2reg.configin11.pend11.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin11.pend11.q ),
// to register interface (read)
.qs (configin11_pend11_qs)
);
// F[rdy11]: 31:31
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin11_rdy11 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (configin11_rdy11_we),
.wd (configin11_rdy11_wd),
// from internal hardware
.de (hw2reg.configin11.rdy11.de),
.d (hw2reg.configin11.rdy11.d ),
// to internal hardware
.qe (),
.q (reg2hw.configin11.rdy11.q ),
// to register interface (read)
.qs (configin11_rdy11_qs)
);
logic [21:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[0] = (reg_addr == USBDEV_INTR_STATE_OFFSET);
addr_hit[1] = (reg_addr == USBDEV_INTR_ENABLE_OFFSET);
addr_hit[2] = (reg_addr == USBDEV_INTR_TEST_OFFSET);
addr_hit[3] = (reg_addr == USBDEV_USBCTRL_OFFSET);
addr_hit[4] = (reg_addr == USBDEV_USBSTAT_OFFSET);
addr_hit[5] = (reg_addr == USBDEV_AVBUFFER_OFFSET);
addr_hit[6] = (reg_addr == USBDEV_RXFIFO_OFFSET);
addr_hit[7] = (reg_addr == USBDEV_RXENABLE_OFFSET);
addr_hit[8] = (reg_addr == USBDEV_IN_SENT_OFFSET);
addr_hit[9] = (reg_addr == USBDEV_STALL_OFFSET);
addr_hit[10] = (reg_addr == USBDEV_CONFIGIN0_OFFSET);
addr_hit[11] = (reg_addr == USBDEV_CONFIGIN1_OFFSET);
addr_hit[12] = (reg_addr == USBDEV_CONFIGIN2_OFFSET);
addr_hit[13] = (reg_addr == USBDEV_CONFIGIN3_OFFSET);
addr_hit[14] = (reg_addr == USBDEV_CONFIGIN4_OFFSET);
addr_hit[15] = (reg_addr == USBDEV_CONFIGIN5_OFFSET);
addr_hit[16] = (reg_addr == USBDEV_CONFIGIN6_OFFSET);
addr_hit[17] = (reg_addr == USBDEV_CONFIGIN7_OFFSET);
addr_hit[18] = (reg_addr == USBDEV_CONFIGIN8_OFFSET);
addr_hit[19] = (reg_addr == USBDEV_CONFIGIN9_OFFSET);
addr_hit[20] = (reg_addr == USBDEV_CONFIGIN10_OFFSET);
addr_hit[21] = (reg_addr == USBDEV_CONFIGIN11_OFFSET);
end
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
tl_addrmiss <= 1'b0;
end else if (reg_re || reg_we) begin
tl_addrmiss <= ~|addr_hit;
end
end
// Write Enable signal
assign intr_state_pkt_received_we = addr_hit[0] && reg_we;
assign intr_state_pkt_received_wd = reg_wdata[0];
assign intr_state_pkt_sent_we = addr_hit[0] && reg_we;
assign intr_state_pkt_sent_wd = reg_wdata[1];
assign intr_state_disconnected_we = addr_hit[0] && reg_we;
assign intr_state_disconnected_wd = reg_wdata[2];
assign intr_state_host_lost_we = addr_hit[0] && reg_we;
assign intr_state_host_lost_wd = reg_wdata[3];
assign intr_state_link_reset_we = addr_hit[0] && reg_we;
assign intr_state_link_reset_wd = reg_wdata[4];
assign intr_state_link_suspend_we = addr_hit[0] && reg_we;
assign intr_state_link_suspend_wd = reg_wdata[5];
assign intr_state_link_resume_we = addr_hit[0] && reg_we;
assign intr_state_link_resume_wd = reg_wdata[6];
assign intr_state_av_empty_we = addr_hit[0] && reg_we;
assign intr_state_av_empty_wd = reg_wdata[7];
assign intr_state_rx_full_we = addr_hit[0] && reg_we;
assign intr_state_rx_full_wd = reg_wdata[8];
assign intr_state_av_overflow_we = addr_hit[0] && reg_we;
assign intr_state_av_overflow_wd = reg_wdata[9];
assign intr_enable_pkt_received_we = addr_hit[1] && reg_we;
assign intr_enable_pkt_received_wd = reg_wdata[0];
assign intr_enable_pkt_sent_we = addr_hit[1] && reg_we;
assign intr_enable_pkt_sent_wd = reg_wdata[1];
assign intr_enable_disconnected_we = addr_hit[1] && reg_we;
assign intr_enable_disconnected_wd = reg_wdata[2];
assign intr_enable_host_lost_we = addr_hit[1] && reg_we;
assign intr_enable_host_lost_wd = reg_wdata[3];
assign intr_enable_link_reset_we = addr_hit[1] && reg_we;
assign intr_enable_link_reset_wd = reg_wdata[4];
assign intr_enable_link_suspend_we = addr_hit[1] && reg_we;
assign intr_enable_link_suspend_wd = reg_wdata[5];
assign intr_enable_link_resume_we = addr_hit[1] && reg_we;
assign intr_enable_link_resume_wd = reg_wdata[6];
assign intr_enable_av_empty_we = addr_hit[1] && reg_we;
assign intr_enable_av_empty_wd = reg_wdata[7];
assign intr_enable_rx_full_we = addr_hit[1] && reg_we;
assign intr_enable_rx_full_wd = reg_wdata[8];
assign intr_enable_av_overflow_we = addr_hit[1] && reg_we;
assign intr_enable_av_overflow_wd = reg_wdata[9];
assign intr_test_pkt_received_we = addr_hit[2] && reg_we;
assign intr_test_pkt_received_wd = reg_wdata[0];
assign intr_test_pkt_sent_we = addr_hit[2] && reg_we;
assign intr_test_pkt_sent_wd = reg_wdata[1];
assign intr_test_disconnected_we = addr_hit[2] && reg_we;
assign intr_test_disconnected_wd = reg_wdata[2];
assign intr_test_host_lost_we = addr_hit[2] && reg_we;
assign intr_test_host_lost_wd = reg_wdata[3];
assign intr_test_link_reset_we = addr_hit[2] && reg_we;
assign intr_test_link_reset_wd = reg_wdata[4];
assign intr_test_link_suspend_we = addr_hit[2] && reg_we;
assign intr_test_link_suspend_wd = reg_wdata[5];
assign intr_test_link_resume_we = addr_hit[2] && reg_we;
assign intr_test_link_resume_wd = reg_wdata[6];
assign intr_test_av_empty_we = addr_hit[2] && reg_we;
assign intr_test_av_empty_wd = reg_wdata[7];
assign intr_test_rx_full_we = addr_hit[2] && reg_we;
assign intr_test_rx_full_wd = reg_wdata[8];
assign intr_test_av_overflow_we = addr_hit[2] && reg_we;
assign intr_test_av_overflow_wd = reg_wdata[9];
assign usbctrl_enable_we = addr_hit[3] && reg_we;
assign usbctrl_enable_wd = reg_wdata[0];
assign usbctrl_device_address_we = addr_hit[3] && reg_we;
assign usbctrl_device_address_wd = reg_wdata[22:16];
assign usbstat_frame_re = addr_hit[4] && reg_re;
assign usbstat_host_lost_re = addr_hit[4] && reg_re;
assign usbstat_link_state_re = addr_hit[4] && reg_re;
assign usbstat_usb_sense_re = addr_hit[4] && reg_re;
assign usbstat_av_depth_re = addr_hit[4] && reg_re;
assign usbstat_av_full_re = addr_hit[4] && reg_re;
assign usbstat_rx_depth_re = addr_hit[4] && reg_re;
assign usbstat_rx_empty_re = addr_hit[4] && reg_re;
assign avbuffer_we = addr_hit[5] && reg_we;
assign avbuffer_wd = reg_wdata[4:0];
assign rxfifo_buffer_re = addr_hit[6] && reg_re;
assign rxfifo_size_re = addr_hit[6] && reg_re;
assign rxfifo_setup_re = addr_hit[6] && reg_re;
assign rxfifo_ep_re = addr_hit[6] && reg_re;
assign rxenable_setup0_we = addr_hit[7] && reg_we;
assign rxenable_setup0_wd = reg_wdata[0];
assign rxenable_setup1_we = addr_hit[7] && reg_we;
assign rxenable_setup1_wd = reg_wdata[1];
assign rxenable_setup2_we = addr_hit[7] && reg_we;
assign rxenable_setup2_wd = reg_wdata[2];
assign rxenable_setup3_we = addr_hit[7] && reg_we;
assign rxenable_setup3_wd = reg_wdata[3];
assign rxenable_setup4_we = addr_hit[7] && reg_we;
assign rxenable_setup4_wd = reg_wdata[4];
assign rxenable_setup5_we = addr_hit[7] && reg_we;
assign rxenable_setup5_wd = reg_wdata[5];
assign rxenable_setup6_we = addr_hit[7] && reg_we;
assign rxenable_setup6_wd = reg_wdata[6];
assign rxenable_setup7_we = addr_hit[7] && reg_we;
assign rxenable_setup7_wd = reg_wdata[7];
assign rxenable_setup8_we = addr_hit[7] && reg_we;
assign rxenable_setup8_wd = reg_wdata[8];
assign rxenable_setup9_we = addr_hit[7] && reg_we;
assign rxenable_setup9_wd = reg_wdata[9];
assign rxenable_setup10_we = addr_hit[7] && reg_we;
assign rxenable_setup10_wd = reg_wdata[10];
assign rxenable_setup11_we = addr_hit[7] && reg_we;
assign rxenable_setup11_wd = reg_wdata[11];
assign rxenable_out0_we = addr_hit[7] && reg_we;
assign rxenable_out0_wd = reg_wdata[16];
assign rxenable_out1_we = addr_hit[7] && reg_we;
assign rxenable_out1_wd = reg_wdata[17];
assign rxenable_out2_we = addr_hit[7] && reg_we;
assign rxenable_out2_wd = reg_wdata[18];
assign rxenable_out3_we = addr_hit[7] && reg_we;
assign rxenable_out3_wd = reg_wdata[19];
assign rxenable_out4_we = addr_hit[7] && reg_we;
assign rxenable_out4_wd = reg_wdata[20];
assign rxenable_out5_we = addr_hit[7] && reg_we;
assign rxenable_out5_wd = reg_wdata[21];
assign rxenable_out6_we = addr_hit[7] && reg_we;
assign rxenable_out6_wd = reg_wdata[22];
assign rxenable_out7_we = addr_hit[7] && reg_we;
assign rxenable_out7_wd = reg_wdata[23];
assign rxenable_out8_we = addr_hit[7] && reg_we;
assign rxenable_out8_wd = reg_wdata[24];
assign rxenable_out9_we = addr_hit[7] && reg_we;
assign rxenable_out9_wd = reg_wdata[25];
assign rxenable_out10_we = addr_hit[7] && reg_we;
assign rxenable_out10_wd = reg_wdata[26];
assign rxenable_out11_we = addr_hit[7] && reg_we;
assign rxenable_out11_wd = reg_wdata[27];
assign in_sent_sent0_we = addr_hit[8] && reg_we;
assign in_sent_sent0_wd = reg_wdata[0];
assign in_sent_sent1_we = addr_hit[8] && reg_we;
assign in_sent_sent1_wd = reg_wdata[1];
assign in_sent_sent2_we = addr_hit[8] && reg_we;
assign in_sent_sent2_wd = reg_wdata[2];
assign in_sent_sent3_we = addr_hit[8] && reg_we;
assign in_sent_sent3_wd = reg_wdata[3];
assign in_sent_sent4_we = addr_hit[8] && reg_we;
assign in_sent_sent4_wd = reg_wdata[4];
assign in_sent_sent5_we = addr_hit[8] && reg_we;
assign in_sent_sent5_wd = reg_wdata[5];
assign in_sent_sent6_we = addr_hit[8] && reg_we;
assign in_sent_sent6_wd = reg_wdata[6];
assign in_sent_sent7_we = addr_hit[8] && reg_we;
assign in_sent_sent7_wd = reg_wdata[7];
assign in_sent_sent8_we = addr_hit[8] && reg_we;
assign in_sent_sent8_wd = reg_wdata[8];
assign in_sent_sent9_we = addr_hit[8] && reg_we;
assign in_sent_sent9_wd = reg_wdata[9];
assign in_sent_sent10_we = addr_hit[8] && reg_we;
assign in_sent_sent10_wd = reg_wdata[10];
assign in_sent_sent11_we = addr_hit[8] && reg_we;
assign in_sent_sent11_wd = reg_wdata[11];
assign stall_stall0_we = addr_hit[9] && reg_we;
assign stall_stall0_wd = reg_wdata[0];
assign stall_stall1_we = addr_hit[9] && reg_we;
assign stall_stall1_wd = reg_wdata[1];
assign stall_stall2_we = addr_hit[9] && reg_we;
assign stall_stall2_wd = reg_wdata[2];
assign stall_stall3_we = addr_hit[9] && reg_we;
assign stall_stall3_wd = reg_wdata[3];
assign stall_stall4_we = addr_hit[9] && reg_we;
assign stall_stall4_wd = reg_wdata[4];
assign stall_stall5_we = addr_hit[9] && reg_we;
assign stall_stall5_wd = reg_wdata[5];
assign stall_stall6_we = addr_hit[9] && reg_we;
assign stall_stall6_wd = reg_wdata[6];
assign stall_stall7_we = addr_hit[9] && reg_we;
assign stall_stall7_wd = reg_wdata[7];
assign stall_stall8_we = addr_hit[9] && reg_we;
assign stall_stall8_wd = reg_wdata[8];
assign stall_stall9_we = addr_hit[9] && reg_we;
assign stall_stall9_wd = reg_wdata[9];
assign stall_stall10_we = addr_hit[9] && reg_we;
assign stall_stall10_wd = reg_wdata[10];
assign stall_stall11_we = addr_hit[9] && reg_we;
assign stall_stall11_wd = reg_wdata[11];
assign configin0_buffer0_we = addr_hit[10] && reg_we;
assign configin0_buffer0_wd = reg_wdata[4:0];
assign configin0_size0_we = addr_hit[10] && reg_we;
assign configin0_size0_wd = reg_wdata[14:8];
assign configin0_pend0_we = addr_hit[10] && reg_we;
assign configin0_pend0_wd = reg_wdata[30];
assign configin0_rdy0_we = addr_hit[10] && reg_we;
assign configin0_rdy0_wd = reg_wdata[31];
assign configin1_buffer1_we = addr_hit[11] && reg_we;
assign configin1_buffer1_wd = reg_wdata[4:0];
assign configin1_size1_we = addr_hit[11] && reg_we;
assign configin1_size1_wd = reg_wdata[14:8];
assign configin1_pend1_we = addr_hit[11] && reg_we;
assign configin1_pend1_wd = reg_wdata[30];
assign configin1_rdy1_we = addr_hit[11] && reg_we;
assign configin1_rdy1_wd = reg_wdata[31];
assign configin2_buffer2_we = addr_hit[12] && reg_we;
assign configin2_buffer2_wd = reg_wdata[4:0];
assign configin2_size2_we = addr_hit[12] && reg_we;
assign configin2_size2_wd = reg_wdata[14:8];
assign configin2_pend2_we = addr_hit[12] && reg_we;
assign configin2_pend2_wd = reg_wdata[30];
assign configin2_rdy2_we = addr_hit[12] && reg_we;
assign configin2_rdy2_wd = reg_wdata[31];
assign configin3_buffer3_we = addr_hit[13] && reg_we;
assign configin3_buffer3_wd = reg_wdata[4:0];
assign configin3_size3_we = addr_hit[13] && reg_we;
assign configin3_size3_wd = reg_wdata[14:8];
assign configin3_pend3_we = addr_hit[13] && reg_we;
assign configin3_pend3_wd = reg_wdata[30];
assign configin3_rdy3_we = addr_hit[13] && reg_we;
assign configin3_rdy3_wd = reg_wdata[31];
assign configin4_buffer4_we = addr_hit[14] && reg_we;
assign configin4_buffer4_wd = reg_wdata[4:0];
assign configin4_size4_we = addr_hit[14] && reg_we;
assign configin4_size4_wd = reg_wdata[14:8];
assign configin4_pend4_we = addr_hit[14] && reg_we;
assign configin4_pend4_wd = reg_wdata[30];
assign configin4_rdy4_we = addr_hit[14] && reg_we;
assign configin4_rdy4_wd = reg_wdata[31];
assign configin5_buffer5_we = addr_hit[15] && reg_we;
assign configin5_buffer5_wd = reg_wdata[4:0];
assign configin5_size5_we = addr_hit[15] && reg_we;
assign configin5_size5_wd = reg_wdata[14:8];
assign configin5_pend5_we = addr_hit[15] && reg_we;
assign configin5_pend5_wd = reg_wdata[30];
assign configin5_rdy5_we = addr_hit[15] && reg_we;
assign configin5_rdy5_wd = reg_wdata[31];
assign configin6_buffer6_we = addr_hit[16] && reg_we;
assign configin6_buffer6_wd = reg_wdata[4:0];
assign configin6_size6_we = addr_hit[16] && reg_we;
assign configin6_size6_wd = reg_wdata[14:8];
assign configin6_pend6_we = addr_hit[16] && reg_we;
assign configin6_pend6_wd = reg_wdata[30];
assign configin6_rdy6_we = addr_hit[16] && reg_we;
assign configin6_rdy6_wd = reg_wdata[31];
assign configin7_buffer7_we = addr_hit[17] && reg_we;
assign configin7_buffer7_wd = reg_wdata[4:0];
assign configin7_size7_we = addr_hit[17] && reg_we;
assign configin7_size7_wd = reg_wdata[14:8];
assign configin7_pend7_we = addr_hit[17] && reg_we;
assign configin7_pend7_wd = reg_wdata[30];
assign configin7_rdy7_we = addr_hit[17] && reg_we;
assign configin7_rdy7_wd = reg_wdata[31];
assign configin8_buffer8_we = addr_hit[18] && reg_we;
assign configin8_buffer8_wd = reg_wdata[4:0];
assign configin8_size8_we = addr_hit[18] && reg_we;
assign configin8_size8_wd = reg_wdata[14:8];
assign configin8_pend8_we = addr_hit[18] && reg_we;
assign configin8_pend8_wd = reg_wdata[30];
assign configin8_rdy8_we = addr_hit[18] && reg_we;
assign configin8_rdy8_wd = reg_wdata[31];
assign configin9_buffer9_we = addr_hit[19] && reg_we;
assign configin9_buffer9_wd = reg_wdata[4:0];
assign configin9_size9_we = addr_hit[19] && reg_we;
assign configin9_size9_wd = reg_wdata[14:8];
assign configin9_pend9_we = addr_hit[19] && reg_we;
assign configin9_pend9_wd = reg_wdata[30];
assign configin9_rdy9_we = addr_hit[19] && reg_we;
assign configin9_rdy9_wd = reg_wdata[31];
assign configin10_buffer10_we = addr_hit[20] && reg_we;
assign configin10_buffer10_wd = reg_wdata[4:0];
assign configin10_size10_we = addr_hit[20] && reg_we;
assign configin10_size10_wd = reg_wdata[14:8];
assign configin10_pend10_we = addr_hit[20] && reg_we;
assign configin10_pend10_wd = reg_wdata[30];
assign configin10_rdy10_we = addr_hit[20] && reg_we;
assign configin10_rdy10_wd = reg_wdata[31];
assign configin11_buffer11_we = addr_hit[21] && reg_we;
assign configin11_buffer11_wd = reg_wdata[4:0];
assign configin11_size11_we = addr_hit[21] && reg_we;
assign configin11_size11_wd = reg_wdata[14:8];
assign configin11_pend11_we = addr_hit[21] && reg_we;
assign configin11_pend11_wd = reg_wdata[30];
assign configin11_rdy11_we = addr_hit[21] && reg_we;
assign configin11_rdy11_wd = reg_wdata[31];
// Read data return
logic [DW-1:0] reg_rdata_next;
always_comb begin
reg_rdata_next = '0;
unique case (1'b1)
addr_hit[0]: begin
reg_rdata_next[0] = intr_state_pkt_received_qs;
reg_rdata_next[1] = intr_state_pkt_sent_qs;
reg_rdata_next[2] = intr_state_disconnected_qs;
reg_rdata_next[3] = intr_state_host_lost_qs;
reg_rdata_next[4] = intr_state_link_reset_qs;
reg_rdata_next[5] = intr_state_link_suspend_qs;
reg_rdata_next[6] = intr_state_link_resume_qs;
reg_rdata_next[7] = intr_state_av_empty_qs;
reg_rdata_next[8] = intr_state_rx_full_qs;
reg_rdata_next[9] = intr_state_av_overflow_qs;
end
addr_hit[1]: begin
reg_rdata_next[0] = intr_enable_pkt_received_qs;
reg_rdata_next[1] = intr_enable_pkt_sent_qs;
reg_rdata_next[2] = intr_enable_disconnected_qs;
reg_rdata_next[3] = intr_enable_host_lost_qs;
reg_rdata_next[4] = intr_enable_link_reset_qs;
reg_rdata_next[5] = intr_enable_link_suspend_qs;
reg_rdata_next[6] = intr_enable_link_resume_qs;
reg_rdata_next[7] = intr_enable_av_empty_qs;
reg_rdata_next[8] = intr_enable_rx_full_qs;
reg_rdata_next[9] = intr_enable_av_overflow_qs;
end
addr_hit[2]: begin
reg_rdata_next[0] = '0;
reg_rdata_next[1] = '0;
reg_rdata_next[2] = '0;
reg_rdata_next[3] = '0;
reg_rdata_next[4] = '0;
reg_rdata_next[5] = '0;
reg_rdata_next[6] = '0;
reg_rdata_next[7] = '0;
reg_rdata_next[8] = '0;
reg_rdata_next[9] = '0;
end
addr_hit[3]: begin
reg_rdata_next[0] = usbctrl_enable_qs;
reg_rdata_next[22:16] = usbctrl_device_address_qs;
end
addr_hit[4]: begin
reg_rdata_next[10:0] = usbstat_frame_qs;
reg_rdata_next[11] = usbstat_host_lost_qs;
reg_rdata_next[13:12] = usbstat_link_state_qs;
reg_rdata_next[14] = usbstat_usb_sense_qs;
reg_rdata_next[18:16] = usbstat_av_depth_qs;
reg_rdata_next[23] = usbstat_av_full_qs;
reg_rdata_next[26:24] = usbstat_rx_depth_qs;
reg_rdata_next[31] = usbstat_rx_empty_qs;
end
addr_hit[5]: begin
reg_rdata_next[4:0] = '0;
end
addr_hit[6]: begin
reg_rdata_next[4:0] = rxfifo_buffer_qs;
reg_rdata_next[14:8] = rxfifo_size_qs;
reg_rdata_next[19] = rxfifo_setup_qs;
reg_rdata_next[23:20] = rxfifo_ep_qs;
end
addr_hit[7]: begin
reg_rdata_next[0] = rxenable_setup0_qs;
reg_rdata_next[1] = rxenable_setup1_qs;
reg_rdata_next[2] = rxenable_setup2_qs;
reg_rdata_next[3] = rxenable_setup3_qs;
reg_rdata_next[4] = rxenable_setup4_qs;
reg_rdata_next[5] = rxenable_setup5_qs;
reg_rdata_next[6] = rxenable_setup6_qs;
reg_rdata_next[7] = rxenable_setup7_qs;
reg_rdata_next[8] = rxenable_setup8_qs;
reg_rdata_next[9] = rxenable_setup9_qs;
reg_rdata_next[10] = rxenable_setup10_qs;
reg_rdata_next[11] = rxenable_setup11_qs;
reg_rdata_next[16] = rxenable_out0_qs;
reg_rdata_next[17] = rxenable_out1_qs;
reg_rdata_next[18] = rxenable_out2_qs;
reg_rdata_next[19] = rxenable_out3_qs;
reg_rdata_next[20] = rxenable_out4_qs;
reg_rdata_next[21] = rxenable_out5_qs;
reg_rdata_next[22] = rxenable_out6_qs;
reg_rdata_next[23] = rxenable_out7_qs;
reg_rdata_next[24] = rxenable_out8_qs;
reg_rdata_next[25] = rxenable_out9_qs;
reg_rdata_next[26] = rxenable_out10_qs;
reg_rdata_next[27] = rxenable_out11_qs;
end
addr_hit[8]: begin
reg_rdata_next[0] = in_sent_sent0_qs;
reg_rdata_next[1] = in_sent_sent1_qs;
reg_rdata_next[2] = in_sent_sent2_qs;
reg_rdata_next[3] = in_sent_sent3_qs;
reg_rdata_next[4] = in_sent_sent4_qs;
reg_rdata_next[5] = in_sent_sent5_qs;
reg_rdata_next[6] = in_sent_sent6_qs;
reg_rdata_next[7] = in_sent_sent7_qs;
reg_rdata_next[8] = in_sent_sent8_qs;
reg_rdata_next[9] = in_sent_sent9_qs;
reg_rdata_next[10] = in_sent_sent10_qs;
reg_rdata_next[11] = in_sent_sent11_qs;
end
addr_hit[9]: begin
reg_rdata_next[0] = stall_stall0_qs;
reg_rdata_next[1] = stall_stall1_qs;
reg_rdata_next[2] = stall_stall2_qs;
reg_rdata_next[3] = stall_stall3_qs;
reg_rdata_next[4] = stall_stall4_qs;
reg_rdata_next[5] = stall_stall5_qs;
reg_rdata_next[6] = stall_stall6_qs;
reg_rdata_next[7] = stall_stall7_qs;
reg_rdata_next[8] = stall_stall8_qs;
reg_rdata_next[9] = stall_stall9_qs;
reg_rdata_next[10] = stall_stall10_qs;
reg_rdata_next[11] = stall_stall11_qs;
end
addr_hit[10]: begin
reg_rdata_next[4:0] = configin0_buffer0_qs;
reg_rdata_next[14:8] = configin0_size0_qs;
reg_rdata_next[30] = configin0_pend0_qs;
reg_rdata_next[31] = configin0_rdy0_qs;
end
addr_hit[11]: begin
reg_rdata_next[4:0] = configin1_buffer1_qs;
reg_rdata_next[14:8] = configin1_size1_qs;
reg_rdata_next[30] = configin1_pend1_qs;
reg_rdata_next[31] = configin1_rdy1_qs;
end
addr_hit[12]: begin
reg_rdata_next[4:0] = configin2_buffer2_qs;
reg_rdata_next[14:8] = configin2_size2_qs;
reg_rdata_next[30] = configin2_pend2_qs;
reg_rdata_next[31] = configin2_rdy2_qs;
end
addr_hit[13]: begin
reg_rdata_next[4:0] = configin3_buffer3_qs;
reg_rdata_next[14:8] = configin3_size3_qs;
reg_rdata_next[30] = configin3_pend3_qs;
reg_rdata_next[31] = configin3_rdy3_qs;
end
addr_hit[14]: begin
reg_rdata_next[4:0] = configin4_buffer4_qs;
reg_rdata_next[14:8] = configin4_size4_qs;
reg_rdata_next[30] = configin4_pend4_qs;
reg_rdata_next[31] = configin4_rdy4_qs;
end
addr_hit[15]: begin
reg_rdata_next[4:0] = configin5_buffer5_qs;
reg_rdata_next[14:8] = configin5_size5_qs;
reg_rdata_next[30] = configin5_pend5_qs;
reg_rdata_next[31] = configin5_rdy5_qs;
end
addr_hit[16]: begin
reg_rdata_next[4:0] = configin6_buffer6_qs;
reg_rdata_next[14:8] = configin6_size6_qs;
reg_rdata_next[30] = configin6_pend6_qs;
reg_rdata_next[31] = configin6_rdy6_qs;
end
addr_hit[17]: begin
reg_rdata_next[4:0] = configin7_buffer7_qs;
reg_rdata_next[14:8] = configin7_size7_qs;
reg_rdata_next[30] = configin7_pend7_qs;
reg_rdata_next[31] = configin7_rdy7_qs;
end
addr_hit[18]: begin
reg_rdata_next[4:0] = configin8_buffer8_qs;
reg_rdata_next[14:8] = configin8_size8_qs;
reg_rdata_next[30] = configin8_pend8_qs;
reg_rdata_next[31] = configin8_rdy8_qs;
end
addr_hit[19]: begin
reg_rdata_next[4:0] = configin9_buffer9_qs;
reg_rdata_next[14:8] = configin9_size9_qs;
reg_rdata_next[30] = configin9_pend9_qs;
reg_rdata_next[31] = configin9_rdy9_qs;
end
addr_hit[20]: begin
reg_rdata_next[4:0] = configin10_buffer10_qs;
reg_rdata_next[14:8] = configin10_size10_qs;
reg_rdata_next[30] = configin10_pend10_qs;
reg_rdata_next[31] = configin10_rdy10_qs;
end
addr_hit[21]: begin
reg_rdata_next[4:0] = configin11_buffer11_qs;
reg_rdata_next[14:8] = configin11_size11_qs;
reg_rdata_next[30] = configin11_pend11_qs;
reg_rdata_next[31] = configin11_rdy11_qs;
end
default: begin
reg_rdata_next = '1;
end
endcase
end
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
reg_valid <= 1'b0;
reg_rdata <= '0;
rsp_opcode <= tlul_pkg::AccessAck;
end else if (reg_re || reg_we) begin
// Guarantee to return data in a cycle
reg_valid <= 1'b1;
if (reg_re) begin
reg_rdata <= reg_rdata_next;
rsp_opcode <= tlul_pkg::AccessAckData;
end else begin
rsp_opcode <= tlul_pkg::AccessAck;
end
end else if (tl_reg_h2d.d_ready) begin
reg_valid <= 1'b0;
end
end
// Outstanding: 1 outstanding at a time. Identical to `reg_valid`
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
outstanding <= 1'b0;
end else if (tl_reg_h2d.a_valid && tl_reg_d2h.a_ready) begin
outstanding <= 1'b1;
end else if (tl_reg_d2h.d_valid && tl_reg_h2d.d_ready) begin
outstanding <= 1'b0;
end
end
// Assertions for Register Interface
`ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
`ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
`ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> reg_valid, clk_i, !rst_ni)
`ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
`ASSERT(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0, clk_i, !rst_ni)
endmodule