| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| // TOP English Breakfast configuration |
| { name: "englishbreakfast", |
| type: "top", |
| |
| ///////////////////////////////////////////////////////////// |
| // Seed for compile-time random constants // |
| // NOTE: REPLACE THIS WITH A NEW VALUE BEFORE THE TAPEOUT // |
| ///////////////////////////////////////////////////////////// |
| rnd_cnst_seed: 4881560218908238235 |
| |
| // 32-bit datawidth |
| datawidth: "32", |
| |
| // Power information for the design |
| power: { |
| // Power domains supported by the design |
| // Aon represents domain aon |
| // 0 represents domain 0 |
| domains: ["Aon", "0"], |
| |
| // Default power domain used for the design |
| default: "0" |
| }, |
| |
| // This is the clock data structure of the design. |
| // The hier path refers to the clock reference path (struct / port) |
| // - The top/ext desgination follows the same scheme as inter-module |
| // The src key indicates the raw clock sources in the design |
| // The groups key indicates the various clock groupings in the design |
| clocks: { |
| |
| hier_paths: { |
| top: "clkmgr_aon_clocks.", // top level is a struct |
| ext: "", // ext is a port of the clock name |
| }, |
| |
| // Clock Source attributes |
| // name: Name of group. |
| // aon: Whether the clock is free running all the time. |
| // If it is, the clock is not hanlded by clkmgr. |
| // freq: Absolute frequency of clk in Hz |
| srcs: [ |
| { name: "main", aon: "no", freq: "100000000" } |
| { name: "io", aon: "no", freq: "96000000" } |
| { name: "usb", aon: "no", freq: "48000000" } |
| { name: "aon", aon: "yes", freq: "200000" } |
| ], |
| |
| // Derived clock source attributes |
| // name: Name of group. |
| // aon: Whether the clock is free running all the time. |
| // If it is, the clock is not hanlded by clkmgr. |
| // freq: Absolute frequency of clk in Hz |
| // src: From which clock source is the clock derived |
| // div: Ratio between derived clock and source clock |
| derived_srcs: [ |
| { name: "io_div2", aon: "no", div: 2, src: "io", freq: "48000000" } |
| { name: "io_div4", aon: "no", div: 4, src: "io", freq: "24000000" } |
| ], |
| |
| // Clock Group attributes |
| // name: name of group. |
| // |
| // src: The hierarchical source of the clock |
| // "ext" - clock is supplied from a port of the top module |
| // "top" - clock is supplied from a net inside the top module |
| // |
| // sw_cg: whether software is allowed to gate the clock |
| // "no" - software is not allowed to gate clocks |
| // "yes" - software is allowed to gate clocks |
| // "hint" - software can provide a hint, and hw controls the rest |
| // |
| // unique: whether each module in the group can be separately gated |
| // if sw_cg is "no", this field has no meaning |
| // "yes" - each clock is individually controlled |
| // "no" - the group is controlled as one single unit |
| // |
| // The powerup and proc groups are unique. |
| // The powerup group of clocks do not feed through the clock |
| // controller as they manage clock controller behavior |
| // The proc group is not peripheral, and directly hardwired |
| |
| groups: [ |
| // the powerup group is used exclusively by clk/pwr/rstmgr/pinmux |
| { name: "powerup", src:"top", sw_cg: "no" } |
| { name: "trans", src:"top", sw_cg: "hint", unique: "yes", } |
| { name: "infra", src:"top", sw_cg: "no", } |
| { name: "secure", src:"top", sw_cg: "no" } |
| { name: "peri", src:"top", sw_cg: "yes", unique: "no" } |
| { name: "timers", src:"top", sw_cg: "no" } |
| { name: "proc", |
| src: "no", |
| sw_cg: "no", |
| unique: "no", |
| clocks: { |
| clk_proc_main: main |
| } |
| } |
| ], |
| }, |
| |
| // This is the reset data strcture of the design. |
| // The hier path refers to the reset reference path (struct / port) |
| // - The top/ext desgination follows the same scheme as inter-module |
| // The node key represents all the known resets in the design |
| resets: { |
| |
| hier_paths: { |
| top: "rstmgr_aon_resets.", // top level is a struct |
| ext: "", // ext is a port of the clock name |
| }, |
| |
| // Reset node attributes |
| // name: name of reset. |
| // |
| // gen: whether the reset is generated |
| // true: it is a generated reset inside rstmgr |
| // false: it is a hardwired design reset inside rstmgr (roots and por) |
| // For non-generated resets, the parent / domain definitions have no meaning. |
| // |
| // type: the reset type [ext, top] |
| // ext: the reset is coming in from the ports, external to englishbreakfast |
| // int: the reset is only used inside rstmgr |
| // top: the reset is output from rstmgr to top level struct |
| // |
| // parent: The parent reset |
| // If type is "ext", there is no root, since it is external |
| // |
| // domains: The power domains of a particular reset |
| // This is a list of of the supported power domains. |
| // Valid values are Aon and (power domain)0 ~ (power domain)1. |
| // If no value is supplied, the default is only the Aon version. |
| // |
| // clk: related clock domain for synchronous release |
| // If type is "por", there is not related clock, since it is |
| // likely external or generated from a voltage comparator |
| // |
| nodes: [ |
| { name: "rst_ni", gen: false, type: "ext", } |
| { name: "por_aon", gen: false, type: "top", domains: ["Aon" ], clk: "aon" } |
| { name: "lc_src", gen: false, type: "int", domains: ["Aon", "0"], clk: "io_div4" } |
| { name: "sys_src", gen: false, type: "int", domains: ["Aon", "0"], clk: "io_div4" } |
| { name: "por", gen: true, type: "top", domains: ["Aon" ], parent: "por_aon", clk: "main" } |
| { name: "por_io", gen: true, type: "top", domains: ["Aon", ], parent: "por_aon", clk: "io" } |
| { name: "por_io_div2", gen: true, type: "top", domains: ["Aon", ], parent: "por_aon", clk: "io_div2" } |
| { name: "por_io_div4", gen: true , type: "top", domains: ["Aon", ], parent: "por_aon", clk: "io_div4" } |
| { name: "por_usb", gen: true, type: "top", domains: ["Aon", ], parent: "por_aon", clk: "usb" } |
| { name: "lc", gen: true, type: "top", domains: [ "0"], parent: "lc_src", clk: "main" } |
| { name: "lc_io_div4", gen: true, type: "top", domains: [ "0"], parent: "lc_src", clk: "io_div4" } |
| { name: "sys", gen: true, type: "top", domains: [ "0"], parent: "sys_src", clk: "main" } |
| { name: "sys_io_div4", gen: true, type: "top", domains: ["Aon", "0"], parent: "sys_src", clk: "io_div4" } |
| { name: "sys_aon", gen: true, type: "top", domains: ["Aon", "0"], parent: "sys_src", clk: "aon" } |
| { name: "spi_device", gen: true, type: "top", domains: [ "0"], parent: "sys_src", clk: "io_div2", sw: 1 } |
| { name: "spi_host0", gen: true, type: "top", domains: [ "0"], parent: "sys_src", clk: "io_div2", sw: 1 } |
| { name: "usb", gen: true, type: "top", domains: [ "0"], parent: "sys_src", clk: "usb", sw: 1 } |
| ] |
| } |
| |
| // Number of cores: used in rv_plic and timer |
| num_cores: "1", |
| |
| |
| // TODO: remove completely |
| host: [ |
| ] |
| |
| // `module` defines the peripherals. |
| // Details are coming from each modules' config file `ip.hjson` |
| // TODO: Define parameter here |
| // attr: There are a few types of modules supported |
| // normal(default): Normal, non-templated modules that will be instantiated |
| // templated: These modules are templated and must be run through topgen |
| // reggen_top: These modules are not templated, but need to have reggen run |
| // because they live exclusively in hw/top_* instead of hw/ip_*. |
| // These modules are also instantiated in the top level. |
| // reggen_only: Similar to reggen_top, but are not instantiated in the top level. |
| module: [ |
| { name: "uart0", // instance name |
| type: "uart", // Must be matched to the ip name in `ip.hson` (_reg, _cfg permitted) |
| // and `hw/ip/{type}` |
| |
| // clock connections defines the port to top level clock connection |
| // the ip.hjson will declare the clock port names |
| // If none are defined at ip.hjson, clk_i is used by default |
| clock_srcs: {clk_i: "io_div4"}, |
| |
| // reset connections defines the port to top level reset connection |
| // the ip.hjson will declare the reset port names |
| // If none are defined at ip.hjson, rst_ni is used by default |
| reset_connections: {rst_ni: "sys_io_div4"}, |
| base_addr: "0x40000000", |
| }, |
| { name: "gpio", |
| type: "gpio", |
| clock_srcs: {clk_i: "io_div4"}, |
| clock_group: "peri", |
| reset_connections: {rst_ni: "sys_io_div4"}, |
| base_addr: "0x40040000", |
| } |
| { name: "spi_device", |
| type: "spi_device", |
| clock_srcs: {clk_i: "io_div4", scan_clk_i: "io_div2"}, |
| clock_group: "peri", |
| reset_connections: {rst_ni: "spi_device"}, |
| base_addr: "0x40050000", |
| }, |
| { name: "spi_host0", |
| type: "spi_host", |
| clock_srcs: {clk_i: "io_div4", clk_core_i: "io_div2"}, |
| clock_group: "peri", |
| reset_connections: {rst_ni: "spi_host0", rst_core_ni: "spi_host0"}, |
| base_addr: "0x40060000", |
| }, |
| { name: "rv_timer", |
| type: "rv_timer", |
| clock_srcs: {clk_i: "io_div4"}, |
| clock_group: "timers", |
| reset_connections: {rst_ni: "sys_io_div4"}, |
| base_addr: "0x40100000", |
| }, |
| { name: "usbdev", |
| type: "usbdev", |
| clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon", clk_usb_48mhz_i: "usb"}, |
| clock_group: "peri", |
| clock_reset_export: ["ast"], |
| reset_connections: {rst_ni: "sys_io_div4", rst_aon_ni: "sys_aon", rst_usb_48mhz_ni: "usb"}, |
| base_addr: "0x40110000", |
| }, |
| { name: "lc_ctrl", |
| type: "lc_ctrl", |
| clock_srcs: {clk_i: "io_div4", clk_kmac_i: "main"}, |
| clock_group: "timers", |
| reset_connections: {rst_ni: "lc_io_div4", rst_kmac_ni: "sys"}, |
| base_addr: "0x40140000", |
| }, |
| { name: "alert_handler", |
| type: "alert_handler", |
| clock_srcs: {clk_i: "io_div4", clk_edn_i: "main"}, |
| clock_group: "timers", |
| reset_connections: {rst_ni: "sys_io_div4", rst_edn_ni: "sys"}, |
| base_addr: "0x40150000", |
| attr: "templated", |
| localparam: { |
| EscCntDw: 32, |
| AccuCntDw: 16, |
| LfsrSeed: "0x7FFFFFFF" |
| } |
| }, |
| // dummy module to capture the alert handler escalation signals |
| // and test them by converting them into IRQs |
| { name: "nmi_gen", |
| type: "nmi_gen", |
| clock_srcs: {clk_i: "io_div4"}, |
| clock_group: "timers", |
| reset_connections: {rst_ni: "sys_io_div4"}, |
| base_addr: "0x40160000", |
| } |
| { name: "pwrmgr_aon", |
| type: "pwrmgr", |
| clock_srcs: {clk_i: "io_div4", clk_slow_i: "aon"}, |
| clock_group: "powerup", |
| reset_connections: {rst_ni: "por", rst_slow_ni: "por_aon"}, |
| domain: "Aon", |
| base_addr: "0x40400000", |
| attr: "templated", |
| |
| }, |
| { name: "rstmgr_aon", |
| type: "rstmgr", |
| clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon", clk_main_i: "main", clk_io_i: "io", clk_usb_i: "usb", |
| clk_io_div2_i: "io_div2", clk_io_div4_i: "io_div4"}, |
| clock_group: "powerup", |
| reset_connections: {rst_ni: "rst_ni"}, |
| domain: "Aon", |
| base_addr: "0x40410000", |
| attr: "templated", |
| }, |
| { name: "clkmgr_aon", |
| type: "clkmgr", |
| clock_srcs: {clk_i: "io_div4"}, |
| clock_group: "powerup", |
| reset_connections: {rst_ni: "por_io_div4", rst_main_ni: "por", rst_io_ni: "por_io", rst_usb_ni: "por_usb" |
| rst_io_div2_ni: "por_io_div2", rst_io_div4_ni: "por_io_div4"}, |
| domain: "Aon", |
| base_addr: "0x40420000", |
| attr: "templated", |
| }, |
| { name: "pinmux_aon", |
| type: "pinmux", |
| clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon"}, |
| clock_group: "powerup", |
| reset_connections: {rst_ni: "sys_io_div4", rst_aon_ni: "sys_aon"}, |
| domain: "Aon", |
| base_addr: "0x40460000", |
| attr: "templated", |
| }, |
| { name: "sensor_ctrl_aon", |
| type: "sensor_ctrl", |
| clock_srcs: {clk_i: "io_div4"}, |
| clock_group: "secure", |
| clock_reset_export: ["ast"], |
| reset_connections: {rst_ni: "sys_io_div4"}, |
| domain: "Aon", |
| base_addr: "0x40490000", |
| attr: "reggen_top", |
| }, |
| { name: "sram_ctrl_ret_aon", |
| type: "sram_ctrl", |
| clock_srcs: {clk_i: "io_div4", clk_otp_i: "io_div4"}, |
| clock_group: "peri", |
| reset_connections: {rst_ni: "sys_io_div4", rst_otp_ni: "lc_io_div4"}, |
| domain: "Aon", |
| base_addr: "0x40500000" |
| }, |
| { name: "flash_ctrl", |
| type: "flash_ctrl", |
| clock_srcs: {clk_i: "main", clk_otp_i: "io_div4"}, |
| clock_group: "infra", |
| reset_connections: {rst_ni: "lc", rst_otp_ni: "lc_io_div4"}, |
| base_addrs: {core: "0x41000000", prim: "0x41008000"} |
| attr: "templated", |
| }, |
| { name: "rv_dm", |
| type: "rv_dm", |
| clock_srcs: {clk_i: "main"}, |
| clock_group: "secure", |
| reset_connections: {rst_ni: "lc"}, |
| // Note that this module also contains a bus host. |
| base_addrs: {rom: "0x00010000", regs: "0x41200000"} |
| }, |
| { name: "rv_plic", |
| type: "rv_plic", |
| clock_srcs: {clk_i: "main"}, |
| clock_group: "secure", |
| reset_connections: {rst_ni: "sys"}, |
| base_addr: "0x41010000", |
| attr: "templated", |
| }, |
| { name: "aes", |
| type: "aes", |
| clock_srcs: {clk_i: "main", clk_edn_i: "main"}, |
| clock_group: "trans", |
| reset_connections: {rst_ni: "sys", rst_edn_ni: "sys"}, |
| base_addr: "0x41100000", |
| }, |
| { name: "hmac", |
| type: "hmac", |
| clock_srcs: {clk_i: "main"}, |
| clock_group: "trans", |
| reset_connections: {rst_ni: "sys"}, |
| base_addr: "0x41110000", |
| }, |
| { name: "sram_ctrl_main", |
| type: "sram_ctrl", |
| clock_srcs: {clk_i: "main", clk_otp_i: "io_div4"}, |
| clock_group: "secure", |
| reset_connections: {rst_ni: "sys", rst_otp_ni: "lc_io_div4"}, |
| base_addr: "0x411C0000", |
| }, |
| { name: "rv_core_ibex", |
| type: "rv_core_ibex", |
| param_decl: {PMPEnable: "1", |
| PMPGranularity: "0", |
| PMPNumRegions: "16", |
| MHPMCounterNum: "10", |
| MHPMCounterWidth: "32", |
| RV32E: "0", |
| RV32M: "ibex_pkg::RV32MSingleCycle", |
| RV32B: "ibex_pkg::RV32BNone", |
| RegFile: "ibex_pkg::RegFileFF", |
| BranchTargetALU: "1", |
| WritebackStage: "1", |
| ICache: "1", |
| ICacheECC: "1", |
| BranchPredictor: "0", |
| DbgTriggerEn: "1", |
| SecureIbex: "1", |
| DmHaltAddr: "ADDR_SPACE_RV_DM__ROM + dm::HaltAddress[31:0]", |
| DmExceptionAddr: "ADDR_SPACE_RV_DM__ROM + dm::ExceptionAddress[31:0]", |
| PipeLine: "0" |
| } |
| clock_srcs: {clk_i: "main", clk_esc_i: "io_div4"}, |
| clock_group: "infra", |
| reset_connections: {rst_ni: "sys", rst_esc_ni: "lc_io_div4"}, |
| base_addr: "0x411F0000", |
| }, |
| ] |
| |
| // Memories (ROM, RAM, eFlash) are defined at the top. |
| // It utilizes the primitive cells but configurable |
| memory: [ |
| { name: "rom", |
| clock_srcs: {clk_i: "main"}, |
| clock_group: "infra", |
| reset_connections: {rst_ni: "sys"}, |
| type: "rom", |
| base_addr: "0x00008000", |
| swaccess: "ro", |
| size: "0x4000", |
| // data integrity width |
| integ_width: 8, |
| inter_signal_list: [ |
| { struct: "tl" |
| package: "tlul_pkg" |
| type: "req_rsp" |
| act: "rsp" |
| name: "tl" |
| } |
| ] |
| }, |
| { name: "ram_main", |
| clock_srcs: {clk_i: "main"}, |
| clock_group: "infra", |
| reset_connections: {rst_ni: "sys"}, |
| type: "ram_1p_scr", |
| base_addr: "0x10000000", |
| size: "0x10000", |
| byte_write: "true", |
| // data integrity width |
| integ_width: 7, |
| exec: "1", |
| inter_signal_list: [ |
| { struct: "tl" |
| package: "tlul_pkg" |
| type: "req_rsp" |
| act: "rsp" |
| name: "tl" |
| }, |
| // Interface to SRAM controller |
| { struct: "sram_scr", |
| package: "sram_ctrl_pkg" |
| type: "req_rsp", |
| name: "sram_scr", |
| act: "rsp", |
| }, |
| { struct: "sram_scr_init", |
| package: "sram_ctrl_pkg" |
| type: "req_rsp", |
| name: "sram_scr_init", |
| act: "rsp", |
| }, |
| { struct: "tl_instr_en", |
| package: "tlul_pkg" |
| type: "uni", |
| name: "en_ifetch", |
| act: "rcv", |
| }, |
| { struct: "logic", |
| package: "" |
| type: "uni", |
| name: "intg_error", |
| act: "req", |
| }, |
| ] |
| }, |
| { name: "ram_ret_aon", |
| clock_srcs: {clk_i: "io_div4"}, |
| clock_group: "infra", |
| reset_connections: {rst_ni: "sys_io_div4"}, |
| domain: "Aon", |
| type: "ram_1p_scr", |
| base_addr: "0x40600000", |
| size: "0x1000", |
| byte_write: "true", |
| // data integrity width |
| integ_width: 7, |
| exec: "0", |
| inter_signal_list: [ |
| { struct: "tl" |
| package: "tlul_pkg" |
| type: "req_rsp" |
| act: "rsp" |
| name: "tl" |
| }, |
| // Interface to SRAM controller |
| { struct: "sram_scr", |
| package: "sram_ctrl_pkg" |
| type: "req_rsp", |
| name: "sram_scr", |
| act: "rsp", |
| }, |
| { struct: "sram_scr_init", |
| package: "sram_ctrl_pkg" |
| type: "req_rsp", |
| name: "sram_scr_init", |
| act: "rsp", |
| }, |
| { struct: "tl_instr_en", |
| package: "tlul_pkg" |
| type: "uni", |
| name: "en_ifetch", |
| act: "rcv", |
| }, |
| { struct: "logic", |
| package: "" |
| type: "uni", |
| name: "intg_error", |
| act: "req", |
| }, |
| ] |
| }, |
| { name: "eflash", |
| clock_srcs: {clk_i: "main"}, |
| clock_group: "infra", |
| reset_connections: {rst_ni: "lc"}, |
| type: "eflash", |
| base_addr: "0x20000000", |
| banks: 2, |
| pages_per_bank: 16, |
| program_resolution: 8, // maximum number of flash words allowed to program at one time |
| swaccess: "ro", |
| inter_signal_list: [ |
| { struct: "flash", // flash_req_t, flash_rsp_t |
| type: "req_rsp", |
| name: "flash_ctrl", // flash_ctrl_i (req), flash_ctrl_o (rsp) |
| act: "rsp", |
| }, |
| { struct: "tl" |
| package: "tlul_pkg" |
| type: "req_rsp" |
| act: "rsp" |
| name: "tl" |
| }, |
| { struct: "lc_tx", |
| package: "lc_ctrl_pkg", |
| type: "uni" |
| act: "rcv" |
| name: "lc_nvm_debug_en" |
| }, |
| { struct: "lc_tx" |
| package: "lc_ctrl_pkg" |
| type: "uni" |
| act: "rcv" |
| name: "flash_bist_enable" |
| }, |
| { struct: "logic" |
| package: "" |
| type: "uni" |
| act: "rcv" |
| name: "flash_power_down_h" |
| }, |
| { struct: "logic" |
| package: "" |
| type: "uni" |
| act: "rcv" |
| name: "flash_power_ready_h" |
| }, |
| { struct: "logic", |
| package: "", |
| width: "4", |
| type: "uni" |
| act: "rcv" |
| name: "flash_test_mode_a" |
| }, |
| { struct: "logic", |
| package: "", |
| type: "uni" |
| act: "rcv" |
| name: "flash_test_voltage_h" |
| }, |
| { struct: "ast_dif", |
| package: "ast_pkg", |
| type: "uni" |
| act: "req" |
| name: "flash_alert" |
| }, |
| ], |
| }, |
| ], |
| |
| // The port data structure is not something that should be used liberally. |
| // It is used specifically to assign special attributes to specific ports. |
| // For example, this allows us to designate a port as part of inter-module |
| // connections. |
| port: [ |
| { name: "ast", |
| inter_signal_list: [ |
| { struct: "edn", |
| type: "req_rsp", |
| name: "edn", |
| // The activity direction for a port inter-signal is "opposite" of |
| // what the external module actually needs. |
| act: "rsp", |
| package: "edn_pkg", |
| }, |
| |
| { struct: "lc_tx", |
| type: "uni", |
| name: "lc_dft_en", |
| // The activity direction for a port inter-signal is "opposite" of |
| // what the external module actually needs. |
| act: "req", |
| package: "lc_ctrl_pkg", |
| }, |
| |
| { struct: "ram_1p_cfg", |
| package: "prim_ram_1p_pkg", |
| type: "uni", |
| name: "ram_1p_cfg", |
| // The activity direction for a port inter-signal is "opposite" of |
| // what the external module actually needs. |
| act: "rcv" |
| }, |
| |
| { struct: "ram_2p_cfg", |
| package: "prim_ram_2p_pkg", |
| type: "uni", |
| name: "ram_2p_cfg", |
| // The activity direction for a port inter-signal is "opposite" of |
| // what the external module actually needs. |
| act: "rcv" |
| }, |
| |
| { struct: "rom_cfg", |
| package: "prim_rom_pkg", |
| type: "uni", |
| name: "rom_cfg", |
| // The activity direction for a port inter-signal is "opposite" of |
| // what the external module actually needs. |
| act: "rcv" |
| } |
| ] |
| }, |
| ] |
| |
| // Inter-module Connection. |
| // format: |
| // requester: [ resp1, resp2, ... ], |
| // |
| // the field and value should be module_inst.port_name |
| // e.g flash_ctrl0.flash: [flash_phy0.flash_ctrl] |
| inter_module: { |
| 'connect': { |
| 'alert_handler.crashdump' : ['rstmgr_aon.alert_dump'], |
| 'alert_handler.esc_rx' : ['rv_core_ibex.esc_rx', |
| 'lc_ctrl.esc_scrap_state0_rx', |
| 'lc_ctrl.esc_scrap_state1_rx' |
| 'pwrmgr_aon.esc_rst_rx'], |
| 'alert_handler.esc_tx' : ['rv_core_ibex.esc_tx', |
| 'lc_ctrl.esc_scrap_state0_tx', |
| 'lc_ctrl.esc_scrap_state1_tx', |
| 'pwrmgr_aon.esc_rst_tx'], |
| 'flash_ctrl.flash' : ['eflash.flash_ctrl'], |
| 'flash_ctrl.rma_req' : ['lc_ctrl.lc_flash_rma_req'], |
| 'flash_ctrl.rma_ack' : ['lc_ctrl.lc_flash_rma_ack'], |
| 'flash_ctrl.rma_seed' : ['lc_ctrl.lc_flash_rma_seed'], |
| 'sram_ctrl_main.sram_scr' : ['ram_main.sram_scr'], |
| 'sram_ctrl_main.sram_scr_init' : ['ram_main.sram_scr_init'], |
| 'sram_ctrl_ret_aon.sram_scr' : ['ram_ret_aon.sram_scr'], |
| 'sram_ctrl_ret_aon.sram_scr_init' : ['ram_ret_aon.sram_scr_init'], |
| 'sram_ctrl_main.en_ifetch' : ['ram_main.en_ifetch'], |
| 'sram_ctrl_ret_aon.en_ifetch' : ['ram_ret_aon.en_ifetch'], |
| 'ram_main.intg_error' : ['sram_ctrl_main.intg_error'], |
| 'ram_ret_aon.intg_error' : ['sram_ctrl_ret_aon.intg_error'], |
| 'pwrmgr_aon.pwr_flash' : ['flash_ctrl.pwrmgr'], |
| 'pwrmgr_aon.pwr_rst' : ['rstmgr_aon.pwr'], |
| 'pwrmgr_aon.pwr_clk' : ['clkmgr_aon.pwr'], |
| 'pwrmgr_aon.pwr_lc' : ['lc_ctrl.pwr_lc'], |
| 'pwrmgr_aon.strap' : ['pinmux_aon.strap_en'], |
| 'pwrmgr_aon.low_power' : ['pinmux_aon.sleep_en'], |
| 'alert_handler.crashdump' : ['rstmgr_aon.alert_dump'], |
| 'rv_core_ibex.crash_dump' : ['rstmgr_aon.cpu_dump'], |
| |
| // usbdev connection to pinmux |
| 'usbdev.usb_out_of_rst' : ['pinmux_aon.usb_out_of_rst'], |
| 'usbdev.usb_aon_wake_en' : ['pinmux_aon.usb_aon_wake_en'], |
| 'usbdev.usb_aon_wake_ack' : ['pinmux_aon.usb_aon_wake_ack'], |
| 'usbdev.usb_suspend' : ['pinmux_aon.usb_suspend'], |
| 'pinmux_aon.usb_state_debug' : ['usbdev.usb_state_debug'], |
| |
| // The idle connection is automatically connected through topgen. |
| // The user does not need to explicitly declare anything other than |
| // an empty list. |
| 'clkmgr_aon.idle' : [], |
| |
| // Pinmux JTAG signals |
| // Note that the DFT TAP will be connected |
| // automatically by the DFT insertion tool, |
| // hence it does not have to be connected here. |
| 'pinmux_aon.lc_jtag' : ['lc_ctrl.jtag'], |
| 'pinmux_aon.rv_jtag' : ['rv_dm.jtag'], |
| |
| // LC function control signal broadcast |
| 'lc_ctrl.lc_dft_en' : ['pinmux_aon.lc_dft_en'], |
| 'lc_ctrl.lc_nvm_debug_en' : ['eflash.lc_nvm_debug_en'], |
| 'lc_ctrl.lc_hw_debug_en' : ['sram_ctrl_main.lc_hw_debug_en', |
| 'sram_ctrl_ret_aon.lc_hw_debug_en', |
| 'pinmux_aon.lc_hw_debug_en', |
| 'rv_dm.lc_hw_debug_en'], |
| 'lc_ctrl.lc_cpu_en' : ['rv_core_ibex.lc_cpu_en'], |
| 'lc_ctrl.lc_keymgr_en' : [], |
| 'lc_ctrl.lc_escalate_en' : ['aes.lc_escalate_en', |
| 'sram_ctrl_main.lc_escalate_en', |
| 'sram_ctrl_ret_aon.lc_escalate_en', |
| 'flash_ctrl.lc_escalate_en'], |
| 'lc_ctrl.lc_clk_byp_req' : ['clkmgr_aon.lc_clk_byp_req'], |
| 'lc_ctrl.lc_clk_byp_ack' : ['clkmgr_aon.lc_clk_byp_ack'], |
| |
| // LC access control signal broadcast |
| 'lc_ctrl.lc_creator_seed_sw_rw_en' : ['flash_ctrl.lc_creator_seed_sw_rw_en'], |
| 'lc_ctrl.lc_owner_seed_sw_rw_en' : ['flash_ctrl.lc_owner_seed_sw_rw_en'], |
| 'lc_ctrl.lc_iso_part_sw_rd_en' : ['flash_ctrl.lc_iso_part_sw_rd_en'], |
| 'lc_ctrl.lc_iso_part_sw_wr_en' : ['flash_ctrl.lc_iso_part_sw_wr_en'], |
| 'lc_ctrl.lc_seed_hw_rd_en' : ['flash_ctrl.lc_seed_hw_rd_en'], |
| |
| // TODO: Put passthrough here? |
| //'spi_device.passthrough': ['spi_host0.passthrough'] |
| |
| // Debug module reset request to reset manager |
| 'rv_dm.ndmreset_req' : ['rstmgr_aon.ndmreset_req'] |
| } |
| |
| // top is to connect to top net/struct. |
| // It defines the signal in the top and connect from the module, |
| // use of the signal is up to top template |
| 'top': [ |
| 'rstmgr_aon.resets', 'rstmgr_aon.rst_cpu_n', |
| 'pwrmgr_aon.pwr_cpu', 'pwrmgr_aon.fetch_en', |
| 'clkmgr_aon.clocks', |
| |
| // Debug request from debug module to CPU |
| 'rv_dm.debug_req', |
| |
| // Xbars |
| 'main.tl_corei', 'main.tl_cored' |
| ], |
| |
| // ext is to create port in the top. |
| 'external': { |
| // 'adc_ctrl_aon.adc' : 'adc' |
| 'ast.edn' : '', |
| 'ast.lc_dft_en' : '', |
| 'ast.ram_1p_cfg' : 'ram_1p_cfg', |
| 'ast.ram_2p_cfg' : 'ram_2p_cfg', |
| 'ast.rom_cfg' : 'rom_cfg', |
| 'clkmgr_aon.clk_main' : 'clk_main', // clock inputs |
| 'clkmgr_aon.clk_io' : 'clk_io', // clock inputs |
| 'clkmgr_aon.clk_usb' : 'clk_usb', // clock inputs |
| 'clkmgr_aon.clk_aon' : 'clk_aon', // clock inputs |
| 'clkmgr_aon.jitter_en' : 'clk_main_jitter_en', |
| 'clkmgr_aon.ast_clk_byp_req' : 'ast_clk_byp_req', |
| 'clkmgr_aon.ast_clk_byp_ack' : 'ast_clk_byp_ack', |
| 'eflash.flash_alert' : 'flash_alert', |
| 'eflash.flash_bist_enable' : 'flash_bist_enable', |
| 'eflash.flash_power_down_h' : 'flash_power_down_h', |
| 'eflash.flash_power_ready_h' : 'flash_power_ready_h', |
| # 'entropy_src.entropy_src_rng' : '', |
| # 'entropy_src.rng_fips' : '', |
| # 'peri.tl_ast' : '', |
| 'pinmux_aon.dft_strap_test' : 'dft_strap_test' |
| 'pinmux_aon.dft_hold_tap_sel' : 'dft_hold_tap_sel', |
| 'pwrmgr_aon.pwr_ast' : 'pwrmgr_ast', |
| # 'otp_ctrl.otp_ast_pwr_seq' : '', |
| # 'otp_ctrl.otp_ast_pwr_seq_h' : '', |
| 'sensor_ctrl_aon.ast_alert' : 'sensor_ctrl_ast_alert', |
| 'sensor_ctrl_aon.ast_status' : 'sensor_ctrl_ast_status', |
| 'sensor_ctrl_aon.ast2pinmux' : '', |
| 'usbdev.usb_ref_val' : '', |
| 'usbdev.usb_ref_pulse' : '', |
| }, |
| }, |
| |
| // Crossbars: having a top level crossbar |
| // This version assumes all crossbars are instantiated at the top. |
| // Assume xbar.hjson is located in the same directory of top.hjson |
| xbar: [ |
| { name: "main", |
| clock_srcs: {clk_main_i: "main", clk_fixed_i: "io_div4"}, |
| clock_group: "infra", |
| reset: "sys", |
| reset_connections: {rst_main_ni: "sys", rst_fixed_ni: "sys_io_div4"} |
| }, |
| { name: "peri", |
| clock_srcs: {clk_peri_i: "io_div4"}, |
| clock_group: "infra", |
| reset: "sys_io_div4", |
| reset_connections: {rst_peri_ni: "sys_io_div4"}, |
| } |
| ], |
| |
| // ===== PINMUX & PINOUT ====================================================== |
| |
| pinout: { |
| // IO power bank declaration. |
| // This list defines the IO bank power domains on the ASIC. |
| // Each individual pad must be in one of the declared power domains. |
| banks: ['VCC', 'AVCC', 'VIOA', 'VIOB'], |
| // Pad declaration. |
| // Each entry must have the following four keys: |
| // |
| // - name: Name of the pad (this will be exposed at the chiplevel). |
| // |
| // - type: Pad type (this maps to the pad types defined in prim_pad_wrapper_pkg.sv) |
| // |
| // - bank: Specifies in which of the IO power banks this pad lives. |
| // |
| // - connection: Can have either of the following values: |
| // |
| // 1) 'direct': This is a dedicated IO Pad that is directly connected to a peripheral. |
| // |
| // 2) 'manual': This is a dedicated IO signal that is not directly connected to a |
| // peripheral. It needs to be manually wired up in the template. |
| // |
| // 3) 'muxed': This is a muxed IO pad that will be connected to the pinmux. |
| // |
| // Optionally, each pad can also have a 'desc' field for further description. |
| pads: [ |
| // Special manually connected pads |
| { name: 'POR_N' , type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'System reset'}, |
| { name: 'USB_P' , type: 'BidirTol', bank: 'VCC' , connection: 'manual', desc: 'USB P signal'}, |
| { name: 'USB_N' , type: 'BidirTol', bank: 'VCC' , connection: 'manual', desc: 'USB N signal'}, |
| { name: 'CC1' , type: 'InputStd', bank: 'AVCC', connection: 'manual', desc: 'ADC input 1'}, |
| { name: 'CC2' , type: 'InputStd', bank: 'AVCC', connection: 'manual', desc: 'ADC input 2'}, |
| { name: 'FLASH_TEST_VOLT' , type: 'AnalogIn0',bank: 'VCC' , connection: 'manual', desc: 'Flash test voltage input'}, |
| { name: 'FLASH_TEST_MODE0', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'}, |
| { name: 'FLASH_TEST_MODE1', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'}, |
| // Dedicated IOs |
| { name: 'SPI_HOST_D0' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'}, |
| { name: 'SPI_HOST_D1' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'}, |
| { name: 'SPI_HOST_D2' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'}, |
| { name: 'SPI_HOST_D3' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'}, |
| { name: 'SPI_HOST_CLK' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host clock'}, |
| { name: 'SPI_HOST_CS_L' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host chip select'}, |
| { name: 'SPI_DEV_D0' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device data'}, |
| { name: 'SPI_DEV_D1' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device data'}, |
| { name: 'SPI_DEV_D2' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device data'}, |
| { name: 'SPI_DEV_D3' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device data'}, |
| { name: 'SPI_DEV_CLK' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device clock'}, |
| { name: 'SPI_DEV_CS_L' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device chip select'}, |
| // IOA |
| { name: 'IOA0' , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOA1' , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOA2' , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOA3' , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOA4' , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOA5' , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOA6' , type: 'BidirOd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOA7' , type: 'BidirOd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOA8' , type: 'BidirOd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| // IOB |
| { name: 'IOB0' , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOB1' , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOB2' , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOB3' , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOB4' , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOB5' , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOB6' , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOB7' , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOB8' , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOB9' , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOB10' , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOB11' , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOB12' , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'}, |
| // IOC |
| { name: 'IOC0' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOC1' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOC2' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOC3' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOC4' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOC5' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOC6' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOC7' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOC8' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOC9' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOC10' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOC11' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOC12' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| // IOR |
| { name: 'IOR0' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOR1' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOR2' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOR3' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOR4' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOR5' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOR6' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOR7' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOR10' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOR11' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOR12' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| { name: 'IOR13' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, |
| ] |
| } |
| |
| pinmux: { |
| // Signal to pinmux/pad mapping. |
| // Each entry in the list below must have the following two mandatory keys: |
| // |
| // - instance: This is the comportable IO instance name where the IO signal comes from. |
| // |
| // - connection: Can have either of the following values: |
| // |
| // 1) 'direct': This is a dedicated IO signal that is directly connected to a pad. |
| // Such an IO signal must also specify the 'port' and 'pad' keys |
| // (see further below). |
| // |
| // 2) 'manual': This is a dedicated IO signal that is not directly connected to a pad. |
| // It needs to be manually wired up in the template. |
| // Such an IO signal may have a 'port' key, but no 'pad' key. |
| // |
| // 3) 'muxed': This is a muxed IO signal that will be connected to the pinmux. |
| // Such an IO signal may have a 'port' key, but no 'pad' key. |
| // |
| // Depending on the connection type specified, each entry may have the following optional keys: |
| // |
| // - port: Name of the available IO signal of the instance. |
| // This is required for 'direct' connections, but optional for the others. |
| // Individual signals of a bus IO signal must be indexed with square brackets, e.g. mybus[1]. |
| // Not specifying this key or setting it to an empty string acts as a wild card |
| // and includes all available IOs of this instance. |
| // |
| // - pad: Name of the pad the 'direct' connection should connect to. |
| // This is not required for 'muxed' and 'manual' connections. |
| // |
| // - desc: Optional description field. |
| // |
| // - attr: Manual direct IOs may specify an additional pad attr field. |
| // This is used to create the correct pad attribute CSR for that DIO channel (since the |
| // DIO is manual, there is no way to automatically infer the corresponding pad type). |
| // |
| signals: [ |
| // SPI Host0 |
| { instance: 'spi_host0', port: 'sck', connection: 'direct', pad: 'SPI_HOST_CLK' , desc: ''}, |
| { instance: 'spi_host0', port: 'csb', connection: 'direct', pad: 'SPI_HOST_CS_L', desc: ''}, |
| { instance: 'spi_host0', port: 'sd[0]', connection: 'direct', pad: 'SPI_HOST_D0' , desc: ''}, |
| { instance: 'spi_host0', port: 'sd[1]', connection: 'direct', pad: 'SPI_HOST_D1' , desc: ''}, |
| { instance: 'spi_host0', port: 'sd[2]', connection: 'direct', pad: 'SPI_HOST_D2' , desc: ''}, |
| { instance: 'spi_host0', port: 'sd[3]', connection: 'direct', pad: 'SPI_HOST_D3' , desc: ''}, |
| // SPI Device |
| { instance: 'spi_device', port: 'sck', connection: 'direct', pad: 'SPI_DEV_CLK' , desc: ''}, |
| { instance: 'spi_device', port: 'csb', connection: 'direct', pad: 'SPI_DEV_CS_L' , desc: ''}, |
| { instance: 'spi_device', port: 'sd[0]', connection: 'direct', pad: 'SPI_DEV_D0' , desc: ''}, |
| { instance: 'spi_device', port: 'sd[1]', connection: 'direct', pad: 'SPI_DEV_D1' , desc: ''}, |
| { instance: 'spi_device', port: 'sd[2]', connection: 'direct', pad: 'SPI_DEV_D2' , desc: ''}, |
| { instance: 'spi_device', port: 'sd[3]', connection: 'direct', pad: 'SPI_DEV_D3' , desc: ''}, |
| // USBDEV |
| { instance: 'usbdev', port: '', connection: 'manual', pad: '' , desc: '', attr: 'BidirTol'}, |
| // MIOs |
| { instance: "gpio", port: '', connection: 'muxed' , pad: '' , desc: ''}, |
| { instance: "uart0", port: '', connection: 'muxed' , pad: '' , desc: ''}, |
| { instance: "flash_ctrl", port: '', connection: 'muxed' , pad: '' , desc: ''}, |
| { instance: "sensor_ctrl_aon", port: '', connection: 'muxed' , pad: '' , desc: ''}, |
| ], |
| |
| // Number of wakeup detectors to instantiate, and bitwidth for the wakeup counters. |
| num_wkup_detect: 8 |
| wkup_cnt_width: 8 |
| } |
| |
| // Implementation targets. |
| // This defines the configuration of the target-specific chip-levels to |
| // generate from the shared template. Each target uses the same base |
| // configuration for the pinmux and pinout as defined above, and the |
| // generated software constants for the pinmux DIF do not change among the |
| // implementation targets. However, in order to accommodate slight |
| // differences among the ASIC, FPGA emulation and simulation environments, |
| // it is possible to make very limited pinout changes below. In particular, |
| // it is possible to remove and tie-off specific pads, or add more 'manual' |
| // pads that need to be manually connected in the template. It is also possible |
| // to override the JTAG and strap locations indices, since the testing and DFT |
| // setups may differ among the targets. |
| targets: [ |
| { name: 'cw305', |
| pinout: { |
| remove_pads: [ |
| 'CC1', 'CC2', |
| 'SPI_DEV_D2', 'SPI_DEV_D3' |
| 'SPI_HOST_CLK', 'SPI_HOST_CS_L', |
| 'SPI_HOST_D0', 'SPI_HOST_D1', 'SPI_HOST_D2', 'SPI_HOST_D3', |
| 'FLASH_TEST_VOLT', |
| 'FLASH_TEST_MODE0', 'FLASH_TEST_MODE1', |
| 'IOB10', 'IOB11', 'IOB12', |
| 'IOC0', 'IOC1', 'IOC2', 'IOC3', 'IOC4', 'IOC5', 'IOC6', 'IOC7', 'IOC8', 'IOC9', 'IOC12', |
| 'IOR0', 'IOR1', 'IOR2', 'IOR3', 'IOR4', 'IOR5', 'IOR6', 'IOR7', 'IOR10', 'IOR11', 'IOR12', 'IOR13' |
| ], |
| |
| add_pads: [ |
| // Additional infrastucture pads |
| { name: 'IO_CLK', type: 'InputStd', bank: 'VCC', connection: 'manual', desc: 'Extra clock input for FPGA target'} |
| { name: 'IO_JSRST_N', type: 'InputStd', bank: 'VCC', connection: 'manual', desc: 'Dedicated JTAG system reset input'} |
| // Custom USB pads |
| { name: 'IO_USB_SENSE0', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB signal for FPGA target'} |
| { name: 'IO_USB_DNPULLUP0', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB signal for FPGA target'} |
| { name: 'IO_USB_DPPULLUP0', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB signal for FPGA target'} |
| // ChipWhisperer IO |
| { name: 'TIO_CLKOUT', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual clock output for SCA setup'} |
| { name: 'IO_UTX_DEBUG', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual UART TX debug output' } |
| ], |
| } |
| |
| pinmux: { |
| special_signals: [ |
| // Straps |
| { name: 'tap0', pad: 'IOC0' , desc: 'TAP strap signal, maps to a stubbed-off MIO.' }, |
| { name: 'tap1', pad: 'IOB7', desc: 'TAP strap signal, maps to MIO pad 16.' }, |
| { name: 'dft0', pad: 'IOC1' , desc: 'DFT strap signal, maps to a stubbed-off MIO.' }, |
| { name: 'dft1', pad: 'IOC12', desc: 'DFT strap signal, maps to a stubbed-off MIO.' }, |
| // JTAG |
| { name: 'tck', pad: 'SPI_DEV_CLK' , desc: 'JTAG tck signal, overlaid on SPI_DEV.' }, |
| { name: 'tms', pad: 'SPI_DEV_CS_L', desc: 'JTAG tms signal, overlaid on SPI_DEV.' }, |
| { name: 'trst_n', pad: 'IOB9' , desc: 'JTAG trst_n signal, maps to MIO pad 18.' }, |
| { name: 'tdi', pad: 'SPI_DEV_D0' , desc: 'JTAG tdi signal, overlaid on SPI_DEV.' }, |
| { name: 'tdo', pad: 'SPI_DEV_D1' , desc: 'JTAG tdo signal, overlaid on SPI_DEV.' }, |
| ], |
| } |
| } |
| ] |
| } |
