[clkmgr, top] clkmgr and top updates to better support ast external clock - ast provides a direct indication whether clock dividers should be stepped down during an external switch. - clkmgr can make use of this mechanism directly without having to piece separate logic together. - This PR may be incomplete at the moment because the relevant signals are in an async domain, this may be changed by an AST update. Signed-off-by: Timothy Chen <timothytim@google.com>

diff --git a/hw/ip/clkmgr/data/clkmgr.hjson b/hw/ip/clkmgr/data/clkmgr.hjson
index 14cf745..92aad75 100644
--- a/hw/ip/clkmgr/data/clkmgr.hjson
+++ b/hw/ip/clkmgr/data/clkmgr.hjson

@@ -24,6 +24,45 @@
     },
   ],
 
+  countermeasures: [
+    { name: "BUS.INTEGRITY",
+      desc: "End-to-end bus integrity scheme."
+    },
+    { name: "TIMEOUT.CLK.BKGN_CHK",
+      desc: "Background check for clock timeout."
+    },
+    { name: "MEAS.CLK.BKGN_CHK",
+      desc: "Background check for clock frequency."
+    },
+    { name: "IDLE.INTERSIG.MUBI",
+      desc: "Idle inputs are multibit encoded."
+    }
+    { name: "LC_CTRL.INTERSIG.MUBI",
+      desc: "The life cycle control signals are multibit encoded."
+    }
+    { name: "LC_CTRL_CLK_HANDSHAKE.INTERSIG.MUBI",
+      desc: "The life cycle clock req/ack signals are multibit encoded."
+    }
+    { name: "CLK_HANDSHAKE.INTERSIG.MUBI",
+      desc: "The external clock req/ack signals are multibit encoded."
+    }
+    { name: "DIV.INTERSIG.MUBI",
+      desc: "Divider step down request is multibit encoded."
+    }
+    { name: "JITTER.CONFIG.MUBI",
+      desc: "The jitter enable configuration is multibit encoded."
+    }
+    { name: "IDLE.CTR.REDUN",
+      desc: "Idle counter is duplicated."
+    }
+    { name: "MEAS.CONFIG.REGWEN",
+      desc: "The measurement controls protected with regwen."
+    }
+    { name: "CLK_CTRL.CONFIG.REGWEN",
+      desc: "Software controlled clock requests are proteced with regwen."
+    }
+  ]
+
   // Define rstmgr struct package
   inter_signal_list: [
     { struct:  "clkmgr_out",

diff --git a/hw/ip/clkmgr/data/clkmgr.hjson.tpl b/hw/ip/clkmgr/data/clkmgr.hjson.tpl
index ebee659..52045fd 100644
--- a/hw/ip/clkmgr/data/clkmgr.hjson.tpl
+++ b/hw/ip/clkmgr/data/clkmgr.hjson.tpl

@@ -110,6 +110,13 @@
       package: "prim_mubi_pkg",
     },
 
+    { struct:  "mubi4",
+      type:    "uni",
+      name:    "div_step_down_req",
+      act:     "rcv",
+      package: "prim_mubi_pkg",
+    },
+
     { struct:  "lc_tx",
       type:    "uni",
       name:    "lc_clk_byp_req",
@@ -166,6 +173,9 @@
     { name: "MEAS.CLK.BKGN_CHK",
       desc: "Background check for clock frequency."
     },
+    { name: "IDLE.INTERSIG.MUBI",
+      desc: "Idle inputs are multibit encoded."
+    }
     { name: "LC_CTRL.INTERSIG.MUBI",
       desc: "The life cycle control signals are multibit encoded."
     }
@@ -175,9 +185,15 @@
     { name: "CLK_HANDSHAKE.INTERSIG.MUBI",
       desc: "The external clock req/ack signals are multibit encoded."
     }
+    { name: "DIV.INTERSIG.MUBI",
+      desc: "Divider step down request is multibit encoded."
+    }
     { name: "JITTER.CONFIG.MUBI",
       desc: "The jitter enable configuration is multibit encoded."
     }
+    { name: "IDLE.CTR.REDUN",
+      desc: "Idle counter is duplicated."
+    }
     { name: "MEAS.CONFIG.REGWEN",
       desc: "The measurement controls protected with regwen."
     }

diff --git a/hw/ip/clkmgr/data/clkmgr.sv.tpl b/hw/ip/clkmgr/data/clkmgr.sv.tpl
index a633a67..c9e0349 100644
--- a/hw/ip/clkmgr/data/clkmgr.sv.tpl
+++ b/hw/ip/clkmgr/data/clkmgr.sv.tpl

@@ -53,6 +53,7 @@
   input prim_mubi_pkg::mubi4_t scanmode_i,
 
   // idle hints
+  // SEC_CM: IDLE.INTERSIG.MUBI
   input prim_mubi_pkg::mubi4_t [${len(typed_clocks.hint_clks)-1}:0] idle_i,
 
   // life cycle state output
@@ -72,9 +73,13 @@
   input mubi4_t all_clk_byp_ack_i,
   output mubi4_t hi_speed_sel_o,
 
-  // jittery enable
+  // jittery enable to ast
   output mubi4_t jitter_en_o,
 
+  // external indication for whether dividers should be stepped down
+  // SEC_CM: DIV.INTERSIG.MUBI
+  input mubi4_t div_step_down_req_i,
+
   // clock gated indications going to alert handlers
   output clkmgr_cg_en_t cg_en_o,
 
@@ -94,7 +99,6 @@
   // Divided clocks
   ////////////////////////////////////////////////////
 
-  mubi4_t step_down_req;
   logic [${len(clocks.derived_srcs)-1}:0] step_down_acks;
 
 % for src_name in clocks.derived_srcs:
@@ -111,7 +115,7 @@
   ) u_${src_name}_step_down_req_sync (
     .clk_i(clk_${src_name}_i),
     .rst_ni(rst_${src_name}_ni),
-    .mubi_i(step_down_req),
+    .mubi_i(div_step_down_req_i),
     .mubi_o(${src_name}_step_down_req)
   );
 
@@ -224,14 +228,15 @@
     .lc_clk_byp_req_i,
     .lc_clk_byp_ack_o,
     .byp_req_i(mubi4_t'(reg2hw.extclk_ctrl.sel.q)),
+    .hi_speed_sel_i(mubi4_t'(reg2hw.extclk_ctrl.hi_speed_sel.q)),
     .all_clk_byp_req_o,
     .all_clk_byp_ack_i,
     .io_clk_byp_req_o,
     .io_clk_byp_ack_i,
+    .hi_speed_sel_o,
 
     // divider step down controls
-    .step_down_acks_i(step_down_acks),
-    .step_down_req_o(step_down_req)
+    .step_down_acks_i(step_down_acks)
   );
 
   ////////////////////////////////////////////////////
@@ -487,9 +492,6 @@
   // SEC_CM: JITTER.CONFIG.MUBI
   assign jitter_en_o = mubi4_t'(reg2hw.jitter_enable.q);
 
-
-  assign hi_speed_sel_o = mubi4_t'(reg2hw.extclk_ctrl.hi_speed_sel.q);
-
   ////////////////////////////////////////////////////
   // Exported clocks
   ////////////////////////////////////////////////////

diff --git a/hw/ip/clkmgr/data/clkmgr_sec_cm_testplan.hjson b/hw/ip/clkmgr/data/clkmgr_sec_cm_testplan.hjson
new file mode 100644
index 0000000..c2be0c2
--- /dev/null
+++ b/hw/ip/clkmgr/data/clkmgr_sec_cm_testplan.hjson

@@ -0,0 +1,99 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Security countermeasures testplan extracted from the IP Hjson using reggen.
+//
+// This testplan is auto-generated only the first time it is created. This is
+// because this testplan needs to be hand-editable. It is possible that these
+// testpoints can go out of date if the spec is updated with new
+// countermeasures. When `reggen` is invoked when this testplan already exists,
+// It checks if the list of testpoints is up-to-date and enforces the user to
+// make further manual updates.
+//
+// These countermeasures and their descriptions can be found here:
+// .../clkmgr/data/clkmgr.hjson
+//
+// It is possible that the testing of some of these countermeasures may already
+// be covered as a testpoint in a different testplan. This duplication is ok -
+// the test would have likely already been developed. We simply map those tests
+// to the testpoints below using the `tests` key.
+//
+// Please ensure that this testplan is imported in:
+// .../clkmgr/data/clkmgr_testplan.hjson
+{
+  testpoints: [
+    {
+      name: sec_cm_bus_integrity
+      desc: "Verify the countermeasure(s) BUS.INTEGRITY."
+      milestone: V2S
+      tests: []
+    }
+    {
+      name: sec_cm_timeout_clk_bkgn_chk
+      desc: "Verify the countermeasure(s) TIMEOUT.CLK.BKGN_CHK."
+      milestone: V2S
+      tests: []
+    }
+    {
+      name: sec_cm_meas_clk_bkgn_chk
+      desc: "Verify the countermeasure(s) MEAS.CLK.BKGN_CHK."
+      milestone: V2S
+      tests: []
+    }
+    {
+      name: sec_cm_idle_intersig_mubi
+      desc: "Verify the countermeasure(s) IDLE.INTERSIG.MUBI."
+      milestone: V2S
+      tests: []
+    }
+    {
+      name: sec_cm_lc_ctrl_intersig_mubi
+      desc: "Verify the countermeasure(s) LC_CTRL.INTERSIG.MUBI."
+      milestone: V2S
+      tests: []
+    }
+    {
+      name: sec_cm_lc_ctrl_clk_handshake_intersig_mubi
+      desc: "Verify the countermeasure(s) LC_CTRL_CLK_HANDSHAKE.INTERSIG.MUBI."
+      milestone: V2S
+      tests: []
+    }
+    {
+      name: sec_cm_clk_handshake_intersig_mubi
+      desc: "Verify the countermeasure(s) CLK_HANDSHAKE.INTERSIG.MUBI."
+      milestone: V2S
+      tests: []
+    }
+    {
+      name: sec_cm_div_intersig_mubi
+      desc: "Verify the countermeasure(s) DIV.INTERSIG.MUBI."
+      milestone: V2S
+      tests: []
+    }
+    {
+      name: sec_cm_jitter_config_mubi
+      desc: "Verify the countermeasure(s) JITTER.CONFIG.MUBI."
+      milestone: V2S
+      tests: []
+    }
+    {
+      name: sec_cm_idle_ctr_redun
+      desc: "Verify the countermeasure(s) IDLE.CTR.REDUN."
+      milestone: V2S
+      tests: []
+    }
+    {
+      name: sec_cm_meas_config_regwen
+      desc: "Verify the countermeasure(s) MEAS.CONFIG.REGWEN."
+      milestone: V2S
+      tests: []
+    }
+    {
+      name: sec_cm_clk_ctrl_config_regwen
+      desc: "Verify the countermeasure(s) CLK_CTRL.CONFIG.REGWEN."
+      milestone: V2S
+      tests: []
+    }
+  ]
+}

diff --git a/hw/ip/clkmgr/doc/_index.md b/hw/ip/clkmgr/doc/_index.md
index 88b470c..0f96920 100644
--- a/hw/ip/clkmgr/doc/_index.md
+++ b/hw/ip/clkmgr/doc/_index.md

@@ -65,8 +65,8 @@
 For this group software can only express its intent to shut-off, and does not have full control over the final state.
 This intent is indicated with a register in the clock manager register file, see {{< regref "CLK_HINTS" >}}.
 
-Even when the hint is set, the `Idle` does not directly manipulate the clock.  When an idle indicaiton is received, the `clkmgr` counts for a period of 10 local clocks to ensure
-the idle was not an accidental or malicious glitch.
+Even when the hint is set, the `Idle` does not directly manipulate the clock.
+When an idle indication is received, the `clkmgr` counts for a period of 10 local clocks to ensure the idle was not a glitch.
 
 Wait-for-interrupt based control is already a software hint, it can thus be applied to this group with the same `Idle` requirement.
 

diff --git a/hw/ip/clkmgr/dv/env/clkmgr_env_pkg.sv b/hw/ip/clkmgr/dv/env/clkmgr_env_pkg.sv
index ffc833a..4976049 100644
--- a/hw/ip/clkmgr/dv/env/clkmgr_env_pkg.sv
+++ b/hw/ip/clkmgr/dv/env/clkmgr_env_pkg.sv

@@ -34,7 +34,7 @@
 
   typedef logic [NUM_PERI-1:0] peri_enables_t;
   typedef mubi4_t [NUM_TRANS-1:0] hintables_t;
-  parameter mubi4_t [NUM_TRANS-1:0] IdleAllBusy = {NUM_TRANS{prim_mubi_pkg::MuBi4False}};
+  parameter hintables_t IdleAllBusy = {NUM_TRANS{prim_mubi_pkg::MuBi4False}};
 
   parameter int MainClkHz = 100_000_000;
   parameter int IoClkHz = 96_000_000;

diff --git a/hw/ip/clkmgr/dv/sva/clkmgr_bind.sv b/hw/ip/clkmgr/dv/sva/clkmgr_bind.sv
index 62bfcd5..2458304 100644
--- a/hw/ip/clkmgr/dv/sva/clkmgr_bind.sv
+++ b/hw/ip/clkmgr/dv/sva/clkmgr_bind.sv

@@ -92,7 +92,7 @@
     .clk(clocks_o.clk_main_powerup),
     .rst_n(rst_main_ni),
     .ip_clk_en(pwr_i.main_ip_clk_en),
-    .sw_clk_en(reg2hw.clk_hints.clk_main_otbn_hint.q || !idle_i[4]),
+    .sw_clk_en(reg2hw.clk_hints.clk_main_otbn_hint.q || !idle_i[3]),
     .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True),
     .gated_clk(clocks_o.clk_main_otbn)
   );

diff --git a/hw/ip/clkmgr/dv/tb.sv b/hw/ip/clkmgr/dv/tb.sv
index 3abf78f..ab8d1e1 100644
--- a/hw/ip/clkmgr/dv/tb.sv
+++ b/hw/ip/clkmgr/dv/tb.sv

@@ -107,6 +107,8 @@
     .io_clk_byp_ack_i (clkmgr_if.io_clk_byp_ack),
     .lc_clk_byp_req_i (clkmgr_if.lc_clk_byp_req),
     .lc_clk_byp_ack_o (clkmgr_if.lc_clk_byp_ack),
+    // TODO: The new external step down signal must be verified
+    .div_step_down_req_i (prim_mubi_pkg::MuBi4False),
 
     .cg_en_o(),
 

diff --git a/hw/ip/clkmgr/rtl/clkmgr_byp.sv b/hw/ip/clkmgr/rtl/clkmgr_byp.sv
index 39cab68..d8bc6ed5 100644
--- a/hw/ip/clkmgr/rtl/clkmgr_byp.sv
+++ b/hw/ip/clkmgr/rtl/clkmgr_byp.sv

@@ -19,22 +19,21 @@
   output lc_tx_t          lc_clk_byp_ack_o,
   // interaction with software
   input  mubi4_t          byp_req_i,
+  input  mubi4_t          hi_speed_sel_i,
   // interaction with ast
   output mubi4_t          all_clk_byp_req_o,
   input  mubi4_t          all_clk_byp_ack_i,
   output mubi4_t          io_clk_byp_req_o,
   input  mubi4_t          io_clk_byp_ack_i,
+  output mubi4_t          hi_speed_sel_o,
   // interaction with dividers
-  input  [NumDivClks-1:0] step_down_acks_i,
-  output mubi4_t          step_down_req_o
+  input  [NumDivClks-1:0] step_down_acks_i
 );
 
   import prim_mubi_pkg::MuBi4Width;
   import prim_mubi_pkg::MuBi4True;
   import prim_mubi_pkg::MuBi4False;
   import prim_mubi_pkg::mubi4_and_hi;
-  import prim_mubi_pkg::mubi4_or_hi;
-  import prim_mubi_pkg::mubi4_test_false_strict;
   import prim_mubi_pkg::mubi4_test_true_strict;
 
   // synchornize incoming lc signals
@@ -97,10 +96,12 @@
   );
 
   // only ack the lc_ctrl if it made a request.
+  mubi4_t io_clk_byp_ack;
   prim_lc_sender u_send (
    .clk_i,
    .rst_ni,
-   .lc_en_i(&step_down_acks_sync ? lc_clk_byp_req[LcClkBypReqLcAck] : lc_ctrl_pkg::Off),
+   .lc_en_i(&step_down_acks_sync & mubi4_test_true_strict(io_clk_byp_ack) ?
+            lc_clk_byp_req[LcClkBypReqLcAck] : lc_ctrl_pkg::Off),
    .lc_en_o(lc_clk_byp_ack_o)
   );
 
@@ -123,11 +124,11 @@
   );
 
   // divider step down handling
-  mubi4_t io_clk_byp_ack;
-  mubi4_t all_clk_byp_ack;
+  mubi4_t unused_all_clk_byp_ack;
 
   prim_mubi4_sync #(
     .AsyncOn(1),
+    .StabilityCheck(1),
     .ResetValue(MuBi4False)
   ) u_io_ack_sync (
     .clk_i,
@@ -136,58 +137,29 @@
     .mubi_o({io_clk_byp_ack})
   );
 
+  // since div_step_down_req is now directly fed externally, there is no longer
+  // a use for the related 'ack' signals
   prim_mubi4_sync #(
     .AsyncOn(1),
+    .StabilityCheck(1),
     .ResetValue(MuBi4False)
   ) u_all_ack_sync (
     .clk_i,
     .rst_ni,
     .mubi_i(all_clk_byp_ack_i),
-    .mubi_o({all_clk_byp_ack})
+    .mubi_o({unused_all_clk_byp_ack})
   );
 
-  // create individual requests
-  mubi4_t lc_step_down_req;
-  assign lc_step_down_req = mubi4_and_hi(io_clk_byp_req_o, io_clk_byp_ack);
-
-  // When requesting a switch, the low speed indication is used to determine step down.
-  // Once switched, the low speed indication is not looked at again until software request
-  // is de-asserted.
-  mubi4_t sw_step_down_en;
-  mubi4_t sw_step_down_req;
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      sw_step_down_en <= MuBi4False;
-    end else if (mubi4_test_true_strict(all_clk_byp_req_o) &&
-                 mubi4_test_true_strict(all_clk_byp_ack)) begin
-      sw_step_down_en <= MuBi4True;
-    end else if (
-      mubi4_test_true_strict(sw_step_down_en) &&
-      mubi4_test_false_strict(all_clk_byp_req_o) &&
-      mubi4_test_false_strict(all_clk_byp_ack)) begin
-      sw_step_down_en <= MuBi4False;
-    end
-  end
-  // when in external clock state, allow low speed select to directly control
-  // clock divider.
-
-  // TODO
-  // This will be updated to a different signaling, see #10890
-  assign sw_step_down_req = sw_step_down_en;
-
-  // combine requests
-  // mubi4_or_hi is not directly used in the always block because it causes confusion
-  // with the lint tool and makes it think `rst_ni` is not appropriately used for some
-  // reason.
-  mubi4_t step_down_req_d;
-  assign step_down_req_d = mubi4_or_hi(lc_step_down_req, sw_step_down_req);
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      step_down_req_o <= MuBi4False;
-    end else begin
-      step_down_req_o <= step_down_req_d;
-    end
-  end
-
+  // the software high speed select is valid only when software requests clock
+  // bypass
+  prim_mubi4_sender #(
+    .AsyncOn(1),
+    .ResetValue(MuBi4True)
+  ) u_hi_speed_sel (
+    .clk_i,
+    .rst_ni,
+    .mubi_i(mubi4_and_hi(all_clk_byp_req_d, hi_speed_sel_i)),
+    .mubi_o(hi_speed_sel_o)
+  );
 
 endmodule // clkmgr_byp

diff --git a/hw/ip/clkmgr/rtl/clkmgr_trans.sv b/hw/ip/clkmgr/rtl/clkmgr_trans.sv
index ccfab84..0201f9c 100644
--- a/hw/ip/clkmgr/rtl/clkmgr_trans.sv
+++ b/hw/ip/clkmgr/rtl/clkmgr_trans.sv

@@ -46,6 +46,7 @@
     .q_o(sw_hint_synced)
   );
 
+  // SEC_CM: IDLE.CTR.REDUN
   prim_count #(
     .Width(IdleCntWidth),
     .OutSelDnCnt('0),

diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index d5eb27a..2ce7efe 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson

@@ -3185,6 +3185,20 @@
           index: -1
         }
         {
+          name: div_step_down_req
+          struct: mubi4
+          package: prim_mubi_pkg
+          type: uni
+          act: rcv
+          width: 1
+          inst_name: clkmgr_aon
+          default: ""
+          external: true
+          top_signame: div_step_down_req
+          conn_type: false
+          index: -1
+        }
+        {
           name: lc_clk_byp_req
           struct: lc_tx
           package: lc_ctrl_pkg
@@ -8111,6 +8125,7 @@
       clkmgr_aon.all_clk_byp_req: all_clk_byp_req
       clkmgr_aon.all_clk_byp_ack: all_clk_byp_ack
       clkmgr_aon.hi_speed_sel: hi_speed_sel
+      clkmgr_aon.div_step_down_req: div_step_down_req
       flash_ctrl.flash_alert: flash_alert
       flash_ctrl.flash_bist_enable: flash_bist_enable
       flash_ctrl.flash_power_down_h: flash_power_down_h
@@ -16062,6 +16077,20 @@
         index: -1
       }
       {
+        name: div_step_down_req
+        struct: mubi4
+        package: prim_mubi_pkg
+        type: uni
+        act: rcv
+        width: 1
+        inst_name: clkmgr_aon
+        default: ""
+        external: true
+        top_signame: div_step_down_req
+        conn_type: false
+        index: -1
+      }
+      {
         name: lc_clk_byp_req
         struct: lc_tx
         package: lc_ctrl_pkg
@@ -19295,6 +19324,18 @@
         netname: hi_speed_sel
       }
       {
+        package: prim_mubi_pkg
+        struct: mubi4
+        signame: div_step_down_req_i
+        width: 1
+        type: uni
+        default: ""
+        direction: in
+        conn_type: false
+        index: -1
+        netname: div_step_down_req
+      }
+      {
         package: ast_pkg
         struct: ast_dif
         signame: flash_alert_o

diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index 493965c..6f55ae4 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson

@@ -1021,6 +1021,7 @@
         'clkmgr_aon.all_clk_byp_req'      : 'all_clk_byp_req',
         'clkmgr_aon.all_clk_byp_ack'      : 'all_clk_byp_ack',
         'clkmgr_aon.hi_speed_sel'         : 'hi_speed_sel',
+        'clkmgr_aon.div_step_down_req'    : 'div_step_down_req',
         'flash_ctrl.flash_alert'          : 'flash_alert',
         'flash_ctrl.flash_bist_enable'    : 'flash_bist_enable',
         'flash_ctrl.flash_power_down_h'   : 'flash_power_down_h',

diff --git a/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson b/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson
index 67b6317..cbcf2a8 100644
--- a/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson
+++ b/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson

@@ -116,6 +116,13 @@
       package: "prim_mubi_pkg",
     },
 
+    { struct:  "mubi4",
+      type:    "uni",
+      name:    "div_step_down_req",
+      act:     "rcv",
+      package: "prim_mubi_pkg",
+    },
+
     { struct:  "lc_tx",
       type:    "uni",
       name:    "lc_clk_byp_req",
@@ -164,6 +171,9 @@
     { name: "MEAS.CLK.BKGN_CHK",
       desc: "Background check for clock frequency."
     },
+    { name: "IDLE.INTERSIG.MUBI",
+      desc: "Idle inputs are multibit encoded."
+    }
     { name: "LC_CTRL.INTERSIG.MUBI",
       desc: "The life cycle control signals are multibit encoded."
     }
@@ -173,9 +183,15 @@
     { name: "CLK_HANDSHAKE.INTERSIG.MUBI",
       desc: "The external clock req/ack signals are multibit encoded."
     }
+    { name: "DIV.INTERSIG.MUBI",
+      desc: "Divider step down request is multibit encoded."
+    }
     { name: "JITTER.CONFIG.MUBI",
       desc: "The jitter enable configuration is multibit encoded."
     }
+    { name: "IDLE.CTR.REDUN",
+      desc: "Idle counter is duplicated."
+    }
     { name: "MEAS.CONFIG.REGWEN",
       desc: "The measurement controls protected with regwen."
     }

diff --git a/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr_sec_cm_testplan.hjson b/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr_sec_cm_testplan.hjson
index a7394b4..c2be0c2 100644
--- a/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr_sec_cm_testplan.hjson
+++ b/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr_sec_cm_testplan.hjson

@@ -42,6 +42,12 @@
       tests: []
     }
     {
+      name: sec_cm_idle_intersig_mubi
+      desc: "Verify the countermeasure(s) IDLE.INTERSIG.MUBI."
+      milestone: V2S
+      tests: []
+    }
+    {
       name: sec_cm_lc_ctrl_intersig_mubi
       desc: "Verify the countermeasure(s) LC_CTRL.INTERSIG.MUBI."
       milestone: V2S
@@ -60,12 +66,24 @@
       tests: []
     }
     {
+      name: sec_cm_div_intersig_mubi
+      desc: "Verify the countermeasure(s) DIV.INTERSIG.MUBI."
+      milestone: V2S
+      tests: []
+    }
+    {
       name: sec_cm_jitter_config_mubi
       desc: "Verify the countermeasure(s) JITTER.CONFIG.MUBI."
       milestone: V2S
       tests: []
     }
     {
+      name: sec_cm_idle_ctr_redun
+      desc: "Verify the countermeasure(s) IDLE.CTR.REDUN."
+      milestone: V2S
+      tests: []
+    }
+    {
       name: sec_cm_meas_config_regwen
       desc: "Verify the countermeasure(s) MEAS.CONFIG.REGWEN."
       milestone: V2S

diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
index 60135a2..6f03363 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv

@@ -59,6 +59,7 @@
   input prim_mubi_pkg::mubi4_t scanmode_i,
 
   // idle hints
+  // SEC_CM: IDLE.INTERSIG.MUBI
   input prim_mubi_pkg::mubi4_t [3:0] idle_i,
 
   // life cycle state output
@@ -78,9 +79,13 @@
   input mubi4_t all_clk_byp_ack_i,
   output mubi4_t hi_speed_sel_o,
 
-  // jittery enable
+  // jittery enable to ast
   output mubi4_t jitter_en_o,
 
+  // external indication for whether dividers should be stepped down
+  // SEC_CM: DIV.INTERSIG.MUBI
+  input mubi4_t div_step_down_req_i,
+
   // clock gated indications going to alert handlers
   output clkmgr_cg_en_t cg_en_o,
 
@@ -97,7 +102,6 @@
   // Divided clocks
   ////////////////////////////////////////////////////
 
-  mubi4_t step_down_req;
   logic [1:0] step_down_acks;
 
   logic clk_io_div2_i;
@@ -112,7 +116,7 @@
   ) u_io_step_down_req_sync (
     .clk_i(clk_io_i),
     .rst_ni(rst_io_ni),
-    .mubi_i(step_down_req),
+    .mubi_i(div_step_down_req_i),
     .mubi_o(io_step_down_req)
   );
 
@@ -261,14 +265,15 @@
     .lc_clk_byp_req_i,
     .lc_clk_byp_ack_o,
     .byp_req_i(mubi4_t'(reg2hw.extclk_ctrl.sel.q)),
+    .hi_speed_sel_i(mubi4_t'(reg2hw.extclk_ctrl.hi_speed_sel.q)),
     .all_clk_byp_req_o,
     .all_clk_byp_ack_i,
     .io_clk_byp_req_o,
     .io_clk_byp_ack_i,
+    .hi_speed_sel_o,
 
     // divider step down controls
-    .step_down_acks_i(step_down_acks),
-    .step_down_req_o(step_down_req)
+    .step_down_acks_i(step_down_acks)
   );
 
   ////////////////////////////////////////////////////
@@ -1156,9 +1161,6 @@
   // SEC_CM: JITTER.CONFIG.MUBI
   assign jitter_en_o = mubi4_t'(reg2hw.jitter_enable.q);
 
-
-  assign hi_speed_sel_o = mubi4_t'(reg2hw.extclk_ctrl.hi_speed_sel.q);
-
   ////////////////////////////////////////////////////
   // Exported clocks
   ////////////////////////////////////////////////////

diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
index e912796..b659e3e 100644
--- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
+++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv

@@ -739,6 +739,7 @@
   prim_mubi_pkg::mubi4_t all_clk_byp_req;
   prim_mubi_pkg::mubi4_t all_clk_byp_ack;
   prim_mubi_pkg::mubi4_t hi_speed_sel;
+  prim_mubi_pkg::mubi4_t div_step_down_req;
 
   // DFT connections
   logic scan_en;
@@ -917,7 +918,7 @@
     .clk_src_io_en_i       ( base_ast_pwr.io_clk_en ),
     .clk_src_io_o          ( ast_base_clks.clk_io ),
     .clk_src_io_val_o      ( ast_base_pwr.io_clk_val ),
-    .clk_src_io_48m_o      (  ),
+    .clk_src_io_48m_o      ( div_step_down_req ),
     // usb source clock
     .usb_ref_pulse_i       ( usb_ref_pulse ),
     .usb_ref_val_i         ( usb_ref_val ),
@@ -1120,6 +1121,7 @@
     .all_clk_byp_req_o            ( all_clk_byp_req            ),
     .all_clk_byp_ack_i            ( all_clk_byp_ack            ),
     .hi_speed_sel_o               ( hi_speed_sel               ),
+    .div_step_down_req_i          ( div_step_down_req          ),
     .ast2pinmux_i                 ( ast2pinmux                 ),
     .ast_init_done_i              ( ast_init_done              ),
 

diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv
index 1dc783a..bf1bc2b 100644
--- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv
+++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv

@@ -693,6 +693,7 @@
   prim_mubi_pkg::mubi4_t all_clk_byp_req;
   prim_mubi_pkg::mubi4_t all_clk_byp_ack;
   prim_mubi_pkg::mubi4_t hi_speed_sel;
+  prim_mubi_pkg::mubi4_t div_step_down_req;
 
   // DFT connections
   logic scan_en;
@@ -871,7 +872,7 @@
     .clk_src_io_en_i       ( base_ast_pwr.io_clk_en ),
     .clk_src_io_o          ( ast_base_clks.clk_io ),
     .clk_src_io_val_o      ( ast_base_pwr.io_clk_val ),
-    .clk_src_io_48m_o      (  ),
+    .clk_src_io_48m_o      ( div_step_down_req ),
     // usb source clock
     .usb_ref_pulse_i       ( usb_ref_pulse ),
     .usb_ref_val_i         ( usb_ref_val ),
@@ -1007,7 +1008,7 @@
     .all_clk_byp_req_o            ( all_clk_byp_req       ),
     .all_clk_byp_ack_i            ( all_clk_byp_ack       ),
     .hi_speed_sel_o               ( hi_speed_sel          ),
-
+    .div_step_down_req_i          ( div_step_down_req     ),
     .ast_tl_req_o                 ( base_ast_bus               ),
     .ast_tl_rsp_i                 ( ast_base_bus               ),
     .adc_req_o                    ( adc_req                    ),

diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
index 46d7deb..c567504 100644
--- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
+++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv

@@ -712,6 +712,7 @@
   prim_mubi_pkg::mubi4_t all_clk_byp_req;
   prim_mubi_pkg::mubi4_t all_clk_byp_ack;
   prim_mubi_pkg::mubi4_t hi_speed_sel;
+  prim_mubi_pkg::mubi4_t div_step_down_req;
 
   // DFT connections
   logic scan_en;
@@ -890,7 +891,7 @@
     .clk_src_io_en_i       ( base_ast_pwr.io_clk_en ),
     .clk_src_io_o          ( ast_base_clks.clk_io ),
     .clk_src_io_val_o      ( ast_base_pwr.io_clk_val ),
-    .clk_src_io_48m_o      (  ),
+    .clk_src_io_48m_o      ( div_step_down_req ),
     // usb source clock
     .usb_ref_pulse_i       ( usb_ref_pulse ),
     .usb_ref_val_i         ( usb_ref_val ),
@@ -1025,7 +1026,7 @@
     .all_clk_byp_req_o            ( all_clk_byp_req       ),
     .all_clk_byp_ack_i            ( all_clk_byp_ack       ),
     .hi_speed_sel_o               ( hi_speed_sel          ),
-
+    .div_step_down_req_i          ( div_step_down_req     ),
     .ast_tl_req_o                 ( base_ast_bus               ),
     .ast_tl_rsp_i                 ( ast_base_bus               ),
     .adc_req_o                    ( adc_req                    ),

diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index e5593ea..40fc6b7 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv

@@ -133,6 +133,7 @@
   output prim_mubi_pkg::mubi4_t       all_clk_byp_req_o,
   input  prim_mubi_pkg::mubi4_t       all_clk_byp_ack_i,
   output prim_mubi_pkg::mubi4_t       hi_speed_sel_o,
+  input  prim_mubi_pkg::mubi4_t       div_step_down_req_i,
   output ast_pkg::ast_dif_t       flash_alert_o,
   input  prim_mubi_pkg::mubi4_t       flash_bist_enable_i,
   input  logic       flash_power_down_h_i,
@@ -1755,6 +1756,7 @@
       .all_clk_byp_req_o(all_clk_byp_req_o),
       .all_clk_byp_ack_i(all_clk_byp_ack_i),
       .hi_speed_sel_o(hi_speed_sel_o),
+      .div_step_down_req_i(div_step_down_req_i),
       .lc_clk_byp_req_i(lc_ctrl_lc_clk_byp_req),
       .lc_clk_byp_ack_o(lc_ctrl_lc_clk_byp_ack),
       .jitter_en_o(clk_main_jitter_en_o),

diff --git a/hw/top_earlgrey/rtl/chip_earlgrey_verilator.sv b/hw/top_earlgrey/rtl/chip_earlgrey_verilator.sv
index 1da5cb1..d468025 100644
--- a/hw/top_earlgrey/rtl/chip_earlgrey_verilator.sv
+++ b/hw/top_earlgrey/rtl/chip_earlgrey_verilator.sv

@@ -221,9 +221,9 @@
   prim_mubi_pkg::mubi4_t all_clk_byp_ack;
   prim_mubi_pkg::mubi4_t io_clk_byp_req;
   prim_mubi_pkg::mubi4_t io_clk_byp_ack;
+  prim_mubi_pkg::mubi4_t div_step_down_req;
   logic hi_speed_sel;
 
-
   // DFT connections
   logic scan_en;
   lc_ctrl_pkg::lc_tx_t dft_en;
@@ -334,7 +334,7 @@
     .clk_src_io_en_i       ( base_ast_pwr.io_clk_en ),
     .clk_src_io_o          ( ast_base_clks.clk_io ),
     .clk_src_io_val_o      ( ast_base_pwr.io_clk_val ),
-    .clk_src_io_48m_o      (  ),
+    .clk_src_io_48m_o      ( div_step_down_req ),
     // usb source clock
     .usb_ref_pulse_i       ( usb_ref_pulse ),
     .usb_ref_val_i         ( usb_ref_val ),
@@ -462,6 +462,7 @@
     .io_clk_byp_req_o             ( io_clk_byp_req             ),
     .io_clk_byp_ack_i             ( io_clk_byp_ack             ),
     .hi_speed_sel_o               ( hi_speed_sel               ),
+    .div_step_down_req_i          ( div_step_down_req          ),
     .ast2pinmux_i                 ( ast2pinmux                 ),
     .ast_init_done_i              ( ast_init_done              ),
 

diff --git a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
index 7b6b908..1fe6aa8 100644
--- a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
+++ b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson

@@ -649,6 +649,7 @@
         'ast.rom_cfg'                  : 'rom_cfg',
         'clkmgr_aon.jitter_en'         : 'clk_main_jitter_en',
         'clkmgr_aon.hi_speed_sel'      : 'hi_speed_sel',
+        'clkmgr_aon.div_step_down_req' : 'div_step_down_req',
         'clkmgr_aon.all_clk_byp_req'   : 'all_clk_byp_req',
         'clkmgr_aon.all_clk_byp_ack'   : 'all_clk_byp_ack',
         'clkmgr_aon.io_clk_byp_req'    : 'io_clk_byp_req',

diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl
index edf1e24..c5fa7c1 100644
--- a/util/topgen/templates/chiplevel.sv.tpl
+++ b/util/topgen/templates/chiplevel.sv.tpl

@@ -635,6 +635,7 @@
   prim_mubi_pkg::mubi4_t all_clk_byp_req;
   prim_mubi_pkg::mubi4_t all_clk_byp_ack;
   prim_mubi_pkg::mubi4_t hi_speed_sel;
+  prim_mubi_pkg::mubi4_t div_step_down_req;
 
   // DFT connections
   logic scan_en;
@@ -862,7 +863,7 @@
     .clk_src_io_en_i       ( base_ast_pwr.io_clk_en ),
     .clk_src_io_o          ( ast_base_clks.clk_io ),
     .clk_src_io_val_o      ( ast_base_pwr.io_clk_val ),
-    .clk_src_io_48m_o      (  ),
+    .clk_src_io_48m_o      ( div_step_down_req ),
     // usb source clock
     .usb_ref_pulse_i       ( usb_ref_pulse ),
     .usb_ref_val_i         ( usb_ref_val ),
@@ -1069,6 +1070,7 @@
     .all_clk_byp_req_o            ( all_clk_byp_req            ),
     .all_clk_byp_ack_i            ( all_clk_byp_ack            ),
     .hi_speed_sel_o               ( hi_speed_sel               ),
+    .div_step_down_req_i          ( div_step_down_req          ),
     .ast2pinmux_i                 ( ast2pinmux                 ),
     .ast_init_done_i              ( ast_init_done              ),
 
@@ -1222,7 +1224,7 @@
     .all_clk_byp_req_o            ( all_clk_byp_req       ),
     .all_clk_byp_ack_i            ( all_clk_byp_ack       ),
     .hi_speed_sel_o               ( hi_speed_sel          ),
-
+    .div_step_down_req_i          ( div_step_down_req     ),
 % if target["name"] != "cw305":
     .ast_tl_req_o                 ( base_ast_bus               ),
     .ast_tl_rsp_i                 ( ast_base_bus               ),