hw/syn/tools/dc/run-syn.tcl

# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
#
# Simple tcl script for DC to do some wire-load-model-based test syntheses.

#####################
##  PREPARE FLOW   ##
#####################

# tool setup
source [getenv "LIB_SETUP_SCRIPT"]

# paths
set WORKLIB  "WORK"
set REPDIR   "REPORTS"
set DDCDIR   "DDC"
set VLOGDIR  "NETLISTS"

exec mkdir -p ${REPDIR} ${DDCDIR} ${VLOGDIR} ${WORKLIB}

# define work lib path
define_design_lib WORK -path $WORKLIB

#######################
##  DESIGN SOURCES  ###
#######################

# just compile the "core" toplevel at the moment
# might want to switch to top_earlgrey_asic later on (with pads)
set TOP_ENTITY [getenv "TOP_ENTITY"]

# read source list generated by fusesoc
set fp [open [ls "*.scr"] r]
set file_data [read $fp]
close $fp
set data [split $file_data "\n"]

# this TECH_LIB_SEL selects the appropriate technology by defining
# PRIM_DEFAULT_IMPL=prim_pkg::Impl<tech identifier>
# TECH_LIB_SEL is set inside the library setup script
set DEFINE "PRIM_DEFAULT_IMPL=${PRIM_DEFAULT_IMPL} "
# go through fusesoc file list and separate +defines from actual source files
set SRC {}
foreach item $data {
  if {[string range $item 0 7] == "+define+"}  {
    set DEFINE "${DEFINE}[string range $item 8 end] "
  } elseif {[string range $item 0 7] == "+incdir+"}  {
    lappend search_path "[string range $item 8 end]"
  } else {
    lappend SRC $item
  }
}

# additional parameters
set PARAMS ""

###########################
##   ELABORATE DESIGN    ##
###########################

# delete previous designs.
remove_design -designs
sh rm -rf $WORKLIB/*

analyze -define ${DEFINE} -format sv ${SRC}
elaborate  ${TOP_ENTITY} -parameters ${PARAMS}
link > "${REPDIR}/${TOP_ENTITY}_link.rpt"

write_file -format ddc -hierarchy -output "${DDCDIR}/${TOP_ENTITY}_elab.ddc"
write_file -format verilog -hierarchy -output "${DDCDIR}/${TOP_ENTITY}_elab.v"

#############################
##   CLOCK GATING SETUP    ##
#############################

# be more specific if defaults do not suffice
# set_clock_gating_style -num_stages 1                   \
#                        -positive_edge_logic integrated \
#                        -control_point before           \
#                        -control_signal scan_enable

###########################
##   APPLY CONSTRAINTS   ##
###########################

source constraints.sdc

# If hold time should be fixed
# set_fix_hold ${CLK_PIN}

######################
##    MAP DESIGN    ##
######################

# TODO: we may have to disable a couple of optimizations in order
# to prevent the tool from optimizing away dummy logic or logic from blocks
# that are only half-finished

# preserve hierarchy for reports
compile_ultra -gate_clock -scan -no_autoungroup

#################
##   REPORTS   ##
#################

report_timing      -nosplit -nworst 100 > "${REPDIR}/${TOP_ENTITY}_timing.rpt"
report_timing      -nosplit -nworst 1000 -input -net -trans -cap > "${REPDIR}/${TOP_ENTITY}_timing_long.rpt"
report_area  -hier -nosplit             > "${REPDIR}/${TOP_ENTITY}_area.rpt"
report_power -hier -nosplit             > "${REPDIR}/${TOP_ENTITY}_power.rpt"
report_constraints -all_violators       > "${REPDIR}/${TOP_ENTITY}_constraints.rpt"

#################
##   NETLIST   ##
#################

# change_names -rules verilog -hierarchy
# define_name_rules fixbackslashes -allowed "A-Za-z0-9_" -first_restricted "\\" -remove_chars
# change_names -rule fixbackslashes -h
write_file -format ddc     -hierarchy -output "${DDCDIR}/${TOP_ENTITY}_mapped.ddc"
write_file -format verilog -hierarchy -output "${VLOGDIR}/${TOP_ENTITY}_mapped.v"

# ##############################
# ##  INCREMENTAL FLATTENING  ##
# ##############################

# compile_ultra -inc

# #################
# ##   REPORTS   ##
# #################

# report_timing      -nosplit -nworst 100 > "${REPDIR}/${TOP_ENTITY}_flat_timing.rpt"
# report_timing      -nosplit -nworst 1000 -input -net -trans -cap > "${REPDIR}/${TOP_ENTITY}_flat_timing_long.rpt"
# report_area  -hier -nosplit             > "${REPDIR}/${TOP_ENTITY}_flat_area.rpt"
# report_power -hier -nosplit             > "${REPDIR}/${TOP_ENTITY}_flat_power.rpt"
# report_constraints -all_violators       > "${REPDIR}/${TOP_ENTITY}_flat_constraints.rpt"

# #################
# ##   NETLIST   ##
# #################

# write_file -format ddc     -hierarchy -output "${DDCDIR}/${TOP_ENTITY}_flat.ddc"
# write_file -format verilog -hierarchy -output "${VLOGDIR}/${TOP_ENTITY}_flat.v"

exit