hw/top_earlgrey/dv/chip_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: chip

  // Top level dut name (sv module).
  dut: top_earlgrey

  // Top level testbench name (sv module).
  tb: tb

  // Default simulator used to sign off.
  tool: vcs

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:chip_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/top_earlgrey/data/chip_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/top_earlgrey/data/top_earlgrey.hjson"

  // Add additional tops for simulation.
  sim_tops: ["-top xbar_main_bind",
             "-top xbar_peri_bind"]

  // Import additional common sim cfg files.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/data/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/data/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/data/tests/mem_tests.hjson",
                "{proj_root}/hw/dv/data/tests/tl_access_tests.hjson",
                // xbar tests
                "{proj_root}/hw/ip/tlul/generic_dv/xbar_tests.hjson"]

  // Override the default vcs_cov_hier flag to supply chip specific coverage hierarchies.
  overrides: [
    {
      name: vcs_cov_hier
      value: "-cm_hier {tool_srcs_dir}/chip_cover.cfg"
    }
  ]

  // Set the vcs_cov_assert_hier to supply the chip specific assertion coverage hierarchies.
  vcs_cov_assert_hier: "-cm_assert_hier {tool_srcs_dir}/chip_assert_cover.cfg"

  // Add these to tool_srcs so that they get copied over.
  tool_srcs: ["{proj_root}/hw/top_earlgrey/dv/cov/chip_cover.cfg",
              "{proj_root}/hw/top_earlgrey/dv/cov/chip_assert_cover.cfg"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 1

  // Default UVM test and seq class name.
  uvm_test: chip_base_test
  uvm_test_seq: chip_sw_base_vseq
  sw_build_device: sim_dv

  // Add default build_opts.
  build_opts: [// Use generic implementations of prim modules.
               "+define+PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric"]

  // Add build modes.
  build_modes: [
    {
      name: en_ibex_tracer
      build_opts: ["+define+RVFI=1"]
    }
  ]

  // Add run modes.
  run_modes: [
    {
      name: stub_cpu
      run_opts: ["+stub_cpu=1"]
    }
    {
      // Append stub cpu mode to csr_tests_mode, run with 20 reseeds.
      name: csr_tests_mode
      en_run_modes: ["stub_cpu"]
      reseed: 20
    }
    {
      // Append stub cpu mode to mem_tests_mode, run with 20 reseeds.
      name: mem_tests_mode
      en_run_modes: ["stub_cpu"]
      reseed: 20
    }
    {
      name: xbar_mode
      run_opts: ["+xbar_mode=1"]
    }
  ]

  // List of test specifications.
  tests: [
    {
      name: chip_uart_tx_rx
      uvm_test_seq: chip_sw_uart_tx_rx_vseq
      sw_test: sw/device/tests/uart_tx_rx_test
    }
    {
      name: chip_aes_test
      uvm_test_seq: chip_sw_base_vseq
      sw_test: sw/device/tests/aes_test
    }
    {
      name: chip_consecutive_irqs_test
      uvm_test_seq: chip_sw_base_vseq
      sw_test: sw/device/tests/consecutive_irqs_test
    }
    {
      name: chip_flash_ctrl_test
      uvm_test_seq: chip_sw_base_vseq
      sw_test: sw/device/tests/flash_ctrl_test
    }
    {
      name: chip_sha256_test
      uvm_test_seq: chip_sw_base_vseq
      sw_test: sw/device/tests/sha256_test
    }
    {
      name: chip_rv_timer_test
      uvm_test_seq: chip_sw_base_vseq
      sw_test: sw/device/tests/rv_timer_test
    }
    {
      name: chip_coremark
      uvm_test_seq: chip_sw_base_vseq
      sw_test: sw/device/benchmarks/coremark/coremark_top_earlgrey
      run_opts: ["+en_uart_logger=1",
                 "+sw_test_timeout_ns=22000000"]
    }
    {
      name: chip_opentitan_tock
      uvm_test_seq: chip_sw_base_vseq
      sw_test: sw/device/tock/prebuilt/opentitan
      sw_test_is_prebuilt: 1
      run_opts: ["+en_uart_logger=1",
                 // TODO #2241: tock reads an uninitialized part of stack, which causes
                 // assertion errors to be thrown. This is a temporary workaround.
                 "+initialize_ram=1",
                 "+sw_test_timeout_ns=50000000"]
    }

    // The test below is added in the included tl_access_tests.hjson.
    // We just need to append the stub_cpu run mode to it.
    {
      name: chip_tl_errors
      en_run_modes: ["stub_cpu"]
    }
  ]

  // List of regressions.
  regressions: [
    {
      name: sanity
      tests: ["chip_uart_tx_rx"]
    }
  ]
}