[clkmgr] External ack readback for external clock switch - when software requests an external clock switch, it can now poll on a status to see when the switch is complete. - fixes #12152 Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/clkmgr/data/clkmgr.hjson.tpl b/hw/ip/clkmgr/data/clkmgr.hjson.tpl index 55a8139..c5e4a96 100644 --- a/hw/ip/clkmgr/data/clkmgr.hjson.tpl +++ b/hw/ip/clkmgr/data/clkmgr.hjson.tpl
@@ -279,6 +279,30 @@ tags: ["excl:CsrAllTests:CsrExclWrite"] }, + { name: "EXTCLK_STATUS", + desc: ''' + Status of requested external clock switch + ''', + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { + bits: "3:0", + name: "ACK", + mubi: true, + desc: ''' + When !!EXTCLK_CTRL.SEL is set to kMultiBitBool4True, this field reflects + whether the clock has been switched the external source. + + kMultiBitBool4True indicates the switch is complete. + kMultiBitBool4False indicates the switch is either not possible or still ongoing. + ''' + resval: "false" + }, + ] + }, + { name: "JITTER_REGWEN", desc: "Jitter write enable", swaccess: "rw0c",
diff --git a/hw/ip/clkmgr/data/clkmgr.sv.tpl b/hw/ip/clkmgr/data/clkmgr.sv.tpl index f19e4db..cb7e52b 100644 --- a/hw/ip/clkmgr/data/clkmgr.sv.tpl +++ b/hw/ip/clkmgr/data/clkmgr.sv.tpl
@@ -238,6 +238,7 @@ .lc_clk_byp_req_i, .lc_clk_byp_ack_o, .byp_req_i(extclk_ctrl_sel), + .byp_ack_o(hw2reg.extclk_status.d), .hi_speed_sel_i(extclk_ctrl_hi_speed_sel), .all_clk_byp_req_o, .all_clk_byp_ack_i,
diff --git a/hw/ip/clkmgr/rtl/clkmgr_byp.sv b/hw/ip/clkmgr/rtl/clkmgr_byp.sv index d8bc6ed5..84aa0c2 100644 --- a/hw/ip/clkmgr/rtl/clkmgr_byp.sv +++ b/hw/ip/clkmgr/rtl/clkmgr_byp.sv
@@ -19,6 +19,7 @@ output lc_tx_t lc_clk_byp_ack_o, // interaction with software input mubi4_t byp_req_i, + output mubi4_t byp_ack_o, input mubi4_t hi_speed_sel_i, // interaction with ast output mubi4_t all_clk_byp_req_o, @@ -107,7 +108,7 @@ // software switch request handling mubi4_t dft_en; - assign dft_en = (en == lc_ctrl_pkg::On) ? MuBi4True : MuBi4False; + assign dft_en = lc_ctrl_pkg::lc_to_mubi4(en); mubi4_t all_clk_byp_req_d; assign all_clk_byp_req_d = mubi4_and_hi(byp_req_i, dft_en); @@ -123,9 +124,6 @@ .mubi_o(all_clk_byp_req_o) ); - // divider step down handling - mubi4_t unused_all_clk_byp_ack; - prim_mubi4_sync #( .AsyncOn(1), .StabilityCheck(1), @@ -147,7 +145,7 @@ .clk_i, .rst_ni, .mubi_i(all_clk_byp_ack_i), - .mubi_o({unused_all_clk_byp_ack}) + .mubi_o(byp_ack_o) ); // the software high speed select is valid only when software requests clock
diff --git a/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson b/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson index 1e0f30a..f6ab73e 100644 --- a/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson +++ b/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson
@@ -277,6 +277,30 @@ tags: ["excl:CsrAllTests:CsrExclWrite"] }, + { name: "EXTCLK_STATUS", + desc: ''' + Status of requested external clock switch + ''', + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { + bits: "3:0", + name: "ACK", + mubi: true, + desc: ''' + When !!EXTCLK_CTRL.SEL is set to kMultiBitBool4True, this field reflects + whether the clock has been switched the external source. + + kMultiBitBool4True indicates the switch is complete. + kMultiBitBool4False indicates the switch is either not possible or still ongoing. + ''' + resval: "false" + }, + ] + }, + { name: "JITTER_REGWEN", desc: "Jitter write enable", swaccess: "rw0c",
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv index 716a9a0..217adbb 100644 --- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv +++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
@@ -271,6 +271,7 @@ .lc_clk_byp_req_i, .lc_clk_byp_ack_o, .byp_req_i(extclk_ctrl_sel), + .byp_ack_o(hw2reg.extclk_status.d), .hi_speed_sel_i(extclk_ctrl_hi_speed_sel), .all_clk_byp_req_o, .all_clk_byp_ack_i,
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv index 5ca405b..85d7da6 100644 --- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv +++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv
@@ -13,7 +13,7 @@ parameter int NumAlerts = 2; // Address widths within the block - parameter int BlockAw = 6; + parameter int BlockAw = 7; //////////////////////////// // Typedefs for registers // @@ -146,6 +146,10 @@ } clkmgr_reg2hw_fatal_err_code_reg_t; typedef struct packed { + logic [3:0] d; + } clkmgr_hw2reg_extclk_status_reg_t; + + typedef struct packed { struct packed { logic d; logic de; @@ -243,39 +247,44 @@ // HW -> register type typedef struct packed { + clkmgr_hw2reg_extclk_status_reg_t extclk_status; // [39:36] clkmgr_hw2reg_clk_hints_status_reg_t clk_hints_status; // [35:28] clkmgr_hw2reg_recov_err_code_reg_t recov_err_code; // [27:6] clkmgr_hw2reg_fatal_err_code_reg_t fatal_err_code; // [5:0] } clkmgr_hw2reg_t; // Register offsets - parameter logic [BlockAw-1:0] CLKMGR_ALERT_TEST_OFFSET = 6'h 0; - parameter logic [BlockAw-1:0] CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET = 6'h 4; - parameter logic [BlockAw-1:0] CLKMGR_EXTCLK_CTRL_OFFSET = 6'h 8; - parameter logic [BlockAw-1:0] CLKMGR_JITTER_REGWEN_OFFSET = 6'h c; - parameter logic [BlockAw-1:0] CLKMGR_JITTER_ENABLE_OFFSET = 6'h 10; - parameter logic [BlockAw-1:0] CLKMGR_CLK_ENABLES_OFFSET = 6'h 14; - parameter logic [BlockAw-1:0] CLKMGR_CLK_HINTS_OFFSET = 6'h 18; - parameter logic [BlockAw-1:0] CLKMGR_CLK_HINTS_STATUS_OFFSET = 6'h 1c; - parameter logic [BlockAw-1:0] CLKMGR_MEASURE_CTRL_REGWEN_OFFSET = 6'h 20; - parameter logic [BlockAw-1:0] CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET = 6'h 24; - parameter logic [BlockAw-1:0] CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET = 6'h 28; - parameter logic [BlockAw-1:0] CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET = 6'h 2c; - parameter logic [BlockAw-1:0] CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET = 6'h 30; - parameter logic [BlockAw-1:0] CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET = 6'h 34; - parameter logic [BlockAw-1:0] CLKMGR_RECOV_ERR_CODE_OFFSET = 6'h 38; - parameter logic [BlockAw-1:0] CLKMGR_FATAL_ERR_CODE_OFFSET = 6'h 3c; + parameter logic [BlockAw-1:0] CLKMGR_ALERT_TEST_OFFSET = 7'h 0; + parameter logic [BlockAw-1:0] CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET = 7'h 4; + parameter logic [BlockAw-1:0] CLKMGR_EXTCLK_CTRL_OFFSET = 7'h 8; + parameter logic [BlockAw-1:0] CLKMGR_EXTCLK_STATUS_OFFSET = 7'h c; + parameter logic [BlockAw-1:0] CLKMGR_JITTER_REGWEN_OFFSET = 7'h 10; + parameter logic [BlockAw-1:0] CLKMGR_JITTER_ENABLE_OFFSET = 7'h 14; + parameter logic [BlockAw-1:0] CLKMGR_CLK_ENABLES_OFFSET = 7'h 18; + parameter logic [BlockAw-1:0] CLKMGR_CLK_HINTS_OFFSET = 7'h 1c; + parameter logic [BlockAw-1:0] CLKMGR_CLK_HINTS_STATUS_OFFSET = 7'h 20; + parameter logic [BlockAw-1:0] CLKMGR_MEASURE_CTRL_REGWEN_OFFSET = 7'h 24; + parameter logic [BlockAw-1:0] CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET = 7'h 28; + parameter logic [BlockAw-1:0] CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET = 7'h 2c; + parameter logic [BlockAw-1:0] CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET = 7'h 30; + parameter logic [BlockAw-1:0] CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET = 7'h 34; + parameter logic [BlockAw-1:0] CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET = 7'h 38; + parameter logic [BlockAw-1:0] CLKMGR_RECOV_ERR_CODE_OFFSET = 7'h 3c; + parameter logic [BlockAw-1:0] CLKMGR_FATAL_ERR_CODE_OFFSET = 7'h 40; // Reset values for hwext registers and their fields parameter logic [1:0] CLKMGR_ALERT_TEST_RESVAL = 2'h 0; parameter logic [0:0] CLKMGR_ALERT_TEST_RECOV_FAULT_RESVAL = 1'h 0; parameter logic [0:0] CLKMGR_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0; + parameter logic [3:0] CLKMGR_EXTCLK_STATUS_RESVAL = 4'h 5; + parameter logic [3:0] CLKMGR_EXTCLK_STATUS_ACK_RESVAL = 4'h 5; // Register index typedef enum int { CLKMGR_ALERT_TEST, CLKMGR_EXTCLK_CTRL_REGWEN, CLKMGR_EXTCLK_CTRL, + CLKMGR_EXTCLK_STATUS, CLKMGR_JITTER_REGWEN, CLKMGR_JITTER_ENABLE, CLKMGR_CLK_ENABLES, @@ -292,23 +301,24 @@ } clkmgr_id_e; // Register width information to check illegal writes - parameter logic [3:0] CLKMGR_PERMIT [16] = '{ + parameter logic [3:0] CLKMGR_PERMIT [17] = '{ 4'b 0001, // index[ 0] CLKMGR_ALERT_TEST 4'b 0001, // index[ 1] CLKMGR_EXTCLK_CTRL_REGWEN 4'b 0001, // index[ 2] CLKMGR_EXTCLK_CTRL - 4'b 0001, // index[ 3] CLKMGR_JITTER_REGWEN - 4'b 0001, // index[ 4] CLKMGR_JITTER_ENABLE - 4'b 0001, // index[ 5] CLKMGR_CLK_ENABLES - 4'b 0001, // index[ 6] CLKMGR_CLK_HINTS - 4'b 0001, // index[ 7] CLKMGR_CLK_HINTS_STATUS - 4'b 0001, // index[ 8] CLKMGR_MEASURE_CTRL_REGWEN - 4'b 0111, // index[ 9] CLKMGR_IO_MEAS_CTRL_SHADOWED - 4'b 0111, // index[10] CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED - 4'b 0111, // index[11] CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED - 4'b 0111, // index[12] CLKMGR_MAIN_MEAS_CTRL_SHADOWED - 4'b 0111, // index[13] CLKMGR_USB_MEAS_CTRL_SHADOWED - 4'b 0011, // index[14] CLKMGR_RECOV_ERR_CODE - 4'b 0001 // index[15] CLKMGR_FATAL_ERR_CODE + 4'b 0001, // index[ 3] CLKMGR_EXTCLK_STATUS + 4'b 0001, // index[ 4] CLKMGR_JITTER_REGWEN + 4'b 0001, // index[ 5] CLKMGR_JITTER_ENABLE + 4'b 0001, // index[ 6] CLKMGR_CLK_ENABLES + 4'b 0001, // index[ 7] CLKMGR_CLK_HINTS + 4'b 0001, // index[ 8] CLKMGR_CLK_HINTS_STATUS + 4'b 0001, // index[ 9] CLKMGR_MEASURE_CTRL_REGWEN + 4'b 0111, // index[10] CLKMGR_IO_MEAS_CTRL_SHADOWED + 4'b 0111, // index[11] CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED + 4'b 0111, // index[12] CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED + 4'b 0111, // index[13] CLKMGR_MAIN_MEAS_CTRL_SHADOWED + 4'b 0111, // index[14] CLKMGR_USB_MEAS_CTRL_SHADOWED + 4'b 0011, // index[15] CLKMGR_RECOV_ERR_CODE + 4'b 0001 // index[16] CLKMGR_FATAL_ERR_CODE }; endpackage
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv index 28aa15c..ebaff4b 100644 --- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv +++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv
@@ -38,7 +38,7 @@ import clkmgr_reg_pkg::* ; - localparam int AW = 6; + localparam int AW = 7; localparam int DW = 32; localparam int DBW = DW/8; // Byte Width @@ -193,6 +193,8 @@ logic [3:0] extclk_ctrl_sel_wd; logic [3:0] extclk_ctrl_hi_speed_sel_qs; logic [3:0] extclk_ctrl_hi_speed_sel_wd; + logic extclk_status_re; + logic [3:0] extclk_status_qs; logic jitter_regwen_we; logic jitter_regwen_qs; logic jitter_regwen_wd; @@ -627,6 +629,21 @@ ); + // R[extclk_status]: V(True) + prim_subreg_ext #( + .DW (4) + ) u_extclk_status ( + .re (extclk_status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.extclk_status.d), + .qre (), + .qe (), + .q (), + .qs (extclk_status_qs) + ); + + // R[jitter_regwen]: V(False) prim_subreg #( .DW (1), @@ -2246,25 +2263,26 @@ - logic [15:0] addr_hit; + logic [16:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == CLKMGR_ALERT_TEST_OFFSET); addr_hit[ 1] = (reg_addr == CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET); addr_hit[ 2] = (reg_addr == CLKMGR_EXTCLK_CTRL_OFFSET); - addr_hit[ 3] = (reg_addr == CLKMGR_JITTER_REGWEN_OFFSET); - addr_hit[ 4] = (reg_addr == CLKMGR_JITTER_ENABLE_OFFSET); - addr_hit[ 5] = (reg_addr == CLKMGR_CLK_ENABLES_OFFSET); - addr_hit[ 6] = (reg_addr == CLKMGR_CLK_HINTS_OFFSET); - addr_hit[ 7] = (reg_addr == CLKMGR_CLK_HINTS_STATUS_OFFSET); - addr_hit[ 8] = (reg_addr == CLKMGR_MEASURE_CTRL_REGWEN_OFFSET); - addr_hit[ 9] = (reg_addr == CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET); - addr_hit[10] = (reg_addr == CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET); - addr_hit[11] = (reg_addr == CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET); - addr_hit[12] = (reg_addr == CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET); - addr_hit[13] = (reg_addr == CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET); - addr_hit[14] = (reg_addr == CLKMGR_RECOV_ERR_CODE_OFFSET); - addr_hit[15] = (reg_addr == CLKMGR_FATAL_ERR_CODE_OFFSET); + addr_hit[ 3] = (reg_addr == CLKMGR_EXTCLK_STATUS_OFFSET); + addr_hit[ 4] = (reg_addr == CLKMGR_JITTER_REGWEN_OFFSET); + addr_hit[ 5] = (reg_addr == CLKMGR_JITTER_ENABLE_OFFSET); + addr_hit[ 6] = (reg_addr == CLKMGR_CLK_ENABLES_OFFSET); + addr_hit[ 7] = (reg_addr == CLKMGR_CLK_HINTS_OFFSET); + addr_hit[ 8] = (reg_addr == CLKMGR_CLK_HINTS_STATUS_OFFSET); + addr_hit[ 9] = (reg_addr == CLKMGR_MEASURE_CTRL_REGWEN_OFFSET); + addr_hit[10] = (reg_addr == CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET); + addr_hit[11] = (reg_addr == CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET); + addr_hit[12] = (reg_addr == CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET); + addr_hit[13] = (reg_addr == CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET); + addr_hit[14] = (reg_addr == CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET); + addr_hit[15] = (reg_addr == CLKMGR_RECOV_ERR_CODE_OFFSET); + addr_hit[16] = (reg_addr == CLKMGR_FATAL_ERR_CODE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -2287,7 +2305,8 @@ (addr_hit[12] & (|(CLKMGR_PERMIT[12] & ~reg_be))) | (addr_hit[13] & (|(CLKMGR_PERMIT[13] & ~reg_be))) | (addr_hit[14] & (|(CLKMGR_PERMIT[14] & ~reg_be))) | - (addr_hit[15] & (|(CLKMGR_PERMIT[15] & ~reg_be))))); + (addr_hit[15] & (|(CLKMGR_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(CLKMGR_PERMIT[16] & ~reg_be))))); end assign alert_test_we = addr_hit[0] & reg_we & !reg_error; @@ -2302,13 +2321,14 @@ assign extclk_ctrl_sel_wd = reg_wdata[3:0]; assign extclk_ctrl_hi_speed_sel_wd = reg_wdata[7:4]; - assign jitter_regwen_we = addr_hit[3] & reg_we & !reg_error; + assign extclk_status_re = addr_hit[3] & reg_re & !reg_error; + assign jitter_regwen_we = addr_hit[4] & reg_we & !reg_error; assign jitter_regwen_wd = reg_wdata[0]; - assign jitter_enable_we = addr_hit[4] & reg_we & !reg_error; + assign jitter_enable_we = addr_hit[5] & reg_we & !reg_error; assign jitter_enable_wd = reg_wdata[3:0]; - assign clk_enables_we = addr_hit[5] & reg_we & !reg_error; + assign clk_enables_we = addr_hit[6] & reg_we & !reg_error; assign clk_enables_clk_io_div4_peri_en_wd = reg_wdata[0]; @@ -2317,7 +2337,7 @@ assign clk_enables_clk_usb_peri_en_wd = reg_wdata[2]; assign clk_enables_clk_io_peri_en_wd = reg_wdata[3]; - assign clk_hints_we = addr_hit[6] & reg_we & !reg_error; + assign clk_hints_we = addr_hit[7] & reg_we & !reg_error; assign clk_hints_clk_main_aes_hint_wd = reg_wdata[0]; @@ -2326,35 +2346,35 @@ assign clk_hints_clk_main_kmac_hint_wd = reg_wdata[2]; assign clk_hints_clk_main_otbn_hint_wd = reg_wdata[3]; - assign measure_ctrl_regwen_we = addr_hit[8] & reg_we & !reg_error; + assign measure_ctrl_regwen_we = addr_hit[9] & reg_we & !reg_error; assign measure_ctrl_regwen_wd = reg_wdata[0]; - assign io_meas_ctrl_shadowed_re = addr_hit[9] & reg_re & !reg_error; - assign io_meas_ctrl_shadowed_we = addr_hit[9] & reg_we & !reg_error; + assign io_meas_ctrl_shadowed_re = addr_hit[10] & reg_re & !reg_error; + assign io_meas_ctrl_shadowed_we = addr_hit[10] & reg_we & !reg_error; - assign io_div2_meas_ctrl_shadowed_re = addr_hit[10] & reg_re & !reg_error; - assign io_div2_meas_ctrl_shadowed_we = addr_hit[10] & reg_we & !reg_error; + assign io_div2_meas_ctrl_shadowed_re = addr_hit[11] & reg_re & !reg_error; + assign io_div2_meas_ctrl_shadowed_we = addr_hit[11] & reg_we & !reg_error; - assign io_div4_meas_ctrl_shadowed_re = addr_hit[11] & reg_re & !reg_error; - assign io_div4_meas_ctrl_shadowed_we = addr_hit[11] & reg_we & !reg_error; + assign io_div4_meas_ctrl_shadowed_re = addr_hit[12] & reg_re & !reg_error; + assign io_div4_meas_ctrl_shadowed_we = addr_hit[12] & reg_we & !reg_error; - assign main_meas_ctrl_shadowed_re = addr_hit[12] & reg_re & !reg_error; - assign main_meas_ctrl_shadowed_we = addr_hit[12] & reg_we & !reg_error; + assign main_meas_ctrl_shadowed_re = addr_hit[13] & reg_re & !reg_error; + assign main_meas_ctrl_shadowed_we = addr_hit[13] & reg_we & !reg_error; - assign usb_meas_ctrl_shadowed_re = addr_hit[13] & reg_re & !reg_error; - assign usb_meas_ctrl_shadowed_we = addr_hit[13] & reg_we & !reg_error; + assign usb_meas_ctrl_shadowed_re = addr_hit[14] & reg_re & !reg_error; + assign usb_meas_ctrl_shadowed_we = addr_hit[14] & reg_we & !reg_error; - assign recov_err_code_we = addr_hit[14] & reg_we & !reg_error; + assign recov_err_code_we = addr_hit[15] & reg_we & !reg_error; assign recov_err_code_shadow_update_err_wd = reg_wdata[0]; @@ -2397,54 +2417,58 @@ end addr_hit[3]: begin - reg_rdata_next[0] = jitter_regwen_qs; + reg_rdata_next[3:0] = extclk_status_qs; end addr_hit[4]: begin - reg_rdata_next[3:0] = jitter_enable_qs; + reg_rdata_next[0] = jitter_regwen_qs; end addr_hit[5]: begin + reg_rdata_next[3:0] = jitter_enable_qs; + end + + addr_hit[6]: begin reg_rdata_next[0] = clk_enables_clk_io_div4_peri_en_qs; reg_rdata_next[1] = clk_enables_clk_io_div2_peri_en_qs; reg_rdata_next[2] = clk_enables_clk_usb_peri_en_qs; reg_rdata_next[3] = clk_enables_clk_io_peri_en_qs; end - addr_hit[6]: begin + addr_hit[7]: begin reg_rdata_next[0] = clk_hints_clk_main_aes_hint_qs; reg_rdata_next[1] = clk_hints_clk_main_hmac_hint_qs; reg_rdata_next[2] = clk_hints_clk_main_kmac_hint_qs; reg_rdata_next[3] = clk_hints_clk_main_otbn_hint_qs; end - addr_hit[7]: begin + addr_hit[8]: begin reg_rdata_next[0] = clk_hints_status_clk_main_aes_val_qs; reg_rdata_next[1] = clk_hints_status_clk_main_hmac_val_qs; reg_rdata_next[2] = clk_hints_status_clk_main_kmac_val_qs; reg_rdata_next[3] = clk_hints_status_clk_main_otbn_val_qs; end - addr_hit[8]: begin + addr_hit[9]: begin reg_rdata_next[0] = measure_ctrl_regwen_qs; end - addr_hit[9]: begin + addr_hit[10]: begin reg_rdata_next = DW'(io_meas_ctrl_shadowed_qs); end - addr_hit[10]: begin + addr_hit[11]: begin reg_rdata_next = DW'(io_div2_meas_ctrl_shadowed_qs); end - addr_hit[11]: begin + addr_hit[12]: begin reg_rdata_next = DW'(io_div4_meas_ctrl_shadowed_qs); end - addr_hit[12]: begin + addr_hit[13]: begin reg_rdata_next = DW'(main_meas_ctrl_shadowed_qs); end - addr_hit[13]: begin + addr_hit[14]: begin reg_rdata_next = DW'(usb_meas_ctrl_shadowed_qs); end - addr_hit[14]: begin + addr_hit[15]: begin reg_rdata_next[0] = recov_err_code_shadow_update_err_qs; reg_rdata_next[1] = recov_err_code_io_measure_err_qs; reg_rdata_next[2] = recov_err_code_io_div2_measure_err_qs; @@ -2458,7 +2482,7 @@ reg_rdata_next[10] = recov_err_code_usb_timeout_err_qs; end - addr_hit[15]: begin + addr_hit[16]: begin reg_rdata_next[0] = fatal_err_code_reg_intg_qs; reg_rdata_next[1] = fatal_err_code_idle_cnt_qs; reg_rdata_next[2] = fatal_err_code_shadow_storage_err_qs; @@ -2535,19 +2559,19 @@ always_comb begin reg_busy_sel = '0; unique case (1'b1) - addr_hit[9]: begin + addr_hit[10]: begin reg_busy_sel = io_meas_ctrl_shadowed_busy; end - addr_hit[10]: begin + addr_hit[11]: begin reg_busy_sel = io_div2_meas_ctrl_shadowed_busy; end - addr_hit[11]: begin + addr_hit[12]: begin reg_busy_sel = io_div4_meas_ctrl_shadowed_busy; end - addr_hit[12]: begin + addr_hit[13]: begin reg_busy_sel = main_meas_ctrl_shadowed_busy; end - addr_hit[13]: begin + addr_hit[14]: begin reg_busy_sel = usb_meas_ctrl_shadowed_busy; end default: begin