commit 145184035848f3734446e753d6fb01b0b9789897
author Timothy Chen <timothytim@google.com> Mon Apr 13 15:25:22 2020 -0700
committer tjaychen <timothytim@google.com> Thu Apr 16 17:52:22 2020 -0700
tree 29d0b0c3dde1881e1e689ef1ea458539bccb32ea
parent c30dad2f9dcfeccc32f834114ec1d2a0bc65c098

[flash_ctrl] Minor refactoring to get ready for upcoming changes

- Move most parameters out of top_pkg to get ready for flash_ctrl templating
- Separate bus width from flash data width to get ready for wider flash

Signed-off-by: Timothy Chen <timothytim@google.com>

hw/top_earlgrey/data/top_earlgrey.sv.tpl

diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index 4bd94e8..ea823a2 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -458,12 +458,12 @@
   logic flash_host_req;
   logic flash_host_req_rdy;
   logic flash_host_req_done;
-  logic [FLASH_DW-1:0] flash_host_rdata;
-  logic [FLASH_AW-1:0] flash_host_addr;
+  logic [flash_ctrl_pkg::BusWidth-1:0] flash_host_rdata;
+  logic [flash_ctrl_pkg::AddrW-1:0] flash_host_addr;
 
   tlul_adapter_sram #(
-    .SramAw(FLASH_AW),
-    .SramDw(FLASH_DW),
+    .SramAw(flash_ctrl_pkg::AddrW),
+    .SramDw(flash_ctrl_pkg::BusWidth),
     .Outstanding(2),
     .ByteAccess(0),
     .ErrOnWrite(1)
@@ -489,12 +489,7 @@
     .rerror_i (2'b00)
   );
 
-  flash_phy #(
-    .NumBanks(FLASH_BANKS),
-    .PagesPerBank(FLASH_PAGES_PER_BANK),
-    .WordsPerPage(FLASH_WORDS_PER_PAGE),
-    .DataWidth(${data_width})
-  ) u_flash_${m["name"]} (
+  flash_phy u_flash_${m["name"]} (
     % for key in clocks:
     .${key}   (${clocks[key]}_clk),
     % endfor