[flash_ctrl] Minor refactoring to get ready for upcoming changes
- Move most parameters out of top_pkg to get ready for flash_ctrl templating
- Separate bus width from flash data width to get ready for wider flash
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
index b9d5aba..388fd5e 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
@@ -24,7 +24,7 @@
],
param_list: [
- { name: "NumBanks",
+ { name: "NBanks",
desc: "Number of flash banks",
type: "int",
default: "2",
@@ -320,7 +320,7 @@
cname: "FLASH_CTRL",
name: "MP_BANK_CFG",
desc: "Memory protect bank configuration",
- count: "NumBanks",
+ count: "NBanks",
swaccess: "rw",
hwaccess: "hro",
regwen: "BANK_CFG_REGWEN"
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
index 80e83ce..25981d6 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
@@ -8,7 +8,7 @@
`include "prim_assert.sv"
-module flash_ctrl (
+module flash_ctrl import flash_ctrl_pkg::*; (
input clk_i,
input rst_ni,
@@ -17,8 +17,8 @@
output tlul_pkg::tl_d2h_t tl_o,
// Flash Interface
- input flash_ctrl_pkg::flash_rsp_t flash_i,
- output flash_ctrl_pkg::flash_req_t flash_o,
+ input flash_rsp_t flash_i,
+ output flash_req_t flash_o,
// Interrupts
output logic intr_prog_empty_o, // Program fifo is empty
@@ -29,24 +29,10 @@
output logic intr_op_error_o // Requested flash operation (wr/erase) done
);
- import flash_ctrl_pkg::*;
import flash_ctrl_reg_pkg::*;
- localparam int NumBanks = top_pkg::FLASH_BANKS;
- localparam int PagesPerBank = top_pkg::FLASH_PAGES_PER_BANK;
- localparam int WordsPerPage = top_pkg::FLASH_WORDS_PER_PAGE;
- localparam int BankW = top_pkg::FLASH_BKW;
- localparam int PageW = top_pkg::FLASH_PGW;
- localparam int WordW = top_pkg::FLASH_WDW;
- localparam int AllPagesW = BankW + PageW;
- localparam int AddrW = top_pkg::FLASH_AW;
- localparam int DataWidth = top_pkg::FLASH_DW;
- localparam int DataBitWidth = $clog2(DataWidth/8);
+ localparam int DataBitWidth = $clog2(BytesPerWord);
localparam int EraseBitWidth = $bits(flash_erase_op_e);
- localparam int FifoDepth = 16;
- localparam int FifoDepthW = $clog2(FifoDepth+1);
- localparam int MpRegions = 8;
-
flash_ctrl_reg2hw_t reg2hw;
flash_ctrl_hw2reg_t hw2reg;
@@ -77,15 +63,15 @@
logic prog_fifo_req;
logic prog_fifo_wen;
logic prog_fifo_ren;
- logic [DataWidth-1:0] prog_fifo_wdata;
- logic [DataWidth-1:0] prog_fifo_rdata;
+ logic [BusWidth-1:0] prog_fifo_wdata;
+ logic [BusWidth-1:0] prog_fifo_rdata;
logic [FifoDepthW-1:0] prog_fifo_depth;
logic rd_fifo_wready;
logic rd_fifo_rvalid;
logic rd_fifo_wen;
logic rd_fifo_ren;
- logic [DataWidth-1:0] rd_fifo_wdata;
- logic [DataWidth-1:0] rd_fifo_rdata;
+ logic [BusWidth-1:0] rd_fifo_wdata;
+ logic [BusWidth-1:0] rd_fifo_rdata;
logic [FifoDepthW-1:0] rd_fifo_depth;
// Program Control Connections
@@ -111,8 +97,8 @@
logic flash_rd_done, flash_prog_done, flash_erase_done;
logic flash_error;
logic [AddrW-1:0] flash_addr;
- logic [DataWidth-1:0] flash_prog_data;
- logic [DataWidth-1:0] flash_rd_data;
+ logic [BusWidth-1:0] flash_prog_data;
+ logic [BusWidth-1:0] flash_rd_data;
logic init_busy;
logic rd_op;
logic prog_op;
@@ -130,7 +116,7 @@
// strategy has been identified
tlul_adapter_sram #(
.SramAw(1), //address unused
- .SramDw(DataWidth),
+ .SramDw(BusWidth),
.ByteAccess(0), //flash may not support byte access
.ErrOnRead(1) //reads not supported
) u_to_prog_fifo (
@@ -144,13 +130,13 @@
.addr_o (),
.wmask_o (),
.wdata_o (prog_fifo_wdata),
- .rdata_i (DataWidth'(0)),
+ .rdata_i (BusWidth'(0)),
.rvalid_i (1'b0),
.rerror_i (2'b0)
);
prim_fifo_sync #(
- .Width(DataWidth),
+ .Width(BusWidth),
.Depth(FifoDepth)
) u_prog_fifo (
.clk_i,
@@ -167,7 +153,7 @@
// Program handler is consumer of prog_fifo
flash_prog_ctrl #(
- .DataW(DataWidth),
+ .DataW(BusWidth),
.AddrW(AddrW)
) u_flash_prog_ctrl (
.clk_i,
@@ -206,7 +192,7 @@
tlul_adapter_sram #(
.SramAw(1), //address unused
- .SramDw(DataWidth),
+ .SramDw(BusWidth),
.ByteAccess(0), //flash may not support byte access
.ErrOnWrite(1) //writes not supported
) u_to_rd_fifo (
@@ -226,7 +212,7 @@
);
prim_fifo_sync #(
- .Width(DataWidth),
+ .Width(BusWidth),
.Depth(FifoDepth)
) u_rd_fifo (
.clk_i,
@@ -245,7 +231,7 @@
// Read handler is consumer of rd_fifo
flash_rd_ctrl #(
- .DataW(DataWidth),
+ .DataW(BusWidth),
.AddrW(AddrW)
) u_flash_rd_ctrl (
.clk_i,
@@ -346,7 +332,7 @@
.req_i(flash_req),
.req_addr_i(flash_addr[WordW +: AllPagesW]),
.addr_ovfl_i(rd_flash_ovfl | prog_flash_ovfl),
- .req_bk_i(flash_addr[WordW + PageW +: BankW]),
+ .req_bk_i(flash_addr[BankAddrW +: BankW]),
.rd_i(rd_op),
.prog_i(prog_op),
.pg_erase_i(erase_op & (erase_flash_type == PageErase)),
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
index 6a3d830..5e919aa 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
@@ -7,8 +7,30 @@
package flash_ctrl_pkg;
- localparam int FlashTotalPages = top_pkg::FLASH_BANKS * top_pkg::FLASH_PAGES_PER_BANK;
- localparam int AllPagesW = $clog2(FlashTotalPages);
+ // parameters for flash macro properties
+ localparam int NumBanks = top_pkg::FLASH_BANKS;
+ localparam int PagesPerBank = top_pkg::FLASH_PAGES_PER_BANK;
+ localparam int WordsPerPage = top_pkg::FLASH_WORDS_PER_PAGE;
+ localparam int BytesPerWord = top_pkg::FLASH_BYTES_PER_WORD;
+ localparam int BankW = $clog2(NumBanks);
+ localparam int PageW = $clog2(PagesPerBank);
+ localparam int WordW = $clog2(WordsPerPage);
+ localparam int AddrW = BankW + PageW + WordW; // all flash range
+ localparam int BankAddrW = PageW + WordW; // 1 bank of flash range
+ localparam int DataWidth = BytesPerWord * 8;
+ localparam int FlashTotalPages = NumBanks * PagesPerBank;
+ localparam int AllPagesW = BankW + PageW;
+
+ // bus interface
+ localparam int BusWidth = top_pkg::TL_DW;
+
+ // flash controller protection regions
+ localparam int MpRegions = 8;
+
+ // fifo parameters
+ localparam int FifoDepth = 16;
+ localparam int FifoDepthW = $clog2(FifoDepth+1);
+
// Flash Operations Supported
typedef enum logic [1:0] {
@@ -31,13 +53,13 @@
// Flash controller to memory
typedef struct packed {
- logic req;
- logic rd;
- logic prog;
- logic pg_erase;
- logic bk_erase;
- logic [top_pkg::FLASH_AW-1:0] addr;
- logic [top_pkg::FLASH_DW-1:0] prog_data;
+ logic req;
+ logic rd;
+ logic prog;
+ logic pg_erase;
+ logic bk_erase;
+ logic [AddrW-1:0] addr;
+ logic [BusWidth-1:0] prog_data;
} flash_req_t;
// default value of flash_req_t (for dangling ports)
@@ -53,11 +75,11 @@
// memory to flash controller
typedef struct packed {
- logic rd_done;
- logic prog_done;
- logic erase_done;
- logic [top_pkg::FLASH_DW-1:0] rd_data;
- logic init_busy;
+ logic rd_done;
+ logic prog_done;
+ logic erase_done;
+ logic [BusWidth-1:0] rd_data;
+ logic init_busy;
} flash_rsp_t;
// default value of flash_rsp_t (for dangling ports)
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
index 8b4db79..44c58b7 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
@@ -7,7 +7,7 @@
package flash_ctrl_reg_pkg;
// Param list
- parameter int NumBanks = 2;
+ parameter int NBanks = 2;
parameter int NumRegions = 8;
////////////////////////////
diff --git a/hw/ip/flash_ctrl/rtl/flash_phy.sv b/hw/ip/flash_ctrl/rtl/flash_phy.sv
index 5b5f691..958cb8f 100644
--- a/hw/ip/flash_ctrl/rtl/flash_phy.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_phy.sv
@@ -10,25 +10,14 @@
// The top level flash_phy is only responsible for dispatching transactions and
// correctly collecting the responses in order.
-module flash_phy #(
- parameter int NumBanks = 2,
- parameter int PagesPerBank = 256, // pages per bank
- parameter int WordsPerPage = 256, // words per page
- parameter int DataWidth = 32, // bits per word
-
- //Do not touch - Derived parameters
- localparam int BankW = $clog2(NumBanks),
- localparam int PageW = $clog2(PagesPerBank),
- localparam int WordW = $clog2(WordsPerPage),
- localparam int AddrW = BankW + PageW + WordW
-) (
+module flash_phy import flash_ctrl_pkg::*; (
input clk_i,
input rst_ni,
input host_req_i,
input [AddrW-1:0] host_addr_i,
output logic host_req_rdy_o,
output logic host_req_done_o,
- output logic [DataWidth-1:0] host_rdata_o,
+ output logic [BusWidth-1:0] host_rdata_o,
input flash_ctrl_pkg::flash_req_t flash_ctrl_i,
output flash_ctrl_pkg::flash_rsp_t flash_ctrl_o
);
@@ -57,7 +46,7 @@
logic [NumBanks-1:0] host_rsp_avail;
logic [NumBanks-1:0] host_rsp_vld;
logic [NumBanks-1:0] host_rsp_ack;
- logic [DataWidth-1:0] host_rsp_data [NumBanks];
+ logic [BusWidth-1:0] host_rsp_data [NumBanks];
logic seq_fifo_rdy;
logic seq_fifo_pending;
@@ -70,11 +59,11 @@
logic [NumBanks-1:0] init_busy;
// common interface
- logic [DataWidth-1:0] rd_data [NumBanks];
+ logic [BusWidth-1:0] rd_data [NumBanks];
// select which bank each is operating on
- assign host_bank_sel = host_req_i ? host_addr_i[PageW + WordW +: BankW] : '0;
- assign ctrl_bank_sel = flash_ctrl_i.addr[PageW + WordW +: BankW];
+ assign host_bank_sel = host_req_i ? host_addr_i[BankAddrW +: BankW] : '0;
+ assign ctrl_bank_sel = flash_ctrl_i.addr[BankAddrW +: BankW];
// accept transaction if bank is ready and previous response NOT pending
assign host_req_rdy_o = host_req_rdy[host_bank_sel] & host_rsp_avail[host_bank_sel] &
@@ -113,7 +102,7 @@
assign host_rsp_ack[bank] = host_req_done_o & (rsp_bank_sel == bank);
prim_fifo_sync #(
- .Width (DataWidth),
+ .Width (BusWidth),
.Pass (1'b1),
.Depth (FlashMacroOustanding)
) i_host_rsp_fifo (
@@ -129,21 +118,17 @@
.rdata (host_rsp_data[bank])
);
- flash_phy_core #(
- .PagesPerBank(PagesPerBank),
- .WordsPerPage(WordsPerPage),
- .DataWidth(DataWidth)
- ) i_core (
+ flash_phy_core i_core (
.clk_i,
.rst_ni,
.req_i(flash_ctrl_i.req & (ctrl_bank_sel == bank)),
.host_req_i(host_req_i & (host_bank_sel == bank)),
- .host_addr_i(host_addr_i[0 +: PageW + WordW]),
+ .host_addr_i(host_addr_i[0 +: BankAddrW]),
.rd_i(flash_ctrl_i.rd),
.prog_i(flash_ctrl_i.prog),
.pg_erase_i(flash_ctrl_i.pg_erase),
.bk_erase_i(flash_ctrl_i.bk_erase),
- .addr_i(flash_ctrl_i.addr[0 +: PageW + WordW]),
+ .addr_i(flash_ctrl_i.addr[0 +: BankAddrW]),
.prog_data_i(flash_ctrl_i.prog_data),
.host_req_rdy_o(host_req_rdy[bank]),
.host_req_done_o(host_req_done[bank]),
diff --git a/hw/ip/flash_ctrl/rtl/flash_phy_core.sv b/hw/ip/flash_ctrl/rtl/flash_phy_core.sv
index 62cb5d7..be643af 100644
--- a/hw/ip/flash_ctrl/rtl/flash_phy_core.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_phy_core.sv
@@ -9,34 +9,26 @@
// scramble, ECC, security and arbitration logic.
// Most of the items are TODO, at the moment only arbitration logic exists.
-module flash_phy_core #(
- parameter int PagesPerBank = 256, // pages per bank
- parameter int WordsPerPage = 256, // words per page
- parameter int DataWidth = 32, // bits per word
- parameter bit SkipInit = 1, // this is an option to reset flash to all F's at reset
-
- // Derived parameters
- localparam int PageW = $clog2(PagesPerBank),
- localparam int WordW = $clog2(WordsPerPage),
- localparam int AddrW = PageW + WordW
+module flash_phy_core import flash_ctrl_pkg::*; #(
+ parameter bit SkipInit = 1 // this is an option to reset flash to all F's at reset
) (
input clk_i,
input rst_ni,
input host_req_i, // host request - read only
- input [AddrW-1:0] host_addr_i,
+ input [BankAddrW-1:0] host_addr_i,
input req_i, // controller request
input rd_i,
input prog_i,
input pg_erase_i,
input bk_erase_i,
- input [AddrW-1:0] addr_i,
- input [DataWidth-1:0] prog_data_i,
+ input [BankAddrW-1:0] addr_i,
+ input [BusWidth-1:0] prog_data_i,
output logic host_req_rdy_o,
output logic host_req_done_o,
output logic rd_done_o,
output logic prog_done_o,
output logic erase_done_o,
- output logic [DataWidth-1:0] rd_data_o,
+ output logic [BusWidth-1:0] rd_data_o,
output logic init_busy_o
);
@@ -56,7 +48,7 @@
logic ack;
// interface with flash macro
- logic [AddrW-1:0] muxed_addr;
+ logic [BankAddrW-1:0] muxed_addr;
// valid request conditions
logic op_clr_cond;
diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index 4bd94e8..ea823a2 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -458,12 +458,12 @@
logic flash_host_req;
logic flash_host_req_rdy;
logic flash_host_req_done;
- logic [FLASH_DW-1:0] flash_host_rdata;
- logic [FLASH_AW-1:0] flash_host_addr;
+ logic [flash_ctrl_pkg::BusWidth-1:0] flash_host_rdata;
+ logic [flash_ctrl_pkg::AddrW-1:0] flash_host_addr;
tlul_adapter_sram #(
- .SramAw(FLASH_AW),
- .SramDw(FLASH_DW),
+ .SramAw(flash_ctrl_pkg::AddrW),
+ .SramDw(flash_ctrl_pkg::BusWidth),
.Outstanding(2),
.ByteAccess(0),
.ErrOnWrite(1)
@@ -489,12 +489,7 @@
.rerror_i (2'b00)
);
- flash_phy #(
- .NumBanks(FLASH_BANKS),
- .PagesPerBank(FLASH_PAGES_PER_BANK),
- .WordsPerPage(FLASH_WORDS_PER_PAGE),
- .DataWidth(${data_width})
- ) u_flash_${m["name"]} (
+ flash_phy u_flash_${m["name"]} (
% for key in clocks:
.${key} (${clocks[key]}_clk),
% endfor
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 50edb69..7ce3c62 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -452,12 +452,12 @@
logic flash_host_req;
logic flash_host_req_rdy;
logic flash_host_req_done;
- logic [FLASH_DW-1:0] flash_host_rdata;
- logic [FLASH_AW-1:0] flash_host_addr;
+ logic [flash_ctrl_pkg::BusWidth-1:0] flash_host_rdata;
+ logic [flash_ctrl_pkg::AddrW-1:0] flash_host_addr;
tlul_adapter_sram #(
- .SramAw(FLASH_AW),
- .SramDw(FLASH_DW),
+ .SramAw(flash_ctrl_pkg::AddrW),
+ .SramDw(flash_ctrl_pkg::BusWidth),
.Outstanding(2),
.ByteAccess(0),
.ErrOnWrite(1)
@@ -479,12 +479,7 @@
.rerror_i (2'b00)
);
- flash_phy #(
- .NumBanks(FLASH_BANKS),
- .PagesPerBank(FLASH_PAGES_PER_BANK),
- .WordsPerPage(FLASH_WORDS_PER_PAGE),
- .DataWidth(32)
- ) u_flash_eflash (
+ flash_phy u_flash_eflash (
.clk_i (main_clk),
.rst_ni (lc_rst_n),
.host_req_i (flash_host_req),
diff --git a/hw/top_earlgrey/rtl/top_pkg.sv b/hw/top_earlgrey/rtl/top_pkg.sv
index 01f6246..bf0b718 100644
--- a/hw/top_earlgrey/rtl/top_pkg.sv
+++ b/hw/top_earlgrey/rtl/top_pkg.sv
@@ -16,10 +16,5 @@
localparam FLASH_PAGES_PER_BANK=256;
localparam FLASH_WORDS_PER_PAGE=256;
localparam FLASH_BYTES_PER_WORD=4;
-localparam FLASH_BKW = $clog2(FLASH_BANKS);
-localparam FLASH_PGW = $clog2(FLASH_PAGES_PER_BANK);
-localparam FLASH_WDW = $clog2(FLASH_WORDS_PER_PAGE);
-localparam FLASH_AW = FLASH_BKW + FLASH_PGW + FLASH_WDW;
-localparam FLASH_DW = FLASH_BYTES_PER_WORD * 8;
endpackage
