| commit | 1330f8548ed014a3ef5ff9a051bf11a78c5b520b | [log] [tgz] |
|---|---|---|
| author | Miguel Osorio <miguelosorio@google.com> | Wed Nov 10 07:52:20 2021 -0800 |
| committer | moidx <migue48@gmail.com> | Tue Nov 16 07:12:24 2021 -0800 |
| tree | 3be7ebd03381e1321f64b561a3adcf1feb19809c | |
| parent | 9c2807d7e7efb92e218a36302e7e0ca402b41ae2 [diff] |
[fpga] Update slice to work with 32kB ROM The 32kB ROM configuration uses 4-bit RAM cells which were previously not supported by the slice scripts. This commit adds the following changes: * Update the Vivado rom.mmi generation script to support 4bit wide address ranges. * Update the gen_vivado_mem_image.py to support swapping of byte nibbles. This is needed in order to match the expected bit order in the updatemem command. Signed-off-by: Miguel Osorio <miguelosorio@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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