)]}'
{
  "commit": "1330f8548ed014a3ef5ff9a051bf11a78c5b520b",
  "tree": "3be7ebd03381e1321f64b561a3adcf1feb19809c",
  "parents": [
    "9c2807d7e7efb92e218a36302e7e0ca402b41ae2"
  ],
  "author": {
    "name": "Miguel Osorio",
    "email": "miguelosorio@google.com",
    "time": "Wed Nov 10 07:52:20 2021 -0800"
  },
  "committer": {
    "name": "moidx",
    "email": "migue48@gmail.com",
    "time": "Tue Nov 16 07:12:24 2021 -0800"
  },
  "message": "[fpga] Update slice to work with 32kB ROM\n\nThe 32kB ROM configuration uses 4-bit RAM cells which were previously\nnot supported by the slice scripts. This commit adds the following\nchanges:\n\n* Update the Vivado rom.mmi generation script to support 4bit wide\n  address ranges.\n* Update the gen_vivado_mem_image.py to support swapping of byte\n  nibbles. This is needed in order to match the expected bit order in\n  the updatemem command.\n\nSigned-off-by: Miguel Osorio \u003cmiguelosorio@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b4b7a8496cfadabb79ba93ec8af9def32966a73c",
      "old_mode": 33261,
      "old_path": "hw/ip/rom_ctrl/util/gen_vivado_mem_image.py",
      "new_id": "5e2e612d8f7d17695653a4ebd0713f8992acd6d2",
      "new_mode": 33261,
      "new_path": "hw/ip/rom_ctrl/util/gen_vivado_mem_image.py"
    },
    {
      "type": "modify",
      "old_id": "7bef3fb5b0e66f880fbd3e44731d487e54294e03",
      "old_mode": 33188,
      "old_path": "hw/top_earlgrey/util/vivado_hook_write_bitstream_pre.tcl",
      "new_id": "cef67b8ec212dfb2b9fb245c9b196850496938cb",
      "new_mode": 33188,
      "new_path": "hw/top_earlgrey/util/vivado_hook_write_bitstream_pre.tcl"
    },
    {
      "type": "modify",
      "old_id": "fd0d9deabc4817709d8a99e920b0eddf12af996e",
      "old_mode": 33261,
      "old_path": "util/fpga/splice_rom.sh",
      "new_id": "60787e342ba4800b045e34999b3c585059072abf",
      "new_mode": 33261,
      "new_path": "util/fpga/splice_rom.sh"
    }
  ]
}