| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| { |
| name: "edn" |
| import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", |
| "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson", |
| "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson", |
| "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson", |
| "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson", |
| "edn_sec_cm_testplan.hjson"] |
| testpoints: [ |
| { |
| name: smoke |
| desc: ''' |
| Enable edn, let edn boot mode generate csrng instantiate/generate commands, |
| endpoint requests genbits, compare csrng/endpoint genbits. |
| ''' |
| milestone: V1 |
| tests: ["edn_smoke"] |
| } |
| { |
| name: firmware |
| desc: ''' |
| Verify SW_CMD_REQ/SW_CMD_STS registers/bits behave as predicted. |
| Verify RESEED/GENERATE software cmds work with 0 and 12 32-bit words of additional data. |
| Verify cmd_fifo_reset bit causes fifos to reset. |
| Verify boot_req_dis bit disables boot_req mode. |
| Verify registers at End-Of-Test. |
| ''' |
| milestone: V2 |
| tests: [] |
| } |
| { |
| name: csrng_cmd |
| desc: ''' |
| Verify endpoint agent reqs generate csrng commands for both fifo full/empty conditions. |
| Verify when no/some/all endpoints requesting (test arbiter). |
| Verify auto-request mode (RESEED_CMD/GENERATE_CMD registers) behaves as predicted. |
| Verify max_num_reqs_between_reseeds in auto-generate mode. |
| Verify boot-time request mode behaves as predicted. |
| Verify SUM_STS register bits behave as predicted. |
| ''' |
| milestone: V2 |
| tests: [] |
| } |
| { |
| name: genbits |
| desc: ''' |
| Verify genbits input is transferred to endpoint(s) as predicted. |
| Verify fips bit(s) are properly transferred to endpoint. |
| ''' |
| milestone: V2 |
| tests: ["edn_genbits"] |
| } |
| { |
| name: interrupts |
| desc: ''' |
| Verify intr_edn_cmd_req_done interrupt asserts/clears as predicted. |
| Verify intr_edn_fatal_err interrupt asserts/clears as predicted. |
| ''' |
| milestone: V2 |
| tests: ["edn_intr"] |
| } |
| { |
| name: alerts |
| desc: ''' |
| Verify recov_alert_sts asserts/clears as predicted. |
| ''' |
| milestone: V2 |
| tests: ["edn_alert"] |
| } |
| { |
| name: errs |
| desc: ''' |
| Verify ERR_CODE asserts as predicted. |
| Verify ERR_CODE all reg bits via ERR_CODE_TEST. |
| ''' |
| milestone: V2 |
| tests: ["edn_err"] |
| } |
| { |
| name: stress_all |
| desc: ''' |
| Combine the other individual testpoints while injecting TL errors and running CSR tests |
| in parallel. |
| ''' |
| milestone: V2 |
| tests: ["edn_stress_all"] |
| } |
| ] |
| |
| covergroups: [ |
| { |
| name: err_test_cg |
| desc: ''' |
| Covers that all fatal errors, all fifo errors and all error codes of edn |
| have been tested. |
| Individual config settings that will be covered include: |
| - which_fatal_err (0 to 4), 5 possible fatal errors |
| - which_fifo_write_err (0 to 1), 2 differnt fifos |
| - which_fifo_read_err (0 to 1), 2 different fifos |
| - which_fifo_state_err (0 to 1), 2 different fifos |
| - which_err_code (0 to 15), 8 ERR_CODE errors, plus 8 ERR_CODE_TEST bits test |
| - which_fifo_err (0 to 2), fifo write/read/state errors |
| - which_invalid_mubi (0 to 3), 4 possible invalid mubi4 value fields |
| ''' |
| } |
| ] |
| } |