hw/ip/spi_device/data/spi_device_testplan.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  name: "spi_device"
  import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/mem_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
                     "spi_device_sec_cm_testplan.hjson"]
  testpoints: [
    {
      name: smoke
      desc: '''
            Use default SRAM fifo setting. Seq:
            - Write a word data to TX memory and update wptr
            - Send a word SPI transfer
            - Read a word data from RX memory and update rptr
            - Compare the data and check no pending data in SRAM FIFO
            - Repeat above steps'''
      milestone: V1
      tests: ["spi_device_smoke"]
    }
    {
      name: base_random_seq
      desc: '''
            Create 3 parallel threads
            - Write random data to TX memory unless fifo is full
            - Send SPI transfer unless TX is empty or RX is full
            - Read RX memory unless RX is empty'''
      milestone: V2
      tests: ["spi_device_txrx"]
    }
    {
      name: fifo_full
      desc: '''
            Increase the chance to have fifo full by following
            - Reduce delay to write TX memory
            - Increase delay to read RX memory'''
      milestone: V2
      tests: ["spi_device_fifo_full"]
    }
    {
      name: fifo_underflow_overflow
      desc: '''
            Override spi_device_txrx_vseq to send SPI transfer without checking TX/RX fifo, note:
            - When TX is underflow, SW shouldn't update wptr if spi isn't idle, otherwise, spi may
              send mis-aligned data
            - When RX is overflow, data will be lost and if SW update rptr, received data may be
              mis-aligned
            - Ensure underflow/overflow is triggered correctly'''
      milestone: V2
      tests: ["spi_device_fifo_underflow_overflow"]
    }
    {
      name: dummy_sck_and_dummy_csb
      desc: '''
            Drive dummy sck without csb or drive dummy csb without sck, and test no impact on the
            design'''
      milestone: V2
      tests: ["spi_device_dummy_item_extra_dly"]
    }
    {
      name: extra_delay_on_spi
      desc: '''
            Add extra delay between spi clock edge or extra delay between 2 words data
            This is to test host pause transfer for a while without turning off csb and then stream
            in data again'''
      milestone: V2
      tests: ["spi_device_dummy_item_extra_dly"]
    }
    {
      name: tx_async_fifo_reset
      desc: '''
            Reset TX async fifo when SPI interface is idle

            - Fill TX SRAM FIFO with some data, which will be transfered to TX async FIFO
            - Write 0 into read and write point of TX SRAM FIFO
            - Program `rst_txfifo` to reset the async FIFO
            - Check `async_fifo_level.txlvl` is 0
            - Fill TX SRAM FIFO with some other data and enable SPI transfer
            - Check SPI device sends and receives the correct data
            '''
      milestone: V2
      tests: ["spi_device_tx_async_fifo_reset"]
    }
    {
      name: rx_async_fifo_reset
      desc: '''
            Reset RX async fifo when SPI interface is idle

            - Configure RX SRAM FIFO with a small size, so that it's easy to fill up
            - Start SPI transfers to fill up the RX SRAM FIFO and at least part of the RX async
              FIFO
            - Program `rst_rxfifo` to reset the async FIFO
            - Check `async_fifo_level.rxlvl` is 0
            - Write 0 into read and write point of RX SRAM FIFO
            - Fill TX SRAM FIFO with some other data and start another SPI transfers
            - Check SPI device sends and receives the correct data
            '''
      milestone: V2
      tests: ["spi_device_rx_async_fifo_reset"]
    }
    {
      name: interrupts
      desc: '''
            Test all supported interrupts:
            - tx/rx lvl
            - rx full
            - rx error
            - overflow/underflow'''
      milestone: V2
      tests: ["spi_device_intr"]
    }
    {
      name: abort
      desc: '''
            - Fill TX FIFO without host traffic
            - Issue Abort to control register
            - Poll until abort_done in status register
            - TBD additional checking
            '''
      milestone: V2
      tests: ["spi_device_abort"]
    }
    {
      name: byte_transfer_on_spi
      desc: '''send spi transfer on byte granularity, and make sure the timer never expires'''
      milestone: V2
      tests: ["spi_device_byte_transfer"]
    }
    {
      name: rx_timeout
      desc: '''
            - Send spi transfer on byte granularity, and timer may expires
            - Only check data in sequence level when timer expires. Monitor and scoreboard don't
              model the timer feature
            - Note: Timeout only for RX'''
      milestone: V2
      tests: ["spi_device_rx_timeout"]
    }
    {
      name: bit_transfer_on_spi
      desc: '''
            Send spi transfer on bit granularity
            - If TX drives < 7 bits, this byte will be sent in next CSB.
            - If TX drives 7 bits and set CSB to high, this byte won't be sent in next CSB'''
      milestone: V2
      tests: ["spi_device_bit_transfer"]
    }
    {
      name: extreme_fifo_setting
      desc: '''Set fifo size to 4 bytes(minimum), 2k-4bytes(maximum) and others'''
      milestone: V2
      tests: ["spi_device_extreme_fifo_size"]
    }
    {
      name: perf
      desc: '''Run spi_device_fifi_full_vseq with very small delays'''
      milestone: V2
      tests: ["spi_device_perf"]
    }
    {
      name: tpm_read
      desc: '''
            - Set TPM_CFG.TPM_MODE to 0 and set TPM_CFG.EN.
            - Randomise other fields in TPM_CFG.
            - Assert the tpm_csb.
            - Send TPM read command over the SPI bus with a randomised address.
            - Check TPM_CMD_ADDR.
            - Confirm FIFO behaviour dictated by TPM_CFG.tpm_mode.
            - Check TPM_STATUS.cmdaddr_notempty and INTR_STATE.tpm_header_notempty, they should be asserted if hw_reg_dis == 0.
            - If hw_reg_dis == 0, the data is returned to the host via return-by-HW register, else the data is returned via read FIFO.
            - Confirm that the TPM submodule sends WAIT until the read FIFO is available.
            - Check the read FIFO.
            - When available, confirm that the TPM submodule sends START followed by the register value.
            - Compare this value with the expected value.'''
      milestone: V2
      tests: ["spi_device_tpm_read"]
    }
    {
      name: tpm_write
      desc: '''
            - Set TPM_CFG.TPM_MODE to 0 and set TPM_CFG.EN.
            - Randomise other fields in TPM_CFG.
            - Assert the tpm_csb.
            - Send TPM write command with a randomised address.
            - Check TPM_CMD_ADDR and write FIFO.
            - Check TPM_STATUS.cmdaddr_notempty and INTR_STATE.tpm_header_notempty.
            - Based on FIFO status, check SPI bus to confirm WAIT or START sent.
            - Check that the TPM submodule accepts write data without the WAIT state if the write FIFO is empty.
            - Otherwise, check WAIT until the write FIFO becomes available (empty).'''
      milestone: V2
      tests: ["spi_device_tpm_write"]
    }
    {
      name: tpm_locality
      desc: '''
            - Make transactions of varying locality to the tpm submodule.
            - Ensure that the data returned is correct for the given locality.
            - Randomise TPM_CFG.invalid_locality and confirm response.'''
      milestone: V2
      tests: []
    }
    {
      name: partial_tpm_txrx
      desc: '''
            - Perform partial txrx over SPI with TPM_CFG.EN is set.
            - Perform multiple partial TX/RX.'''
      milestone: V2
      tests: []
    }
  ]
  covergroups: [
    {
      name: spi_device_tpm_all_modes_cg
      desc: '''
            Cover every combination of all possible modes:
            - All modes perform tx/rx interleaved tpm tx/rx.'''
    }
    {
      name: spi_device_tpm_states_cg
      desc: '''
            Cover all tpm states on the SPI bus (WAIT, INVALID, ETC).'''
    }
    {
      name: spi_device_fifo_fsm_cg
      desc: '''
            Cover all fsm states for RX/TX FIFO.'''
    }
    {
      name: spi_device_abort_all_cg
      desc: '''
            Cover the correct abort functionality for all modes.

            TODO: Functionality of abort to be clarified.'''
    }
    {
      name: spi_device_txrx_order_cg
      desc: '''
            Verify that data being tx/rx is valid regardless of bit order and that the functionality behaves as expected:

            Cover all configurations of rx/tx order in SPI_DEVICE.CFG for all valid modes.'''
    }
    {
      name: spi_device_sram_size_cg
      desc: '''
            Cover the SramAw local parameter to confirm all sizes 1 - 32kB.'''
    }
    {
      name: spi_device_sck_config_cg
      desc: '''
            Cover all combinations of SPI_DEVICE.CFG.CPOL and SPI_DEVICE.CFG.CPHA.

            Cover valid combinations for each mode.'''
    }
  ]
}