hw/ip/uart/dv/uart_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: uart

  // Top level dut name (sv module).
  dut: uart

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: vcs

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:uart_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/ip/uart/data/uart_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/ip/uart/data/uart.hjson"

  // Import additional common sim cfg files.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/data/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/data/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/data/tests/intr_test.hjson",
                "{proj_root}/hw/dv/data/tests/tl_access_tests.hjson",
                "{proj_root}/hw/dv/data/tests/stress_tests.hjson"]

  // Add additional tops for simulation.
  sim_tops: ["-top uart_bind"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  // Default UVM test and seq class name.
  uvm_test: uart_base_test
  uvm_test_seq: uart_base_vseq

  // Add UART specific exclusion files.

  // Add excl files to tool_srcs so that it gets copied over to the scratch area.
  tool_srcs: ["{proj_root}/hw/ip/uart/dv/cov/uart_cov_excl.el"]

  // Refer to the excl file with vcs_cov_excl_files var with the rel path from tool_srcs_dir
  // so the VCS can find it.
  vcs_cov_excl_files: ["{tool_srcs_dir}/uart_cov_excl.el"]

  // List of test specifications.
  tests: [
    {
      name: uart_sanity
      uvm_test_seq: uart_sanity_vseq
    }

    {
      name: uart_tx_rx
      uvm_test_seq: uart_tx_rx_vseq
    }

    {
      name: uart_fifo_full
      uvm_test_seq: uart_fifo_full_vseq
    }

    {
      name: uart_fifo_overflow
      uvm_test_seq: uart_fifo_overflow_vseq
    }

    {
      name: uart_fifo_reset
      // need more seeds to cover uart_env_cov::fifo_level_cg
      reseed: 300
      uvm_test_seq: uart_fifo_reset_vseq
    }

    {
      name: uart_rx_oversample
      uvm_test_seq: uart_rx_oversample_vseq
      run_opts: ["+zero_delays=1"]
    }

    {
      name: uart_intr
      uvm_test_seq: uart_intr_vseq
      // 3ms
      run_opts: ["+test_timeout_ns=3000000000"]
    }

    {
      name: uart_noise_filter
      uvm_test_seq: uart_noise_filter_vseq
    }

    {
      name: uart_rx_start_bit_filter
      uvm_test_seq: uart_rx_start_bit_filter_vseq
    }

    {
      name: uart_rx_parity_err
      uvm_test_seq: uart_rx_parity_err_vseq
    }

    {
      name: uart_tx_ovrd
      uvm_test_seq: uart_tx_ovrd_vseq
    }

    {
      name: uart_loopback
      uvm_test_seq: uart_loopback_vseq
    }

    {
      name: uart_perf
      uvm_test_seq: uart_perf_vseq
      run_opts: ["+zero_delays=1"]
    }

    {
      name: uart_stress_all_with_rand_reset
      // need more seeds to cover uart_agent_cov::uart_reset_cg
      reseed: 100
    }
  ]

  // List of regressions.
  regressions: [
    {
      name: sanity
      tests: ["uart_sanity"]
    }
  ]
}