[ibex] Fix lint warnings from parameter width mismatch

This parameter gets passed to tlul_fifo_sync, which expects a bit. The
possible values here are also single bits, but we're storing the
intermediate value in an int, causing Verilator lint warnings.

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>

hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv

diff --git a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
index ca05c10..59cbc3b 100644
--- a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
+++ b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
@@ -74,7 +74,7 @@
 
   // if pipeline=1, do not allow pass through and always break the path
   // if pipeline is 0, passthrough the fifo completely
-  localparam int FifoPass = PipeLine ? 1'b0 : 1'b1;
+  localparam bit FifoPass = PipeLine ? 1'b0 : 1'b1;
   localparam int FifoDepth = PipeLine ? 4'h2 : 4'h0;
   // ICache creates more outstanding transactions
   localparam int NumOutstandingReqs = ICache ? 8 : 2;