[es/csrng/edn] Don't clear packer FIFOs upon read Previously, all packer FIFOs in the entropy complex where by default cleared to zero upon read. However, as this may simplify attacks trying to manipulate the random number distribution it should better be avoided. Leaving around the previous random data on the bus/wires after the read is preferred over outputting a deterministic value in this case. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org> Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/hw/ip/csrng/rtl/csrng_core.sv b/hw/ip/csrng/rtl/csrng_core.sv index f36dcbb..61362b9 100644 --- a/hw/ip/csrng/rtl/csrng_core.sv +++ b/hw/ip/csrng/rtl/csrng_core.sv
@@ -795,7 +795,8 @@ prim_packer_fifo #( .InW(BlkLen), - .OutW(32) + .OutW(32), + .ClearOnRead(1'b0) ) u_prim_packer_fifo_sw_genbits ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -989,7 +990,8 @@ prim_packer_fifo #( .InW(32), - .OutW(SeedLen) + .OutW(SeedLen), + .ClearOnRead(1'b0) ) u_prim_packer_fifo_adata ( .clk_i (clk_i), .rst_ni (rst_ni),
diff --git a/hw/ip/edn/rtl/edn_core.sv b/hw/ip/edn/rtl/edn_core.sv index 17b284c..ff68865 100644 --- a/hw/ip/edn/rtl/edn_core.sv +++ b/hw/ip/edn/rtl/edn_core.sv
@@ -615,7 +615,8 @@ prim_packer_fifo #( .InW(CSGenBitsWidth), - .OutW(CSGenBitsWidth) + .OutW(CSGenBitsWidth), + .ClearOnRead(1'b0) ) u_prim_packer_fifo_cs ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -675,7 +676,8 @@ prim_packer_fifo #( .InW(CSGenBitsWidth), - .OutW(EndPointBusWidth) + .OutW(EndPointBusWidth), + .ClearOnRead(1'b0) ) u_prim_packer_fifo_ep ( .clk_i (clk_i), .rst_ni (rst_ni),
diff --git a/hw/ip/entropy_src/rtl/entropy_src_core.sv b/hw/ip/entropy_src/rtl/entropy_src_core.sv index 7da5d52..4951a18 100644 --- a/hw/ip/entropy_src/rtl/entropy_src_core.sv +++ b/hw/ip/entropy_src/rtl/entropy_src_core.sv
@@ -720,7 +720,8 @@ prim_packer_fifo #( .InW(1), - .OutW(RngBusWidth) + .OutW(RngBusWidth), + .ClearOnRead(1'b0) ) u_prim_packer_fifo_esbit ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -1915,7 +1916,8 @@ prim_packer_fifo #( .InW(RngBusWidth), - .OutW(PostHTWidth) + .OutW(PostHTWidth), + .ClearOnRead(1'b0) ) u_prim_packer_fifo_postht ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -1987,7 +1989,8 @@ prim_packer_fifo #( .InW(ObserveFifoWidth), - .OutW(PreCondWidth) + .OutW(PreCondWidth), + .ClearOnRead(1'b0) ) u_prim_packer_fifo_precon ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -2086,7 +2089,8 @@ prim_packer_fifo #( .InW(PreCondWidth), - .OutW(SeedLen) + .OutW(SeedLen), + .ClearOnRead(1'b0) ) u_prim_packer_fifo_bypass ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -2232,7 +2236,8 @@ prim_packer_fifo #( .InW(SeedLen), - .OutW(FullRegWidth) + .OutW(FullRegWidth), + .ClearOnRead(1'b0) ) u_prim_packer_fifo_swread ( .clk_i (clk_i), .rst_ni (rst_ni),