hw/top_earlgrey/dv/chip_mask_rom_tests.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  # This auxiliary chip sim cfg specification focuses on chip level mask rom functional tests.
  # Please see chip_sim_cfg.hjson for full setup details.

  # Note: Please maintain alphabetical order.
  tests: [
    // Signed chip-level tests to be run with mask ROM, instead of test ROM.
    {
      name: chip_sw_uart_smoketest_signed
      uvm_test_seq: chip_sw_base_vseq
      sw_images: ["sw/device/tests/uart_smoketest:1:signed"]
      en_run_modes: ["sw_test_mode_mask_rom"]
      run_opts: ["+sw_test_timeout_ns=20000000"]
    }

    // Mask ROM func tests to be run with test ROM.
    {
      name: mask_rom_keymgr_functest
      uvm_test_seq: chip_sw_base_vseq
      sw_images: ["sw/device/silicon_creator/testing/sw_silicon_creator_lib_driver_keymgr_functest:1"]
      en_run_modes: ["sw_test_mode_test_rom"]
      run_opts: ["+sw_test_timeout_ns=5000000"]
    }
  ]

  regressions: [
    {
      name: mask_rom_functests
      tests: ["mask_rom_keymgr_functest"]
    }
    {
      name: signed
      tests: ["chip_sw_uart_smoketest_signed"]
    }
  ]
}